US20110278527A1 - Semiconductor device - Google Patents

Abstract

According to one embodiment, a semiconductor device includes a substrate and an interconnect region on the substrate. The interconnect region includes a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the first contact portion and electrically connecting the first interconnect and the second interconnect.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2010-113533, filed May 17, 2010; the entire contents of which are incorporated herein by reference.
FIELD
• Embodiments described herein relate generally to a semiconductor device.
BACKGROUND
• A semiconductor memory as a semiconductor device is mounted on various electronic equipment. Recently, resistance change memories such as ReRAM (Resistive RAM) using a variable resistance device as a memory device, PCRAM (Phase Change RAM) using a phase change device as a memory device, and the like have received attention as a next generation non-volatile semiconductor memory.
• These resistance change memories have a feature in that a memory cell array is of a cross point type and can realize a large memory capacity by a three-dimensional integration and operation at a high speed similar to a DRAM (refer to, for example, Jpn. PCT National Publication No. 2005-522045).
• In the resistance change memory, a cross point type memory cell array includes cell units. Each of the cell units is formed of a memory device and a non-ohmic device. In the cross point type memory cell array, the cell units are disposed two-dimensionally as well as stacked in a vertical direction with respect to a substrate surface.
• The resistance change memory having the stacked structure includes a contact electrode for connecting an interconnect having a certain interconnect level and another interconnect having a different interconnect level (an upper layer or a lower layer) (refer to, for example, Jpn. Pat. Appln. KOKAI Publication No. 2009-130140 reference). In the cross point type memory cell array, a contact portion connected to the contact electrode is disposed to a part of the interconnect.
• In a semiconductor device such as the resistance change memory, when a connecting state of a contact electrode and an interconnect (contact portion) is deteriorated, a contact resistance of the contact electrode and the interconnect is increased, and electric characteristics of each interconnect are dispersed. Further, when an area for disposing the contact electrode and the contact portion is simply reduced here, the dispersion of the electric characteristics is increased.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is view showing a resistance change memory of an example of a semiconductor device of an embodiment of the invention;
• FIG. 2 is a view showing a configuration example of a cross point type memory cell array;
• FIG. 3A is view showing a configuration example of a cell unit of the memory cell array ofFIG. 2;
• FIG. 3B is view showing an example of the cell unit;
• FIG. 4 is view showing a connection relation between a memory device and a rectifier device;
• FIG. 5A is view showing a layout of first and second control circuits;
• FIG. 5B is view showing a layout of first and second control circuits;
• FIG. 6 is view showing a layout of first and second control circuits;
• FIG. 7 is view showing a layout in the vicinity of the memory cell array;
• FIG. 8 is a plan view showing a basic example of an interconnect and a contact of a semiconductor device of the embodiment;
• FIG. 9 is a sectional view showing the basic example of the interconnect and the contact of the semiconductor device of the embodiment;
• FIG. 10 is view describing a configuration of the interconnect and the contact of the semiconductor device of the embodiment;
• FIG. 11 is view showing a structure example of an interconnect and a contact of a resistance change memory;
• FIG. 12 is view showing a structure example of an interconnect and a contact of a resistance change memory;
• FIG. 13 is view showing a structure example of an interconnect and a contact of a resistance change memory;
• FIG. 14A is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 14B is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 14C is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 15A is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 15B is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 15C is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 16A is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 16B is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 17 is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 18A is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 18B is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 19A is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 19B is view showing a process of a method of manufacturing the resistance change memory;
• FIG. 20 is a view describing a modification of the semiconductor device of the embodiment;
• FIG. 21A is a view describing a modification of the semiconductor device of the embodiment;
• FIG. 21B is a view describing a modification of the semiconductor device of the embodiment;
• FIG. 22A is a view describing a modification of the semiconductor device of the embodiment;
• FIG. 22B is a view describing a modification of the semiconductor device of the embodiment; and
• FIG. 23 is a view describing a modification of the semiconductor device of the embodiment.
DETAILED DESCRIPTION
• A semiconductor device according to an embodiment will be described below in detail referring to the drawings. In the following description, the components having the same functions and the same configurations are denoted by the same reference numerals and will be described in duplication when necessary.
• In general, according to one embodiment, a semiconductor device includes a substrate and an interconnect region on the substrate. The interconnect region includes a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the first contact portion and electrically connecting the first interconnect and the second interconnect.
• A subject of the embodiment is a resistance change memory as a semiconductor device using, for example, a variable resistance device or a phase change device as a memory device.
Embodiment(1) Basic Example
• A semiconductor device according to an embodiment will be described usingFIGS. 1,2,3,4,5,6,7,8,9, and10. In the embodiment, a resistance change memory will be described as an example of the semiconductor device.
• FIG. 1 shows a main portion of the resistance change memory.
• The resistance change memory (for example, chip)1 includes a cross point typememory cell array2.
• Afirst control circuit3 is disposed to an end of the cross point typememory cell array2 in a first direction, and asecond control circuit4 is disposed to one end in a second direction intersecting the first direction.
• Thefirst control circuit3 selects a row of the cross point typememory cell array2 based on, for example, a row address signal. Further, thesecond control circuit4 selects a column of the cross point typememory cell array2 based on, for example, a column address signal.
• The first andsecond control circuits3,4 control write, erase, and read of data to a memory device in thememory cell array2.
• In theresistance change memory1 of the embodiment, for example, the write is referred to as a set and the erase is referred to as a reset. It is sufficient that a resistance value of a set state is different from a resistance value of a reset state, and it is not important whether the resistance value of the set state is higher or lower than the resistance value of the reset state.
• Further, a multi-level resistance change memory, in which one memory device stores multi-level data, can be also realized by selectively writing one level of levels of resistance values which can be set to the memory device in a set operation.
• Acontroller5 supplies a control signal and data to theresistance change memory1. The control signal is input to acommand interface circuit6, and the data is input to a data input/output buffer7. Thecontroller5 may be disposed in thechip1 or may be disposed in a chip (host device) different from thechip1.
• Thecommand interface circuit6 determines whether or not data from thecontroller5 is command data based on the control signal. When the data is the command data, thecommand interface circuit6 transfers the data from the data input/output buffer7 to astate machine8.
• Thestate machine8 manages an operation of theresistance change memory1 based on the command data. For example, thestate machine8 manages a set/reset operation and a read operation based on the command data from thecontroller5. It is also possible for thecontroller5 to receive status information managed by thestate machine8 and to determine a result of operation in theresistance change memory1.
• In the set/reset operation and the read operation, thecontroller5 supplies an address signal to theresistance change memory1. The address signal is input to the first andsecond control circuits3,4 via anaddress buffer9.
• Apotential supply circuit10 outputs a voltage pulse or a current pulse necessary for, for example, the set/reset operation and the read operation at a predetermined timing based on a command from thestate machine8. Thepotential supply circuit10 includes, for example, apulse generator10A and controls the voltage value/current value and the pulse width of a voltage pulse/current pulse output in response to an operation shown by the command data and the control signal.
• Hereinafter, circuits other than the cross point typememory cell array2, which constitutes the resistance change memory (chip), are called peripheral circuits.
• FIG. 2 is a bird's eye view showing a structure of the cross point type memory cell array.
• The cross point typememory cell array2 is disposed on asubstrate11. Thesubstrate11 is a semiconductor substrate (for example, a silicon substrate) or an interlayer insulation film on the semiconductor substrate. Note that when thesubstrate11 is the interlayer insulation film, a circuit using a field effect transistor and the like may be formed on the surface of the semiconductor substrate under the cross point typememory cell array2 as a peripheral circuit of the resistance change memory.
• The cross point typememory cell array2 has a stack structure of, for example, memory cell arrays (also called memory cell layers).
• FIG. 2 shows, as an example, a case in which the cross point typememory cell array2 has four memory cell arrays, M1, M2, M3 and M4, stacked in a third direction (direction vertical to a main plane of the substrate11). It is sufficient that at least two memory cell arrays are stacked. Note that the cross point typememory cell array2 may have one memory cell array. Further, an insulation film may be disposed between two stacked memory cell arrays and the two memory cell arrays may be electrically separated by the insulation film.
• As shown inFIG. 2, when the memory cell arrays M1, M2, M3 and M4 are stacked, the address signal includes, for example, a memory cell array selection signal, a row address signal, and a column address signal. The first andsecond control circuits3,4 select one of the stacked memory cell arrays based on, for example, the memory cell array selection signal. The first andsecond control circuits3,4 can write, erase, and read data to one of the stacked memory cell arrays or can also write, erase, and read data to at least two or all of the stacked memory cell arrays at the same time.
• The memory cell array M1 includes cell units CU1 disposed in first and second directions in an array state. Likewise, the memory cell array M2 includes cell units CU2 disposed in the array state, the memory cell array M3 includes cell units CU3 disposed in the array state, and the memory cell array M4 includes cell units CU4 disposed in the array state.
• Further, control lines L1(j−1), L1(j), L1(j+1), control lines L2(i−1), L2(i), L2(i+1), control lines L3(j−1), L3(j), L3(j+1), control lines L4(i−1), L4(i), L4(i+1), and control lines L5(j−1), L5(j), L5(j+1) are sequentially disposed on thesubstrate11 from thesubstrate11 side.
• Odd numbers of interconnects from thesubstrate11 side, that is, the control lines L1(j−1), L1(j), L1(j+1), the control lines L3(j−1), L3(j), L3(j+1), and the control lines L5(j−1), L5(j), L5(j+1) extend in the second direction.
• Even numbers of interconnects from thesemiconductor substrate11 side, that is, the control lines L2 (i−1), L2(i), L2(i+1), and the control lines L4(i−1), L4(i), L4(i+1) extend in the first direction intersecting the second direction.
• The control lines are used as word lines or bit lines.
• The first memory cell array M1 of a lowermost layer is disposed between the first control lines L1(j−1), L1(j), L1(j+1) and the second control line L2(i−1), L2(i), L2(i+1). In the set/reset operation and the read operation of the memory cell array M1, one control lines of the control lines L1(j−1), L1(j), L1(j+1) or the control lines L2(i−1), L2(i), L2(i+1) are used as the word lines, and the other control lines are used as the bit lines.
• The memory cell array M2 is disposed between the second control lines L2(i−1), L2(i), L2(i+1) and the third control line L3 (j−1), L3(j), L3(j+1). In the set/reset operation and the read operation of the memory cell array M2, one control lines of the control lines L2(i−1), L2(i), L2(i+1) or the control lines L3(j−1), L3(j), L3(j+1) are used as the word lines, and the other control lines are used as the bit lines.
• The memory cell array M3 is disposed between the third control lines L3(j−1), L3(j), L3(j+1) and the fourth control lines L4(i−1), L4(i), L4(i+1). In the set/reset operation and the read operation of the memory cell array M3, one control lines of the control lines L3(j−1), L3(j), L3(j+1) or the control lines L4(i−1), L4(i), L4(i+1) are used as the word lines, and the other control lines are used as the bit lines.
• The memory cell array M4 is disposed between the fourth control lines L4(i−1), L4(i), L4(i+1) and the fifth control lines L5(j−1), L5(j), L5(j+1). In the set/reset operation and the read operation of the memory cell array M4, one control lines of the control lines L4(i−1), L4(i), L4(i+1) or the control lines L5(j−1), L5(j), L5(j+1) are used as the word lines, and the other control lines are used as the bit lines.
• The cell units CU1 are disposed to the portions where the control lines L1(j−1), L1(j), L1(j+1) intersect the control lines L2(i−1), L2(i), L2(i+1). Likewise, the cell units CU2, CU3, CU4 are disposed respectively to the portions where the control lines L2(i−1), L2(i), L2(i+1) intersect the control lines L3(j−1), L3(j), L3(j+1), the portions where the control lines L3(j−1), L3(j), L3(j+1) intersect the control lines L4(i−1), L4(i), L4(i+1), and the portions where the control lines L4(i−1), L4(i), L4(i+1) intersect the control lines L5(j−1), L5(j), L5(j+1). More specifically, in the cross point typememory cell array2, the cell units are disposed to the portions where the control lines, which are continuously stacked in the third direction, intersect.
• Note that, when the stacked memory cell arrays are separated to respective layers by insulation films, the control lines extending in the first and second directions are not shared by the two stacked memory cell arrays, and control lines as the word lines and as the bit lines are disposed to the memory cell arrays of the respective layers.
• FIG. 3A shows an example of a structure of interconnects and cell units in the cross point type memory cell array.FIG. 3B shows an example of a more specific structure of one cell unit.
• FIG. 3A shows the cell units CU1, CU2 in the two memory cell arrays M1, M2 inFIG. 2. The configuration of the cell units in the two memory cell arrays M3, M4 inFIG. 2 are the same as the configuration of the cell units in the two memory cell arrays M1, M2 inFIG. 2.
• The stacked cell units CU1, CU2 share the one control line L2(i).
• One end of a current path of the cell unit CU1 is connected to the control line L1(j), and the other end of the current path of the cell unit CU1 is connected to the control line L2(i). One end of a current path of the cell unit CU2 is connected to the control line L2(i), and the other end of the current path of the cell unit CU2 is connected to the control line L3(j).
• Each of the cell units CU1, CU2 includes a memory device and a non-ohmic device. The memory device is connected in series to the non-ohmic device. For example, a rectifier device is used for the non-ohmic device.
• Various patterns exist as a connection relation between the memory device and the rectifier device as the non-ohmic device. However, it is necessary that all the cell units in one memory cell array have the same connection relation between the memory device and the rectifier device.
• FIG. 4 shows the connection relation between the memory device and the rectifier device.
• As to the connection relation between the memory device and the rectifier device in one cell unit, there exist two different ways of a positional relation between the memory device and the rectifier device and two different ways of the direction of the rectifier, that is, there exist four different ways of the connection relation in total. Accordingly, as to the cell units in the two memory cell arrays, there exist 16 different ways (four different ways×four different ways) of patterns of the connection relation between the memory device and the rectifier device. InFIG. 4, “a” to “p” show the 16 different ways of the connection relation. The embodiment can be applied to all the 16 different ways of the connection relation.
• FIG. 3B shows a structure example of the cell unit CU1 shown in “a” ofFIG. 4.
• In the cell unit CU1 of the embodiment ofFIG. 3B, amemory device20 is stacked on anon-ohmic device30. A stacked body including thememory device20 and thenon-ohmic device30 is sandwiched between the two control lines L2(i), L3(j) as one cell unit CU. However, the structure of the cell unit CU shown inFIG. 3A is an example, and thenon-ohmic device30 may be stacked on thememory device20 in response to a connection relation between the cell unit shown inFIG. 4.
• Thememory device20 is a variable resistance device or a phase change device. Here, the variable resistance device is a device including a material whose resistance value is changed by an application of energy such as a voltage, a current, and heat. Further, the phase change device is a device including a material in which a crystal phase of the device is changed by the energy applied thereto and a physical property (impedance) such as a resistance value and a capacitance is changed by the phase change.
• Such phase change (phase transition) includes the ones shown below.
• Metal-semiconductor transition, metal-insulator transition, metal-metal transition, insulator-insulator transition, insulator-semiconductor transition, insulator-metal transition, semiconductor-semiconductor transition, semiconductor-metal transition, semiconductor-insulator transition
• Phase change (metal-superconductor transition and the like) in quantum state
• Paramagnetic-ferromagnetic transition, anti ferromagnetic-ferromagnetic transition, ferromagnetic-ferromagnetic transition, ferrimagnetic-ferromagnetic transition, and transitions composed of these transitions
• Paraelectric-ferroelectric transition, paraelectric-pyroelectric transition, paraelectric-piezoelectric transition, ferroelectric-ferroelectric transition, anti ferroelectric-ferroelectric transition, and transitions composed of these transitions
• Transitions composed of a combination of these transitions
• For example, transition from metal, insulator, semiconductor, ferroelectric, paraelectric, pyroelectric, piezoelectric, ferromagnetic, ferrimagnetic, spiral magnetic body, paramagnetic, or antiferromagnetic to a ferroelectric ferromagnetic material and transition opposite to the above transition.
• According to the definition, the variable resistance device includes the phase change device.
• In the embodiment, the variable resistance device is mainly composed of metal oxides (for example, binary or ternary metal oxides and the like), metal compounds, chalcogenide materials (for example, Ge—Sb—Te, In—Sb—Te, and the like), organic substances, carbon, carbon nanotubes, and the like.
• Note that the resistance value of a magneto-resistive effect element used for an MRAM (Magnetoresistive RAM) is also changed by changing a relative direction of magnetization of two magnetic layers of the device. In the embodiment, a magneto-resistive effect element, for example, MTJ (Magnetic Tunnel Junction) device is also included in the variable resistance device.
• An operation called a bipolar operation and an operation called a unipolar operation exist as a method of changing the resistance value of thememory device20.
• The bipolar operation reversibly changes the resistance value of thememory device20 between at least a first value (first level) and a second value (second level) by changing the polarity of a voltage applied to thememory device20. The bipolar operation is employed to a memory in which it is necessary to flow a current for a memory device in a dual direction in a write operation as in, for example, a spin transfer type MRAM and the like.
• The unipolar operation reversibly changes a resistance value of a memory device between at least a first value and a second value by controlling the magnitude of a voltage and/or the application time (pulse width) of the voltage without changing the polarity of the voltage applied to the memory device.
• Thememory device20 includes electrode layers25,26 at one end and the other end in the third direction (stacked direction). The electrode layer25 is disposed at a bottom portion of thememory device20, and theelectrode layer26 is disposed at an upper portion of thememory device20. The electrode layers25,26 are used as, for example, electrodes of the memory device. For example, a metal film, a metal compound film, a conductive semiconductor film, or a stacked film of such is used as the electrode layers25,26.
• In the embodiment, a portion sandwiched between the twoelectrode layers25,26 is referred to as aresistance change film21. Theresistance change film21 is a film formed of a material whose resistance value or crystal phase is changed by energy such as a voltage, a current, and heat. Theresistance change film21 includes a material having a property such that a resistance value or a crystal phase of the film itself changes due to the energy applied thereto.
• In contrast, theresistance change film21 may be composed of a material having a property such that the resistance value (or the crystal phase) is changed by changing the interface characteristics between theresistance change film21 and the electrode layers25,26 by the energy applied to the material. In the case, the property for changing the resistance value of thememory device20 is stably obtained by a combination of a material used for theresistance change film21 and a material used for the electrode layers25,26.
• The electrode layers25,26 may have a function as diffusion prevention layers. The diffusion prevention layers prevent impurities caused by thelower device30 and the control lines from dispersing to thememory device20 or prevent impurities caused by thememory device20 from dispersing to the lower device and the control lines.
• Further, the electrode layers25,26 may have a function as adhesion layers for preventing thememory device20 from exfoliating thelower device30 and the control lines.
• Thenon-ohmic device30 is a device whose input/output characteristics (voltage-current characteristics) do not have linearity, that is, a device whose input/output characteristics have non-ohmic characteristics.
• Thenon-ohmic device30 includesconductive layers35,36 at one end and the other end in the third direction (stacked direction). Theconductive layer35 is disposed at a bottom portion of thenon-ohmic device30, and theconductive layer36 is disposed at an upper portion of thenon-ohmic device30.
• Theconductive layers35,36 are used as electrodes of, for example, the non-ohmic device. Theconductive layers35,36 include any one of silicide, metal, a metal compound, a conductive semiconductor, and the like. Further, theconductive layers35,36 may be stacked bodies of these materials. Hereinafter, theconductive layers35,36 for which silicide is used will be particularly referred to as silicide layers35,36.
• FIG. 3B exemplifies a PIN diode as the non-ohmic device. The PIN diode is a diode having an intrinsic semiconductor layer between a P-type semiconductor layer (anode layer) and an N-type semiconductor layer (cathode layer). In the structure shown inFIG. 3, alayer32 sandwiched between twolayer31,33 is the intrinsic semiconductor layer, one of the twolayers31,33, that is, thelayer33 is the P-type semiconductor layer, and the other remaininglayer31 is the N-type semiconductor layer. Note that the intrinsic semiconductor layer includes not only a case in which it does not contain N-type or P-type impurities at all but also a case in which it has an impurity concentration lower than the impurity concentrations of the N-type and P-type semiconductor layers.
• The non-ohmic device is not limited to the PIN diode shown inFIG. 3B, and the PN diode, a MIS diode, a SIS structure, a MIM structure, and the like may be appropriately used in response to an operation required by the cell unit.
• The PN diode is a diode in which a P-type semiconductor layer (anode layer) and an N-type semiconductor layer (cathode layer) form a PN junction. The MIS (Metal-Insulator-Semiconductor) diode is a diode having an insulation layer between a metal layer and a semiconductor layer. The MIM (Metal-Insulator-Metal) structure and the SIS (Semiconductor-Insulator-Semiconductor) structure are devices having a structure in which an insulation layer is sandwiched between two layers composed of a metal layer or a semiconductor layer.
• In the resistance change memory driven by the unipolar operation, a rectifier device such as a diode is mainly used as thenon-ohmic device30. In the resistance change memory driven by the bipolar operation, the MIM structure and the SIS structure are mainly used as thenon-ohmic device30.
• In the embodiment, the resistance change memory using the unipolar operation will be described. However, it is needless to say that the resistance change memory of the embodiment may be the memory using the bipolar operation.
• FIGS. 5A and 5B show a first example of a layout of first and second control circuits.
• A memory cell array Ms ofFIG. 5A corresponds to any one layer of the memory cell arrays M1, M2, M3 and M4 shown inFIG. 2. As shown inFIG. 5A, the memory cell array Ms includes cell units CUs disposed in an array state. One end of each of the cell units CUs is connected to control lines Ls(j−1), Ls(j), Ls(j+1), and the other end of each of the cell units CUs is connected to control lines Ls+1(i−1), Ls+1(i), Ls+1(i+1).
• As shown inFIG. 5B, a memory cell array Ms+1 includes cell units CUs+1 disposed in the array state. One end of each of the cell units CUs+1 is connected to control lines Ls+1(i−1), Ls+1(i), Ls+1(i+1), and the other end of each of the cell units is connected to control lines Ls+2(j−1), Ls+2(j), Ls+2(j+1).
• However, inFIG. 5A andFIG. 5B, “s” is set to 1, 3, 5, 7, . . . .
• Afirst control circuit3 is connected to one end of each of the control lines Ls+1(i−1), Ls+1(i), Ls+1(i+1) in a first direction via switch devices SW1. The switch devices SW1 are controlled by, for example, control signals φs+1(i−1), φs+1(i), φs+1(i+1). The switch devices SW1 are formed of, for example, an N channel type field effect transistor (FET).
• Asecond control circuit4 is connected to one end of each of the control lines Ls(j−1), Ls(j), Ls(j+1) in a second direction via switch devices SW2. The switch devices SW2 are controlled by, for example, control signals φs(j−1), φs(j), φs(j+1). The switch devices SW2 are formed of, for example, an N channel type FET.
• Thesecond control circuit4 is connected to one end of each of control lines Ls+2(j−1), Ls+2(j), Ls+2(j+1) in the second direction via switch devices SW2′. The switch devices SW2′ are controlled by, for example, control signals φs+2(j−1), φs+2(j), φs+2(j+1). The switch devices SW2′ are formed of, for example, an N channel type FET.
• FIG. 6 shows a second example of the layout of the first and second control circuits. Note that, inFIG. 6, since the internal configuration of memory cell arrays Ms, Ms+1, Ms+2, Ms+3 is substantially the same as the memory cell arrays shown inFIG. 5A orFIG. 5B, an illustration of the internal configuration of the memory cell arrays will not be repeated inFIG. 6.
• The layout of the second example is different from the layout of the first example in that thefirst control circuits3 are disposed at both ends of the memory cell arrays Ms, Ms+1, Ms+2, Ms+3 in the first direction, respectively, and thesecond control circuits4 are disposed at both ends of the memory cell array Ms, Ms+1, Ms+2, Ms+3 in the second direction, respectively. However, “s” ofFIG. 6 is set to 1, 5, 9, 13, . . . .
• Thefirst control circuits3 are connected to both ends of the control lines Ls+1(i−1), Ls+1(i), Ls+1(i+1) in the first direction via the switch devices SW1 respectively. The switch devices SW1 are controlled by, for example, control signals φs+1(i−1), φs+1(i), φs+1(i+1), φs+3(i−1), φs+3(i), φs+3(i+1). The switch devices SW1 are formed of, for example, an N channel type FET.
• Thesecond control circuits4 are connected to both ends of the control lines Ls(j−1), Ls(j), Ls(j+1) in the second direction, respectively via the switch devices SW2. The switch devices SW2 are controlled by, for example, control signals φs(j−1), φs(j), φs(j+1), φs+2(j−1), φs+2(j), φs+2(j+1). The switch devices SW2 are formed of, for example, an N channel type FET.
• In the resistance change memory using the unipolar operation, the potential levels of the two control lines to which a selected cell unit, which is subjected to the set/reset operation, are controlled so that a forward bias is applied to the non-ohmic device (for example, the PIN diode). In contrast, the potential levels of two control lines, to which the remaining cell units (non-selected cell units) excluding the selected cell unit are connected, are controlled so that a reverse bias is applied to the non-ohmic devices or so that the potential difference between the terminals of the non-ohmic devices becomes 0V.
• In the set operation, a voltage of, for example, 3V to 6V is applied to the memory devices in the selected cell unit for a period (pulse width) of about 10 ns to 100 ns. A current value of a set current applied to the memory devices (in a high resistance state) is, for example, about 10 nA, and the current density of the set current is set to a value within a range of 1×10⁵to 1×10⁷A/cm². As a result, the resistance state of the memory devices in the selected cell unit changes from the high resistance state to a low resistance state.
• In the reset operation, a voltage of about 0.5V to 3V is applied to the memory devices in the selected cell unit for a period (pulse width) of 200 ns to 1 μs. The current value of a reset current applied to the memory devices (in the low resistance state) is about 1 μA to 100 μA, and the current density of the set current is set to a value within a range of 1×10³to 1×10⁶A/cm². As a result, the resistance state of the memory devices in the selected cell unit changes from the low resistance state to the high resistance state.
• Note that the current value of the set current is different from the current value of the reset current. Further, when the set/reset operation of the memory devices depends on the pulse widths of the current and the voltage, the pulse width of the set current is different from the pulse width of the reset current. The voltage value and the period (pulse width) for changing the resistance value of the memory devices in the cell unit depend on a material of the memory devices.
• In the read operation of the resistance change memory, the potential level of a selected control line is controlled so that a forward bias is applied to the non-ohmic devices in the selected cell unit likewise in the set/reset operation. It is necessary that the current value of a read current I-read is sufficiently smaller than the current value of a set current I-set and the current value of a reset current I-reset so that the resistance value of the memory devices does not change in the read operation. Further, when the change of the resistance value of the memory devices depends on the pulse width of the current, the pulse width of the read current is set to a pulse width by which the resistance value of the memory devices does not change.
• In the resistance change memory shown inFIGS. 5A,5B, and6, an area in which interconnects are wired is formed in thechip1 to connect the control lines of the cross point typememory cell array2 to theperipheral circuits3,4 in thechip1. The interconnect wiring area is referred to as an interconnect region in the embodiment.
• For example, as shown inFIG. 7, aninterconnect region15 is formed on the substrate (for example, the interlayer insulation film)11 to be adjacent to a region (hereinafter, called a memory cell array region)12 in which the cross point typememory cell array2 is disposed. Then, thecontrol circuits3,4 and theother circuits6,7,8,9 and10 are disposed as peripheral circuits on the surface of the semiconductor substrate (active region) under the memorycell array region12 and theinterconnect region15.
• Note that, inFIG. 7, theinterconnect region15 is disposed so as to surround the memorycell array region12. However, theinterconnect region15 is not limited to this configuration and may be disposed adjacent only to an end of the memorycell array region12 in the first direction (or the second direction), or theinterconnect regions15 may be disposed adjacent to one end and the other end of the memorycell array region12 in the first direction (or the second direction).
• The control lines included in the cross point type memory cell array are drawn out from inside of the memorycell array region12 to theinterconnect region15. To simplify the illustration,FIG. 7 shows the control lines L1 (j) extending in the second direction and the control lines L2(i) extending in the first direction of the control lines.
• A conversion of the line width of the control lines L1(j), L2 (i), a conversion of the interconnect pitch between the control lines (interconnects), or a connection between interconnects at different interconnect levels are executed in theinterconnect region15.
• Interconnects40 in theinterconnect region15 continuously extend from, for example, the memorycell array region12. However, theinterconnects40 in theinterconnect region15 are individually disposed in theinterconnect region15, and some of theinterconnects40 are connected to the control lines L1(i), L2(j), which are drawn out from the memorycell array region12 to theinterconnect region15, in theinterconnect region15.
• Contact electrodes (ref.60 inFIG. 8) are disposed in theinterconnect region15. The contact electrodes electrically connect at least twointerconnects40 having a different interconnect level. The contact electrodes are in contact withcontact portions41 disposed at parts of theinterconnects40. In the embodiment, the interconnect level means the height of the interconnects (a position in the third direction) based on a substrate surface as a reference.
• The semiconductor device (here, the resistance change memory) of the embodiment includes the control lines L1(j), L2(i) and/or theinterconnects40 having the ring-like contact portions41. Hereinafter, a case, in which the interconnects40 (control lines L1(j), L2(i)) have the ring-like contact portions41 in theinterconnect region15, will be described. However, it is needless to say that the embodiment includes a case in which the ring-like contact portions41 are disposed at the control lines L1(j), L2(i) and theinterconnects40 in the memorycell array region12.
• An interconnect having the ring-like contact portion41 will be described usingFIGS. 8,9, and10.FIG. 8 is a plan view in which a portion, in which acontact portion41 of aninterconnect40 is formed, is extracted.FIG. 9 is a sectional view along an IX-IX line ofFIG. 8.FIG. 10 is a schematic view describing a connection relation between an interconnect to which the ring-like contact portion41 is disposed and a contact electrode.
• As shown inFIGS. 8 to 10, two interconnects,40,50, are disposed in theinterconnect region15.
• Theinterconnect40, theinterconnect50, aninterlayer insulation film81, aninterlayer insulation film82, and aninterlayer insulation film83 are disposed on thesubstrate11 via aninterlayer insulation film17. Theinterconnect40 is disposed in theinterlayer insulation film82, and theinterconnect50 is disposed in theinterlayer insulation film81 below theinterconnect40. Theinterlayer insulation film83 is disposed above theinterlayer insulation film82.
• Theinterconnect40 and theinterconnect50 are disposed at different interconnect levels, respectively, so that theinterconnect40 is overlapped above theinterconnect50 in the stacked direction (third direction) of theinterlayer insulation films81,82,83.
• InFIGS. 8 to 10, theinterconnect40 extends in the first direction, and theinterconnect50 extends in the second direction intersecting the first direction. However, as long as the twointerconnects40,50 are disposed in a layout in which they are overlapped vertically (the third direction), the twointerconnects40,50 may extend in other directions or in the same direction, respectively.
• Thecontact portion41 is disposed at a portion of theinterconnect40. The portion (location) of theinterconnect40 where thecontact portion41 is disposed may be an end portion of theinterconnect40 in a direction in which the interconnect extends or may be a portion other than the end portion of the interconnect.
• Thecontact portion41 projects in a direction (the second direction inFIG. 8) intersecting the extending direction (the first direction inFIG. 8) of theinterconnect40 in a direction (horizontal direction) parallel to the surface of thesubstrate11. Note that thecontact portion41 of theinterconnect40 includes not only a portion projecting in the direction intersecting the extending direction of theinterconnect40 but also a portion extending in the extending direction of theinterconnect40.
• Thecontact portion41 is formed above theinterconnect50 at an interconnect level below theinterconnect40. Thecontact portion41 is disposed at a position where it overlaps thelower interconnect50 vertically.
• Thecontact portion41 of the embodiment has a ring-like plane shape when viewed from a vertical direction (third direction) to the surface of thesubstrate11. In the embodiment, the ring shape is a square annular shape or a circular annular shape, and the portion excluding an outer peripheral portion of the contact portion is configured as a through hole.
• The ring-like contact portion41 having the ring-like plane includes an opening portion (through hole)49 formed thereto. The openingportion49 is positioned above theinterconnect50. In the embodiment, the portion excluding the openingportion49 of thecontact portion41 is referred to as aring portion48.
• InFIG. 8, although thering portion48 and the openingportion49 of thecontact portion41 have a square plane shape, they are not limited to the square plane shape.
• Acontact electrode60 is buried in a contact hole formed in theinterlayer insulation films82,81 across them. Thecontact electrode60 is in contact with the twointerconnects40,50 having different interconnect levels.
• Thecontact electrode60 is in contact with thering portion48 formed in thecontact portion41 of theinterconnect40. Thecontact electrode60 is in contact with the upper surface of theinterconnect50 below theinterconnect40 via (passing through) theopening portion49 formed in thecontact portion41 of theinterconnect40.
• In the direction horizontal to the substrate surface, the size of aportion61 of thecontact electrode60, which is in contact with the upper surface of thecontact portion41, is set larger than the size of aportion62 under theportion61 of thecontact electrode60. That is, thecontact electrode60 has a sectional shape formed convex in a downward direction.
• Hereinafter, in thecontact electrode60, theportion61 on the upper surface of thecontact portion41 is referred to as anupper electrode portion61, and theportion62 under theupper portion61 is referred to as alower electrode portion62.
• The size of thelower electrode portion62 in the direction horizontal to the substrate surface is set equal to or smaller than the size of the openingportion49 of thecontact portion41.
• Note that although thecontact electrode60 includes the twoelectrode portions61,62, it is composed of one continuous conductor. Further, although thecontact electrode60 has the square plane shape inFIG. 8, it may have a plane shape including a curved line such as a circular shape and an oval shape.
• The contact areas between therespective interconnects40,50 and thecontact electrode60 will be described usingFIG. 10. InFIG. 10, an illustration of the interlayer insulation films that cover theinterconnects40,50 and thecontact electrode60 will not be repeated. Theinterconnect50 is referred to as aninterconnect50 of a lower layer (a first interconnect level), and theinterconnect40 is referred to as aninterconnect40 of an upper layer (a second interconnect level).
• Further, to simplify description, it is assumed that the openingportion49 formed in thecontact portion41 has the square plane shape. Likewise, an upper surface and a bottom surface of thecontact electrode60 have a square shape. However, as described above, the plane shape of thecontact portion41, the openingportion49, and thecontact electrode60 is not limited to the square shape, and a shape including the curved line such as the circular shape and the oval shape and a square shape without corners, or with rounded corners also can be applied to the embodiment.
• As described inFIGS. 8 and 9, theinterconnect40 of the upper layer includes the ring-like contact portion41 inFIG. 10. Thecontact electrode60 is in contact with theinterconnect40 of the upper layer via thecontact portion41 as well as in contact with theinterconnect50 of the lower layer passing through the ring-like opening portion49. With such configuration, thecontact electrode60 is electrically connected to theinterconnect40 of the upper layer and to theinterconnect50 of the lower layer.
• InFIG. 10, the line width of thering portion48 of thecontact portion41 is shown by “RW”. The line width RW of thering portion48 is set equal to or larger than the line width LW of theinterconnect40.
• InFIG. 10, the size of a side of the openingportion49 formed in thecontact portion41 along the first direction is shown by “X1”, and the size of a side of the openingportion49 along the second direction is shown by “Y1”. The size of the openingportion49 along the third direction is shown by “Z1”. The size Z1 is substantially the same as the film thickness of theinterconnect40 and thecontact portion41.
• As shown inFIG. 10, the size of the upper surface of theupper electrode portion61 of thecontact electrode60 along the first direction is shown by “Xce”, and the size of the upper surface of theupper electrode portion61 along the second direction is shown by “Yce”. The size of thecontact electrode60 from an upper end to thecontact portion48 along the third direction is shown by “Zce”. The sizes Xce, Yce of theupper electrode portion61 depend on the size of the upper surface of the contact hole in the interlayer insulation film (not shown) in which theupper electrode portion61 is buried. Further, the size Zce of theupper electrode portion61 of thecontact electrode60 depends on the film thickness of the interlayer insulation film in which theupper electrode portion61 is buried.
• The contact area (regions Ace1, Ace2 shown by slant lines inFIG. 10) S1 between the contact portion (ring portion48) and thecontact electrode60 is the sum of a contact area Ace1 between a bottom surface of theupper electrode portion61 of thecontact electrode60 and the upper surface of thecontact portion41 and a contact area Ace2 between thelower electrode portion62 of thecontact electrode60 and a side surface of the opening portion49 (ring portion48).
• The contact area between the bottom surface of theupper electrode portion61 of thecontact electrode60 and the upper surface of thecontact portion41 corresponds to the value obtained by subtracting the area (X1×Y1) of the upper surface of the openingportion49 from the area (Xa×Ya) of the bottom surface of thecontact electrode60.
• The contact area between thelower electrode portion62 of thecontact electrode60 and the side surface of the opening portion49 (ring portion48) corresponds to the area (Z1×(2×X1+2×Y1)) of the side surface of the openingportion49.
• Therefore, the contact area S1 between thecontact portion41 and thecontact electrode60 is determined by the followingExpression 1.
• 
  S1=(Xce×Yce−X1×Y1)+Z1×(2×X1+2×Y1)  (Expression 1)
• Thelower electrode portion62 of thecontact electrode60 passes through the openingportion49 and comes into contact with theinterconnect50 below theinterconnect40. The sizes of the upper surface of thelower electrode portion62 are substantially the same as, for example, the sizes X1, Y1 of the openingportion49.
• InFIG. 10, the size of a bottom surface of thelower electrode portion62 along the first direction is shown by “X2”, and the size of thelower electrode portion62 along the second direction is shown by “Y2”. In the case, the contact area S2 between thelower electrode portion62 of thecontact electrode60 and thelower interconnect50 is shown by the followingExpression 2.
• 
  S2=X2×Y2  (Expression 2)
• Note that when the size Zce of theupper electrode portion61 in the third direction increases, the sizes Xa, Ya of the bottom surface of theupper electrode portion61 of thecontact electrode60 tend to become smaller than the sizes Xce, Yce of the upper surface of theupper electrode portion61. Further, since the contact hole is formed via the openingportion49, the sizes X1, Y1 of the openingportion49 become approximately the same as the sizes X2, Y2 of the bottom surface of thelower electrode portion62. However, the sizes X2, Y2 of the bottom surface of thelower electrode portion62 of thecontact electrode60 tend to become smaller than the sizes X1, Y1 of the upper surface of thelower electrode portion62 in response to the magnitude of the size (height) H2 of thelower electrode portion62 in the third direction; and this relation similarly applies between the sizes Xa, Ya of the bottom surface of theupper electrode portion61 and the sizes Xce, Yce of the upper surface of theupper electrode portion61.
• Since such tendencies depend on the ratio (aspect ratio) of the size in the first direction (or the second direction) and the size in the third direction, the magnitudes of the contact areas S1, S2 between therespective interconnects40,50 and thecontact electrode60 can be controlled by taking the size of the openingportion49 of thecontact portion41, the opening size of the contact hole in which thecontact electrode60 is buried, and the film thickness of the interlayer insulation films into consideration.
• Note that when the size Z1 of the opening portion in the third direction, that is, the film thickness Z1 of theinterconnect40 and thecontact portion41 is sufficiently smaller than the sizes Xce (Xa), Yce (Ya) of theupper electrode portion61 of thecontact electrode60, the effective value of the contact area S1 between thecontact portion41 and theupper electrode portion61 becomes the contact area Ace1 between the upper surface of the contact portion41 (ring portion48) and the bottom surface of theupper electrode portion61.
• As described above, in the semiconductor device of the embodiment, for example, in the resistance change memory, thecontact electrode60 reaches thelower interconnect50 via the openingportion49 of the ring-like contact portion41 formed at theupper interconnect40. That is, the alignment position of thelower electrode portion62 of thecontact electrode60 with thelower interconnect50 can be determined by determining the magnitude of the openingportion49 of thecontact portion41 and the position of the openingportion49 to thelower interconnect50.
• Therefore, in the embodiment, the alignment offset between thecontact electrode60 and thelower interconnect50 is less affected by the alignment offset between a mask and an interconnect when the contact hole is formed and affected only by the alignment offset between theinterconnects40,50 disposed at the positions where they are overlapped vertically.
• Accordingly, in the semiconductor device in which the onecontact electrode60 is disposed across theinterconnects40,50 as in the resistance change memory described in the embodiment, a restriction of alignment between theinterconnects40,50 and thecontact electrode60, which is caused by a lithography process and an etching process for forming the contact hole in which thecontact electrode60 is buried, is relaxed.
• Accordingly, in the semiconductor device of the embodiment (for example, in the resistance change memory), the margin of an alignment offset of thecontact electrode60 connected to the interconnects having different interconnect levels can be secured by forming the plane shape of thecontact portion41 formed at the interconnect in the ring shape, without increasing the sizes of thecontact electrode60 and the contact hole in which thecontact electrode60 is buried, and without increasing the sizes of theinterconnect40 and thecontact portion41. As a result, since the sizes of the contact electrode and the contact portion of the semiconductor device of the embodiment need not be increased, an increase of the area occupied by the interconnect region can be prevented in the semiconductor device.
• Further, in the embodiment, the contact area S1 between theupper interconnect40 and theupper electrode portion61 of thecontact electrode60 includes the sizes X1, Y1 of the openingportion49 as parameters as shown inExpression 1.
• Since thecontact electrode60 reaches theinterconnect50 passing through the openingportion49, the sizes X2, Y2 of the bottom surface of thelower electrode portion62 of thecontact electrode60 depend on the sizes X1, Y1 of the openingportion49.
• The contact area S1 between theupper interconnect40 and the contact electrode60 (upper electrode portion61) can be adjusted by the magnitude of the contact hole in which thecontact electrode60 is buried and the sizes of thering portion48 of thecontact portion41. However, the sizes (sizes of the opening portion) of the contact hole are preferably small to prevent the increase of the area occupied by theinterconnect region15.
• When thecontact portion41 is set to a predetermined area, the area (sizes X1, Y1) of the openingportion49 and the magnitude of the line width RW of thering portion48 can be adjusted.
• When, for example, the line width RW of thering portion48 is increased in the ring-like contact portion41, the margin of an alignment offset between thecontact electrode60 and thecontact portion41 disposed to theinterconnect40 can be increased.
• Further, when the line width RW of thering portion48 is increased, since the size Xce, Yce of theupper electrode portion61 can be increased, the contact area between theupper electrode portion61 of thecontact electrode60 and thecontact portion41 can be increased.
• Therefore, in the semiconductor device of the embodiment, the margins of the sizes of thecontact electrode60 and the margins of the alignment offset between thecontact portion41 and thecontact electrode60 can be increased by adjusting the line width of thering portion48 of thecontact portion41. Further, an increase of the contact resistance between theupper interconnect40 and thecontact electrode60 can be suppressed.
• In contrast, since thecontact electrode60 is in contact with thelower interconnect50 via the opening portion (space inside of the ring portion48)49, when the area of the openingportion49 is increased, the contact resistance between thecontact electrode60 and thelower interconnect50 can be reduced.
• Therefore, in the semiconductor device of the embodiment, the contact resistance between the interconnect and the contact electrode can be reduced by adjusting the area of the openingportion49 of thecontact portion41.
• Note that when the area of thecontact portion41 is set constant, an increase of the area (sizes X1, Y1) of the openingportion49 reduces the contact area between the upper surface of thering portion48 and the bottom surface of theupper electrode portion61. However, since the contact area Ace2 between a side surface of thering portion48 in the openingportion49 and a side surface of thelower electrode portion62 is increased, when the film thickness of the contact portion (interconnect) is increased, even if the openingportion49 is increased, the influence of reduction of the contact area between thecontact portion41 of theupper interconnect40 and thecontact electrode60 is reduced.
• The contact area S2 between thelower interconnect50 and the contact electrode60 (lower electrode portion62) can be adjusted (controlled) by the size of the openingportion49.
• That is, the magnitude of the contact area S1 and the magnitude of the contact area S2 can be made the same magnitude by adjusting the line width RW of the ring portion and the sizes X1, Y1 of the openingportion49.
• As a result, in the semiconductor device of the embodiment, since the magnitude of the contact resistance generated between theupper interconnect40 and thecontact electrode60 and the magnitude of the contact resistance generated between thelower interconnect50 and thecontact electrode60 can be made the same magnitude, a dispersion of the contact resistances generated at the interconnects can be reduced.
• As described above, according to the semiconductor device of the embodiment, the contact electrodes can be stably connected to the interconnects.
(2) Specific Example
• A specific example of the embodiment will be described usingFIGS. 11,12,13,14A,14B,14C,15A,15B,15C,16A,16B,17,18A,18B,19A, and19B by exemplifying a resistance change memory such as a ReRAM (Resistive RAM) and PCRAM (Phase Change RAM).
• Note that the detailed description of the components and the effects which are substantially the same as those described usingFIGS. 1 to 10 will not be repeated here.
(a) Structure
• A structure of the resistance change memory of the specific example of the embodiment will be described usingFIGS. 11,12, and13. Note that members in a front direction and a depth direction inFIGS. 11 and 13 are shown by broken lines.
• FIG. 11 is a view schematically showing sectional structures of a memorycell array region12 and aninterconnect region15 described in the specific example.FIG. 11 shows the sectional structure of the memorycell array region12 along the first direction.
• AlthoughFIG. 11 shows an example in which theinterconnect region15 is disposed at one end of the memorycell array region12 in the first direction, it is needless to say that theinterconnect region15 may be disposed at the other end of the memorycell array region12 in the first direction, or theinterconnect regions15 may be disposed at one end and the other end of the memorycell array region12 in the second direction in response to a layout of interconnects.
• As shown inFIG. 11, a cross point typememory cell array2 is disposed in the memorycell array region12. Accordingly, the memorycell array region12 includes stacked cell units CU1, CU2, CU3, CU4 and CU5. The cell units CU1, CU2, CU3, CU4 and CU5 are stacked on asubstrate11 across control lines L1, L2, L3, L4, L5 and L6, respectively. The cell units CU1, CU2, CU3, CU4 and CU5 and the control lines L1, L2, L3, L4, L5 and L6 are covered by aninterlayer insulation film80.
• Interconnects40A,40B,40C and50 andcontact electrodes60A,60B,60C are disposed in theinterconnect region15.
• Three interconnects50,51,52 are disposed on aninterlayer insulation film17 in theinterconnect region15. Theinterconnects50,51,52 extend in a direction (for example, the second direction) intersecting the first direction.
• In theinterconnect region15, theinterconnects40A,40B,40C are disposed above theinterconnects50,51,52. Theinterconnects40A,40B,40C extend in a direction where they intersect theinterconnects50,51,52.
• As shown inFIG. 11, theinterconnect40A is disposed at the same interconnect level as the control line L2 and electrically connected to the control line L2. Theinterconnect40B is disposed at the same interconnect level as the control line L4 and positioned above theinterconnect40A. Theinterconnect40B is electrically connected to the control line L4. Theinterconnect40C is formed at the same interconnect level as the control line L6 and positioned above theinterconnect40B. Theinterconnect40C is electrically connected to the control line L6.
• Note that althoughFIG. 11 shows theinterconnects40A,40B,40C at the same levels as the control lines L2, L4, L6, it is needless to say that interconnects at the same interconnect levels as the control lines L1, L3, L5 are disposed in theinterconnect region15.
• Theinterconnects40A,40B,40C have ring-like contact portions41A,41B,41C, respectively.
• Thecontact electrodes60A,60B,60C connect interconnects disposed at different interconnect levels via opening portions of the ring-like contact portions41A,41B,41C.
• Theinterconnect40A is connected to theinterconnect50 by thecontact electrode60A passing through the ring-like contact portion41A. Theinterconnect40B is connected to theinterconnect51 by thecontact electrode60B passing through the ring-like contact portion41B.
• For example, theinterconnect40C is connected to anintermediate layer70 at the same interconnect level as the control line L5 by thecontact electrode60A passing through the ring-like contact portions41C. The control line L5 is positioned at an interconnect level between the control line L4 and the control line L6. Further, the control line L5 and theintermediate layer70 are made of the same material.
• Theintermediate layer70 does not have a ring-like contact portion, and thecontact electrode60C does not pass through theintermediate layer70. Theintermediate layer70 is connected to theinterconnect52 by acontact electrode69. As a result, theupper interconnect40C is electrically connected to thelower interconnect52 by appropriately combining thecontact electrode60C passing through an opening portion in thecontact portion41C, theintermediate layer70, and theordinary contact electrode69.
• FIG. 12 shows a plan view of a region XII ofFIG. 11 when viewed from the third direction (upper side).FIG. 13 shows cross sections along an A-A′ line and a B-B′ line ofFIG. 12. To clarify a difference,FIG. 13 shows the cross sections along the A-A′ line and the B-B′ line side by side without showing the interlayer insulation film.
• As shown inFIGS. 12 and 13, theinterconnect50 and theinterconnect51 are disposed side by side in the first direction when viewed from the third direction at the same interconnect level (on the substrate11).
• Theinterconnect40A and theinterconnect40B are disposed side by side in planes, where thecontact portions41A,41B thereof are disposed, in the second direction when viewed from the third direction. Theinterconnect40A and theinterconnect40B are disposed at different interconnect levels, respectively. Note that theinterconnect40A and theinterconnect40B are drawn in theinterconnect region15 so that they are formed in a predetermined interconnect layout.
• Thecontact portion41A of theinterconnect40A is disposed at a position where it is not overlapped vertically on thecontact portion41B of theinterconnect40B. The ring-like contact portion41A is positioned above theinterconnect50, and the ring-like contact portion41B is positioned above theinterconnect51.
• The ring-like contact portion41A disposed at theinterconnect40A projects to theinterconnect40B side with respect to the surface of thesubstrate11 in a horizontal direction. The ring-like contact portion41B disposed to theinterconnect40B projects to theinterconnect40A side with respect to the surface of the substrate in the horizontal direction. The directions in which thecontact portions41A,41B project are opposite to each other. An increase of the area of theinterconnect region15 is suppressed by disposing thecontact portions41A,41B so that they alternately project in a different direction in the interconnects adjacent to each other in the horizontal direction in the planes with respect to the surface of thesubstrate11 when viewed from the third direction.
• Note thatFIGS. 11 to 13 show the example in which thecontact portions41A,41B at the different interconnect levels are disposed so as to alternately project. However, it is needless to say that the same effect can be also obtained even in a case in which two contact portions at the same interconnect level alternately project.
• As described usingFIGS. 8,9, and10, the resistance change memory shown inFIGS. 11,12, and13 includes theinterconnects40A,40B having thecontact portions41A,41B whose plane shape is formed in the ring-shape, and the margin of an alignment offset of thecontact electrodes60A,60B of theupper interconnects40A,40B and of thelower interconnects50,51 can be secured by controlling the line widths of thering portions48A,48B of thecontact portions41A,41B and the sizes of the openingportions49A,49B.
• Accordingly, since the resistance change memory of the specific example of the embodiment can secure a margin of an alignment offset without increasing the sizes of thecontact portions41A,41B in theinterconnect region15 and the sizes of thecontact electrodes60A,60B and theinterconnects40A,40B,50,51, an increase of the area occupied by theinterconnect region15 on the surface of the chip (substrate11) can be suppressed.
• The contact area between thecontact electrodes60A,60B and theupper interconnects40A,40B can be set within a certain predetermined range by setting the line widths of thering portions48A,48B of thecontact portions41A,41B to sizes that account for the alignment offset. Further, the contact area between thecontact electrodes60A,60B and thelower interconnects50,51 can be adjusted by controlling the sizes of the openingportions49A,49B of thecontact portions41A,41B.
• As a result, the contact resistances between therespective interconnects40A,40B,50,51 and thecontact electrodes60A,60B in the specific example of the embodiment of the resistance change memory can be reduced. Further, as described later, a dispersion of electric characteristics of theinterconnects40A,40B,50,51 can be suppressed, resulting from the reduction in a dispersion of the contact resistances between therespective interconnects40A,40B,50,51 and thecontact electrodes60A,60B. Accordingly, thecontact electrodes60A,60B can be electrically stably connected to therespective interconnects40A,40B,50,51.
• Note that, when the twocontact electrode60A,61, which are connected to theinterconnects40A,40B at the different interconnect levels, are formed by processes executed at the same time, the effect described above can be more prominently obtained.
• As described above, according to the resistance change memory of the specific example of the embodiment, occurrence of the alignment offset of the interconnects and the dispersion of the electric characteristics can be suppressed.
(b) Manufacturing Method
• An example of a manufacturing method of the resistance change memory as a specific example of the embodiment will be described as an example of the manufacturing method of the semiconductor device of the embodiment usingFIGS. 14A,14B,14C,15A,15B,15C,16A,16B,17,18A,18B,19A, and19B.
• FIG. 14A shows a plane structure of the memorycell array region12 in a process of the manufacturing method of the resistance change memory according to the specific example of the embodiment, andFIG. 14B shows a plane structure of theinterconnect region15.FIG. 14C shows a sectional structure along a D-D′ line ofFIG. 14A and a sectional structure along an E-E′ line ofFIG. 14B, respectively. Note that a cross section along the D-D′ line ofFIG. 14A corresponds to a cross section of the memorycell array region12 shown inFIG. 2 along the first direction.
• As shown inFIGS. 14A,14B, and14C, a conductive layer is deposited on the substrate (for example, the interlayer insulation film17)11 using, for example, CVD (Chemical Vapor Deposition) and sputtering. The conductive layer is made into a control line of a lowermost layer in the memorycell array region12 and an interconnect of a lowermost layer in theinterconnect region15.
• Layers for forming a rectifier device (non-ohmic device) and a memory device of a cell unit are sequentially deposited on the conductive layer using, for example, CVD (Chemical Vapor Deposition) or sputtering. A stacking order of the layers for configuring the cell unit differs according to a configuration of the rectifier device and the memory device shown inFIG. 4.
• When the cell unit has the configuration shown inFIG. 3B, the non-ohmic device is, for example, a PIN diode. In the case, three semiconductor layers are stacked on a lower electrode layer of the non-ohmic device formed on an interconnect layer. For example, a silicide layer is formed on an uppermost semiconductor layer (for example, a P-type semiconductor layer) as upper electrode layers of the PIN diode.
• A lower electrode layer, a resistance change film, and an upper electrode layer of the memory device are sequentially stacked on the silicide layer.
• Further, simultaneously with the deposition of the respective layers on the memorycell array region12, layers are deposited on thesubstrate11 in theinterconnect region15.
• The conductive layer and the layers on thesubstrate11 are processed using photolithography, side wall processing, and RIE (Reactive Ion Etching), and control lines L1 andstacked bodies100A extending in the second direction are formed. Thestacked bodies100A are formed on the control lines L1. The control lines L1 and thestacked bodies100A are disposed side by side in the first direction intersecting the second direction.
• Simultaneously with the processing of the memorycell array region12, theinterconnect region15 is processed. For example, layers having the same configuration as thestacked bodies100A are removed in theinterconnect region15, and theinterconnects50 having a predetermined layout and shape are formed at the same interconnect level as the control lines L1.
• Thereafter, theinterlayer insulation film81 is formed in thememory cell array2 and in theinterconnect region15 in thesubstrate11 by, for example, CVD or coating. With such configuration, theinterlayer insulation film81 is buried between the cell units adjacent to each other in the first direction. Theinterconnect50 above the substrate11 (interlayer insulation film17) is covered by theinterlayer insulation film81.
• After theinterlayer insulation film81 is subjected to a planar processing, aconductive layer59A is formed on theinterlayer insulation film81 using, for example, sputtering or CVD.
• The cell units may be formed by dividing thestacked bodies100A in the second direction using RIE, thereby forming the memory cell array of the lowermost layer. However, to simplify the manufacturing process, it is preferable to deposit a component of a second memory cell array M2 from the substrate side on aconductive layer59A and to simultaneously execute a processing (etching) in the second direction on a lowermost (first) memory cell array M1 and on a second memory cell array M2 without dividing thestacked bodies100A in the second direction at this stage.
• In the case, layers (stacked bodies)100B′, which constitute the second memory cell array M2 from the substrate side, are formed on theconductive layer59A. Then, the upperstacked bodies100B′ and thestacked bodies100A extending in the first direction are commonly processed in the second direction, respectively by a process described later. As a result, the manufacturing process of the resistance change memory having a cross point type memory cell array is simplified and a manufacturing cost of the resistance change memory is reduced as compared with a case in which each of the memory cell arrays of each layer (at each interconnect level) is processed in the first direction and the second direction.
• As shown inFIGS. 14A,14B, and14C, a mask material used for a processing in the second direction is deposited on thestacked bodies100B′ in the memorycell array region12 and on stackedbodies101 in theinterconnect region15. The mask material is processed in a predetermined layout and shape by photolithography and RIE, andcore members91 are formed on thestacked bodies100B′,101. The core members (mask material)91 are made of a material which can secure an etching select ratio on theconductive layer59A.
• Note that layers (transfer layers), which become substantial masks by being transferred with mask patterns, may be disposed between thecore members91 and thestacked bodies100B′.
• As shown inFIG. 14A, in the memorycell array region12, thecore members91 have a linear plane pattern extending in the first direction. Thelinear core members91 are disposed adjacent to each other in the second direction.
• The size (line width) W1 of thelinear core members91 in the second direction is set, for example, equal to or smaller than a limit of processing executed by photolithography. The adjacent pitch ptc1 of twocore members91 adjacent in the second direction is, for example, about four times the size of thestacked bodies100A in the first direction.
• InFIG. 14B,core members91′ in theinterconnect region15show core members91′ extending in the first direction. However, thecore members91′ in theinterconnect region15 are patterned to have a predetermined layout and shape in response to a layout of interconnects formed in a process, to be described later, different from a layout and shape of thecore members91′ in the memorycell array region12.
• Thecore members91′ in theinterconnect region15 may be members that continue from the memorycell array region12 to theinterconnect region15 or may be members that are separated from thecore members91 of the memorycell array region12.
• Thecore members91′ have projectingportions92 projecting in a direction (for example, the second direction) intersecting the direction in which thecore members91′ extend. The portions of thecore members91′ other than the projectingportions92 are also called main portions.
• The projectingportions92 are formed at the positions where they overlap, for example, thelower interconnect50 vertically. The projectingportions92 are formed at the positions where contact electrodes are connected to theinterconnect50. The sizes DX1, DX2 of the projectingportions92 in the first and second directions are appropriately set in response to the magnitude of contact portions disposed on the interconnects.
• The projectingportions92 disposed on therespective core members91′ are disposed so as to alternately project in twocore members91′ adjacent to each other.
• The size (line width) W2 of the portions (main portions) of thecore members91′ other than the projectingportions92 in the second direction is, for example, equal to or larger than the line width W1 of thecore members91 in the memorycell array region12.
• The adjacent pitch ptc2 of the main portions of twocore members91 is set larger than the adjacent pitch ptc1 of the twocore members91′ in the memorycell array region12 so that the projectingportion92 of acore member91′ is not in contact with another adjacent core member.
• FIG. 15A shows a plane structure of the memorycell array region12 in a process of the manufacturing method of the resistance change memory as the specific example of the embodiment, andFIG. 15B shows a plane structure of theinterconnect region15 in the process of the manufacturing method.FIG. 15C shows a sectional structure along an F-F′ line ofFIG. 15A and a sectional structure along a G-G′ line ofFIG. 15B.
• As shown inFIGS. 15A,15B, and15C, a sidewall masking material is deposited on theconductive layer59A in the memorycell array region12 and theinterconnect region15 so as to cover thecore members91,91′ using, for example, CVD or sputtering. The sidewall masking material is made of a material which can secure an etching selection ratio for thecore members91,91′ and theconductive layer59A.
• When anisotropic etching is executed on the sidewall masking material, the mask material remains on side surfaces of thecore members91,91′ and side wall masks93A,93A′ are formed in self-alignment so as to surround the peripheries of thecore members91,91′. Just after the side wall masks93A,93A′ are formed, they have a closed-loop like plane shape around the peripheries of thecore members91,91′. Looped portions of the side wall masks93A,93A′ are cut off at the ends of thecore members91,91′ in the extending direction thereof, and the side wall masks93A,93A′ are formed in independent patterns, respectively.
• As shown inFIG. 15A andFIG. 15C, the side wall masks93A are formed along side surfaces of thelinear core members91 in the memorycell array region12. In thememory cell array2, the side wall masks93A have a linear pattern and extend in the first direction.
• The size (line width) of the side wall masks93A in thememory cell array2 in the second direction is set, for example, smaller than a limit of processing executed by photolithography and is, for example, approximately the same as or smaller than the line width W1 of thecore members91. The adjacent pitch ptc3 of two side wall masks93A adjacent in the second direction is the sum of, for example, the line width W3 of the side wall masks93A and the line width of thecore members91.
• As shown inFIGS. 15B and 15C, in theinterconnect region15, the side wall masks93A′ are formed on side surfaces of thecore members91′. As described above, since thecore members91′ in theinterconnect region15 have the projectingportions92 projecting in the second direction, the shape of the side wall masks93′ in theinterconnect region15 is curved due to the shape of the projectingportions92. Hereinafter, in the side wall masks93A′ in theinterconnect region15,portions94A, which are curved in response to the shape of the projectingportions92, are particularly calledcurved portions94A. Thecurved portions94A have, for example, a concave (or U-like) plane shape.
• In side wall masks93A′ adjacent to each other in the second direction in theinterconnect region15, the pitch ptc4 of the portions other than thecurved portions94A is substantially the same as the sum of the line width W2 of thecore members91′ and the line width W4 of the side wall masks93A′.
• The size (line width) W4 of the side wall masks93A′ in theinterconnect region15 in the second direction is substantially the same as, for example, the line width W3 of the side wall masks93A in the memorycell array region12. The side wall masks93A′ of thecurved portions94A also have the line width W4.
• However, the line width W4 of the side wall masks93A′ may be different from the line width W3 of the side wall masks93A depending on the adjacent pitch ptc4 between thecore members91′. In other words, the size of the line width W4 of the side wall masks93A and thecurved portions94A can be controlled by adjusting the adjacent pitch ptc4.
• Thecurved portions94A of the side wall masks93A′ and the portions of the projectingportions92 adjacent to thecurved portions94A have an interval via which they are not in contact with each other. The interval is set by adjusting the interval between the projectingportions92 of thecore members91′ ofFIG. 14B and thecore members91′ adjacent to the projectingportions92 when the projectingportions92 are formed.
• FIG. 16A shows a plane structure of theinterconnect region15 in a process of the manufacturing method of the resistance change memory as the specific example of the embodiment.FIG. 16B shows a sectional structure along an H-H′ line ofFIG. 16A and a sectional structure along an I-I′ line ofFIG. 16A. Note that, in the process, since the structure of the memorycell array region12 is substantially the same as that in the manufacturing process shown inFIGS. 15A,15B, and15C, illustration of the structure will not be repeated here.
• In the process shown inFIGS. 16A and 16B, the core members in the memorycell array region12 and in theinterconnect region15 are selectively removed using, for example, wet etching, RIE, and the like. As a result, opening portions OP are formed which are surrounded by thecurved portions94A of the side wall masks93A′ as well as parts of which have segmented portions in which the side wall masks92,93A′ are segmented. Thereafter, in theinterconnect region15, resistmasks95A are formed on thestacked bodies101 using photolithography.
• The resist masks95A are formed to bridge one ends and the other ends of the side wall masks93A′ segmented in the segmented portions of the openings OP formed to thecurved portions94A in the first direction. The portions, which are surrounded by thecurved portions94A and the resistmasks95A, are made into cavities. The resist masks95A are formed so as not to be in contact with the portions of thecurved portions94A adjacent thereto in the second direction.
• As shown inFIGS. 16A and 16B, ring-like mask patterns99A are formed by the resistmasks95A and thecurved portions94A of the side wall masks93A′. Further, the opening OP, which are surrounded by the ring-like mask patterns99A, are made into cavities, and upper surfaces of thestacked bodies101 are exposed via the openings OP.
• The size X1 of the openings OP of the ring-like mask patterns99A in the first direction depends on an interval between the two portions of thecurved portions94A extending in the second direction. That is, the size X1 of the openings OP of themask patterns99A in the first direction is determined by the size of the projectingportions92 of thecore members91′ ofFIG. 14B in the first direction.
• The size Y2 of the openings OP of the ring-like mask patterns99A in the second direction depends on the magnitude of thecurved portions94A in the second direction, the positions where the resistmasks95A are formed to thecurved portions94A, and the magnitude (size) of the resistmasks95A.
• Note that, in the memorycell array region12, only the core members are removed and the resist masks are not formed.
• The conductive layer and the stacked bodies are processed using the side wall masks93A,93A′,94A and the resistmasks95A.
• FIG. 17 shows a sectional structure after the conductive layer and the stacked bodies are processed using the side wall masks and the resist masks.FIG. 17 shows sectional structures disposed side by side after the processing, the sectional structures corresponding to the F-F′ line ofFIG. 15A, a J-J′ line ofFIG. 15A, the H-H′ line ofFIG. 16A, and the I-I′ line ofFIG. 16A.
• In the memorycell array region12, stackedbodies100B and the control lines L2 which extend in the first direction are formed based on the linear side wall mask extending in the first direction.
• Further, the stacked bodies extending in the second direction on the control lines L1 are processed based on the side wall mask extending in the first direction and divided to the cell units CU1. However, in the process, the lower control lines L1 are not etched. The cell units CU1 are disposed at the locations where the lower control lines L1 intersect the upper control lines L2. When the memories operate, the control lines L1 or the control lines L2 are driven as the word lines, and the remaining control lines are driven as the bit lines.
• As described above, the memory cell array M1, in which the cell units CU1 are two-dimensionally disposed, is formed in the memorycell array region12.
• Simultaneously with the processing of the memorycell array region12, the conductive layer in theinterconnect region15 is processed by the side wall masks93A′ and the resistmasks95A shown inFIGS. 16A and 16B.
• With this operation, theinterconnect40A, which extends from the memorycell array region12 to theinterconnect region15, is formed based on a predetermined interconnect layout and shape. For example, the control lines L2 in the memorycell array region12 are not cut off from theinterconnect40A in theinterconnect region15 and are configured as continuous conductive wires.
• The ring-like contact portions41A are formed to theinterconnect40A in theinterconnect region15 by the ring-like mask patterns99A composed of the resistmasks95A and the side wall masks93A′ in thecurved portions94A. Theopening portion49A of thecontact portion41A is formed in thering portion48.
• The line width and the area of thering portion48A of thecontact portion41A are determined corresponding to the line widths of the side wall masks93A′ and the resistmasks95A. The magnitude of the openingportion49 of thecontact portion41A is determined corresponding to the sizes of the projectingportions92 of thecore members91′ in the first and second directions, the size of the resistmasks95A, and the positions where the resistmasks95A are formed to thecurved portions94A of the side wall masks93A′.
• In the process shown inFIGS. 14A,14B, and14C, when thecore members91′ are formed, the projecting portions disposed to thecore members91′ are alternately projected toward adjacent core members side in two core members adjacent to each other in the second direction. Accordingly, the ring-like contact portions41A, which are processed based on thecore members91′ and the side wall masks93A′, are disposed also alternately toward adjacent interconnects side in two interconnects. That is, a layout in theinterconnect region15 does not have a layout in which twocontact portions41A face each other.
• As described above, since the positions where the ring-like contact portions41A are formed are alternately offset to adjacent interconnects, even if the plane shape of thecontact portion41A is formed in the ring shape, an increase of the area occupied by the interconnect region, which is caused by the formation of thecontact portion41A, is suppressed.
• As shown inFIG. 17, the two memory cell arrays M1, M2 are processed in the second direction at the same time. Simultaneously with the processing, the interconnects in theinterconnect region15 are processed at the same time. Thereafter, the side wall masks and the resist masks are removed. Further, in theinterconnect region15, components of thestacked bodies100B remaining in theinterconnect region15 are removed. Note that the same components as thestacked bodies100B in theinterconnect region15 may not be removed and may remain in theinterconnect region15 as dummy layers.
• Thereafter, interlayer insulation films (not shown) are buried between the cell units CU1 adjacent to each other in the second direction and between thestacked bodies100B adjacent to each other in the second direction using, for example, coating and CVD. At the same time, interlayer insulation films are deposited also in theinterconnect region15.
• FIG. 18A shows a plane structure of theinterconnect region15 in a process of the manufacturing method of the resistance change memory as the specific example of the embodiment.FIG. 18B shows a sectional structure along an H-H′ line ofFIG. 18A and a sectional structure along a K-K′ line ofFIG. 18A. Further,FIG. 18B shows also a sectional structure of the memorycell array region12 along the second direction in the process shown inFIG. 18A.
• In the process shown inFIGS. 18A and 18B, a conductive layer and a component of the third memory cell array M3 from the substrate side are sequentially deposited on the components (stacked bodies) of the second memory cell array M2 by processes substantially the same as the processes shown inFIGS. 14A,14B,14C,15A,15B,15C,16A,16B, and17. The stacked bodies for configuring the memory cell array M2 andstacked bodies100C for configuring the memory cell array M3 are processed in the first direction at the same time. The control lines L3 extending in the second direction are formed simultaneously with the processing of the memory cell arrays M2, M3.
• Ring-like contact portions are formed to the interconnects in the interconnect region on the second direction side with respect to, for example, the control lines L3 by the same processes as those shown inFIGS. 14A to 17.
• After the cell unit CU2 that configures the second memory cell array M2 is formed, aninterlayer insulation film82 is deposited in the memorycell array region12 and in theinterconnect region15.
• In the memorycell array region12 and in theinterconnect region15, aconductive layer59B for forming control lines extending in the first direction is deposited on theinsulation film82. Further,components100D′ of the fourth memory cell array M4 from the substrate side are formed on theconductive layer59B.
• As shown inFIGS. 18A and 18B, linear side wall masks93B are formed in the memorycell array region12 and side wall masks93B′ havingcurved portions94B are formed in theinterconnect region15 on thecomponents100D′ by the same processes as those shown inFIGS. 14A,14B,14C,15A,15B,15C,16A, and16B. Further, resistmasks95B are formed on thestacked bodies100D′ across openings of thecurved portions94B. With such configuration, ring-like mask patterns99B are formed above theinterconnect51 and theconductive layer59B. For example, the ring-like mask patterns99B are formed at the positions where they are not overlapped vertically on the ring-like contact portions41A formed at interconnect levels below themask patterns99B (in the third direction).
• The portions surrounded by thecurved portions94B and the resistmasks95B are configured as cavities having certain sizes in the first and the second directions. The size of cavities of themask patterns99B for forming the contact portions of an upper interconnect may or may not have the same size as the openingportions49 of the ring-like contact portions41A of thelower interconnect40A.
• As shown inFIGS. 18A and 18B, the contact portion formed by the ring-like mask patterns99B is formed at an interconnect level above theinterconnect40A.
• As described above, the mask pattern is formed so that the ring-like contact portions have an alternate layout in planes in interconnects adjacent to each other in the second direction (or in the first direction) when viewed from the third direction as to also the contact portions disposed respectively to the interconnects at different interconnect levels. As a result, the area occupied by theinterconnect region15 in which the ring-like contact portions are disposed can be reduced.
• The stacked bodies for configuring the third memory cell array M3 and the fourth memory cell array are formed in the memorycell array region12 using the side wall masks and the resist masks, and the interconnects having the ring-like contact portions are formed in theinterconnect region15. Thereafter, in theinterconnect region15, the components of the cell units are removed, and interlayer insulation films are deposited in the memorycell array region12 and in theinterconnect region15.
• FIGS. 19A and 19B show a process of the manufacturing process of the resistance change memory as the specific example of the embodiment.FIGS. 19A and 19B show a sectional structure of the process of the manufacturing process for theinterconnect region15, and the sectional structure corresponds to cross sections along the H-H′ line and the K-K′ line ofFIG. 18A. Note that illustration of the manufacturing process for the memorycell array region12 will not be repeated here.
• As shown inFIG. 19A, after the ring-like contact portions41A,41B are formed at two different interconnect levels, contact holes CHA, CHB are formed to burycontact electrodes60A to theinterconnects40A,40B at different interconnect levels therein, respectively. The contact holes CHA, CHB are formed in theinterlayer insulation films81,82,83 by executing etching once. The contact holes CHA, CHB partially expose upper surfaces of the ring-like contact portions41A,41B disposed to theinterconnects40A,40B, respectively, as well as expose upper surfaces of theinterconnect50 and theinterconnect51 via the openingportions49A,49B of thecontact portions41A,41B. As shown inFIG. 19B, thecontact electrodes60A,60B are buried in the contact holes CHA, CHB at the same time.
• As described above, since the contact holes CHA, CHB are collectively processed (etched) to the interconnects at the interconnect levels, the number of processes for manufacturing the resistance change memory is reduced.
• In a conventional contact electrode forming process, when one contact electrode is formed to interconnects disposed below an interconnect level, thecontact electrode60A connected to lower and upper interconnects is aligned to any one interconnect of the interconnects at interconnect levels and cannot be directly aligned to the other interconnects. Accordingly, there is a possibility that the alignment of thecontact electrode60A to the interconnects which cannot be directly aligned to thecontact electrode60A is offset. This may cause a deterioration of a manufacturing yield of the resistance change memory. To prevent the deterioration of the manufacturing yield, it is necessary in a conventional resistance change memory to increase the size of the interconnects and the size of contact portions disposed to the interconnects or the size of contact holes to increase an alignment margin.
• Further, the contact areas between the contact electrode and the respective interconnects are dispersed by the alignment offset. In particular, in the interconnects which cannot be directly aligned to the contact electrode, since only a part of the contact electrode comes into contact with (hooked to) parts of the interconnects (contact portions), the interconnects are greatly affected by the alignment offset.
• As a result, there is a possibility that the contact resistances between the contact electrode and the respective interconnects are dispersed and thus the electric characteristics of the interconnects are dispersed.
• In the semiconductor device, for example, in the resistance change memory of the embodiment, thecontact portions41A,41B formed to theinterconnects40A,40B have the ring-like plane shape.
• An alignment between thecontact electrodes60A,60B and theinterconnects40A,40B having the ring-like contact portions41A,41B is determined by thering portions48A and48B of thecontact portions41A,41B.
• An alignment of thecontact electrodes60A,60B to the interconnects below theinterconnects40A,40B having the ring-like contact portions41B,41B is determined by the sizes X1, X1′ in the first direction and the sizes in the second direction of the opening portions (inside of the ring portions)49A,49B of the ring-like contact portions41A,41B.
• That is, the alignment between theupper interconnects40A,40B and thecontact electrodes60A,60B is set within the range of the areas of thering portions48A,48B, and an alignment between thelower interconnects50,51 and thecontact electrodes60A,60B is set within the range of the magnitudes of the openingportions49A,49B.
• Therefore, when thecontact portions41A,41B have the ring-like plane shape as in the resistance change memory as the specific example of the embodiment, it is sufficient to determine the alignment of thecontact electrodes60A,60B (the positions where the contact holes are formed) only in consideration of an alignment offset between thecontact portions41A,41B and the interconnects below thecontact portions41A,41B.
• Accordingly, when the ring-like contact portions41A,41B are formed to theinterconnects40A,40B as in the resistance change memory of the example, a restriction to an alignment for forming thecontact electrode60A,60B is relaxed in thecontact electrodes60A,60B which are commonly connected to theinterconnects40A,40B,50,51 across interconnect levels.
• Further, when the sizes and the areas of thering portions48A,48B of thecontact portions41A,41B are designed in consideration of an alignment offset between thecontact electrodes60A,60B and the contact portions, a dispersion of the contact areas A-xy, A′-xy between thecontact electrodes60A,60B and the ring-like contact portions41A,41B can be suppressed in therespective interconnects40A,40B having thecontact portions41A,41B.
• Further, since thecontact electrodes60A,60B are in contact with the upper surfaces of the ring-like contact portions41A,41B, even when thecontact electrodes60A,60B and thecontact portions41A,41B cause an alignment offset in any of the first direction and the second direction or in both the first and second directions, the dispersion of the contact areas A-xy, A′-xy between thecontact electrodes60A,60B and the ring-like contact portions41A,41B can be suppressed.
• As a comparative example, a case, in which the resistmasks95A are not formed and the ring-like contact portions are partially segmented inFIG. 16A, will be examined. In the comparative example, when thecontact electrodes60A,60B and thecontact portions41A,41B cause an alignment offset in the second direction, the contact areas between thecontact electrodes60A,60B and thecontact portions41A,41B are changed as compared with a case in which they do not cause the alignment offset. As a result, the contact resistances between thecontact electrodes60A,60B and theinterconnects40A,40B are changed.
• In contrast, since thecontact portions41,41B have the ring-like plane shape, even when thecontact electrodes60A,60B and thecontact portions41A,41B cause an alignment offset in any of the first and second directions or in both the first and second directions, the contact areas A-xy, A′-xy between thecontact electrodes60A,60B and the ring-like contact portions41A,41B remain constant. As a result, a change of the contact resistances between thecontact electrodes60A,60B and theinterconnects40A,40B can be prevented.
• A dispersion of the contact areas B-xy, B-xy′ between thecontact electrodes60A,60B and theinterconnects50,51 can be suppressed also for thelower interconnects50,51 similarly to theupper interconnects40A,40B by adjusting the sizes and the areas of the openingportions49A,49B of thecontact portions41A,41B.
• In addition to that mentioned above, the contact areas B-xy, B′-xy between thelower interconnects50,51 and thecontact electrodes60A,60B can be set by controlling the magnitudes of the opening portions (inside of thering portions48A,48B)49A,49B of thecontact portions41A,41B in consideration of the contact areas A-xy, A′-xy between theupper interconnects40A,40B and thecontact electrodes60A,60B.
• Therefore, a dispersion of the contact resistance of the interconnects due to a dispersion of the contact areas can be suppressed.
• Note that the sizes of thering portions48A,48B and the openingportions49A,49B of thecontact portions41A,41B can be controlled by the magnitude of the projecting portions of the core members which are formed by the processes shown inFIGS. 14A,14B,14C,15A,15B,15C,16A,16B,17,18A, and18B, the size of the side wall masks in theinterconnect region15, the size of the resist masks, and the positions where the resist masks are formed to the curved portions.
• Thereafter, substantially the same processes as those shown inFIGS. 14A toFIG. 18B are repeatedly executed until the number of the memory cell arrays and the interconnects in the memorycell array region12 reaches a predetermined stack number.
• Note that although the manufacturing process for theinterconnect region15 adjacent to the memorycell array region12 in the first direction has been described here, interconnects having ring-like contact portions and contact electrodes connected to the interconnects at respective interconnect levels can be formed in also an interconnect region adjacent to the memorycell array region12 in the second direction by substantially the same processes as those described usingFIGS. 14A to 18B except that control lines and the interconnects have different interconnect levels.
• Although the masks for forming the ring-like contact portions are formed by combining the side wall masks and the resist masks here, the masks for forming the ring-like contact portions may be formed of only the resist masks.
• The resistance change memory as the specific example of the embodiment as shown inFIGS. 8,9,10,11,12, and13 is completed by the processes described above.
• As described usingFIGS. 8 to 13, theinterconnects40A,40B in theinterconnect region15 include the ring-like contact portions41A,41B. Thecontact electrodes60A,60B are electrically connected to theupper interconnects40A,40B by coming into contact with thering portions48A,48B of thecontact portions41A,41B. Together with such configuration, thecontact electrodes60A,60B are electrically connected to thelower interconnects50,51 via the openingportions49A,49B of the ring-like contact portions41A,41B.
• With such configuration, in a semiconductor device such as the resistance change memory in which onecontact electrode60 is disposed across thestacked interconnects40A,40B,50,51, an alignment of thecontact electrodes60A,60B to thelower interconnects50,51 is determined by the sizes and the positions inside (the openingportions49A,49B) of thering portions48A,48B of thecontact portions41A,41B.
• Accordingly, a restriction of an alignment between therespective interconnects40A,40B,50,51 and thecontact electrodes60A,60B, for example, a restriction of an alignment between the interconnects and the contact electrodes from a process viewpoint of, for example, an aspect ratio between the interconnects, a change of the size of the interconnects due to a proximity effect, and the like is relaxed.
• Therefore, according to the embodiment, a margin can be secured for an alignment offset of the contact electrodes connected between the interconnects having different interconnect levels.
• The contact areas between theupper interconnects40A,40B having the ring-like contact portions41A,41B and thecontact electrodes60A,60B are determined by the magnitudes (line widths) of thering portions48A,48B of thecontact portions41A,41B. The contact areas between thelower interconnects50,51 and thecontact electrodes60A,60B are determined by the magnitudes of the openingportions49A,49B.
• Accordingly, since the contact areas between therespective interconnects40A,40B,50,51 and thecontact electrodes60A,60B can be made substantially the same by adjusting (controlling) the sizes of thering portions48A,48B in thecontact portions41A,41B and the sizes of the openingportions49A,49B, a dispersion of the contact resistances can be suppressed. Thus, according to the embodiment, a dispersion of the electric characteristics generated by the respective interconnects can be suppressed.
• When the line widths of thering portions48A,48B are increased, since the sizes Xce, Yce of theupper electrode portion61 can be increased, the contact area between theupper electrode portion61 of thecontact electrode60 and thecontact portion41 can be increased. As a result, the contact resistances between theupper interconnects40A,40B and thecontact electrodes60A,60B can be reduced.
• Further, the areas of the openingportions49A,49B are increased. The contact areas between thelower interconnects50,51 and thecontact electrodes60A,60B can be adjusted (controlled) by the sizes of theopening portion portions49A,49B. Therefore, since the contact areas between thelower interconnects50,51 and thecontact electrodes60A,60B can be increased by increasing the areas of theopening49A,49B, the contact resistances between thecontact electrodes60A,60B and the lower interconnect layers50,51 can be reduced.
• As described above, in the embodiment, the contact resistances between theinterconnects50,51 and thecontact electrodes60A,60B can be reduced by adjusting the areas of thering portions48A,48B and the openingportions49A and49B. Further, the magnitude of the contact areas between thelower interconnects50,51 and thecontact electrodes60A,60B can be the same as magnitude of the contact areas as those between theupper interconnects40A,40B and thecontact electrodes60A,60B by adjusting the line widths of thering portions48A,48B and the areas of the openingportions49A and49B. As a result, since the magnitudes of the contact resistances between theupper interconnects40A,40B and thecontact electrodes60A,60B can be made to be the same as those of the contact resistances between thelower interconnects50,51 and thecontact electrodes60A,60B, the dispersion of the contact resistances generated to the respective interconnects can be reduced.
• As described above, the manufacturing method of the semiconductor device (for example, the resistance change memory) according to the embodiment can manufacture the semiconductor device in which occurrence of the alignment offset of the interconnects and the dispersion of the electric characteristics of the interconnects are suppressed. As a result, the manufacturing method of the semiconductor device according to the embodiment can provide the semiconductor in which the contact electrodes can be stably connected to the interconnects.
(3) Modification
• A modification of the semiconductor device (for example, the resistance change memory) according to the embodiment will be described usingFIGS. 20,21A,21B,22A,22B, and23.
• As described usingFIGS. 16A and 18A, a mask pattern whose plane shape is formed in a ring-like mask pattern is formed by combining a curved portion of a side wall mask with a resist mask. A contact portion having a ring-like plane shape is formed to an interconnect by processing a conductive layer based on the ring-like mask pattern.
• When one mask pattern is formed by combining the side wall mask and the resist mask, the plane shape of the ring-like contact portion is changed in response to a position where the resist mask is formed to the curved portion of the side wall mask.
• FIG. 20 is a plan view showing a layout of thecurved portion94 of the side wall mask and the resistmask95. The size DX1 of the inside (anopening portion49X) of the portion of the side wall mask surrounded by thecurved portion94 in the x-direction is set by the size of a projecting portion (refer toFIG. 14B) of a core member for forming the side wall mask in the x-direction (first direction ofFIG. 14B), and the size DY1 of the inside (theopening portion49X) of the portion surrounded by thecurved portion94 in the y-direction is set by the size of the projecting portion of the core member in the y-direction (second direction ofFIG. 14B).
• To form the ring-like mask pattern, the resistmask95 is formed from an end to the other end of theside wall mask93 segmented by thecurved portion94 to bridge theopening portion49X formed by thecurved portion94 in the x-direction. Accordingly, the size DL1 of the resistmask95 in the x-direction is set equal to or larger than the size DX1 of theopening portion49X in the x-direction.
• However, to form the ring-like mask pattern, it is necessary to adjust the size DW1 of the resistmask95 in the y-direction and a position where the resistmask95 is formed on thecurved portion94 so that the resistmask95 does not entirely cover theopening portion49X.
• The plane shape of the ring-like contact portion is changed in response to the size DW1 of the resistmask95 in the y-direction and the position, where the resist mask is formed, to thecurved portion95.
• FIGS. 21A and 21B show plane structures of ring-like contact portions41V,41X disposed to interconnects in the modification of the semiconductor device (for example, the resistance change memory) of the embodiment, respectively.
• When, for example, the size DW1 of the resist mask is larger than the size (line width) MW of theside wall mask93 in the y-direction inFIG. 20, the ring-like contact portion41V includes a portion (first portion)48 curved from an interconnect and a portion (second portion)47B projecting (swelling) in an opposite direction of thecurved portion48 as shown inFIG. 21A.
• Even when the position where the resistmask95 ofFIG. 20 is formed is offset to a side opposite to the side to which the curved portion (ring portion) is curved on the side wall mask, a projectingportion47A is also formed to thecontact portion41V as shown inFIG. 21A.
• The line width (size in the y-direction) RWa of thesecond portion47A is thicker than, for example, the line width RW of thefirst portion48. Note that the line width RWa of thesecond portion47A is thicker than, for example, the line width of aninterconnect40. The line width RW of thering portion48 is equal or thicker than, for example, the line width of theinterconnect40. Further, the size dRW1 of the projecting portion in a direction (y-direction) intersecting in the extending direction (x-direction) of the interconnect depends on the projecting magnitude of the resistmask95 projecting from theinterconnect40 in the y-direction inFIG. 20. When, for example, the width of the interconnect40 (the line width MW of the side wall mask93) is thinner than the line width RW of thefirst portion48, an alignment margin is reduced when a position where a contact hole is formed is offset to a side opposite to the side to which the mask is curved. To cope with the problem, the alignment margin can be increased when the position where the contact hole is formed is offset to the side opposite to the side to which the mask is curved by making the size DW1 of the resistmask95 thicker than the line width MW of theside wall mask93. As a result, a contact electrode can be stably connected to the interconnects.
• The size dLA1 of the projecting portion in an interconnect extending direction (x-direction) depends on the size DL1 of the resistmask95 ofFIG. 20 in the x-direction. The size of the projecting portion (second portion)47A in the x-direction is larger than the size of the inside (opening portion49) of thering portion48 in the x-direction. However, the size dLA1 of the projecting portion in the interconnect extending direction (x-direction) may be smaller or larger than the size RWx of the outside of thering portion48 in the x-direction.
• In contrast, when the size DW1 of the resistmask95 ofFIG. 20 in the y-direction is smaller than the size (line width of a formed interconnect) MW of theside wall mask93 in the y-direction or when the position, where the resistmask95 ofFIG. 20 is formed, is offset to a side to which the curved portion (ring portion)94 projects, thecontact portion41X has a shape in which a portion thereof facing the curved portion of thering portion48 is recessed to the side to which thering portion48 is curved. Further, the size dRW2 of the recess in a direction (y-direction) intersecting in the interconnect extending direction depends on the magnitude of the resistmask95 recessed from the interconnect40 (side wall mask) inFIG. 20 in the y-direction.
• Although the example described above shows a structure in which the ring portion and the opening portion of the contact portion disposed to the interconnect have a square plane shape, the plane shape of the contact portion may be deformed in response to a shape of the mask (core member) and an etching condition.
• FIGS. 22A and 22B show plane structures of the ring-like contact portions41Y,41Z disposed to the interconnects in the modification of the semiconductor device (for example, the resistance change memory) of the embodiment, respectively.
• As shown in, for example,FIG. 22A, the plane shape of aring portion48Y of acontact portion41Y may have a pattern including a curved line such as an oval shape and a circular shape. In the case, the plane shape of anopening portion49Y may also have the oval shape and the circular shape.
• Further, as shown inFIG. 22B, the plane shape of aring portion48Z of acontact portion41Z may have a square shape with no corners, and thering portion48Z may have a polygonal plane shape. Likewise, anopening portion49Z may also have a polygonal shape without corners. Further, thering portion48Z and theopening portion49Z may have a square shape without corners.
• FIG. 23 shows sectional structures of ring-like contact portions71X,71Y and a contact electrode60Z disposed to interconnects40X,40Y in the modification of the semiconductor device (for example, the resistance change memory) of the embodiment.
• In the example described above, a case, in which one contact electrode is formed across two stacked interconnects via a ring-like contact portion disposed to the interconnects, will be exemplified. However, as shown inFIG. 23, the contact electrode60Z may be formed across at least threeinterconnects40X,40Y,40Z via the ring-like contact portions71X,71Y.
• Also in the case, the contact areas between therespective interconnects40X,40Y,40Z and the contact electrode60Z can be made substantially the same by adjusting (controlling) the size D1 of contact holes formed to interlayer insulation films (not shown), the sizes RW1, RW2 ofring portions78X,78Y of contact portions70X,70Y, and the sizes D2, D3 of openingportions79X,79Y of the contact portions70X,70Y.
• As shown inFIG. 23, when the one contact electrode60Z passes through the openingportions79X,79Y of thecontact portions71X,71Y, the size D2 of theopening portion79X of thecontact portion71X positioned to an upper layer is larger than the size D3 of theopening portion79Y of thecontact portion71Y of a lower layer.
• Note that thecontact portion71Y between thecontact portion71X connected to theinterconnect40X and the interconnect40Z on asubstrate11 may be an intermediate layer which is not connected to any interconnect.
• Further, as shown inFIG. 23,respective portions61,62,63 of the contact electrode60Z may have a taper (trapezoidal) sectional shape with an upper surface side size larger than a bottom surface side size according to the intervals H1, H2, H3 of the stackedinterconnects40X,40Y,40Z. The intervals H1, H2, H3 correspond to, for example, the film thickness of the interlayer insulation films (not shown) interposed between the interconnects.
• The same effect as those of the basic example and the applied example described above can also be obtained even in the modification of the semiconductor device of the embodiment (for example, the resistance change memory) shown inFIGS. 21A,21B,22A,22B, and23.
• Note that all the contact portions of the semiconductor device (for example, the resistance change memory) need not have the same plane shape as long as the plane shape of the contact portions have the ring-like plane shape, and the plane shape of the contact portions may be a square shape in certain interconnects and may be an oval shape in the other interconnects.
• As described above, the contact electrodes can be stably connected to the interconnects also in the modification of the semiconductor device of the embodiment.
[Other]
• The semiconductor device according to the embodiment can be applied to resistance change memories such as ReRAM and PCRAM.
• Although the resistance change memory having the cross point type memory cell array has been described in the embodiment, the embodiment is not limited thereto. The ring-like contact portions described in the embodiment can be applied to, for example, interconnects of a flash memory (BiCS memory) formed by, for example, a BiCS (Bit Cost Scalable) technology. Further, it is needless to say that the embodiment can be applied to a semiconductor integrated circuit such as a logic circuit in addition to the memories described above.
• While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (20)

1. A semiconductor device comprising:

a substrate; and

an interconnect region on the substrate, the interconnect region including a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the first contact portion and electrically connecting the first interconnect and the second interconnect.

2. The semiconductor device according toclaim 1, wherein

the interconnect region further includes a third interconnect having a second contact portion whose plane shape is a ring-like plane shape, and is disposed at a position adjacent to the first interconnect in a plane,

the first contact portion projects to the third interconnect side with respect to the surface of the substrate in a horizontal direction, and

the second contact portion projects to the first interconnect side with respect to the surface of the substrate in the horizontal direction.

3. The semiconductor device according toclaim 2, wherein the first contact portion and the second contact portion project in an alternate direction.

4. The semiconductor device according toclaim 1, wherein

the interconnect region further includes a fourth interconnect having a third contact electrode whose plane shape is a ring-like plane shape, and is disposed at an interconnect level different from the first interconnect, and

the third contact portion is disposed at a position which does not overlap the first contact portion in a vertical direction with respect to the surface of the substrate.

5. The semiconductor device according toclaim 1, wherein the first contact portion includes:

a first portion projecting from the first interconnect in a direction intersecting the extending direction of the first interconnect; and

a second portion projecting to a side opposite to the side to which the first portion projects.

6. The semiconductor device according toclaim 5, wherein the line width of the second portion is wider than the line width of the first portion.

7. The semiconductor device according toclaim 1, wherein the contact electrode includes:

a first electrode portion on the upper surface of the first contact portion; and

a second electrode portion passing through a ring-like portion of the first contact portion and in contact with the second interconnect, and

the size of the first electrode portion in the horizontal direction with respect to the surface of the substrate is larger than the size of the second electrode in the horizontal direction with respect to the surface of the substrate.

8. The semiconductor device according toclaim 7, wherein the second electrode portion is in contact with a side surface of an opening portion of the contact portion and with the upper surface of the second interconnect.

9. The semiconductor device according toclaim 1, further comprising:

a cross point type memory cell on the substrate adjacent to the interconnect region, the cross point type memory cell including a first control line extending in a first direction, a second control line extending in a second direction intersecting the first direction, and a cell unit disposed at a position where the first control line intersects the second control line and including a memory device for storing data in response to a reversible change of a resistance state.

10. The semiconductor device according toclaim 9, wherein the first control line is disposed at the same interconnect level as the first interconnect.

11. The semiconductor device according toclaim 9, wherein the first interconnect is connected to the first control line.

12. A semiconductor device comprising:

a substrate;

an interconnect region on the substrate, the interconnect region including a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the contact portion and electrically connecting the first interconnect and the second interconnect; and

a memory array region on the substrate adjacent to the interconnect region, the memory array region including a first control line extending in a first direction, a second control line extending in a second direction intersecting the first direction, a third control line extending in the first direction and disposed at an interconnect level different from the first control line, and cell units having a memory device connected to the first and second control lines and connected to the second and third control lines, respectively.

13. The semiconductor device according toclaim 12, wherein the interconnect region further includes a third interconnect having a second contact portion whose plane shape is a ring-like plane shape and disposed at the same interconnect level as the third control line, and

the second contact portion is disposed at a position which does not overlap the first contact portion in a vertical direction with respect to the surface of the substrate.

14. The semiconductor device according toclaim 12, wherein the interconnect region further includes a forth interconnect having a third contact portion whose plane shape is a ring-like plane shape and disposed at a position adjacent to the first interconnect in a plane,

the first contact portion projects to the fourth interconnect side in a horizontal direction with respect to the surface of the substrate, and

the third contact portion projects to the first interconnect side in the horizontal direction with respect to the surface of the substrate.

15. The semiconductor device according toclaim 14, wherein the first contact portion and the second contact portion project in an alternate direction.

16. The semiconductor device according toclaim 12, wherein the first contact portion includes:

a first portion projecting from the first interconnect in a direction intersecting the extending direction of the first interconnect; and

a second portion projecting to a side opposite to the side to which the first portion projects.

17. The semiconductor device according toclaim 16, wherein the line width of the second portion is wider than the line width of the first portion.

18. The semiconductor device according toclaim 12, wherein the contact electrode includes:

a first electrode portion on the upper surface of the first contact portion; and

a second electrode portion passing through the ring-like portion of the first contact portion and in contact with the second interconnect, and

the size of the first electrode portion in the horizontal direction with respect to the surface of the substrate is larger than the size of the second electrode portion on the surface of the substrate.

19. The semiconductor device according toclaim 12, wherein the first control line is disposed at the same interconnect level as the first interconnect, and the second control line is disposed at the same interconnect level as the second interconnect.

20. The semiconductor device according toclaim 12, wherein the first interconnect is connected to the first control line, and the second interconnect is connected to the second control line.

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