US20110227082A1 - Semiconductor device - Google Patents

Abstract

An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time τ₁until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• One of embodiments of the present invention relates to a semiconductor element such as a transistor and/or a semiconductor device at least part of which is formed using the semiconductor element. For example, an active element including an oxide semiconductor is described as the semiconductor element, and a display device including the active element is described.
• 2. Description of the Related Art
• Although transistors including amorphous silicon have been used for conventional display devices typified by liquid crystal televisions, an oxide semiconductor has attracted attention as a material which replaces a silicon semiconductor in order to form transistors. For example, an active matrix display device is disclosed, in which an amorphous oxide containing In, Ga, and Zn is used for an active layer of a transistor and the electron carrier concentration of the amorphous oxide is less than 10¹⁸/cm³(see Patent Document 1).
• However, some problems of a transistor including an oxide semiconductor have been pointed out. One of the problems is the stability of the characteristics, and it is pointed out that the electric characteristics of the transistor are changed by irradiation with visible light and ultraviolet light.
REFERENCEPatent Document
• [Patent Document 1] Japanese Published Patent Application No. 2006-165528
SUMMARY OF THE INVENTION
• An oxide semiconductor formed of a metal oxide has a band gap of about 3 eV and originally has a light-transmitting, property with respect to visible light. However, it is known that a film comprising the oxide semiconductor deteriorates when being irradiated with strong light (the deterioration is called light deterioration).
• Any method for improving such a change in the characteristics caused by light in a transistor including an oxide semiconductor has not been proposed, which causes a delay in practical use of the oxide semiconductor which is expected as a new material.
• In addition, a backlight is used in a liquid crystal display device; when a transistor including an oxide semiconductor is irradiated with light from the backlight, for example, leakage current might be generated in an off state of the transistor owing to photoexcitation, which leads to reduction in display quality, or light deterioration might be caused. Further, it is known that a single-layer oxide semiconductor film formed of a metal oxide has a photoelectric current value of about 10 μA.
• It is an object of an embodiment of the present invention to provide a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable.
• The mechanism of photoelectric current will be described below.
• Carriers in a semiconductor can be described by continuity equations, Formula 1 and Formula 2.
• $\begin{array}{cc}\frac{n}{t}=\frac{1}{q}\frac{\partial J_n}{\partial x}+\left(G_n-R_n\right)& \left[\mathrm{Formula}1\right]\\ \frac{p}{t}=-\frac{1}{q}\frac{\partial J_p}{\partial x}+\left(G_p-R_p\right)& \left[\mathrm{Formula}2\right]\end{array}$
• Note that in the above two equations, t represents time, x represents a position, and q represents a charge. Here, n and p represent carrier density of electrons and carrier density of holes, J_nand J_prepresent a current value of electrons and a current value of holes, G_nand G_prepresent a generation probability of electrons and a generation probability of holes, and R_nand R_prepresent a recombination probability of electrons and a recombination probability of holes. The number of hole carriers is divided into the number of hole carriers p₀in a thermal equilibrium state and the number of hole carriers Δp in a non-thermal equilibrium state. The carrier density of holes can be expressed by Formula 3.
• 
  p=p₀+ΔP  [Formula 3]
• When the semiconductor is irradiated with light having an energy of greater than or equal to the band gap, electrons in the valence band are transferred to the conduction band while the semiconductor absorbs the light, whereby holes are generated. When the generation probability of holes is represented by G_0p, the recombination probability is expressed by Formula 4. Here, τ_prepresents relaxation time of holes.
• $\begin{array}{cc}R=\frac{p}{{\tau }_p}=\frac{{\mathrm{<figure-callout\; label="p"\; filenames="US20110227082A1-20110922-D00001.png,US20110227082A1-20110922-D00002.png"\; state="\{\{state\}\}">p</figure-callout>}}_0}{{\tau }_p}+\frac{\Delta p}{{\tau }_p}& \left[\mathrm{Formula}4\right]\end{array}$
• When a device is uniformly irradiated with light, a continuity equation represented by Formula 5 is obtained if a diffusion term in a source direction or a drain direction can be ignored.
• $\begin{array}{cc}\frac{\left(\Delta p\right)}{t}=G_{\mathrm{op}}-R=G_{\mathrm{op}}-\frac{\Delta p}{{\tau }_p}& \left[\mathrm{Formula}5\right]\end{array}$
• Formula 5 is solved with an initial photoelectric current value at 0, which leads to a carrier concentration expressed by Formula 6.
• $\begin{array}{cc}\Delta p\left(t\right)=G_{\mathrm{op}}{\tau }_p\left[1-\exp \left(-\frac{t}{{\tau }_p}\right)\right]& \left[\mathrm{Formula}6\right]\end{array}$
• When the time at which a light source is turned off is represented by t₀, the carrier concentration is expressed by Formula 7.
• $\begin{array}{cc}\Delta p\left(t\right)=\Delta p\left(t_0\right)\exp \left(-\frac{t-{\mathrm{<figure-callout\; label="t"\; filenames="US20110227082A1-20110922-D00001.png,US20110227082A1-20110922-D00002.png"\; state="\{\{state\}\}">t</figure-callout>}}_0}{{\tau }_p}\right)\left(t\ge t_0\right)& \left[\mathrm{Formula}7\right]\end{array}$
• Since the photoelectric current is in proportion to the excess carrier concentration, the current formula is expressed by Formula 8.
• $\begin{array}{cc}I\left(t\right)=\{\begin{array}{cc}{I}_0\left[1-\exp \left(-\frac{t}{{\tau }_p}\right)\right]& \left(0\le t\le t_0\right)\\ I_0\left[1-\exp \left(-\frac{{\mathrm{<figure-callout\; label="t"\; filenames="US20110227082A1-20110922-D00001.png,US20110227082A1-20110922-D00002.png"\; state="\{\{state\}\}">t</figure-callout>}}_0}{{\tau }_p}\right)\right]\exp \left(-\frac{t-{\mathrm{<figure-callout\; label="t"\; filenames="US20110227082A1-20110922-D00001.png,US20110227082A1-20110922-D00002.png"\; state="\{\{state\}\}">t</figure-callout>}}_0}{{\tau }_p}\right)& \left(t\ge t_0\right)\end{array}& \left[\mathrm{Formula}8\right]\end{array}$
• (I_odepends on constant, physical property, and structure.)
• The relaxation time τ depends on a model of carrier recombination. There are many types of recombination processes. Basically, two types of processes, direct recombination and indirect recombination (SRH recombination), can be given.
• Further, for example, some traps can capture a hole but cannot easily capture an electron, where recombination hardly occurs. Such a trap is called a “safe” trap in this specification.
• FIG. 6A is a schematic diagram of the “safe” trap.FIG. 6B is a schematic diagram showing a transition due to heat after trapping.
• Since the position of the “safe” trap is closer to the valence band than the intrinsic Fermi level and an electron is not easily captured by the “safe” trap, part of holes captured by the “safe” traps are transferred to the valence band by heat and thus contribute to electric conduction. A semiconductor in which the “safe” traps exist exhibits two kinds of modes in photoresponse.
• According to an embodiment of the present invention disclosed in this specification, an oxide semiconductor layer which exhibits two kinds of modes in photoresponse is used, whereby a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable is achieved. Note that the oxide semiconductor layer which exhibits two kinds of modes in photoresponse has a photoelectric current value of greater than or equal to 1 pA, preferably greater than or equal to 10 pA and less than or equal to 10 nA. In addition, in the oxide semiconductor layer, a photoelectric current value after 100 seconds of light irradiation is greater than or equal to 400 aA/μm and less than or equal to 0.1 pA/μm at 25° C. and light deterioration can be suppressed to the minimum.
• When the average time τ₁until which carriers are captured by “safe” traps is large enough, there are two kinds of modes in photoresponse, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.
• In consideration of the “safe” trap, the current formula after τ₁(when almost all excess carriers are captured by the “safe” traps) is expressed by Formula 9. Note that τ₂represents average time during which carriers stay at the “safe” traps.
• $\begin{array}{cc}I\left(t\right)=A{\tau }_p\left(\frac{D_e}{D_h}·\frac{{\mathrm{<figure-callout\; label="\tau "\; filenames="US20110227082A1-20110922-D00003.png,US20110227082A1-20110922-D00004.png"\; state="\{\{state\}\}">\tau </figure-callout>}}_2}{{\tau }_1}\right)\exp \left(-\frac{t}{{\tau }_2}\right)\left(t\ge {\tau }_1\right)& \left[\mathrm{Formula}9\right]\end{array}$
• A: constant depending on physical property or temperature
  D_e,D_h: diffusion coefficient of electron and diffusion coefficient of hole
  τ_p: relaxation time of hole in thermal equilibrium
• Estimation of trap levels corresponding to τ₁and τ₂leads to evaluation of defects. Such a method for evaluation with the use of τ₁and τ₂is referred to as a photoresponse defect evaluation method (PDEM).
• A liquid crystal display device in which a transistor including an oxide semiconductor is provided in a pixel has high reliability with respect to light deterioration.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a graph showing photoresponse characteristics of oxide semiconductor layers.
• FIG. 2 is a graph enlarging a region in the range of 0 sec to 100 sec inFIG. 1.
• FIG. 3 is a graph showing photoresponse characteristics of oxide semiconductor layers with the use of a logarithmic scale.
• FIG. 4 is a graph showing photoresponse characteristics of oxide semiconductor layers with the use of a linear scale.
• FIG. 5 is a graph for showing a method for estimating τ₁with the use of data inFIG. 2.
• FIGS. 6A and 6B are schematic diagrams of a “safe” trap.
• FIG. 7A is a top view of an electrode andFIG. 7B is a cross-sectional view illustrating the structure of a TEG.
• FIGS. 8A to 8D are cross-sectional views each illustrating the structure of a transistor.
• FIG. 9 is a graph showing the emission spectrum of a white LED.
DETAILED DESCRIPTION OF THE INVENTION
• Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details thereof can be modified in various ways. Therefore, the present invention is not construed as being limited to the description of the embodiments.
Embodiment 1
• In this embodiment, a TEG was manufactured with the use of an oxide semiconductor. With the use of the TEG, the photoresponse characteristics of the oxide semiconductor before and after irradiation with light (luminance: 17000 cd/cm²) for 600 seconds were measured. By using the result thereof, a graph of the photoresponse characteristics (a graph showing time dependence of photoelectric current) is made.
• The structure of the TEG used for evaluation is as follows: the channel length (L) is 200 μm, the channel width (W) is 2.09 cm, the thickness of a thick portion of an In—Ga—Zn—O film is 50 nm, and the thickness of a thin portion of the In—Ga—Zn—O film is 25 nm. The cross-sectional structure of this TEG is illustrated inFIG. 7B. InFIG. 7B, an In—Ga—Zn—O film102 is formed over a glass substrate101, and a first electrode103 and asecond electrode104 are formed over the In—Ga—Zn—O film102.FIG. 7A illustrates the top shapes of the first electrode103 and thesecond electrode104. The space between the first electrode103 and thesecond electrode104 is 200 μm, and a region of the In—Ga—Zn—O film102 which overlaps with the region between the first electrode103 and thesecond electrode104 is 25 nm, which is thinner than a region overlapping with the first electrode103 or thesecond electrode104 as illustrated in FIG.7B. In addition, an insulating layer105 is formed over the first electrode103 and thesecond electrode104 so as to prevent the In—Ga—Zn—O film102 from being exposed.
• A white LED (MDBL-CW100 produced by Moritex Corporation) was used as a light source for emitting light with which the In—Ga—Zn—O film102 was irradiated. The emission spectrum of this white LED is shown inFIG. 9.
• In order to observe the temperature characteristics, three samples were manufactured and the temperature characteristics were measured at 25° C., 85° C., and 150° C. by using the three samples. The manufacturing process of the three samples will be described below.
• An In—Ga—Zn—O film is formed to a thickness of 50 nm by a sputtering method with the use of an oxide target having a composition ratio of In₂O₃:Ga₂O₃:ZnO=1:1:1 [molar ratio] over a glass substrate (126.6 mm×126.6 mm). The film formation conditions of the In—Ga—Zn—O film are as follows: the film formation temperature is room temperature, the flow of argon is 10 sccm, the flow of oxygen is 5 sccm, the pressure is 0.4 Pa, and the power is 500 W.
• Then, heat treatment is performed at 450° C. for 1 hour in a nitrogen atmosphere. This heat treatment is preferably performed in an atmosphere of nitrogen or a rare gas such as helium, neon, or argon in which water, hydrogen, or the like is not contained, for example, the dew point is lower than or equal to −40° C., preferably lower than or equal to −60° C. It is preferable that the purity of nitrogen or a rare gas such as helium, neon, or argon which is introduced into a heat treatment apparatus be set to be greater than or equal to 6N (99.9999%), preferably greater than or equal to 7N (99.99999%) (that is, the impurity concentration is less than or equal to 1 ppm, preferably less than or equal to 0.1 ppm).
• After the heat treatment, a layered conductive film is formed by stacking a titanium nitride film with a thickness of 50 nm, a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 200 nm, and a titanium film with a thickness of 50 nm by a sputtering method.
• A resist mask is formed over the layered conductive film through a photolithography step, and etching is performed selectively to form the first electrode103 and thesecond electrode104. After that, O₂ashing is performed, whereby a part of the In—Ga—Zn—O film which is exposed is thinned to 25 nm, and then, the resist mask is removed.
• Next, by a sputtering method with the use of a silicon oxide target, a silicon oxide film with a thickness of 300 nm is formed over the first electrode103 and thesecond electrode104.
• Then, a resist mask is formed over the silicon oxide film through a photolithography step, and etching is performed selectively to form the insulating layer105. After that, heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.
• Finally, the glass substrate is divided into a plurality of pieces such that one TEG is placed in each piece having an area of 10 mm×10 mm. After irradiation with white light having a luminance of 17000 cd/cm²for 600 seconds, measurement was performed by setting the time right after the light source is turned off to 0.FIG. 1 is a graph showing the photoresponse characteristics of oxide semiconductor layers. InFIG. 1, the horizontal axis indicates time and the vertical axis indicates a current value. The light source is turned off attime 0.FIG. 2 is a graph enlarging a region in the range of 0 sec to 100 sec inFIG. 1.
• Table 1 is a list showing numerical values inFIG. 1. A photoelectric current value per micrometer shown in Table 1 was obtained by calculation. The photoelectric current value per micrometer after 100 seconds of irradiation of the oxide semiconductor layer with light at 25° C. was found to be 593 pA/μm.

• TABLE 1
  						Ioff per
  Measurement	0sec	10sec	100sec	500sec	1000 sec	micrometer after
  Temperature	(A)	(A)	(A)	(A)	(A)	100 sec (A)

  25° C.	3.27E−10	3.33E−11	1.19E−11	6.31E−12	5.51E−12	5.93E−14
  85° C.	4.14E−10	7.84E−11	4.4E−11	2.56E−11	2.123E−11	2.202E−13
  150° C.	7.86E−10	1.95E−10	8.84E−11	3.61E−11	2.027E−11	4.422E−13

• Other TEGs were manufactured under conditions partly different from those of the above three samples. The film formation conditions of the In—Ga—Zn—O film of a fourth sample and a fifth sample are as follows: the film formation temperature is room temperature, the flow of argon is 10.5 sccm, the flow of oxygen is 4.5 sccm, and the power is 100 W. Note that other film formation conditions and the film thickness are the same as the above three samples.
• The fourth sample was subjected to heat treatment at 650° C. for 1 hour in a nitrogen atmosphere. The fifth sample was subjected to heat treatment at 650° C. for 1 hour in a nitrogen atmosphere and then heat treatment at 450° C. for 1 hour in an atmosphere containing oxygen and nitrogen.
• The steps after the heat treatment are performed in the same manner as the above three samples, so that the TEGs were manufactured.
• After irradiation with white light having a luminance of 17000 cd/cm²for 600 seconds, the photoresponse characteristics after the light source was turned off were measured. The result of measuring the photoresponse characteristics of the fourth sample is expressed by “OS film1”, and the result of measuring the photoresponse characteristics of the fifth sample is expressed by “OS film2”, which are shown inFIG. 3 with the use of a logarithmic scale. In addition, after irradiation with white light having a luminance of 17000 cd/cm²for 600 seconds, the light source was turned off and time right after the light source was turned off was set to 0. The result of measuring the photoresponse characteristics under this condition is shown inFIG. 4 with the use of a linear scale. According toFIG. 3 andFIG. 4, a single-layer oxide semiconductor film (OS film1) formed using a metal oxide which was used as a comparative example has a photoelectric current value of about greater than or equal to 1 μA and less than or equal to 10 μA. On the other hand, a single-layer oxide semiconductor film (OS film2) of this embodiment has a photoelectric current value of about greater than or equal to 10 pA and less than or equal to 10 nA. In the case of the single-layer oxide semiconductor film (OS film2) of this embodiment, the rise and the fall of the photoresponse characteristics are sharp, and the current value is very small. Also in the case of using light having a wavelength of 350 nm, which is considered to have an energy that is greater than or equal to the band gap, a tendency similar to the above is observed.
• Fitting of τ₂can be performed using the current formula expressed by Formula 9. A region in the range of 20 sec to 100 sec inFIG. 2 which is a graph using a logarithmic scale was plotted with the use of a linear scale, and fitting was performed.FIG. 5 shows a method for estimating τ₁.
• Since the temporal resolution is 1 [sec], sharpness around time 0 [sec] right after the light source is turned off cannot be correctly measured, and τ₁might be estimated to be larger than the real value. Table 2 shows τ₁and τ₂at following temperatures.

• 	25° C.	85° C.	150° C.

  	τ1[sec]	2.3	1.6	1.5
  	τ2[sec]	350	480	340

• Since τ₁can be regarded as substantially the same at all temperatures in consideration of the temporal resolution for measurement, τ₂does not depend on the temperature, either. This is because τ₁and τ₂depend on the trap density. On the other hand, according toFIG. 2, as the temperature is higher, the rate of reduction in current is small. This is because the probability of thermal excitation from the traps is higher as the temperature is higher.
• The curve showing the photoresponse characteristics has two kinds of modes because “safe” traps exist around the conduction band or the valence band. When fitting is performed to obtain the rapid relaxation time τ₁and the gradual relaxation time τ₂, it is found that these two kinds of relaxation time (τ₁and τ₂) less depend on the temperature but depend on the trap density, and it can be said from the temperature dependence of reduction in current that the traps exist at very shallow levels.
• The channel length was varied, and the measurement was performed under the conditions shown in Table 1. The structures of the TEGs used for evaluation are as follows: the channel length (L) was set to 50 μm, 100 μm, and 200 μm in respective TEGs, and the channel width (W) was set to 2.09 cm. The measurement results are shown in Table 3. Note that the measurement temperature is 25° C. A photoelectric current value per micrometer was obtained by calculation and shown in Table 3. In the TEG in which the channel length (L) is 50 μm, after 100 seconds of irradiation of the oxide semiconductor layer with light, a photoelectric current value per micrometer of channel length is 97.7 fA/μm. In the TEG in which the channel length (L) is 100 μm, after 100 seconds of irradiation of the oxide semiconductor layer with light, a photoelectric current value per micrometer of channel length is 42.5 fA/μm. In the TEG in which the channel length (L) is 200 μm, after 100 seconds of irradiation of the oxide semiconductor layer with light, a photoelectric current value per micrometer of channel length is 13.7 fA/μm. In the TEG in which the channel length (L) is 500 μm, after 100 seconds of irradiation of the oxide semiconductor layer with light, a photoelectric current value per micrometer of channel length is 413 aA/μm. As described above, at 25° C., the oxide semiconductor layer has a photoelectric current value of greater than or equal to 400 aA/μm and less than or equal to 0.1 pA/μm after 100 seconds of light irradiation, which means that light deterioration is suppressed to the minimum. Therefore, a transistor whose electric characteristics are stable can be achieved by using the oxide semiconductor layer.

• TABLE 3
  					Ioff per
  		Ioff after	Ioff after	Ioff after	micrometer after
  L (μm)	Ion (A)	1 sec (A)	10 sec (A)	100 sec (A)	100 sec (A)

  50	3.2704E−08	6.707E−11	1.39891E−11	4.88727E−12	9.77455E−14
  100	2.19308E−08	9.256E−11	1.28518E−11	4.24727E−12	4.24727E−14
  200	7.1513E−09	9.15E−12	2.19636E−12	2.73364E−12	1.36682E−14
  500	1.7527E−09	2.34E−12	1.25455E−12	2.06364E−13	4.12727E−16

• In this embodiment, a TEG is shown as an example, but the present invention is not limited thereto. For example, in a transistor including the same oxide semiconductor, light deterioration can be suppressed to the minimum and the electric characteristics can be stable. In addition, a liquid crystal display device in which a transistor including the same oxide semiconductor is provided in a pixel has high reliability with respect to light deterioration.
Embodiment 2
• In this embodiment, an example of a transistor that can be applied to a liquid crystal display device disclosed in this specification will be described. There is no particular limitation on the structure of a transistor which can be applied to a liquid crystal display device disclosed in this specification. For example, a staggered type and a planar type of a top-gate structure or a bottom-gate structure can be used. Further, the transistor may have a single gate structure including one channel formation region, a double gate structure including two channel formation regions, or a triple gate structure including three channel formation regions. Alternatively, the transistor may have a dual gate structure including two gate electrode layers positioned over and below a channel region with a gate insulating layer provided therebetween.FIGS. 8A to 8D each illustrate an example of the cross-sectional structure of a transistor. The transistors illustrated inFIGS. 8A to 8D each include an oxide semiconductor as a semiconductor. An advantage of using an oxide semiconductor is that high mobility and low off-state current can be obtained through a relatively easy and low-temperature process.
• Atransistor410 illustrated inFIG. 8A is a kind of bottom-gate thin film transistor, and is also referred to as an inverted-staggered thin film transistor.
• Thetransistor410 includes, over asubstrate400 having an insulating surface, agate electrode layer401, agate insulating layer402, anoxide semiconductor layer403, asource electrode layer405a, and adrain electrode layer405b. Further, an insulatinglayer407 stacked over theoxide semiconductor layer403 is provided so as to cover thetransistor410. A protective insulatinglayer409 is formed over the insulatinglayer407.
• The insulatinglayer407 is in contact with theoxide semiconductor layer403 and can be formed using a material such as GaOx (x>0), SiOx (x>0), or nitride (except for titanium nitride). In particular, when GaOx is used, the insulatinglayer407 can function as a film for preventing electrification of a back channel.
• Atransistor420 illustrated inFIG. 8B has a kind of bottom-gate structure referred to as a channel-protective type (channel-stop type) and is also referred to as an inverted-staggered thin film transistor.
• Thetransistor420 includes, over asubstrate400 having an insulating surface, agate electrode layer401, agate insulating layer402, anoxide semiconductor layer403, an insulatinglayer427 which functions as a channel protective layer covering a channel formation region of theoxide semiconductor layer403, asource electrode layer405a, and adrain electrode layer405b. Further, a protectiveinsulating layer409 is formed so as to cover thetransistor420.
• Atransistor430 illustrated inFIG. 8C is a bottom-gate thin film transistor and includes, over asubstrate400 which is a substrate having an insulating surface, agate electrode layer401, agate insulating layer402, asource electrode layer405a, adrain electrode layer405b, and anoxide semiconductor layer403. Further, an insulatinglayer407 being in contact with theoxide semiconductor layer403 is provided so as to cover thetransistor430. A protective insulatinglayer409 is formed over the insulatinglayer407.
• In thetransistor430, thegate insulating layer402 is provided on and in contact with thesubstrate400 and thegate electrode layer401, and thesource electrode layer405aand thedrain electrode layer405bare provided on and in contact with thegate insulating layer402. Further, theoxide semiconductor layer403 is provided over thegate insulating layer402, thesource electrode layer405a, and thedrain electrode layer405b.
• Atransistor440 illustrated inFIG. 8D is a kind of top-gate thin film transistor. Thetransistor440 includes, over asubstrate400 having an insulating surface, an insulatinglayer437, anoxide semiconductor layer403, asource electrode layer405a, adrain electrode layer405b, agate insulating layer402, and agate electrode layer401. Awiring layer436aand awiring layer436bare provided in contact with and electrically connected to thesource electrode layer405aand thedrain electrode layer405b, respectively.
• In this embodiment, as described above, theoxide semiconductor layer403 is used as a semiconductor layer. As an oxide semiconductor used for theoxide semiconductor layer403, a four-component metal oxide such as an In—Sn—Ga—Zn—O-based oxide semiconductor; a three-component metal oxide such as an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, or a Sn—Al—Zn—O-based oxide semiconductor; a two-component metal oxide such as an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, an In—Ga—O-based oxide semiconductor, or an In—Mg—O-based oxide semiconductor; or an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor, or a Zn—O-based oxide semiconductor, or the like can be used. Further, SiO₂may be contained in the above oxide semiconductor. Here, for example, the In—Ga—Zn—O-based oxide semiconductor means an oxide containing at least In, Ga, and Zn, and the composition ratio of the elements is not particularly limited. The In—Ga—Zn—O-based oxide semiconductor may contain an element other than In, Ga, and Zn.
• In addition, as theoxide semiconductor layer403, a thin film of a material represented by a chemical formula, InMO₃(ZnO)_m(m>0), can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, M can be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like.
• In the case where an In—Zn—O-based material is used as the oxide semiconductor, a target to be used has a composition ratio of In:Zn=50:1 to 1:2 in an atomic ratio (In₂O₃:ZnO=25:1 to 1:4 in a molar ratio), preferably In:Zn=20:1 to 1:1 in an atomic ratio (In₂O₃:ZnO=10:1 to 1:2 in a molar ratio), more preferably In:Zn=15:1 to 1.5:1 in an atomic ratio (In₂O₃:ZnO=15:2 to 3:4 in a molar ratio). For example, when a target used for forming the In—Zn—O-based oxide semiconductor has a composition ratio of In:Zn:O X:Y:Z in an atomic ratio, Z>(1.5X+Y).
• Theoxide semiconductor layer403 in each of thetransistors410,420,430, and440 is preferably heated at a temperature of higher than or equal to 450° C. in an atmosphere which does not contain moisture and hydrogen. For example, heat treatment is performed at 650° C. for 1 hour in a nitrogen atmosphere and then heat treatment is performed at 450° C. for 1 hour in an atmosphere containing nitrogen and oxygen. The heat treatment may be performed with the use of ultra-dry air (in which the dew point is lower than or equal to −40° C., preferably lower than or equal to −60° C.) as an atmosphere containing nitrogen and oxygen. With this heat treatment, light deterioration can be suppressed to the minimum, and a transistor whose electric characteristics are stable can be provided.
• In thetransistors410,420,430, and440 each including theoxide semiconductor layer403, the amount of current in an off state (off-state current) can be small. Therefore, by using the transistor including theoxide semiconductor layer403 in a pixel portion of a liquid crystal display device, an electric signal such as image data can be held for a longer period and a writing interval can be set longer. Accordingly, frequency of refresh operation can be reduced, which leads to an effect of suppressing power consumption.
• In addition, thetransistors410,420,430, and440 each including theoxide semiconductor layer403 can have relatively high field-effect mobility and thus can operate at high speed. Therefore, by using any of the above transistors in a pixel portion of a liquid crystal display device, a high-quality image can be provided. In addition, since a driver circuit portion and the pixel portion can be manufactured over one substrate with the use of the transistor including theoxide semiconductor layer403, the number of components of the liquid crystal display device can be reduced.
• Although there is no particular limitation on a substrate that can be used as thesubstrate400 having an insulating surface, a glass substrate made of barium borosilicate glass, aluminoborosilicate glass, or the like can be used.
• In thebottom-gate transistors410,420, and430, an insulating film serving as a base film may be provided between the substrate and the gate electrode layer. The base film has a function of preventing diffusion of impurity elements from the substrate, and can be formed to have a single-layer structure or a layered structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.
• Thegate electrode layer401 can be formed to have a single-layer structure or a layered structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
• Thegate insulating layer402 can be formed with a single-layer structure or a layered structure using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, and a hafnium oxide layer by a plasma CVD method, a sputtering method, or the like. For example, by a plasma CVD method, a silicon nitride layer (SiN_y(y>0)) with a thickness of greater than or equal to 50 nm and less than or equal to 200 nm is formed as a first gate insulating layer, and a silicon oxide layer (SiO_x(x>0)) with a thickness of greater than or equal to 5 nm and less than or equal to 300 nm is formed as a second gate insulating layer over the first gate insulating layer, so that a gate insulating layer with a total thickness of 200 nm is formed.
• As a conductive film used for thesource electrode layer405aand thedrain electrode layer405b, for example, a film of an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, a film of an alloy containing any of these elements as its component, a film of an alloy containing any of these elements in combination, or the like can be used. The conductive film may have a structure in which a high-melting-point metal layer of Ti, Mo, W, or the like is stacked over and/or below a metal layer of Al, Cu, or the like. When an Al material to which an element (e.g., Si, Nd, or Sc) which prevents generation of hillocks and whiskers in an Al film is added is used, heat resistance can be increased.
• A material similar to that for thesource electrode layer405aand thedrain electrode layer405bcan be used for a conductive film used for thewiring layer436aand thewiring layer436bwhich are respectively connected to thesource electrode layer405aand thedrain electrode layer405b.
• Alternatively, the conductive film used for thesource electrode layer405aand thedrain electrode layer405b(including a wiring layer formed using the same layer as thesource electrode layer405aand thedrain electrode layer405b) may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium oxide-tin oxide alloy (In₂O₃—SnO₂; abbreviated to ITO), indium oxide-zinc oxide alloy (In₂O₃—ZnO), or any of these metal oxide materials in which silicon oxide is contained can be used.
• As the insulatinglayers407,427, and437, an inorganic insulating film, typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film, can be used.
• For the protective insulatinglayer409, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum nitride oxide film can be used.
• Further, a planarization insulating film may be formed over the protective insulatinglayer409 so that surface roughness due to the transistor can be reduced. For the planarization insulating film, an organic material such as polyimide, acrylic, or benzocyclobutene can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material) or the like. Alternatively, the planarization insulating film may be formed by stacking a plurality of insulating films formed from these materials.
• As described above, in this embodiment, a high-performance liquid crystal display device can be provided by using the transistor including the oxide semiconductor layer.
• This application is based on Japanese Patent Application serial no. 2010-064751 filed with Japan Patent Office on Mar. 19, 2010, the entire contents of which are hereby incorporated by reference.

Claims (12)

1. A semiconductor device, comprising:

an oxide semiconductor layer at least a part of which overlaps with a gate electrode with a gate insulating layer provided therebetween,

wherein the oxide semiconductor layer has a channel formation region, and

wherein photoresponse characteristics of the channel formation region of the oxide semiconductor layer have two kinds of modes after light irradiation is performed and a light source is turned off.

2. The semiconductor device according toclaim 1, wherein the oxide semiconductor layer has a photoelectric current value of greater than or equal to 1 pA and less than or equal to 10 nA.

3. The semiconductor device according toclaim 1, wherein the oxide semiconductor layer comprises at least one of In, Zn, and Ga.

4. The semiconductor device according toclaim 1, wherein a photoelectric current value of the oxide semiconductor layer after 100 seconds of light irradiation is greater than or equal to 400 aA/μm and less than or equal to 0.1 pA/μm.

5. The semiconductor device according toclaim 1, wherein the two kinds of modes comprise a region where a photoelectric current value of the oxide semiconductor layer falls rapidly and a region where the photoelectric current value falls gradually, in a result of a change in photoelectric current over time.

6. A semiconductor device comprising:

a pixel porting including a transistor,

wherein a channel formation region of the transistor is formed in an oxide semiconductor layer whose photoresponse characteristics have two kinds of modes after light irradiation is performed and a light source is turned off.

7. The semiconductor device according toclaim 6, wherein the oxide semiconductor layer has a photoelectric current value of greater than or equal to 1 pA and less than of equal to 10 nA.

8. The semiconductor device according toclaim 6, wherein the oxide semiconductor layer comprises at least one of In, Zn, and Ga.

9. The semiconductor device according toclaim 6, wherein a photoelectric current value of the oxide semiconductor layer after 100 seconds of light irradiation is greater than or equal to 400 aA/μm and less than or equal to 0.1 pA/μm.

10. The semiconductor device according toclaim 6, wherein the two kinds of modes comprise a region where a photoelectric current value of the oxide semiconductor layer falls rapidly and a region where the photoelectric current value falls gradually, in a result of a change in photoelectric current over time.

11. A semiconductor device, comprising:

an oxide semiconductor layer at least a part of which overlaps with a gate electrode with a gate insulating layer provided therebetween,

wherein the oxide semiconductor layer has a channel formation region, and

wherein photoresponse characteristics of the channel formation region of the oxide semiconductor layer have at least a first mode and a second mode after light irradiation is performed and a light source is turned off.

12. The semiconductor device according toclaim 11, wherein the first mode is a region where a photoelectric current value of the oxide semiconductor layer falls rapidly and the second mode is a region where the photoelectric current value of the oxide semiconductor layer falls gradually, in a result of a change in photoelectric current over time.

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