US20110204472A1 - Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame - Google Patents

Abstract

A semiconductor device is made by mounting a semiconductor component over a carrier. A ferromagnetic inductor core is formed over the carrier. A pillar frame including a plurality of bodies is mounted over the carrier, semiconductor component, and inductor core. An encapsulant is deposited around the semiconductor component, plurality of bodies, and inductor core. A portion of the pillar frame is removed. A first remaining portion of the pillar frame bodies provide inductor pillars around the inductor core and a second remaining portion of the pillar frame bodies provide an interconnect pillar. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors.

Description

CLAIM OF DOMESTIC PRIORITY
• The present application is a continuation of U.S. patent application Ser. No. 12/467,908, filed May 18, 2009, and claims priority to the foregoing parent application pursuant to 35 U.S.C. §120.
FIELD OF THE INVENTION
• The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a 3D inductor from a prefabricated pillar frame.
BACKGROUND OF THE INVENTION
• Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
• Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
• Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
• A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
• Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
• One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
• Another goal of semiconductor manufacturing is to produce higher performance semiconductor devices. Increases in device performance can be accomplished by forming active components that are capable of operating at higher speeds. In high frequency applications, such as radio frequency (RF) wireless communications, integrated passive devices (IPDs) are often contained within the semiconductor device. Examples of IPDs include resistors, capacitors, and inductors. A typical RF system requires multiple IPDs in one or more semiconductor packages to perform the necessary electrical functions.
• An integrated three dimensional (3D) inductor can be made by forming through mold via (TMV) in the encapsulant around a ferromagnetic core material, as described in US Publication 20080135977. The TMVs are plated to form metal inductor pillars which are electrically connected in a coiled arrangement around the ferromagnetic core. The lithography and plating processes needed to form the inductor pillars are time consuming and costly.
SUMMARY OF THE INVENTION
• A need exists for 3D inductors without using costly lithography and plating processes to form the inductor pillars. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a carrier, mounting a semiconductor component over the carrier, forming an inductor core over the carrier, and mounting a pillar frame over the carrier and semiconductor component. The pillar frame includes a plurality of bodies with a first portion of the bodies being disposed around the inductor core. The method further includes the steps of depositing an encapsulant around the semiconductor component, plurality of bodies, and inductor core, removing a portion of the pillar frame while leaving the first portion of the bodies to form inductor pillars, forming a first interconnect structure over a first surface of the encapsulant, removing the carrier, and forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected to the inductor pillars to form a 3D inductor.
• In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a carrier, mounting a semiconductor component over the carrier, mounting a pillar frame over the carrier and semiconductor component, depositing an encapsulant over the semiconductor component and pillar frame, and removing a portion of the pillar frame. A first remaining portion of the pillar frame provides inductor pillars. The method further includes the steps of forming a first interconnect structure over a first surface of the encapsulant, removing the carrier, and forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected to the inductor pillars to form a 3D inductor.
• In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a carrier, mounting a semiconductor component over the carrier, mounting a pillar frame over the carrier and semiconductor component, depositing an encapsulant over the semiconductor component and pillar frame, removing a portion of the pillar frame, and forming a first interconnect structure over a first surface of the encapsulant. A first remaining portion of the pillar frame provides inductor pillars. The first interconnect structure is electrically connected to the inductor pillars to form a 3D inductor.
• In another embodiment, the present invention is a semiconductor device comprising a semiconductor component and inductor core disposed in proximity to the semiconductor component. A pillar frame is mounted over the semiconductor component and inductor core. An encapsulant is deposited over the semiconductor component, pillar frame, and inductor core. A portion of the pillar frame is removed to form inductor pillars around the inductor core. A first interconnect structure is formed over a first surface of the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 illustrates a PCB with different types of packages mounted to its surface;
• FIGS. 2a-2cillustrate further detail of the representative semiconductor packages mounted to the PCB;
• FIGS. 3a-3killustrate a process of using a prefabricated pillar frame to form interconnect pillars and inductor pillars around an inductor core;
• FIG. 4 illustrates the semiconductor device with 3D inductors and without interconnect pillars;
• FIG. 5 illustrates the semiconductor device having multiple 3D inductors;
• FIG. 6 illustrates stacked semiconductor die with 3D inductors and interconnect pillars;
• FIG. 7 illustrates side-by-side semiconductor die with 3D inductors and interconnect pillars;
• FIG. 8 illustrates the semiconductor device with 3D inductors and a shielding layer formed over the semiconductor die;
• FIG. 9 illustrates the semiconductor device with 3D inductors and capacitor and resistor formed in build-up interconnect structure; and
• FIG. 10 illustrates the semiconductor device with 3D inductors and discrete semiconductor components formed over the build-up interconnect layer.
DETAILED DESCRIPTION OF THE DRAWINGS
• The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
• Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.
• Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
• Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
• The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.
• Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.
• Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation. To singulate the die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
• FIG. 1 illustrateselectronic device50 having a chip carrier substrate orPCB52 with a plurality of semiconductor packages mounted on its surface.Electronic device50 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1 for purposes of illustration.
• Electronic device50 may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively,electronic device50 may be a subcomponent of a larger system. For example,electronic device50 may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.
• InFIG. 1,PCB52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces54 are formed over a surface or within layers ofPCB52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components.Traces54 also provide power and ground connections to each of the semiconductor packages.
• In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
• For the purpose of illustration, several types of first level packaging, includingwire bond package56 andflip chip58, are shown onPCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quadflat package72, are shown mounted onPCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected toPCB52. In some embodiments,electronic device50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
• FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail ofDIP64 mounted onPCB52. Semiconductor die74 includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contactpads76 are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly ofDIP64, semiconductor die74 is mounted to anintermediate carrier78 using a gold-silicon eutectic layer or adhesive material such as thermal epoxy. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80 andwire bonds82 provide electrical interconnect between semiconductor die74 andPCB52.Encapsulant84 is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die74 or wire bonds82.
• FIG. 2billustrates further detail ofBCC62 mounted onPCB52. Semiconductor die88 is mounted overcarrier90 using an underfill or epoxy-resin adhesive material92.Wire bonds94 provide first level packing interconnect betweencontact pads96 and98. Molding compound orencapsulant100 is deposited over semiconductor die88 andwire bonds94 to provide physical support and electrical isolation for the device. Contactpads102 are formed over a surface ofPCB52 using a suitable metal deposition such electrolytic plating or electroless plating to prevent oxidation. Contactpads102 are electrically connected to one or more conductive signal traces54 inPCB52.Bumps104 are formed betweencontact pads98 ofBCC62 andcontact pads102 ofPCB52.
• InFIG. 2c, semiconductor die58 is mounted face down tointermediate carrier106 with a flip chip style first level packaging.Active region108 of semiconductor die58 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements withinactive region108. Semiconductor die58 is electrically and mechanically connected tocarrier106 throughbumps110.
• BGA60 is electrically and mechanically connected toPCB52 with a BGA style second levelpackaging using bumps112. Semiconductor die58 is electrically connected to conductive signal traces54 inPCB52 throughbumps110,signal lines114, and bumps112. A molding compound orencapsulant116 is deposited over semiconductor die58 andcarrier106 to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58 to conduction tracks onPCB52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58 can be mechanically and electrically connected directly toPCB52 using flip chip style first level packaging withoutintermediate carrier106.
• FIGS. 3a-3killustrate a process of forming a semiconductor device having 3D inductors made with a prefabricated pillar frame placed over semiconductor die and inductor core. InFIG. 3a, a sacrificial or temporary reusable substrate orcarrier120 contains base material such as silicon, polymer, polymer composite, metal, ceramic, glass, glass epoxy, beryllium oxide, tape, or other suitable low-cost, rigid material for structural support.
• Semiconductor die orcomponents122 are mounted tocarrier120 withcontact pads124 oriented downward over the carrier. Semiconductor die122 each include anactive region126 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed withinactive surface126 to implement baseband analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die122 may also contain IPD, such as inductors, capacitors, and resistors, for RF signal processing. Semiconductor die122 can be a flipchip type device or wire bond type device. In another embodiment, a discrete component can be mounted overcarrier120.
• A preformedinductor core128 is mounted overcarrier120 between semiconductor die122. Theinductor core128 is typically surface mounted at designated locations oncarrier120. Alternatively,inductor core128 can be deposited by PVD, CVD, or other suitable deposition process. Theinductor core128 can be suitable either crystalline or non-crystalline ferromagnetic material or ferromagnetic composite material. In other embodiment,inductor core128 can include alloys such as FeOFe2O3, NiOFe2O3, CuOFe2O3, or MgOFe2O3.
• Aprefabricated pillar frame130 is mounted over semiconductor die122 andinductor core128, as shown inFIGS. 3c-3d.In one embodiment,prefabricated pillar frame130 is made with Cu using leadframe technology.Pillar frame130 includes aflat plate132 with a plurality of bodies134a-134fintegrated withplate132 and separated bycavities136. Bodies134a-134fare sufficiently thick to extend down tocarrier120 whenpillar frame130 is mounted over semiconductor die122. An optional adhesive orthermal interface material138 provides a secure physical contact betweenplate132 and a back surface of semiconductor die122. A plurality ofopenings140 is formed throughplate132 intocavities136. Theprefabricated pillar frame130 is simple to manufacture and cost effective in comparison to the plated TMV pillars discussed in the background.
• FIG. 3dshowspillar frame130 mounted over semiconductor die122.Bodies134aand134dare vertical (z-direction) interconnect pillars. Theinductor core128 is disposed incavity136 betweenbodies134b-134cand between bodies134e-134f.Bodies134b,134c,134e,and134fare inductor pillars aroundinductor core128.
• FIG. 3eshows an encapsulant ormolding compound146 deposited over semiconductor die122 andprefabricated pillar frame130 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator. The encapsulation process disperses encapsulant146 throughopenings140 intocavities136 belowpillar frame130.Encapsulant146 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.Encapsulant146 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.Encapsulant146 encloses semiconductor die122,inductor core128, and bodies134a-34f.
• InFIG. 3f,grinder148 removes a portion ofpillar frame130, includingplate132 andadhesive layer138, to planarize the surface and exposeencapsulant146 incavities136. The remaining portion ofpillar frame130 between semiconductor die122 becomes conductive pillars orposts134aand134dfor vertical z-direction interconnection, andinductor pillars134b,134c,134e,and134ffor RF signal processing. Alternatively, the grinding can be done after removing the sacrificial substrate ortemporary carrier120.FIG. 3gshows a top view ofinterconnect pillars134aaround semiconductor die122 andinductor pillars134b-134caroundinductor core128, all enclosed inencapsulant146.
• InFIG. 3h, a build-upinterconnect structure149 is formed over the back surface of semiconductor die122,encapsulant146,interconnect pillars134aand134d,andinductor pillars134b-134cand134e-134f.The build-upinterconnect structure149 includes at least one insulating or passivation layer. For example,passivation layer150 is formed with PVD, CVD, printing, sintering, or thermal oxidation. Thepassivation layer150 can be dielectric polymer insulation materials, such as low temperature cured photosensitive resist. Alternatively,passivation layer150 can be one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties. A portion ofpassivation layer150 is removed by an etching process to exposeinterconnect pillars134aand134d,andinductor pillars134b-134cand134e-134f.
• The build-upinterconnect structure149 further includes at least one electricallyconductive layer152 formed over or between passivation layers, for example, overpassivation layer150.Conductive interconnect pillars134aand134d,andinductor pillars134b-134cand134e-134fusing patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer152 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.Conductive layer152 is electrically connected to interconnectpillars134aand134dto provide vertical, z-direction interconnect.Conductive layer152 is also electrically connected between rows ofinductor pillars134b-134cand134e-134f,as shown inFIG. 3j, to provide an integrated 3D inductor coiled aroundinductor core128.
• InFIG. 3i,carrier120 is removed by chemical etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wet stripping. A build-upinterconnect structure153 is formed over the front surface of semiconductor die122,encapsulant146,interconnect pillars134aand134d,andinductor pillars134b-134cand134e-134f.The build-upinterconnect structure153 includes at least one insulating orpassivation layer154 formed with PVD, CVD, printing, sintering, or thermal oxidation. Thepassivation layer154 can be dielectric polymer insulation materials, such as low temperature cured photosensitive resist. Alternatively,passivation layer154 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion ofpassivation layer154 is removed by an etching process to exposeinterconnect pillars134aand134d,andinductor pillars134b-134cand134e-134f.
• The build-upinterconnect structure153 further includes at least one electricallyconductive layer156 formed over or between passivation layers, for example overpassivation layer154,interconnect pillars134aand134d,andinductor pillars134b-134cand134e-134fusing patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer156 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.Conductive layer156 is electrically connected to interconnectpillars134aand134dto provide vertical, z-direction interconnect.Conductive layer156 is also electrically connected between rows ofinductor pillars134b-134cand134e-134f,as shown inFIG. 3j, to provide an integrated 3D inductor coiled aroundinductor core128.Conductive layer156 is electrically connected to contactpads124.
• InFIG. 3k, semiconductor die orcomponents158 are mounted over build-upinterconnect structure149. Solder bumps160 are electrically connected toconductive layer152. Anoptional underfill material162 is deposited between semiconductor die158 andconductive layer152. Semiconductor die158 each include a substrate and active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within its active surface to implement baseband analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die158 may also contain IPD, such as inductors, capacitors, and resistors, for RF signal processing. Semiconductor die158 can be a flipchip type device or wire bond type device. In another embodiment, a discrete semiconductor component can be mounted over semiconductor die122. The discrete semiconductor component can be a resistor, capacitor, inductor, or active semiconductor device.
• An electrically conductive material is deposited overconductive layer156 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux material. For example, the conductive material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The conductive material is bonded toconductive layer156 using a suitable attachment or bonding process. In one embodiment, the conductive material is reflowed by heating the material above its melting point to form spherical balls or bumps166. In some applications, bumps166 are reflowed a second time to improve electrical contact toconductive layer156. The bumps can also be compression bonded toconductive layer156.Bumps166 represent one type of interconnect structure that can be formed overconductive layer156. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.
• The structure is singulated with saw blade orlaser cutting tool164 intoindividual semiconductor devices168. The IPDs insemiconductor device168, including the 3D inductor, provide the electrical characteristics needed for high frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, matching networks, and tuning capacitors. The IPDs can be used as front-end wireless RF components, which can be positioned between the antenna and transceiver. The inductor can be a hi-Q balun, transformer, or coil, operating up to 100 Gigahertz. In some applications, multiple baluns are formed on a same substrate, allowing multi-band operation. For example, two or more baluns are used in a quad-band for mobile phones or other global system for mobile (GSM) communications, each balun dedicated for a frequency band of operation of the quad-band device. A typical RF system requires multiple IPDs and other high frequency circuits in one or more semiconductor packages to perform the necessary electrical functions.
• FIG. 4 shows an embodiment of the semiconductor device having the 3D inductor made with the prefabricated pillar frame, without the interconnect pillars. Theinductor pillars170aand170bare formed aroundinductor core172, using a process similar toFIGS. 3a-3k.The build-upinterconnect layer149 can be optional ifpassivation layer150 is part of the encapsulation andconductive layer152 is fabricated in lead frame technology by half etching other portions of the frame.
• FIG. 5 shows an embodiment of the semiconductor device with multiple 3D inductors made with the prefabricated pillar frame. Theinductor pillars180aand180bare formed aroundinductor core182, andinductor pillars180cand180dare formed aroundinductor core184, using a process similar toFIGS. 3a-3k. The build-upinterconnect layer149 can be optional ifpassivation150 is part of the encapsulation andconductive layer152 is fabricated in lead frame technology by half etching other portions of the frame.
• FIG. 6 shows an embodiment of the semiconductor device having stacked semiconductor die and multiple 3D inductors made with the prefabricated pillar frame. A back surface of semiconductor die190 is mounted to a back surface of semiconductor die192 with an adhesive193. Contactpads194 of semiconductor die190 are oriented upward and electrically connect toconductive layer152 of build-upinterconnect structure149. Contactpads196 of semiconductor die192 are oriented downward and electrically connect toconductive layer156 of build-upinterconnect structure153. Theinductor pillars198aand198bare formed aroundinductor core200, andinductor pillars198cand198dare formed aroundinductor core202, using a process similar toFIGS. 3a-3k.
• FIG. 7 shows an embodiment of the semiconductor device having side-by-side semiconductor die206 and multiple 3D inductors made with the prefabricated pillar frame. Contactpads208 of semiconductor die206 are oriented downward and electrically connect toconductive layer156 of build-upinterconnect structure153. Theinductor pillars210aand210bare formed aroundinductor core212, andinductor pillars210cand210dare formed aroundinductor core214, using a process similar toFIGS. 3a-3k.
• FIG. 8 shows an embodiment of the semiconductor device with the 3D inductor made with the prefabricated pillar frame and ashielding layer220 formed over semiconductor die122 to reduce inter-device interference of the IPD.Shielding layer220 can be Cu, Al, ferrite or carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon-iron steel, foil, epoxy, conductive resin, and other metals and composites capable of blocking or absorbing EMI, RFI, and other inter-device interference.Shielding layer220 can also be a non-metal material such as carbon-black or aluminum flake to reduce the effects of EMI and RFI.Shielding layer220 thermally contacts the backside of semiconductor die122.Shielding layer220 is electrically connected to a low-impedance ground point throughconductive layer152,interconnect pillars134a,andsolder bump166.Shielding layer220 also dissipates heat generated by semiconductor die122.
• InFIG. 9, the semiconductor device with the 3D inductor made with the prefabricated pillar frame further includes athin film capacitor222 is formed in build-upinterconnect layer149, andthin film capacitor224 is formed in build-upinterconnect layer153. In addition, athin film resistor226 is formed in build-upinterconnect layer149, andthin film resistor228 is formed in build-upinterconnect layer153. The thin film capacitors222-224 and thin film resistor226-228 constitute additional IPDs that can be formed in build-upinterconnect structures149 and153.
• InFIG. 10, the semiconductor device with 3D inductor made with the prefabricated pillar frame further includesdiscrete semiconductor components230 and232 are formed over build-upinterconnect layer149 and electrically connected toconductive layer152.
• While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (25)

1. A method of making a semiconductor device, comprising:

providing a carrier;

mounting a semiconductor component over the carrier;

forming an inductor core over the carrier;

mounting a pillar frame over the carrier and semiconductor component, the pillar frame including a plurality of bodies with a first portion of the bodies being disposed around the inductor core;

depositing an encapsulant around the semiconductor component, plurality of bodies, and inductor core;

removing a portion of the pillar frame while leaving the first portion of the bodies to form inductor pillars;

forming a first interconnect structure over a first surface of the encapsulant;

removing the carrier; and

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected to the inductor pillars to form a 3D inductor.

2. The method ofclaim 1, wherein the inductor core includes ferromagnetic material.

3. The method ofclaim 1, wherein removing the portion of the pillar frame further leaves a second portion of the bodies to form an interconnect pillar.

4. The method ofclaim 3, further including stacking a plurality of the semiconductor components electrically connected through the interconnect pillar.

5. The method ofclaim 3, further including disposing a plurality of the semiconductor components side-by-side electrically connected through the interconnect pillar.

6. The method ofclaim 1, further including forming a shielding layer over the semiconductor component.

7. The method ofclaim 1, further including forming an integrated passive device within the first or second interconnect structures.

8. A method of making a semiconductor device, comprising:

providing a carrier;

mounting a semiconductor component over the carrier;

mounting a pillar frame over the carrier and semiconductor component;

depositing an encapsulant over the semiconductor component and pillar frame;

removing a portion of the pillar frame, wherein a first remaining portion of the pillar frame provides inductor pillars;

forming a first interconnect structure over a first surface of the encapsulant;

removing the carrier; and

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected to the inductor pillars to form a 3D inductor.

9. The method ofclaim 8, wherein a second remaining portion of the pillar frame provides an interconnect pillar.

10. The method ofclaim 8, wherein the first or second interconnect structure is electrically connected to a contact pad of the semiconductor component.

11. The method ofclaim 8, further including forming a shielding layer over the semiconductor component.

12. The method ofclaim 8, further including forming an integrated passive device within the first or second interconnect structures.

13. The method ofclaim 8, further including forming a discrete semiconductor component over the first interconnect structure.

14. A method of making a semiconductor device, comprising:

providing a carrier;

mounting a semiconductor component over the carrier;

mounting a pillar frame over the carrier and semiconductor component;

depositing an encapsulant over the semiconductor component and pillar frame;

removing a portion of the pillar frame, wherein a first remaining portion of the pillar frame provides inductor pillars; and

forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure being electrically connected to the inductor pillars to form a 3D inductor.

15. The method ofclaim 14, further including:

removing the carrier; and

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected to the inductor pillars to form the 3D inductor.

16. The method ofclaim 15, further including forming an integrated passive device within the first or second interconnect structures.

17. The method ofclaim 14, further including forming an inductor core over the carrier, the inductor pillars being disposed around the inductor core.

18. The method ofclaim 14, wherein a second remaining portion of the pillar frame provides an interconnect pillar.

19. The method ofclaim 14, further including forming a shielding layer over the semiconductor component.

20. The method ofclaim 14, further including forming a plurality of 3D inductors with the inductor pillars.

21. A semiconductor device, comprising:

a semiconductor component;

an inductor core disposed in proximity to the semiconductor component;

a pillar frame mounted over the semiconductor component and inductor core;

an encapsulant deposited over the semiconductor component, pillar frame, and inductor core, wherein a portion of the pillar frame is removed to form inductor pillars around the inductor core;

a first interconnect structure formed over a first surface of the encapsulant; and

a second interconnect structure formed over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected to the inductor pillars to form a 3D inductor.

22. The semiconductor device ofclaim 21, wherein removing the portion of the pillar frame leaves an interconnect pillar.

23. The semiconductor device ofclaim 21, further including a shielding layer formed over the semiconductor component.

24. The semiconductor device ofclaim 21, further including an integrated passive device formed within the first or second interconnect structures.

25. The semiconductor device ofclaim 21, further including a plurality of 3D inductors formed with the inductor pillars.

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