US20110170329A1 - Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof - Google Patents

Abstract

A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
• The present application claims the benefit of priority of Korean Patent Application Nos. 10-2006-0070963 filed on Jul. 27, 2006, and 10-2006-0132602 filed on Dec. 22, 2006, which is incorporated by reference in its entirety. Moreover, the present application is related to U.S. Pat. Nos. 6,775,172, and 6,980,461, the contents of which are also incorporated herein by reference in their entirety.
BACKGROUND
• The present invention generally relates to a nonvolatile ferroelectric memory device using a silicon substrate, a method for manufacturing the same, and a refresh method thereof, and more specifically, to a technology of providing a double gate one transistor (1T) capacitorless type nonvolatile ferroelectric memory device using a bulk-silicon substrate.
• In general, a DRAM requires a continuous power supply to store data as a volatile memory. When a power is not supplied, data of a RAM may be destroyed because a memory cell of the DRAM is designed to have small capacitors for keeping the charged power and for retaining the data. If these capacitors are not recharged, the capacitor loses the previously charged power, thus losing the data.
• A refresh operation refers to a recharging process of a memory cell in a memory chip. Memory cells in a row can be charged in each refresh cycle. Although the refresh operation is performed by memory control of the system, some chips are designed to perform a self-refresh operation.
• For example, there is disclosed a DRAM chip, which has a self-refresh circuit configured to perform a self-refresh operation without a Central Processing Unit (CPU) or an external refresh circuit. The self-refresh method has been frequently used in portable computers to reduce power consumption.
• In the conventional volatile DRAM having a short refresh cycle, the refresh operation is frequently performed, which results in large power consumption and degradation of operation performance.
• As an example of these integrated circuits, a nonvolatile ferroelectric memory, such as a Ferroelectric Random Access Memory (FeRAM) device, has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (DRAM) and conserves data even after the power is turned off.
• An FeRAM having a structure similar to that of a DRAM includes capacitors made of a ferroelectric substance, which has a high residual polarization allowing for retention of data after power is turned off.
• A One-Transistor One-Capacitor (1T1C) type unit cell of the conventional FeRAM includes one switching element configured to perform a switching operation depending on a state of a word line so as to connect a nonvolatile ferroelectric capacitor to a bit line, and one nonvolatile ferroelectric capacitor connected between a plate line and one end of the switching element. The switching element of the conventional FeRAM is an NMOS transistor whose switching operation is controlled by a gate control signal.
SUMMARY
• Various embodiments consistent with the present invention are directed at providing a double gate one transistor field effect transistor (1T-FET) type nonvolatile ferroelectric memory cell using a bulk-silicon substrate.
• Various embodiments consistent with the present invention are directed at preserving data of a nonvolatile FeRAM device when a power source is off and performing a refresh operation in a given cycle to restore degraded cell data, thereby improving data retention characteristics. Unlike DRAMs, the nonvolatile FeRAM device is configured to have the whole data retention time including the on/off time of the power source so as not to perform a refresh operation frequently, thereby reducing power consumption and improving operation performance.
• According to an embodiment consistent with the present invention, a nonvolatile ferroelectric memory device using a silicon substrate comprises an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.
• According to an embodiment consistent with the present invention, a nonvolatile ferroelectric memory device using a silicon substrate comprises a memory cell, a register configured to store information of the memory cell, and a refresh control unit configured to perform a refresh operation with a given refresh cycle so as to improve retention characteristics of data stored in the memory cell. The memory cell comprises a silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer. The silicon substrate includes a bottom word line, a floating channel layer formed over the bottom word line, and drain/source regions formed at both ends of the floating channel layer. The memory cell is configured to induce a different channel resistance to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so as to read/write data.
• According to an embodiment consistent with the present invention, a nonvolatile ferroelectric memory device using a silicon substrate comprises a cell array including a plurality of nonvolatile memory cells each being configured to read/write data, a refresh control unit configured to control a refresh operation in a given cycle in response to a refresh control signal for improving retention characteristics of data stored in the memory cell so as to output a count address for refresh operations, a row address control unit configured to latch and decode a row address in response to a RAS signal and an output signal from the refresh control unit and to select the count address in the refresh mode, a column address control unit configured to latch and decode a column address in response to a CAS signal, and an input/output logic circuit configured to control read/write operations of the cell array in response to an output enable signal and read/write commands. The cell array comprises an insulating layer formed in an etching region of the silicon substrate, a bottom word line in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.
• Consistent with the present invention, there is also provided a method for refreshing a nonvolatile ferroelectric memory device using a silicon substrate that comprises a double gate 1T-FET type memory cell includes the steps of: reading/writing data in the memory cell; and refreshing data of the memory cell so as to improve retention characteristics of data stored in the memory cell. The memory cell comprises a silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer. The silicon substrate includes a bottom word line, a floating channel layer formed over the bottom word line and drain/source regions formed at both ends of the floating channel layer. The memory cell is configured to induce a different channel resistance to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so as to read/write data.
• Further consistent with the present invention, there is also provided a method for manufacturing a nonvolatile ferroelectric memory device using a silicon substrate comprises the steps of: etching a silicon substrate to have a T shape with an etching mask formed over the silicon substrate to form a plurality of T-shaped silicons spaced with a given interval; forming a first insulating layer having a given thickness over the resulting structure including the plurality of T-shaped silicons, and filling bottom word lines each having a given thickness at both ends of an etching region between the plurality of T-shaped silicons; performing a gap-fill process on the resulting structure to fill a second insulating layer, and etching the first insulating layer and the second insulating layer that cover the top portions of the plurality of T-shaped silicons; filling a silicon in the etching region between the plurality of T-shaped silicons to grow crystallization; sequentially forming a ferroelectric layer and a word line over the resulting structure, and etching the ferroelectric layer and the word line; ion-implanting impurities into the plurality of T-shaped silicons and the silicon to form drain/source regions, and forming a floating channel layer separated from the drain/source regions; and forming a sensing line and a bit line over the impurities.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a cross-sectional diagram illustrating a cell of a conventional nonvolatile ferroelectric memory device.
• FIGS. 2 through 14 are cross-sectional diagrams illustrating a method for manufacturing a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 15 is a cross-sectional diagram illustrating a cell array of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 16 is a cross-sectional diagram illustrating a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 17 is a cross-sectional diagram illustrating a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 18 is a diagram illustrating a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 19 is a timing diagram illustrating a read operation of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 20 is a timing diagram illustrating a write operation of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 21 is timing diagram illustrating a refresh method of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIGS. 22 and 23 are flow charts illustrating a refresh method of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 24 is a diagram illustrating a refresh method of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 25 is a diagram illustrating a timer control operation in the refresh method of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• FIG. 26 is a graph illustrating a data retaining characteristic of a nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention.
DETAILED DESCRIPTION
• The present invention will be described in detail with reference to the accompanying drawings.
• FIG. 1 is a cross-sectional diagram illustrating a cell of a conventional nonvolatile ferroelectric memory device.
• A conventional One-Transistor Field Effect Transistor (1-T FET)type memory cell10 may include a P-type channel region6, an N-type drain region2, and a N-type source region3 over a P-type region substrate1. Aferroelectric layer4 may be formed over channel region6, and aword line5 may be formed overferroelectric layer4.
• Data may be read/written by a channel resistance ofmemory cell10. The channel resistance may be differentiated depending on polarization states offerroelectric layer4.
• When the polarity offerroelectric layer4 induces positive charges to channel region6,memory cell10 becomes at a high resistance channel state, and the channel is turned off. On the other hand, when the polarity offerroelectric layer4 induces negative charges to channel region6,memory cell10 becomes at a low resistance channel state, and the channel is turned on. In this way, the conventional nonvolatile FeRAM device may select polarization kinds offerroelectric layer4 to write data inmemory cell10, which becomes a nonvolatile memory cell.
• However, a memory cell of the conventional 1T-FET type ferroelectric memory device is formed in a Silicon On Insulator (SOI) substrate which is expensive, thereby increasing the manufacturing cost of the memory cell.
• Manufacturing processes of a 1T type memory cell using a SOI substrate is not interchangeable with that of a 1T1C type memory cell using a silicon substrate. That is, wafers, equipments, and processes used in the 1T type memory cell are different from those used in the 1T1C type memory cell. As a result, the 1T type memory cell using a SOT substrate requires additional set-ups for new wafers, equipments, and processes.
• Although the 1T-FET type memory cell of the conventional FeRAM device has nonvolatile characteristics, cell data may be degraded as time passes, thereby limiting data retention life. As a result, data retention characteristics may be degraded, such that the best state of nonvolatile cell storage characteristics is not maintained.
• FIGS. 2 through 14 are cross-sectional diagrams illustrating a method for manufacturing a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• A P-type substrate100, which is a bare wafer, is formed. A T-shapedetching mask102 is formed over P-type substrate100. P-type substrate100 for forming a T-shaped silicon structure includes bulk silicon.
• P-type substrate100 is etched to have a T shape with T-shapedetching mask102 as an etching mask. As a result, a T-shapedsilicon104 is formed with a given interval over P-type substrate100. A T-shaped etching region (A) having a reversed T-shape is formed between T-shapedsilicons104.
• An insulatinglayer106 is formed over the resulting structure including T-shapedsilicon104. Insulatinglayer106 having a given thickness is formed to cover T-shapedsilicon104 and the top portion of P-type substrate100.
• Abottom word line108 is formed at both ends of T-shaped etching region (A).Bottom word line108 is filled in both ends of the bottom edge region of T-shapedsilicon104, and not in the middle region where T-shaped etching region (A) is exposed.
• A gap-fill process for filling a space between bottom word lines108 is performed on the resulting structure to form an insulatinglayer110, which is filled in the middle region of T-shaped etching region (A). Insulatinglayer110 may be formed to have the same height as that of insulatinglayer106.
• An etch-back process is performed on a portion of insulatinglayer106 that covers the side surface and the top portion of T-shapedsilicon104. As a result, insulatinglayer110 surroundsbottom word line108 formed in the bottom edge region between adjacent T-shapedsilicons104. That is, insulatinglayer110 is not filled in a top etching region (B) between adjacent T-shapedsilicons104.
• Asingle crystal silicon112 having the same height as that of top region (B) of T-shapedsilicon104 is filled in top etching region (B) between T-shapedsilicons104.Single crystal silicon112 is filled and crystallized in top portion (B) of T-shapedsilicon104.
• In one embodiment, T-shapedsingle crystal silicon104 andsilicon region112 may be grown to form a single crystal so as to be interconnected. As a result, there is no space between T-shapedsilicon104 andsilicon region112 so that a floating channel region is sufficiently formed.
• Althoughsingle crystal silicon112 may be grown in region (B) between T-shapedsilicons104, in this embodiment, a poly crystalline silicon (not shown) may be filled in region (B) between T-shapedsilicons104 and thermally grown to be single-crystallized. The poly crystalline silicon may include amorphous silicon or poly silicon.
• Aferroelectric layer114 is formed over T-shapedsilicon104 andsilicon region112.
• Aword line116 gate region is formed overferroelectric layer114.Ferroelectric layer114 andword line116 are selectively etched through an etching mask (not shown). As a result, a plurality ofword lines116 are spaced with a given interval overbottom word line108.Word lines116 are formed in a floating body region at both ends of T-shapedsilicon104, but not over a region (C) connected to T-shapedsilicon104 and P-type substrate100.
• AnN+ layer118, which is an impurity-implanting layer, is implanted intosilicon region110 and the top region of T-shapedsilicon104 to form floating channel layers104b, which are spaced with a given interval. A channel region of floatingchannel layer104bbecomes floated, and theN+ layer118 is not implanted into floatingchannel layer104b. Floating channel layers104bare formed in the top side ofbottom word line108 and in the bottom offerroelectric layer114.N+ layer118 formed in both ends of floatingchannel layer104bis used as drain/source regions.
• Abulk connection silicon104ais formed in a region where the top side of T-shapedsilicon104 implanted withN+ layer118 is connected to P-type substrate100.Bulk connection silicon104amay have the same height as that of insulatinglayer110. Floatingchannel layer104bmay be formed over a portion ofbottom word line108 wherebulk connection silicon104ais not formed.
• N+ layer118 is implanted into the top portion ofbulk connection silicon104ato electrically separate a bulk silicon from the source and drain ends.N+ layer118 formed over thebulk connection silicon104amay be used as source and drain regions.N+ layer118 may be implanted into a filling layer ofsilicon112 to form a source/drain end so that the floating body region may employ good silicon characteristics.
• In one embodiment, sensingline contacts120a˜120cand bitline contacts122a,122bare formed to have a zigzag type arrangement withword lines116 overN+ layer118. In another embodiment, sensingline contacts120a˜120cand bitline contacts122a,122bformed overN+ layer118 are formed alternately betweenword lines116 by a line pattern process.
• Sensingline contacts120a˜120care formed over regions of insulatinglayer110 wherebulk connection silicon104ais not formed.Bit line contacts122a,122bconnected to the bit line are formed over the region ofbulk connection silicon104a.
• Sensinglines124a˜124care formed oversensing line contacts120a˜120c, respectively. Bitline contact pads126a,126bare formed overbit line contacts122a,122b, respectively.
• Bit line contacts128 are formed over bitline contact pads126a,126b, respectively. Abit line130 having a bar type extended length is formed overbit line contacts128.
• In this embodiment, T-shapedsilicon104 may be formed fromsilicon substrate100,bottom word line108 may be formed in the bottom edge region of T-shapedsilicon104, and the 1T-FET type ferroelectric memory cell having a floating channel may be formed oversilicon region112.
• An N-type semiconductor may be used as the drain/source regions, and a P-type semiconductor is used as the channel region of floatingchannel layer104b. Alternatively, a P-type semiconductor may be used as the drain/source regions, and an N-type semiconductor is used as the channel region of floatingchannel layer104b. The semiconductor of floatingchannel layer104bmay include a carbon nano tube, silicon, or germanium (Ge).
• Consistent with an embodiment of the present invention, data is read/written according to a channel resistance of floatingchannel layer104b, which is differentiated depending on polarization states offerroelectric layer114.
• Suppose that the drain and source regions of floatingchannel layer104bare formed to be N-type and the channel region is formed to be P-type. Whenferroelectric layer114 induces positive charges to the channel region of floatingchannel layer104b, the memory cell transitions to a high resistance state so that the channel is turned off. On the other hand, when the polarity offerroelectric layer114 induces negative charges to the channel region, the memory cell transitions to a low resistance state so that the channel is turned on. In this way, polarization states offerroelectric layer114 are selected to write data in the cell. The cell thus become a nonvolatile memory cell.
• FIG. 15 is a cross-sectional diagram illustrating a cell array of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• The cell array includes a plurality of word lines WL and a plurality of sensing lines SL. Word lines WL and sensing lines SL are arranged with a given interval in a row direction. A plurality of bit lines BL are arranged in a column direction so that bit lines BL are crossed with word lines WL and sensing lines SL. A plurality of unit cells C are formed where bit lines BL, word lines WL, and sensing lines SL are crossed.
• Adjacent unit cells C1 and C2 have a common source connected to sensing line SL and a common drain connected to bit line BL. Gates of unit cells C1 and C2 are connected to word lines WL<0>, WL<1> and bottom word lines BWL<0>, BWL<1>.
• A sense amplifier S/A senses and amplifies cell data to distinguish the data “1” from the data “0” so that sense amplifier S/A is connected to bit line BL. When data are written in the memory cell, a write driver W/D is configured to generate a driving voltage depending on write data so as to supply the driving voltage to bit line BL. Write driver W/D is connected to bit line BL. Register REG, which may serve as a temporary memory element for storing data of sense amplifier S/A temporarily, is connected to bit line BL.
• FIG. 16 is a diagram illustrating a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• The nonvolatile ferroelectric memory device ofFIG. 16 is different from that ofFIG. 14 in that abuffer insulating layer132 is formed betweenferroelectric layer114 and floatingchannel layer104b. Buffer insulatinglayer132 is formed in order to overcome difference in processes and materials of floatingchannel layer104bandferroelectric layer114.
• FIG. 17 is a cross-sectional diagram illustrating a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• The nonvolatile ferroelectric memory device ofFIG. 17 is different from that ofFIG. 16 in that a floatingconductive layer134 is formed betweenbuffer insulating layer132 and floatingchannel layer104b. Floatingconductive layer134 is formed in order to protect polarization charges so as to improve data retention characteristics. An insulating layer is formed between floatingconductive layer134 and floatingchannel layer104b, and a buffer layer is formed for electric insulation.
• Data of all cells of the selected row address are read, amplified and stored in a register. Since data “1” is written in all memory cells, it is not known which data are stored in the existing memory cell. As a result, data are stored in order to know which data are stored in the existing memory cell before the data “1” is written in the memory cell.
• The data “1” is written in all cells of the selected row address. The data stored in the register are rewritten and restored in the memory cell so that new external data are written in new cells. As a result, the data “1” is preseved because the data “1” is previously written, and new data is written to data “0” stored in the memory cell.
• FIG. 18 is a diagram illustrating a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• The nonvolatile ferroelectric memory device includes apad array200, arefresh control unit210, arow address register220, a row timinglogic circuit230, arow decoder240, acell array250, a read/write control unit260, acolumn decoder270, acolumn address register280, a columntiming logic circuit290, a refresh information register300, a sense amplifier, register and writedriver310, an input/output logic circuit320, an I/O register330, an I/O buffer340, and I/O pins350.
• Refresh control unit210 includes arefresh controller211 and arefresh counter212.Cell array250 includes a plurality of 1T-FET type unit cells ofFIGS. 2 through 14.
• Pad array200 includes a plurality of pads PAD each of which may be configured to receive a row address and a column address so as to output the addresses with a time variance.Refresh controller211 outputs a refresh signal REF and a refresh enable signal REF_EN for controlling a refresh operation in response to a RAS signal /RAS, a CAS signal /CAS, read/write commands R,/W, and a refresh control signal. Refresh counter212 counts a refresh cycle in response to refresh signal REF applied fromrefresh controller211 and the refresh control signal received from refresh information register300 to output a count address CA.Refresh controller211 and refresh counter212 outputs refresh operation information and refresh count information to refresh information register300
• Row address register220 may receive the row address received frompad array unit200 and stores the address temporarily.Row address register220 outputs row address RADD activated in response to an output signal from row timinglogic circuit230 and a read/write control signal RWCON received from read/write control unit260 intorow decoder240. Rowtiming logic circuit230 controls the storage operation and address output timing ofrow address register220 in response to a RAS signal /RAS.Row decoder240 decodes row address RADD applied fromrow address register220 to output the address tocell array250.
• Read/write control unit260 outputs a read/write control signal RWCON for controlling read/write operations intorow address register220 in response to a RAS signal /RAS, a CAS signal /CAS, and a read/write command R/W so as to controlcolumn decoder270 and sense amplifier, register and writedriver310.
• Column decoder270 decodes the column address applied from column address register280 depending on control of read/write control unit260 to output the address to input/output logic circuit320.Column address register280 may temporarily store the column address received frompad array200 so as to output the address intocolumn decoder270 depending on control of columntiming logic circuit290.
• Columntiming logic circuit290 controls the storage operation and address output timing ofcolumn address register280 in response to CAS signal /CAS.Register310 outputs refresh data to the memory cell depending on control of columntiming logic circuit290 when refresh signal REF is activated.
• Refresh information register300 is a nonvolatile register configured to store parameters related to refresh operations. Refresh information register300 stores refresh count information, power-off timing information of the system or internal memories and other parameter information so as to output a refresh control signal based on the parameter information in the refresh operations. In the power-off timing, information ofrefresh control unit211 and refreshcounter212 is transmitted into refresh information register300, and information related to external commands received from the I/O buffer340 is stored. The information stored in refresh information register300 through I/O buffer340 and I/O pins350 is outputted into asystem controller400.
• Sense amplifier S/A senses and amplifies cell data to distinguish data “1” from data “0”. Write driver W/D generates a driving voltage in response to write data when data are written in the memory cell to supply the driving voltage to the bit line. Register REG may temporarily store data sensed in sense amplifier S/A, and re-stores data in the memory cell in the write operation.
• Input/output logic circuit320 reads data stored incell array250 depending on an output signal fromcolumn decoder270 and read/write commands R and /W, and stores data incell array250. Input/output logic circuit320 includes a column selecting signal C/S, and outputs data stored in cell array150 to data I/O register330 in response to an output enable signal /OE.
• I/O buffer340 buffers read data stored in I/O register330 to output the buffered data into I/O pins350. I/O buffer340 buffers write data received through I/O pins350 to output the buffered data into I/O register330. I/O buffer340 outputs information stored in refresh information register300 intosystem controller400 through I/O pins350. I/O pins350 outputs data received from I/O buffer340 intosystem controller400 through data buses, or outputs data fromsystem controller400 through the data buses into I/O buffer340.
• FIG. 19 is a timing diagram illustrating a read operation of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.FIG. 20 is a timing diagram illustrating a write operation of a nonvolatile ferroelectric memory device using a silicon substrate according to an embodiment consistent with the present invention.
• Pad array200 receives a row address and a column address through a plurality of pads PAD, and outputs the addresses to rowaddress register220 andcolumn address register280.Row address register220 and column address register280 output the row address and the column address with a given time difference depending on control of row timinglogic circuit230 and columntiming logic circuit290.
• Row address register220 stores the row address temporarily in synchronization with RAS signal /RAS, and outputs the row address to rowdecoder240. When the row address is outputted, column address register280 stores the column address temporarily.
• Column address register280 stores the column address temporarily in synchronization with CAS signal /CAS, and outputs the column address tocolumn decoder270. When the column address is outputted, row address register220 stores the row address temporarily.
• In the read mode, when output enable signal /OE is activated while read command R is activated, data stored incell array250 are outputted to the data buses depending on input/output logic circuit320. On the other hand, in the write mode, when output enable signal /OE is inactivated while write command /W is activated, data is stored incell array250 depending on input/output logic circuit320.
• Refresh controller211 outputs refresh signal REF for performing a refresh operation when a refresh operation command is applied. Refresh counter212 counts a refresh cycle in response to refresh signal REF applied fromrefresh controller211 to output a refresh address to rowaddress register220. The refresh address output fromrefresh counter212 is stored inrow address register220. Columntiming logic circuit290 writes refresh data stored in register REG incell array250 in response to CAS signal /CAS.
• Refresh signal REF may be a control signal using RAS signal /RAS and CAS signal /CAS. That is, when refresh signal REF is a control signal using RAS signal /RAS and CAS signal /CAS, the refresh operation is performed with a /CAS before /RAS system (/CSR).
• In a normal mode, RAS signal /RAS is activated earlier than CAS signal /CAS so that a normal operation is performed depending on row timinglogic circuit230 and columntiming logic circuit290.
• In a refresh mode, a signal sensing unit (not shown) senses when CAS signal /CAS is transited earlier than RAS signal /RAS so that refresh signal REF is activated. While a path of the normal operation mode is disconnected, the refresh operation is performed in response to the refresh address generated depending onrefresh counter212. When the simultaneous transition of CAS signal /CAS and RAS signal /RAS is sensed, the refresh signal REF is activated.
• Although the refresh method using /CBR system is exemplified in the embodiment consistent with the present invention, the refresh operation may be performed by various methods with self-refresh, auto-refresh, or clock.
• FIG. 21 is a timing diagram illustrating a refresh method of a nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention.
• Refresh controller111 outputs refresh signal REF for performing a refresh operation intorefresh counter212, and outputs refresh enable signal REF_EN intorow address register220 in response to RAS signal /RAS, CAS signal /CAS, read/write commands R,/W, and the refresh control signal when a refresh operation command is applied. Refresh counter212 counts a refresh cycle in response to refresh signal REF applied fromrefresh controller211 and the refresh control signal to output count address CA to rowaddress register220.
• Count address CA outputted fromrefresh counter212 is stored inrow address register220. Columntiming logic circuit290 outputs data stored in column address register280 intocolumn decoder270 in response to CAS signal /CAS. When sense amplifier S/A is activated, refresh data stored in register REG through input/output logic circuit320 are written incell array250.
• Refresh signal REF may be a control signal using RAS signal /RAS and CAS signal /CAS. That is, when refresh signal REF is a control signal using RAS signal /RAS and CAS signal /CAS, the refresh operation is performed with a /CAS before /RAS system (/CBR).
• In the normal mode for performing read and write operations, RAS signal /RAS is activated earlier than CAS signal /CAS so that a normal operation is performed depending on row timinglogic circuit230 and columntiming logic circuit290. As shown in (A), when RAS signal /RAS is activated earlier, an external row address is activated so that sense amplifier S/A is activated. As shown in (B), when CAS signal /CAS is activated, an external column address is activated.
• In the refresh mode,refresh controller211 senses CAS signal /CAS transited earlier than RAS signal /RAS to activate refresh signal /REF. That is, whenrefresh controller211 senses CAS signal /CAS transited earlier than RAS signal /RAS,refresh controller211 decides the refresh mode to activate refresh enable signal REF_EN.
• Row address register220 performs a refresh operation in response to count address CA generated depending onrefresh counter212 while a path of the normal mode is disconnected when refresh enable signal REF_EN is activated.Row address register220 may sense simultaneous transition of CAS signal /CAS and RAS signal /RAS to activate refresh signal REF.
• Although the refresh method using /CBR system is exemplified in the embodiment consistent with the present invention, the refresh operation may be performed by various methods with self-refresh, auto-refresh, or clock.
• In the refresh mode, a word line WL ofcell array250, which is an output signal ofrefresh counter212, is selected depending on count address CA. As a result, data of the corresponding cell having a 1T structure incell array250 are sensed, amplified, and stored in sense amplifier register REG. New data are written incell array250, or the data stored in register REG are re-stored incell array250.
• FIGS. 22 and 23 are flow charts illustrating a refresh method of a nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention.
• When the power is turned on (S11) while a system power of the DRAM, which is a volatile memory, is turned off (S10), data of the memory are uploaded (S12) so that a new refresh operation starts (S13). That is, when the system power is turned on, data of the memory are required to be uploaded.
• However, in the nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention, when the power is turned on (S21) while the system power is turned off (S20), refresh information register300 decides whether the refresh time is exceeded (S22).
• When the refresh time is exceeded, data of the memory are uploaded (S23) so that a new refresh operation starts (S25). On the other hand, when the refresh time is not exceeded, the refresh time is effective so that the previous refresh operation continues (S24).
• Refresh information register300 stores a parameter related to the refresh operation in a nonvolatile register. Refresh information register300 stores refresh count information, power-off timing information of the system, or internal memories and other parameter information to be nonvolatile. In refresh information register300, an additional power sensing unit (not shown) senses on/off states of the system or the internal memory.
• When the power is off, data stored in refresh information register300 are read to calculate the refresh passing time. The refresh passing time may be stored in a mode register set MRS and controlled in a system level.
• The refresh passing time calculated in response to the refresh control signal is transmitted intorefresh controller211 in response to the refresh control signal. As a result, in one embodiment, it is unnecessary to upload the refresh related information even when the power is on.
• FIG. 24 is a diagram illustrating a refresh method of a nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention. The refresh method includes a distributed refresh method and a burst refresh method.
• In the distributed refresh method, the refresh operation is performed with the same time distribution so that all cells may be refreshed within the refresh time in response to count address CA counted inrefresh counter212. That is, when 8k rows are refreshed, each distributed refresh operation cycle is represented by (refresh time)/8k. As a result, the cell becomes initialized only when data are written in all word lines WL.
• In the burst refresh method, 8k refresh cycles are continuously performed within a burst refresh cycle time. Each pulse means each refresh cycle, and a normal operation is performed in read/write operation cycle periods where the pulse is inactivated.
• FIG. 25 is a diagram illustrating a timer control operation in the refresh method of a nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention.
• Refresh information register300 identifies whether the system power is off, and stores the result (S30). When the power is off, a system timer in the system is used (S31) while an internal memory timer is off so that the refresh operation is controlled (S32). The system timer stores a date and a time with a battery while the power source is required to be on continuously.
• On the other hand, when the power is not off, the internal memory timer operated individually is used (S33) so that the internal refresh operation is controlled (S34).
• One of the external system timer or the internal memory timer is selected depending on on/off states of the power through input/output data pins350. That is, the refresh information register of the memory device including the memory timer exchanges data with the data buses through I/O buffer340 and I/O pins350. The system CPU including the system timers exchanges data with the memory device through the data buses.
• When the power is off through data exchange between the memory device andsystem controller400, the refresh operation is performed with the external system timer whose power is continuously on. When the power is on, the refresh operation is performed with the internal memory timer.
• As a result, the refresh period and the memory data are effectively maintained regardless of on/off state of the power of the memory chip. Between the refresh periods, the memory chip power is turned off to reduce power consumption, and a chip power is supplied only in the refresh period.
• FIG. 26 is a graph illustrating data retention characteristics of a nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention.
• Although the 1T-FET type memory cell of the conventional FeRAM device has nonvolatile characteristics, cell data are degraded as time passes, thereby limiting data retention life. As a result, bit line BL current corresponding cell data “1” and “0” is reduced as time passes.
• However, the refresh operation may be performed with a given cycle at a given timing when bit line BL current is reduced, thereby restoring cell data to improve data retention characteristics.
• When the data retention characteristics of the memory cell are reduced to over a pre-set target value, a refresh circuit is driven to restore the cell data at the initial state. The degradation limit target time of the cell a refresh time so that all cells are operated within the refresh time.
• The above-described FeRAM is operated due to its nonvolatile characteristic unlike the DRAM even when a power source is off. The on/off time of the power source is added and set as the whole data retention time so that the refresh operation is not frequently performed, thereby reducing power consumption and improving operation performance.
• As described above, in a nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention, a refresh operation is performed with a given cycle while data are preserved when a power source is off, so as to restore degraded cell data and improve data retention characteristics. Also, the nonvolatile ferroelectric memory device has the entire data retention time including the on/off time of the power source so that the refresh operation is not frequently performed, thereby reducing power consumption and improving operation performance.
• The foregoing description of various embodiments consistent with the invention has been presented for purposes of illustrating and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. Thus, the embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated.

Claims (24)

1-10. (canceled)

11. A nonvolatile ferroelectric memory device comprising:

a memory cell comprising a silicon substrate including a bottom word line formed therein, a floating channel layer formed over the bottom word line and drain/source regions formed at both ends of the floating channel layer; a ferroelectric layer formed over the floating channel layer; and a word line formed over the ferroelectric layer, the memory cell being configured to induce a different channel resistance to a channel region of the floating channel layer depending on a polarity state of the ferroelectric layer so as to read/write data;

a register configured to store information of the memory cell; and

a refresh control unit configured to perform a refresh operation in a given refresh cycle using the information stored in the register to improve retention characteristics of data stored in the memory cell.

12. The nonvolatile ferroelectric memory device according toclaim 11, wherein the memory cell has a double gate 1T-FET type cell structure.

13. The nonvolatile ferroelectric memory device according toclaim 11, wherein the memory cell comprises:

an insulating layer formed in an etching region of the silicon substrate;

a bottom word line in the insulating layer enclosed by the insulating layer;

a floating channel layer formed over the bottom word line; and

an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate.

14. The nonvolatile ferroelectric memory device according toclaim 13, wherein the silicon substrate is a P-type substrate.

15. The nonvolatile ferroelectric memory device according toclaim 13, wherein the drain region is connected to a bulk connection silicon region, thereby exposing a part of the silicon substrate.

16. The nonvolatile ferroelectric memory device according toclaim 15, wherein the bulk connection silicon region is formed to have substantially the same height as that of the insulating layer.

17. The nonvolatile ferroelectric memory device according toclaim 13, further comprising a sensing line contact and a bit line contact, the sensing line contact and the bit line contact being formed over the impurity layer and arranged alternately with the word line.

18. The nonvolatile ferroelectric memory device according toclaim 13, further comprising a bit line formed over the drain region and at a top side of the silicon substrate where the insulating layer is not formed.

19. The nonvolatile ferroelectric memory device according toclaim 13, further comprising a sensing line formed over the source region and at a top side of the insulating layer where the silicon substrate is not formed.

20. The nonvolatile ferroelectric memory device according toclaim 13, wherein the impurity layer is an N+ layer.

21. The nonvolatile ferroelectric memory device according toclaim 11, further comprising a buffer insulating layer formed between the floating channel layer and the ferroelectric layer.

22. The nonvolatile ferroelectric memory device according toclaim 21, further comprising a floating conductive layer formed between the buffer insulating layer and the floating channel layer.

23. A nonvolatile ferroelectric memory device comprising:

a cell array including a plurality of nonvolatile memory cells, the nonvolatile memory cells being configured to read/write data;

a refresh control unit configured to control a refresh operation in a given cycle in response to a refresh control signal for improving retention characteristics of data stored in the memory cell to output a count address for refresh operations;

a row address control unit configured to latch and decode a row address in response to a RAS signal and an output signal from the refresh control unit and to select the count address in the refresh mode;

a column address control unit configured to latch and decode a column address in response to a CAS signal; and

an input/output logic circuit configured to control read/write operations of the cell array in response to an output enable signal and read/write commands,

wherein the cell array further comprises:

an insulating layer formed in an etching region of a silicon substrate;

a bottom word line formed in the insulating layer and enclosed by the insulating layer;

a floating channel layer formed over the bottom word line;

an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate;

a ferroelectric layer formed over the floating channel layer; and

a word line formed over the ferroelectric layer.

24. The nonvolatile ferroelectric memory device according toclaim 23, wherein the refresh control unit comprises:

a refresh information register configured to store various nonvolatile parameter information for controlling the refresh operation to output a refresh control signal corresponding to the parameter information;

a refresh controller configured to output a refresh signal and a refresh enable signal for performing a refresh operation in response to the refresh control signal; and

a refresh counter configured to count a refresh cycle in response to the refresh signal to output a count address.

25. The nonvolatile ferroelectric memory device according toclaim 23, further comprising a pad array unit configured to selectively output the row address and the column address with a given time difference to the row address control unit and the column address control unit.

26. The nonvolatile ferroelectric memory device according toclaim 25, wherein the row address and the column address are input through the same pad and selectively output with a given time difference.

27. The nonvolatile ferroelectric memory device according toclaim 23, wherein the row address control unit comprises:

a row timing logic circuit configured to control a latch timing of the row address in response to the RAS signal;

a row address register configured to latch the row address depending on control of the row timing logic circuit and to selectively output one of the row address and the count address according to a refresh enable signal; and

a row decoder configured to decode an output signal from the row address register to output the signal to the cell array.

28. The nonvolatile ferroelectric memory device according toclaim 23, wherein the column address control unit comprises:

a column timing logic circuit configured to control the latch timing of the column address in response to the CAS signal;

a column address register configured to latch the column address depending on control of the column timing logic circuit; and

a column decoder configured to decode an output signal from the column address register.

29. The nonvolatile ferroelectric memory device according toclaim 23, wherein the cell array comprises:

a plurality of word lines arranged in a row direction;

a plurality of bottom word lines arranged in parallel with the word lines in the row direction;

a plurality of sensing lines arranged in parallel with the word lines in the row directions;

a plurality of bit lines arranged in a column direction, the bit lines being crossed with the word lines, the bottom word lines and the sensing lines; and

a plurality of unit cells arranged in a region where the word lines, the bottom word lines, the sensing lines, and the bit lines are crossed.

30. The nonvolatile ferroelectric memory device according toclaim 29, wherein the plurality of unit cells share the bit lines and the sensing lines with adjacent unit cells.

31. The nonvolatile ferroelectric memory device according toclaim 29, wherein the plurality of unit cells share one active region, and share bit line contacts and sensing line contacts with adjacent unit cells.

32. The nonvolatile ferroelectric memory device according toclaim 29, wherein the cell array further comprises:

a sense amplifier configured to sense and amplify data of the bit line;

a write driver configured to output a driving voltage for writing the data in the unit cell to the bit line; and

a register configured to store output data of the sense amplifier temporarily.

33-55. (canceled)

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