US20110151676A1 - Methods of thin film process - Google Patents

Abstract

A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 11/947,674, filed Nov. 29, 2007, which claims the benefit of U.S. Provisional Application No. 60/869,066, filed Dec. 7, 2006. This application is also related to the U.S. patent application filed on the same day as the present application having Attorney Docket No. A11598/T76820, titled “Mult-step Dep-Etch-Dep High Aspect Ratio Process for Dielectric Gapfills.” The entire contents of both application are herein incorporated by reference for all purposes.
• This application is related to co-assigned U.S. Provisional Patent Application No. 60/803,499 to Lubomirsky et al, filed May 30, 2006, and titled “PROCESS CHAMBER FOR DIELECTRIC GAPFILL.” This application is related to co-assigned U.S. Pat. No. 6,387,207 to Janakiraman et al., issued May 14, 2002, and titled “INTEGRATION OF REMOTE PLASMA GENERATOR WITH SEMICONDUCTOR PROCESSING CHAMBER.” This application is related to and co-assigned U.S. Pat. No. 6,830,624 to Janakiraman et al., issued Dec. 14, 2004, and titled “BLOCKER PLATE BY-PASS FOR REMOTE PLASMA CLEAN.” This application is also related to co-assigned U.S. Pat. No. 5,558,717 to Zhao et al., and titled “CVD PROCESSING CHAMBER.” The entire contents of both related applications is hereby incorporated by reference for all purposes.
BACKGROUND OF THE INVENTION
• Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produces devices with 250 nm, 180 nm, and 65 nm feature sizes, and new equipment is being developed and implemented to make devices with even smaller geometries. The smaller sizes, however, mean device elements have to work closer together which can increase the chances of electrical interference, including cross-talk and parasitic capacitance.
• To reduce the degree of electrical interference, dielectric insulating materials are used to fill the gaps, trenches, and other spaces between the device elements, metal lines, and other device features. The aspect ratio of a gap is defined by the ratio of the gap's height or depth to its width. These spaces are difficult to fill using conventional CVD methods. A film's ability to completely fill such gaps is referred to as the film's “gapfilling” ability.
• Silicon oxide is one type of insulation film that is commonly used to fill the gaps in intermetal dielectric (IMD) applications, premetal dielectric (PMD) applications and shallow trench isolation (STI) applications among others. Such a silicon oxide film is often referred to as a gapfill film or a gapfill layer.
• Some integrated circuit manufacturers have turned to the use of high density plasma CVD (HDP-CVD) systems to deposit silicon oxide gapfill layers. HDP-CVD systems form a plasma that is approximately two orders of magnitude or greater than the density of a standard, capacitively-coupled plasma CVD system. Examples of HDP-CVD systems include inductively-coupled plasma systems and electron cyclotron resonance (ECR) plasma systems, among others. HDP-CVD systems generally operate at lower pressure ranges than low density plasma systems. The low chamber pressure employed in HDP-CVD systems provides active species having a long mean-free-path and reduced angular distribution. These factors, in combination with the plasma's density, contribute to a significant number of constituents from the plasma reaching even the deepest portions of closely spaced gaps, providing a film with improved gapfill capabilities as compared to films deposited in a low density plasma CVD system.
• Another factor that allows films deposited by HDP-CVD techniques to have improved gapfill characteristics as compared to films deposited by other CVD techniques is the occurrence of sputtering, promoted by the plasma's high density, simultaneous with film deposition. The sputtering element of HDP deposition slows deposition on certain features, such as the corners of raised surfaces, thereby contributing to the increased gapfill ability of IDP deposited films. Some HDP-CVD systems introduce argon or a similar heavy inert gas to further promote the sputtering effect. These HDP-CVD systems typically employ an electrode within the substrate support pedestal that enables the creation of an electric field to bias the plasma toward the substrate. The electric field can be applied throughout the HDP deposition process to generate sputtering and provide better gapfill characteristics for a given film. One HDP-CVD process commonly used to deposit a silicon oxide film forms a plasma from a process gas that includes silane (SiH₄), molecular oxygen (O₂) and argon (Ar).
• However, a limitation associated with sputtering is an angular redistribution of sputtered material. For example, in an STI gapfill, the sputtered SiO₂can be sputtered from above the trench and deposit on the sides of the trench, causing excess buildup, and limiting the opening through which bottom-up gapfill is achieved. If there is too much re-deposition, the trench can close off before the bottom is filled, leaving a buried void within the trench.
BRIEF SUMMARY OF THE INVENTION
• Accordingly to an exemplary embodiment, a method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.
• Accordingly to an exemplary embodiment, forming a plurality of features comprises forming at least a plurality of trenches, conductive lines, openings and transistor gates.
• Accordingly to an exemplary embodiment, forming the first dielectric layer includes forming a silicon oxide layer.
• Accordingly to an exemplary embodiment, interacting the portion of the first dielectric layer with a reactant includes ionizing the first precursor and the second precursor; and interacting the ionized first precursor and the ionized second precursor with the portion of the first dielectric layer.
• Accordingly to an exemplary embodiment, the first precursor is ammonia (NH₃) and the second precursor is nitrogen trifluoride (NF₃).
• Accordingly to an exemplary embodiment, interacting the portion of the first dielectric layer with a reactant includes interacting the portion of the first dielectric layer with the ionized first precursor and the second precursor.
• Accordingly to an exemplary embodiment, the first precursor is nitrogen trifluoride (NF₃) and the second precursor is hydrogen fluoride (HF) or ammonia (NH₃).
• Accordingly to an exemplary embodiment, interacting the portion of the first dielectric layer with a reactant includes interacting the portion of the first dielectric layer with the first precursor and the second precursor.
• Accordingly to an exemplary embodiment, the first precursor is ammonia (NH₃) and the second precursor is hydrogen fluoride (HF).
• Accordingly to an exemplary embodiment, forming the first dielectric layer comprises forming a silicon nitride layer.
• Accordingly to an exemplary embodiment, interacting the portion of the first dielectric layer with a reactant includes ionizing the first precursor and the second precursor; and interacting the portion of the silicon nitride layer with the ionized first precursor and the ionized second precursor.
• Accordingly to an exemplary embodiment, the first precursor is hydrogen (H₂) and the second precursor is nitrogen trifluoride (NF₃).
• Accordingly to an exemplary embodiment, decomposing the first solid product includes thermally treating the first solid product to substantially sublimate the first solid product.
• Accordingly to an exemplary embodiment, the method further includes forming a liner under the first dielectric layer, wherein an etch selectivity of the first dielectric layer to the liner is about 8:1 or more.
• Accordingly to an exemplary embodiment, the method further includes interacting a portion of the liner with a reactant derived from a third precursor and a fourth precursor to generate a second solid product; and decomposing the second solid product to remove the portion of the liner.
• Accordingly to an exemplary embodiment, the method further includes interacting another portion of the first dielectric layer with a reactant derived from a third precursor and a fourth precursor to generate a second solid product; and decomposing the second solid product to remove the another portion of the first dielectric layer.
• Accordingly to an exemplary embodiment, forming the first dielectric layer on the features and within the at least one space has a process pressure of about 600 torr or more.
• Accordingly to an exemplary embodiment, decomposing the first solid product forms an angle between slanted sidewalls of the removed first dielectric layer and a bottom of the removed first dielectric layer about 87° or less.
• Accordingly to an exemplary embodiment, a method for forming a semiconductor structure includes forming a plurality of trenches across a surface of a substrate. A first dielectric layer is formed on and within the trenches. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is thermally treated to substantially sublimate the first solid product to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the spaces.
• Accordingly to exemplary embodiments, the steps in the above-described method may be repeated for one or more additional cycles of etching and depositing dielectric layers. For example, a portion of the second dielectric layer deposited at the end of the above-described method may further interact with the reactant to form a second solid product that is sublimated in a thermal treatment to remove that portion of the second dielectric layer. A third dielectric layer may be formed on the remaining (i.e., non-etched) portion of the second dielectric layer. Additional etching and dielectric deposition cycles may be performed until a final dielectric layer is deposited that substantially fills the remaining spaces (e.g., a dielectric cap layer).
BRIEF DESCRIPTION OF THE DRAWINGS
• A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings wherein like reference numerals are used throughout the several drawings to refer to similar components. In some instances, a sublabel is associated with a reference numeral and follows a hyphen to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sublabel, it is intended to refer to all such multiple similar components.
• FIGS. 1A-1D are schematic drawings showing an exemplary process method for forming an exemplary shallow trench isolation structure.
• FIG. 2 is a schematic drawing showing an exemplary flowchart of forming an exemplary shallow trench isolation structure.
• FIG. 3 is a schematic flowchart of an exemplary process for forming an exemplary trench isolation structure.
• FIG. 4 is a schematic flowchart of an exemplary process for forming an exemplary trench isolation structure.
• FIG. 5A shows a vertical cross-sectional view of an exemplary thin film deposition system.
• FIG. 5B is a simplified diagram of an exemplary system monitor/controller component of a thin film deposition system.
• FIG. 6 is a schematic cross-sectional view of an exemplary etch system.
DETAILED DESCRIPTION OF THE INVENTION
• Systems and methods are described for forming at least one dielectric layer over at least one feature, e.g., transistor gate, formed across a surface of a substrate. A portion of the dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a solid product. The solid product can be decomposed so as to substantially remove the portion of the dielectric layer. Another dielectric layer then may be formed over the etched dielectric layer, such that the aspect ratio gaps and/or trenches may be filled with dielectric materials substantially without gaps or seams.
Exemplary Processes
• FIGS. 1A-1D are schematic drawings showing an exemplary process method for forming an exemplary shallow trench isolation structure.FIG. 2 is a schematic drawing showing an exemplary flowchart of forming an exemplary shallow trench isolation structure.
• Referring toFIG. 1A, at least one feature, such as trenches115, is formed across a surface of asubstrate100. The trenches115 can be, for example, transistors, transistor gates, trenches, openings, gaps, conductive lines or other feature that has an aspect ratio of about 5:1 or more. In some embodiments, the trenches115 can be trenches. The trenches115 can be formed across thesubstrate100. Thesubstrate100 may be a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, an epi-substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. In some embodiments, thesubstrate100 may be a semiconductor wafer (e.g., a 200 mm, 300 mm, 400 mm, etc. silicon wafer).
• Referring toFIG. 2, anexemplary process200 for forming an shallow trench isolation structure can include steps210-250. Step210 can form a plurality of trenches115 across a surface of thesubstrate100.
• Referring again toFIG. 1A, at least one pad dielectric layer105, such as pad oxide, can be formed over thesubstrate100. In some embodiments, at least onepad dielectric layer110, such as pad nitride, can be formed over the pad oxide105. The paddielectric layers105 and110 can be formed, for example, by a chemical vapor deposition (CVD) process, a thermal process and/or other process that can desirably form a dielectric film layer. In some embodiments, the trenches115 can be formed by an etch process which removes portions of the paddielectric layers105,110 and thesubstrate100. In some embodiments, the pad dielectric layer105 is nitride and thepad dielectric layer110 is oxide. In some embodiments, the paddielectric layers105 and110 can be different dielectric materials which have a desired etch selectivity.
• Referring toFIGS. 1B and 2, step220 can form at least one dielectric layer, such as dielectric layer120, over the trenches115. The dielectric layer120 can reduce the dimensions of the trenches115 to those of trenches115a. The dielectric layer120 can include at least one of a silicon oxide layer, a silicon nitride layer, silicon oxynitride layer, a silicon oxycarbide layer and other dielectric layer. In some embodiments, the dielectric layer120 can be thermal CVD oxide, such as high aspect ratio process (HARP) oxide, eHARP oxide, atmosphere pressure CVD (APCVD) oxide, or high temperature undoped silicate glass (HTUSG); high density plasma (HDP) oxide; plasma-enhanced CVD (PECVD) oxide; furnace deposited oxide, such as high temperature oxide, medium temperature oxide or low temperature oxide; atomic layer deposition (ALD) oxide, and other oxide. In some embodiments, the dielectric layer120 can be, for example, PECVD nitride, furnace deposited nitride, HDP nitride, thermal CVD nitride, ALD nitride, and other nitride. In some embodiments, the dielectric layer120 may be referred to as a high aspect ratio process (HARP) liner. In some embodiments, thestep220 may have a process pressure of about 600 torrs or more.
• In some embodiments, the dielectric layer120 may be formed from a silicon-containing precursor such as silane (SiH₄), dichlorosilane (SiH₂Cl₂), tricholorosilane (SiHCl₃), and silicontetrachloride (SiCl₄) and a nitrogen-containing precursor, such as nitrogen (N₂) and ammonia (NH₃). In some embodiments, the dielectric layer125 may be formed from a silicon-containing precursor such as alkoxy disilanes, alkoxy-alkyl disilanes, alkoxy-acetoxy disilanes and polysilanes; and a nitrogen-containing precursor such as nitrogen and ammonia. For example, the alkoxy disilanes may include Si₂(EtO)₆ethoxy disilanes, Si₂(MeO)₆methoxy disilanes, and Si₆(MeO)₁₂methoxy cyclohexylsilanes, where Et denotes ethyl group (C₂H₆) and Me denotes methyl group (CH₃). In some embodiments, the alkoxy-alkyl disilanes may include Si₂(EtO)₄(Me)₂tetraethoxy-dimethyl disilanes, Si₂(EtO)₄(Et)₂tetraethoxy-diethyl disilanes, Si₂(EtO)₂(Me)₄diethoxy-tetramethyl disilanes, Si₂(MeO)₄(Me)₂tetramethoxy-dimethyl disilanes, and Si₄O₂(Me)₈methyl cyclohexylsiloxanes, Si₆(MeO)₆(Me)₆methoxy-methyl cyclohexylsilanes, Si₄O₂(H₂)₄hydro-cyclohexylsiloxanes. In some embodiments, the alkoxy-acetoxy disilanes may include Si₂(AcO)₆acetoxy disilanes, Si₂(Me)₄(AcO)₂tetramethyl-diacetoxy disilanes, and Si₂(Me)₂(AcO)₄dimethyl-tetracetoxy disilanes, where Ac denotes acetyl group. In some embodiments, the polysilanes may include cyclopentylsilanes or other substitutes.
• In some embodiments, the dielectric layer120 can be formed over thepad dielectric layer110, such that the trenches115amay have a top gap smaller than the middle and/or bottom gap of the trenches115a.
• Referring toFIG. 1C, an etch process130 can remove a portion of the dielectric layer120, such that the etcheddielectric layer120acan have tapered sidewalls along thetrenches115b. In some embodiments, the etch process130 can includesteps230, and240 shown inFIG. 2. Step230 may interact a portion of the dielectric layer120 with a reactant to form a solid product. Step240 can decompose the solid product to remove the interacted portion of the dielectric layer120, resulting thedielectric layer120a. Following are exemplary embodiments of the etch process130.
Exemplary Embodiment 1
• In some embodiments, the dielectric layer120 can be a silicon oxide layer. A first precursor can be, for example, hydrogen (H₂), ammonia (NH₃), hydrazine (N₂H₄), hydrazoic acid (HN₃), other hydrogen-containing precursor and various combinations thereof. A second precursor can be, for example, nitrogen trifluoride (NF₃), silicon tetrafluorid (SiF₄), tetrafluoromethane (CF₄), fluoromethane (CH₃F), difluoromethane (CH₂F₂), trifluoromethane (CHF₃), octafluoropropane (C₃F₈), hexafluoroethane (C₂F₆), other fluorine-containing precursor or various combinations thereof. In some embodiments, the first precursor such as ammonia (NH₃) and the second precursor such as nitrogen trifluoride (NF₃) can be ionized as a plasma. In some embodiments, the ionization process can be performed within the chamber that deposits the dielectric layer120. In some embodiments, the ionization process can be occurred externally and then introduced into the chamber that deposits the dielectric layer120. In some embodiments, the etch process130 can be performed within an etch chamber different from the deposition chamber. In some embodiments, the etch process130 may form an angle between slanted sidewalls of thetrenches115band a bottom of thetrenches115babout 87° or less.
• In some embodiments, NH₃may have a flow rate between about 10 standard cubic centimeter per minute (sccm) and about 1,000 sccm. In some embodiments, NH₃may have a flow rate of about 100 sccm. NF₃can have a flow rate between about 10 sccm and about 1,000 sccm. In some embodiments, NF₃may have a flow rate of about 100 sccm. The process temperature can be between about 0° C. and about 80° C. In some embodiment, the process temperature can be about 30° C. The process pressure can be between about 1 millitorr (mTorr) and about 1 atm. In some embodiments, the process pressure can be 3 Tons. The plasma power can be between about 10 Watts and about 2,000 Watts. In some embodiments, the plasma power can be about 45 Watts. The interaction of plasma of NH₃and NF₃can be represented by the formula described below:
• 
  NH_3(g)+NF_3(g)→NH₄F_(s)and/or NH₄F_y.HF_(s)
• The reactant, NH₄F_(s)and/or NH₄F_y.HF_(s), then can be introduced to interact with a portion of the silicon oxide layer. The reactant, NH₄F_(s)and/or NH₄F_y.HF_(s), may interact with silicon oxide to form a solid product, e.g., (NF₄)₂SiF₆. In some embodiments, thesubstrate100 is disposed over a pedestal having a temperature between about −100° C. and about 1,000° C. (e.g., about −50° C. to about 200° C.). In other embodiments, the pedestal may have a temperature of about 30° C. The temperature of the pedestal may desirably enhance the interaction of the plasma and silicon nitride. The interaction of the silicon oxide and the reactant, NH₄F_(s)and/or NH₄F_y.HF_(s), can be described as the following formula:
• 
  NH₄F_(s)and/or NH₄F_y.HF_(s)+SiO_2(s)→(NF₄)₂SiF_6(s)+H₂O
• Referring again toFIG. 2, step240 can decompose the solid product, (NF₄)₂SiF₆. In some embodiments, step240 can include thermally treating the solid product to substantially sublimate the solid product (NF₄)₂SiF₆. In some embodiments, the thermal process may be carried out by approaching the solid product (NF₄)₂SiF₆to a showerhead, which may be operative to provide a process temperature between about −100° C. and about 1,000° C. (e.g., about −50° C. to about 200° C.). In an embodiment, the process temperature is about 180° C. In other embodiments, the thermal process may be carried out by, for example, an oven, a furnace, a rapid thermal anneal (RTA) apparatus, or other thermal apparatus. The decomposition and/or sublimation of the solid product (NF₄)₂SiF₆may be described as the following formula:
• 
  (NF₄)₂SiF_6(s)→SiF_4(g)+NH_3(g)+HF_(g)
• Additional embodiments of a method to remove the solid product may include the steps of rinsing the product containing substrate with an aqueous solution (e.g., purified water) in lieu of sublimating the product with a thermal treatment. The substrate may also be rinsed with a polar solvent such as ethanol or glycol in lieu of (or in addition to) the aqueous solution rinse.
Exemplary Embodiment 2
• In some embodiments, the dielectric layer120 can be a silicon oxide layer. A first precursor can be, for example, hydrogen (H₂), ammonia (NH₃), hydrazine (N₂H₄), hydrazoic acid (HN₃), other hydrogen-containing precursor and various combinations thereof. A second precursor can be, for example, hydrogen fluoride (HF), nitrogen trifluoride (NF₃), silicon tetrafluorid (SiF₄), tetrafluoromethane (CF₄), fluoromethane (CH₃F), difluoromethane (CH₂F₂), trifluoromethane (CHF₃), octafluoropropane (C₃F₈), hexafluoroethane (C₂F₆), other fluorine-containing precursor or various combinations thereof. In some embodiments, the first precursor such as ammonia (NH₃) and the second precursor such as hydrogen fluoride (HF) can be used to interact with the dielectric layer120. In some embodiments, NH₃and HF can be introduced within the chamber that deposits the dielectric layer120. In some embodiments, NH₃and HF can be introduced within an etch chamber different from the deposition chamber so as to interact with the dielectric layer120.
• In some embodiments, NH₃may have a flow rate between about 10 standard cubic centimeter per minute (sccm) and about 1,000 sccm. In some embodiments, NH₃may have a flow rate of about 100 sccm. HF can have a flow rate between about 10 sccm and about 2,000 sccm. In some embodiments, HF may have a flow rate of about 200 sccm. The process temperature can be between about 0° C. and about 80° C. In some embodiment, the process temperature can be about 30° C. The process pressure can be between about 1 millitorr (mTorr) and about 1 atm. In some embodiments, the process pressure can be 3 Tons. The interaction of NH₃and HF may be represented as the formula described below:
• 
  NH_3(g)+HF_(g)→NH₄F_(s)and/or NH₄F_y.HF_(s)
• In some embodiments, NH₃and HF can be introduced into the chamber for interacting with a portion of the silicon oxide layer. NH₃and HF may interact with silicon oxide to form a solid product, e.g., (NF₄)₂SiF_6(s). In some embodiments, thesubstrate100 is disposed over a pedestal having a temperature between about −100° C. and about 1,000° C. (e.g., about −50° C. to about 200° C.). In other embodiments, the pedestal may have a temperature of about 30° C. The temperature of the pedestal may desirably enhance the interaction of the plasma and silicon nitride. The interaction of the silicon oxide and the plasma can be described as the following formula:
• 
  NH₄F_(s)and/or NH₄F_y.HF_(s)+SiO_2(s)→(NF₄)₂SiF_6(s)+H₂O
• Referring again toFIG. 2, step240 can decompose the solid product, (NF₄)₂SiF₆. In some embodiments, step240 can include thermally treating the solid product to substantially sublimate the solid product (NF₄)₂SiF₆. In some embodiments, the thermal process may be carried out by approaching the solid product (NF₄)₂SiF₆to a showerhead, which may be operative to provide a process temperature between about −100° C. and about 1,000° C. (e.g., about −50° C. to about 200° C.). In an embodiment, the process temperature is about 180° C. In other embodiments, the thermal process may be carried out by, for example, an oven, a furnace, a rapid thermal anneal (RTA) apparatus, or other thermal apparatus. The decomposition and/or sublimation of the solid product (NF₄)₂SiF₆may be described as the following formula:
• 
  (NF₄)₂SiF_6(s)→SiF_4(g)+NH_3(g)+HF_(g)
• As noted above additional embodiments of the method to remove the solid product may include the step of rinsing the product containing substrate with an aqueous solution (e.g., purified water) in lieu of (or in addition to) sublimating the product with a thermal treatment. The substrate may also be rinsed with a polar solvent such as ethanol or glycol in lieu of (or in addition to) the aqueous solution rinse.
Exemplary Embodiment 3
• In some embodiments, the dielectric layer120 can be a silicon nitride layer. A first precursor can be, for example, hydrogen (H₂), ammonia (NH₃), hydrazine (N₂H₄), hydrazoic acid (HN₃), other hydrogen-containing precursor and various combinations thereof. A second precursor can be, for example, hydrogen fluoride (HF), nitrogen trifluoride (NF₃), silicon tetrafluorid (SiF₄), tetrafluoromethane (CF₄), fluoromethane (CH₃F), difluoromethane (CH₂F₂), trifluoromethane (CHF₃), octafluoropropane (C₃F₈), hexafluoroethane (C₂F₆), other fluorine-containing precursor or various combinations thereof. A first precursor such as hydrogen (H₂) and a second precursor such as nitrogen trifluoride (NF₃) can be ionized as a plasma. In some embodiments, the ionization process can be occurred within the chamber that deposits the dielectric layer120. In some embodiments, the ionization process can be occurred externally and then introduced into the chamber that deposits the dielectric layer120. In some embodiments, the etch process130 can be performed within an etch chamber different from the deposition chamber.
• In some embodiments, NF₃may have a flow rate between about 10 standard cubic centimeter per minute (sccm) and about 1,000 sccm. In some embodiments, NF₃may have a flow rate of about 100 sccm. H₂can have a flow rate between about 10 sccm and about 3,000 sccm. In some embodiments, H₂may have a flow rate of about 600 sccm. The process temperature can be between about 0° C. and about 80° C. In some embodiment, the process temperature can be about 30° C. The process pressure can be between about 1 millitorr (mTorr) and about 1 atm. In some embodiments, the process pressure can be 3 Torrs. The plasma power can be between about 10 Watts and about 2,000 Watts. In some embodiments, the plasma power can be about 45 Watts.
• The plasma then may be introduced into the chamber for etching portions of the silicon oxide layer. The remote-generated plasmas may interact with silicon oxide to form a solid product, e.g., (NF₄)₂SiF₆. In some embodiments, thesubstrate100 is disposed over a pedestal having a temperature between about −100° C. and about 1,000° C. (e.g., about −50° C. to about 200° C.). In other embodiments, the pedestal may have a temperature of about 30° C. The temperature of the pedestal may desirably enhance the interaction of the plasma and silicon nitride. The interaction of the silicon oxide and the plasma can be described as the following formula:
• 
  NF_3(g)+H_2(g)+Si₃N₄→(NF₄)₂SiF_6(s)
• Referring again toFIG. 2, step240 can decompose the solid product, (NF₄)₂SiF₆. In some embodiments, step240 can include thermally treating the solid product to substantially sublimate the solid product (NF₄)₂SiF₆. In some embodiments, the thermal process may be carried out by approaching the solid product (NF₄)₂SiF₆to a showerhead, which may be operative to provide a process temperature between about −50° C. and about 1,000° C. In an embodiment, the process temperature is about 180° C. In other embodiments, the thermal process may be carried out by, for example, an oven, a furnace, a rapid thermal anneal (RTA) apparatus, or other thermal apparatus. The decomposition and/or sublimation of the solid product (NF₄)₂SiF₆may be described as the following formula:
• 
  (NF₄)₂SiF_6(s)→SiF_4(g)+NH_3(g)+HF_(g)
• As noted above additional embodiments of the method to remove the solid product may include the step of rinsing the product containing substrate with an aqueous solution (e.g., purified water) in lieu of (or in addition to) sublimating the product with a thermal treatment. The substrate may also be rinsed with a polar solvent such as ethanol or glycol in lieu of (or in addition to) the aqueous solution rinse.
• Referring again toFIG. 1C, the pinch-off and the negative profile of the dielectric layer120 may be substantially eliminated. The etcheddielectric layer120amay have a desired profile, such that a subsequent dielectric layer such as dielectric layer140 (shown inFIG. 1D) can be desirably formed within thetrenches115b.
• Referring toFIGS. 1D and 2, step250 can form adielectric layer140 over the etcheddielectric layer120a. Thedielectric layer140 may be formed of, for example, oxide, nitride, oxynitride, low-k dielectric material, ultra low-k dielectric material, other dielectric material or various combinations thereof. Thedielectric layer140 may be formed by, for example, a CVD process, a spin-coating process, other method that is adapted to form a dielectric layer or various combinations thereof. In some embodiments, thedielectric layer140 can be thermal CVD oxide, such as high aspect ratio process (HARP) oxide, eHARP oxide, atmosphere pressure CVD (APCVD) oxide, or high temperature undoped silicate glass (HTUSG), high density plasma (HDP) oxide, plasma-enhanced CVD (PECVD) oxide, furnace deposited oxide, such as high temperature oxide, medium temperature oxide or low temperature oxide, atomic layer deposition (ALD) oxide, and other oxide. In some embodiments, thedielectric layer140 can be, for example, PECVD nitride, furnace deposited nitride, HDP nitride, thermal CVD nitride, ALD nitride, and other nitride. In some embodiments, thedielectric layer140 may be referred to as a high aspect ratio process (HARP) cap layer. Since the pinch-off and negative profile of the dielectric layer120 (shown inFIG. 1B) is substantially removed, thedielectric layer140 may be desirably filled within the gap between the etcheddielectric layer120a.
• In some embodiments, an etch-back process and/or chemical mechanical planarization (CMP) process is performed to substantially planarize the top surface of thedielectric layer140.
• FIG. 3 is a schematic flowchart of an exemplary process for forming an exemplary trench isolation structure. Inprocess300,steps310,320,330,340, and350 are similar tosteps210,220,230,240, and250 described above in conjunction withFIG. 2, respectively.
• InFIG. 3, step312 may form a liner before forming the dielectric layer120. In some embodiments, the liner can include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbide layer and other dielectric layer. In some embodiments, an etch process may have an etch selectivity of the dielectric layer120 to the liner about 8:1 or more.
• In some embodiments, the liner is oxide and the dielectric layer120 is nitride. For embodiments using plasma reaction, the etch selectivity of the dielectric layer120 to the liner can be modified by changing process temperatures, plasma powers, NF₃flow rates, NH₃flow rates and/or process pressure. For embodiments without using plasma reaction, the etch selectivity of the dielectric layer120 to the liner can be modified by changing process temperatures, NH₃flow rates, HF flow rates and/or process pressure.
• In some embodiments, the liner is nitride and the dielectric layer120 is oxide. For embodiments using plasma reaction, the etch selectivity of the dielectric layer120 to the liner can be modified by changing process temperatures, plasma powers, NF₃flow rates, H₂flow rates and/or process pressure.
• Referring again toFIG. 3, step314 can interact the liner with a reactant derived from a third precursor and a fourth precursor to form a solid product. In some embodiments, step314 can be similar to step230 set forth above in conjunction withFIG. 2. Step316 can decompose the solid product to remove a portion of the liner. In some embodiments, step316 can be similar to step240 described above in conjunction withFIG. 2.
• In some embodiments,steps314, and316 can remove a portion of the liner, such that the etched liner may provide a desired profile over which the dielectric layer120 (shown inFIG. 1A) can be formed. By usingsteps314, and316 to etch a portion of the liner, the pinch-off and the negative profile of the dielectric layer120 may be desirably eliminated.
• FIG. 4 is a schematic flowchart of an exemplary process for forming an exemplary trench isolation structure. Inprocess400,steps410,420,430,440, and450 are similar tosteps210,220,230,240, and250 described above in conjunction withFIG. 2, respectively.
• InFIG. 4, step442 can interact another portion of the etcheddielectric layer120awith a reactant derived from a third precursor and a fourth precursor to form a solid product. In some embodiments,step442 may be similar to step230 described above in conjunction withFIG. 2. Step444 can decompose the solid product to remove the interacting portion of the etcheddielectric layer120a. In some embodiments, step444 may be similar to step240 described above in conjunction withFIG. 2.
• In some embodiments,steps442, and444 can remove a portion of the etcheddielectric layer120a, such that the etcheddielectric layer120amay provide a desired profile over which the dielectric layer140 (shown inFIG. 1A) can be formed. By usingsteps442, and444 to etch a portion of the etcheddielectric layer120a, the pinch-off and the negative profile of the dielectric layer120 can be desirably eliminated. In some embodiments,steps442, and444 can be repeated for one or more times to achieve a desired profile of the etcheddielectric layer120a.
• It is noted that the present invention is not limited to the embodiments described above in conjunction withFIGS. 1A-1D and2-4. Other methods for desirably filling dielectric layers within gaps or openings of semiconductor substrates can be modified based on the exemplary embodiments set forth above. For example, steps312-316 shown inFIG. 3 may be incorporated with steps442-444 shown inFIG. 4 to desirably fill dielectric layers within gaps or openings of semiconductor substrates.
Exemplary Film Deposition System
• Deposition systems that may deposit a dielectric layer may include high-density plasma chemical vapor deposition (HDP-CVD) systems, plasma enhanced chemical vapor deposition (PECVD) systems, sub-atmospheric chemical vapor deposition (SACVD) systems, and thermal chemical vapor deposition systems, among other types of systems. Specific examples of CVD systems that may implement embodiments of the invention include the CENTURA ULTIMA™ HDP-CVD chambers/systems, and PRODUCER™ PECVD chambers/systems such as PRODUCER™ Celera™ PECVD, available from Applied Materials, Inc. of Santa Clara, Calif.
• Examples of substrate processing systems that can be used with exemplary methods of the invention may include those shown and described in co-assigned U.S. Provisional Patent App. No. 60/803,499 to Lubomirsky et al, filed May 30, 2006, and titled “PROCESS CHAMBER FOR DIELECTRIC GAPFILL,” the entire contents of which is herein incorporated by reference for all purposes. Additional exemplary systems may include those shown and described in U.S. Pat. Nos. 6,387,207 and 6,830,624, which are also incorporated herein by reference for all purposes.
• Referring now toFIG. 5A, vertical cross-sectional views of aCVD system10 is shown that has a vacuum or processing chamber15 that includes a chamber wall15aand a chamber lid assembly15b. TheCVD system10 may contain a gas distribution manifold11 for dispersing process gases to a substrate (not shown) that can rest on aheated pedestal12 centered within the process chamber15. Gas distribution manifold11 may be formed from an electrically conducting material in order to serve as an electrode for forming a capacitive plasma. During processing, the substrate (e.g. a semiconductor wafer) can be positioned on a flat (or slightly convex) surface12aof thepedestal12. Thepedestal12 can be moved controllably between a lower loading/off-loading position (depicted inFIG. 5A) and an upper processing position (indicated by dashed line14 inFIG. 5A), which is closely adjacent to the manifold11. A centerboard (not shown) may include sensors for providing information on the position of the wafers.
• Deposition and carrier gases can be introduced into the chamber15 through perforated holes of a conventional flat, circular gas distribution faceplate13a. In some embodiments, deposition process gases can flow into the chamber through the inlet manifold11, through a conventional perforated blocker plate and then through holes in gas distribution faceplate13a.
• Before reaching the manifold11, deposition and carrier gases can be input from gas sources through gas supply lines into a mixing system where they can be combined and then sent to manifold11. In some embodiments, the supply line for each process gas can include (i) several safety shut-off valves (not shown) that can be used to automatically or manually shut-off the flow of process gas into the chamber, and (ii) mass flow controllers (also not shown) that measure the flow of gas through the supply line. When toxic gases are used in the process, the several safety shut-off valves are positioned on each gas supply line in conventional configurations.
• The deposition process performed in theCVD system10 can be a thermal process and/or a plasma-enhanced process. In a plasma-enhanced process, an RF power supply can apply electrical power between the gas distribution faceplate13aand thepedestal12 so as to excite the process gas mixture to form a plasma within the cylindrical region between the faceplate13aand thepedestal12. (This region will be referred to herein as the “reaction region”). Constituents of the plasma react to deposit a desired film on the surface of the semiconductor wafer supported onpedestal12. RF power supply can be a mixed frequency RF power supply that typically supplies power at a high RF frequency (RF1) of 13.56 MHz and at a low RF frequency (RF2) of 360 KHz to enhance the decomposition of reactive species introduced into the vacuum chamber15. In a thermal process, the RF power supply44 would not be utilized, and the process gas mixture can thermally react to deposit the desired films on the surface of the semiconductor wafer supported on thepedestal12, which is resistively heated to provide thermal energy for the reaction.
• During a plasma-enhanced deposition process, the plasma can heat theentire process chamber10, including the walls of the chamber body15asurrounding theexhaust passageway23 and the shut-offvalve24. When the plasma is not turned on or during a thermal deposition process, a hot liquid is circulated through the walls15aof the process chamber15 to maintain the chamber at an elevated temperature. The passages in the remainder of the chamber walls15aare not shown. Fluids used to heat the chamber walls15acan include the typical fluid types, i.e., water-based ethylene glycol or oil-based thermal transfer fluids. This heating (referred to as heating by the “heat exchanger”) can desirably reduce and/or eliminate condensation of undesirable reactant products and improve the elimination of volatile products of the process gases and other contaminants that might contaminate the process if they were to condense on the walls of cool vacuum passages and migrate back into the processing chamber during periods of no gas flow.
• The remainder of the gas mixture that is not deposited in a layer, including reaction byproducts, is evacuated from the chamber15 by a vacuum pump (not shown). In some embodiments, the gases can be exhausted through an annular, slot-shaped orifice16 surrounding the reaction region and into an annular exhaust plenum17. The annular slot16 and the plenum17 can be defined by the gap between the top of the chamber's cylindrical side wall15a(including the upper dielectric lining19 on the wall) and the bottom of thecircular chamber lid20. The 360.degree. circular symmetry and uniformity of the slot orifice16 and the plenum17 can be configured to achieve a uniform flow of process gases over the wafer so as to deposit a uniform film on the wafer.
• From the exhaust plenum17, the gases may flow underneath a lateral extension portion21 of the exhaust plenum17, past a viewing port (not shown), through a downward-extendinggas passage23, past a vacuum shut-off valve24 (whose body is integrated with the lower chamber wall15a), and into the exhaust outlet25 that connects to the external vacuum pump (not shown) through a foreline (also not shown).
• The wafer support platter of the pedestal12 (preferably aluminum, ceramic, or a combination thereof) can be resistively heated using an embedded single-loop embedded heater element configured to make two full turns in the form of parallel concentric circles. An outer portion of the heater element can run adjacent to a perimeter of the support platter, while an inner portion runs on the path of a concentric circle having a smaller radius. The wiring to the heater element can pass through the stem of thepedestal12.
• Typically, any or all of the chamber lining, gas inlet manifold faceplate, and various other reactor hardware can be made out of material such as aluminum, anodized aluminum, or ceramic. An example of such a CVD apparatus is described in co-assigned U.S. Pat. No. 5,558,717 entitled “CVD Processing Chamber,” issued to Zhao et al, and hereby incorporated by reference in its entirety.
• A lift mechanism and motor32 (FIG. 5A) can raise and/or lower theheater pedestal assembly12 and its wafer lift pins12bas wafers are transferred into and out of the body of the chamber15 by a robot blade (not shown) through an insertion/removal opening26 in the side of thechamber10. The motor32 can raise and/orlower pedestal12 between a processing position14 and a lower, wafer-loading position. The motor, valves or flow controllers connected to the supply lines, gas delivery system, throttle valve, RF power supply, and chamber and substrate heating systems can be controlled by a system controller over control lines, of which only some are shown. Controller can rely on feedback from optical sensors to determine the position of movable mechanical assemblies such as the throttle valve and susceptor which are moved by appropriate motors under the control of controller.
• In the exemplary embodiment, the system controller can include a hard disk drive (memory), a floppy disk drive and a processor. The processor may contain a single-board computer (SBC), analog and digital input/output boards, interface boards and stepper motor controller boards. Various parts ofCVD system10 can conform to the Versa Modular European (VME) standard which defines board, card cage, and connector dimensions and types. The VME standard can define the bus structure as having a 16-bit data bus and a 24-bit address bus.
• System controller can control the activities of the CVD machine. The system controller executes system can control software, which is a computer program stored in a computer-readable medium such as a memory. In some embodiments, the memory can be a hard disk drive or other kinds of memory. The computer program can include sets of instructions that dictate the timing, mixture of gases, chamber pressure, chamber temperature, RF power levels, susceptor position, and other parameters of a particular process. Other computer programs stored on other memory devices including, for example, a floppy disk or other another appropriate drive, may also be used to operate controller.
• A process for depositing a film on a substrate or a process for cleaning the chamber15 can be implemented using a computer program product that is executed by the controller. The computer program code can be written in any conventional computer readable programming language: for example, 68000 assembly language, C, C++, Pascal, Fortran or others. Suitable program code is entered into a single file, or multiple files, using a conventional text editor, and stored or embodied in a computer usable medium, such as a memory system of the computer. If the entered code text is in a high level language, the code is compiled, and the resultant compiler code is then linked with an object code of precompiled Microsoft Windows® library routines. To execute the linked, compiled object code the system user invokes the object code, causing the computer system to load the code in memory. The CPU then reads and executes the code to perform the tasks identified in the program.
• The interface between a user and the controller34 can be via a CRT monitor50aand light pen50b, shown inFIG. 5B, which can be a simplified diagram of the system monitor andCVD system10 in a substrate processing system, which may include one or more chambers. In some embodiments, two monitors50acan be used, one mounted in the clean room wall for the operators and the other behind the wall for the service technicians. The monitors50acan simultaneously display the same information. In some embodiments, only one light pen50bmay be enabled. A light sensor in the tip of light pen50bcan detect light emitted by CRT display. To select a particular screen or function, the operator can touch a designated area of the display screen and pushes the button on the pen50b. The touched area can change its highlighted color, or a new menu or screen is displayed, confirming communication between the light pen and the display screen. Other devices, such as a keyboard, mouse, or other pointing or communication device, may be used instead of or in addition to light pen50bto allow the user to communicate with controller34.
• FIG. 5A shows a remote plasma generator60 mounted on the lid assembly15bof the process chamber15 including the gas distribution faceplate13aand the gas distribution manifold11. A mountingadaptor64 can mount the remote plasma generator60 on the lid assembly15b, as best seen inFIG. 5A. Theadaptor64 can be made of metal. Theadaptor64 may include a hole95, which is coupled to a ceramic isolator66. A mixing device70 may be coupled to the upstream side of the gas distribution manifold11 (FIG. 5A). The mixing device70 can include a mixing insert72 disposed inside a slot of a mixing block for mixing process gases. The ceramic isolator66 can be placed between the mountingadaptor64 and the mixing device70 (FIG. 5A). The ceramic isolator66 may be made of a ceramic material such as Al₂O₃(99% purity), Teflon®, or the like. When installed, the mixing device70 and ceramic isolator66 may form part of the lid assembly15b. The isolator66 can isolate themetal adaptor64 from the mixing device70 and gas distribution manifold11 to minimize the potential for a secondary plasma to form in the lid assembly15bas discussed in more detail below. A three-way valve can control the flow of the process gases to the process chamber15 either directly or through the remote plasma generator60.
• The remote plasma generator60 can be desirably a compact, self-contained unit that can be conveniently mounted on the lid assembly15band be easily retrofitted onto existing chambers without costly and time-consuming modifications. One suitable unit can be the ASTRON® generator available from Applied Science and Technology, Inc. of Woburn, Mass. The ASTRON® generator utilizes a low-field toroidal plasma to dissociate a process gas. In one example, the plasma dissociates a process gas including a fluorine-containing gas such as NF₃and a carrier gas such as argon to generate free fluorine which is used to clean film deposits in the process chamber15.
Exemplary Etch System
• Etch systems that may implement an etch process may include, for example, a SiConi™ Preclean chamber/system, available from Applied Materials, Inc. of Santa Clara, Calif.
• FIG. 6 is a schematic cross-sectional view of an exemplary etch chamber. Theetch chamber600 may include achamber wall630. Theetch chamber600 may include a plasma distribution apparatus610 such as a tube, pipe and/or manifold for dispersing a process plasma615 to thesubstrate100 that rests on apedestal620 centered within the process chamber. Theetch chamber600 may be coupled to aplasma generator605 through the plasma distribution apparatus610. Theplasma generator605 is configured to generate the plasma615. Thesubstrate100 may be moved controllably between a lower position/upper position near to a showerhead650 bypins640. Thesubstrate100 may have the trenches115 and the dielectric layer120 (shown inFIG. 1B) formed thereover.
• In some embodiments, the plasma distribution apparatus610 may introduce the plasmas615 generated by, for example, steps230,330,430,314, and442 described above in connection withFIGS. 2-4, into theprocessing chamber600. In some embodiments, the supply line for the etch plasmas615 may include (i) several safety shut-off valves (not shown) that can be used to automatically or manually shut-off the flow of process plasmas into the chamber, and (ii) mass flow controllers (not shown) that measure the flow of the plasmas615 through the supply line.
• Referring again toFIG. 6, thechamber wall630 may have a temperature to substantially prevent condensations of etchants and/or byproducts thereon. In some embodiments, thepedestal620 may be operative to provide a desired temperature between about −100° C. and about 1,000° C. (e.g., about −50° C. to about 200° C.) to condense etchants on the surface of thesubstrate100, i.e., the dielectric layer120 over thesubstrate100. The etchants then may desirably interact with the dielectric layer120 formed over thesubstrate100 so as to generate the solid product described above in conjunction withFIG. 2-4. After the generation of the byproduct, pins640 may lift thesubstrate100 approaching the showerhead650. The showerhead650 may be operative to provide a process temperature between about −50° C. and about 1,000° C. In some embodiments, the showerhead650 may performsteps240,340,440,316, and444 described above in conjunction withFIGS. 2-4 to decompose and/or sublimate the solid product to remove the portions of the dielectric layer120 and liner.
• Referring again toFIG. 6, at least onepumping channel660 may be configured within theetch chamber600 to desirably remove the byproducts and/or the decomposed gases. The pumpingchannel660 may be coupled to, for example, a pump or motor, such that the byproducts may be desirably removed. In some embodiments, the pumpingchannel660 may have at least one aperture (not shown) through which the byproducts can be desirably removed.
• In some embodiments, an RF power supply (not shown) may be coupled to theplasma generator605 to excite a process gas including a fluorine-containing precursor and a hydrogen-containing precursor to form the plasma615. The RF power supply may be operative to provide a RF power between about 5 watts and about 3,000 watts. The RF power supply may supply the power at a RF frequency between about 100 kHz and about 64 MHz.
• system controller (not shown) may controls all of the activities of the etch system. The system controller executes system control software, which is a computer program stored in a computer-readable medium such as a memory. In some embodiments, the memory is a hard disk drive, but the memory may also be other kinds of memory. The computer program includes sets of instructions that dictate the timing, mixture of gases, chamber pressure, chamber temperature and other parameters of a particular process. Other computer programs stored on other memory devices including, for example, a floppy disk or other another appropriate drive, may also be used to operate controller.
• A process for etching portions of a film over a substrate can be implemented using a computer program product that is executed by the controller described above. The computer program code can be written in any conventional computer readable programming language: for example, 68000 assembly language, C, C++, Pascal, Fortran or others. Suitable program code is entered into a single file, or multiple files, using a conventional text editor, and stored or embodied in a computer usable medium, such as a memory system of the computer. If the entered code text is in a high level language, the code is compiled, and the resultant compiler code is then linked with an object code of precompiled Microsoft Windows® library routines. To execute the linked, compiled object code the system user invokes the object code, causing the computer system to load the code in memory. The CPU then reads and executes the code to perform the tasks identified in the program.
• Having described several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. Additionally, a number of well known processes and elements have not been described in order to avoid unnecessarily obscuring the present invention. Accordingly, the above description should not be taken as limiting the scope of the invention.
• Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.
• As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a method” includes a plurality of such methods and reference to “the precursor” includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.
• Also, the words “comprise,” “comprising,” “include,” “including,” and “includes” when used in this specification and in the following claims are intended to specify the presence of stated features, integers, components, or steps, but they do not preclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims (20)

1. A method of fabricating a semiconductor structure, the method comprising:

providing a substrate having a least one trench between two or more adjacent features;

depositing a first layer comprising silicon oxide within at least a portion of the trench;

reacting at least a portion of the first layer with reactive species from a reactant gas mixture comprising a fluorine-containing gas and a reducing gas, wherein the reaction forms a solid product comprising materials from the first layer and the reactive species;

sublimating the solid product from the substrate to leave a remaining portion of the first layer; and

depositing a second layer comprising a dielectric material on at least a part of the remaining portion of the first layer.

2. The method ofclaim 1, wherein semiconductor substrate comprises a semiconductor wafer.

3. The method ofclaim 2, wherein the semiconductor substrate comprises a plurality of semiconductor wafers.

4. The method ofclaim 1, wherein fluorine-containing gas comprises hydrogen fluoride.

5. The method ofclaim 1, wherein the fluorine-containing gas comprises nitrogen trifluoride.

6. The method ofclaim 1, wherein the reducing gas comprises ammonia.

7. The method ofclaim 1, wherein the solid product comprises an ammonia fluorosilicate.

8. The method ofclaim 7, wherein the solid product comprises (NF₄)₂SiF₆.

9. The method ofclaim 1, wherein the second layer comprises a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric material, and an ultra low-κ dielectric material.

10. The method ofclaim 1, wherein the first layer is deposited by a process selected from the group consisting of a spin-coating process, a high aspect ratio process, an e-HARP process, an APCVD process, a HTUSG process, an HDP-CVD process, an PECVD process, a furnace deposited oxide process, and an atomic layer deposition process.

11. The method ofclaim 1, wherein the second layer is deposited by a process selected from the group consisting of a spin-coating process, a high aspect ratio process, an e-HARP process, an APCVD process, a HTUSG process, an HDP-CVD process, an PECVD process, a furnace deposited oxide process, and an atomic layer deposition process.

12. A method of fabricating a semiconductor structure, the method comprising:

providing one or more wafer substrates each having at least one trench between two or more adjacent features;

depositing a silicon oxide layer within at least a portion of the trench;

etching at least a portion of the silicon oxide layer by sublimating an ammonia fluorosilicate solid product that is formed from the reaction of the silicon oxide with a reactive species generated from a gas mixture comprising hydrogen fluoride and ammonia; and

depositing a dielectric layer on a remaining portion of the silicon oxide layer within the trench.

13. The method ofclaim 12, wherein the silicon oxide layer is deposited by a high aspect ratio process.

14. The method ofclaim 12, wherein the remaining portion of the silicon oxide layer forms an angle between slanted sidewalls of the silicon oxide remaining in the trench and the silicon oxide remaining in the bottom of the trench of about 87° or less.

15. The method ofclaim 12, wherein the dielectric layer comprises silicon oxide deposited by a high aspect ratio process.

16. A method of processing a semiconductor substrate, the method comprising:

depositing a first silicon oxide layer on the semiconductor substrate, wherein the substrate has at least one trench formed thereon;

exposing the semiconductor substrate at a first temperature to hydrogen fluoride and ammonia, wherein the hydrogen fluoride and ammonia react with a portion of the silicon oxide layer to form a solid product;

adjusting the substrate to a second temperature greater than the first temperature to remove the solid product and leave a remaining portion of the first silicon oxide layer; and

depositing a second silicon oxide layer on the remaining portion of the first silicon oxide layer, wherein the at least a portion of the second silicon oxide layer is deposited in the trench.

17. The method ofclaim 16, wherein the first silicon oxide layer is deposited by a high aspect ratio process.

18. The method ofclaim 16, wherein the second silicon oxide layer is deposited by a high aspect ratio process.

19. The method ofclaim 16, wherein the solid product comprises an ammonia fluorosilicate.

20. The method ofclaim 16, wherein the semiconductor substrate comprises a silicon substrate.

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