US20110147695A1

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Publication number: US20110147695A1
Application number: US12/646,267
Authority: US
Inventors: Jong-Won Sean Lee; DerChang Kau; Gianpaolo Spadini
Original assignee: Individual
Current assignee: Intel Corp
Priority date: 2009-12-23
Filing date: 2009-12-23
Publication date: 2011-06-23
Also published as: US8278641B2; US20120282752A1; US8404514B2

Abstract

In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.

Description

BACKGROUND

Phase change memory devices use phase change materials for non-volatile storage in electronic memory applications. Phase change materials may be electrically switched between a generally amorphous and a generally crystalline state. One type of memory element utilizes a phase change material that may be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. The phase change materials are non-volatile in that, when set in a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until changed by another programming event. The phase change materials remain in the set phase or physical state of the value the phase change material represents.

Power consumption in phase change memory devices can be significant. Reducing the power consumption in phase change memory devices is a design consideration, especially for use in portable electronic devices. Another consideration during the design of phase change memory devices includes dealing with the complexity of phase change materials in semiconductor processing. Further, switch devices in phase change memory devices are not physically isolated and contribute to cell-to-cell disturb, thus limiting scaling of architecture.

BRIEF DESCRIPTION OF THE DRAWINGS

The claimed subject matter will be understood more fully from the detailed description given below and from the accompanying drawings of disclosed embodiments which, however, should not be taken to limit the claimed subject matter to the specific embodiment(s) described, but are for explanation and understanding only.

It will be appreciated that for simplicity and clarity, the figures and the elements therein are not necessarily drawn to scale. Some features in the figures may be exaggerated to show particular details.

FIG. 1 is a schematic diagram of a portion of a memory in accordance with one embodiment.

FIG. 2 is a cross-sectional view depicting an intermediate structure during fabrication of a portion of a memory cell ofFIG. 1 in accordance with one embodiment.

FIG. 3 is a cross-sectional view of the structure ofFIG. 2 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 4 is a cross-sectional view of the structure ofFIG. 3 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 5 is a cross-sectional view of the structure ofFIG. 4 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 6 is a cross-sectional view of the structure ofFIG. 5 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 7 is a cross-sectional view of the structure ofFIG. 6 through line A-A′ in accordance with one embodiment.

FIG. 8 is a cross-sectional view of the structure ofFIG. 6 through line A-A′ in accordance with one embodiment.

FIG. 9 is a top view of the structures ofFIGS. 7-8 in accordance with various embodiments.

FIG. 10 is a cross-sectional view of the structure ofFIG. 6 through line A-A′ in accordance with one embodiment.

FIG. 11 is a top view of the structure ofFIG. 10 in accordance with one embodiment.

FIG. 12 is a cross-sectional view depicting an intermediate structure during fabrication of a portion of a memory cell ofFIG. 1 in accordance with one embodiment, including a spacer.

FIG. 13 is a cross-sectional view of the structure ofFIG. 12 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 14 is a cross-sectional view of the structure ofFIG. 13 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 15 is a cross-sectional view of the structure ofFIG. 14 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 16 is a cross-sectional view of the structure ofFIG. 15 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 17 is a cross-sectional view of the structure ofFIG. 16 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 18 is a cross-sectional view of the structure ofFIG. 17 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 19 is a cross-sectional view of the structure ofFIG. 18 through line B-B′ in accordance with one embodiment.

FIG. 20 is a cross-sectional view depicting an intermediate structure during fabrication of a portion of a memory cell ofFIG. 1 in accordance with one embodiment, using trimming.

FIG. 21 is a cross-sectional view of the structure ofFIG. 20 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 22 is a cross-sectional view of the structure ofFIG. 21 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 23 is a cross-sectional view of the structure ofFIG. 22 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 24 is a cross-sectional view of the structure ofFIG. 23 through line C-C′ in accordance with one embodiment.

FIG. 25 is a cross-sectional view depicting an intermediate structure during fabrication of a portion of a memory cell ofFIG. 1 in accordance with one embodiment, using trimming.

FIG. 26 is a cross-sectional view of the structure ofFIG. 25 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 27 is a cross-sectional view of the structure ofFIG. 26 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 28 is a cross-sectional view depicting an intermediate structure during fabrication of a portion of a memory cell ofFIG. 1 in accordance with one embodiment, including a spacer.

FIG. 29 is a cross-sectional view of the structure ofFIG. 28 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 30 is a cross-sectional view of the structure ofFIG. 29 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 31 is a cross-sectional view of the structure ofFIG. 30 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 32 is a cross-sectional view of the structure ofFIG. 31 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 33 is a cross-sectional view of the structure ofFIG. 32 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 34 is a cross-sectional view of the structure ofFIG. 33 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 35 is a cross-sectional view of the structure ofFIG. 34 through line D-D′ in accordance with one embodiment.

FIG. 36 is a cross-sectional view depicting an intermediate structure during fabrication of a portion of a memory cell ofFIG. 1 in accordance with one embodiment, using trimming.

FIG. 37 is a cross-sectional view of the structure ofFIG. 36 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 38 is a cross-sectional view of the structure ofFIG. 37 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 39 is a cross-sectional view depicting an intermediate structure during fabrication of a portion of a memory cell ofFIG. 1 in accordance with one embodiment, using over-etching.

FIG. 40 is a cross-sectional view of the structure ofFIG. 39 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 41 is a cross-sectional view of the structure ofFIG. 40 at a subsequent stage of fabrication in accordance with one embodiment.

FIG. 42 is a block diagram illustrating a portion of a system in accordance with one embodiment.

DETAILED DESCRIPTION

Referring toFIG. 1, a schematic diagram of a portion of amemory100 including amemory array102 is shown according to one embodiment. As an example,memory array102 may include a 3×3 array of memory cells104-112. In one embodiment, each memory cell104-112 includes amemory element114 and aselect device116. Although a 3×3 array is illustrated inFIG. 1, the scope of the claimed subject matter is not limited in this respect.Memory100 may include a larger array of memory cells.

In one embodiment,memory array102 may be formed on a portion of a substrate (not shown). The substrate may include a semiconductor substrate such as a silicon substrate. Other substrates such as those containing ceramic material, organic material, or glass material, may be suitable for use. The disclosure below details the formation of a portion ofmemory array102 including memory cells. Many, and possibly all, memory cells ofmemory array102, along with other integrated circuit circuitry may be fabricated simultaneously.

Memory

100 may include column lines118-120 and row lines122-124 to select a particular memory cell of thememory array102 during a program or read operation. In one embodiment, column lines118-120 and row lines122-124 may be referred to as address lines since these lines may be used to address memory cells104-112 during programming or reading. In one embodiment, column lines118-120 may be referred to as bit lines and row lines122-124 may be referred to as word lines.

Memory elements

114 may be connected to row lines122-124 and may be coupled to column lines118-120 viaselect devices116. When a particular memory cell is selected, voltage potentials may be applied to the memory cell's associated column line and row line to apply a voltage potential across the memory cell. In one example, a voltage is applied tocolumn line119 androw line122 to readmemory cell105.

In one embodiment,memory100 may be referred to as a phase change memory.Memory elements114 may comprise a phase change material and may be referred to as phase change memory elements in one embodiment. The phase change material may be a material having electrical properties such as, for example, resistance, capacitance, etc. These properties may be changed through the application of energy such as, for example, heat, light, voltage potential, or electrical current. Examples of a phase change material may include a chalcogenide and an ovonic material. The chalcogenide may be a material that includes at least one element from column VI of the periodic table or may be a material that includes one or more of the chalcogen elements. For example, chalcogen elements may include tellurium (Te), sulfur (S), or selenium (Se). The ovonic material may be a material that undergoes electronic or structural changes and acts as a semiconductor when subjected to the application of energy. The ovonic material may be used inmemory element114 or inselect device116.

As used herein, in general, “chalcogenide” may be used either as a phase change memory material or a switching material. When chalcogenide is inmemory element114 and utilized as phase change memory material, chalcogenide may be referred to as “memory chalcogenide”. When chalcogenide is used inselect device116 and intended to be a switching material, chalcogenide may be referred to as “switch chalcogenide”.

Select device

116 may be used to accessmemory element114 during programming or reading ofmemory element114.Select device116 may operate as a switch that is either “off” or “on” depending on the amount of voltage potential applied across a memory cell. The “off” state may be a substantially electrically nonconductive state and the “on” state may be a substantially conductive state. For example,select device116 may have a threshold voltage and if a voltage potential less than the threshold voltage ofselect device116 is applied acrossselect device116, then selectdevice116 may remain “off” or in a relatively high resistive state so that little or no electrical current passes through the memory cell. Alternatively, if a voltage potential greater than the threshold voltage ofselect device116 is applied acrossselect device116, then selectdevice116 may turn “on”. Whileselect device116 is on,select device116 operates in a relatively low resistive state so that electrical current passes through the memory cell. In other words,select device116 may be in a substantially electrically nonconductive state if less than a predetermined voltage potential, such as the threshold voltage, is applied acrossselect device116.Select device116 may be in a substantially conductive state if greater than the predetermined voltage potential is applied acrossselect device116.Select device116 may also be referred to as an access device, an isolation device, or a switch.

In one embodiment,select device116 may comprise a switching material such as, for example, a chalcogenide or an ovonic material, and may be referred to as an ovonic threshold switch (OTS), or simply an ovonic switch. The switching material ofselect device116 may be a material in a substantially amorphous state positioned between two electrodes, or an interconnect material and an electrode. The switching material may be repeatedly and reversibly switched between a higher resistance “off” state and a relatively lower resistance “on” state by application of a predetermined electrical current or voltage potential. For example, in the “off” state, resistance may be greater than about ten mega-ohms, and in contrast, in the “on” state, about zero ohms. In one embodiment,select device116 may be a two terminal device that may have a current-voltage (I-V) characteristic similar to a phase change memory element that is in the amorphous state. However, unlike a phase change memory element, the switching material ofselect device116 may not change phase. That is, the switching material ofselect device116 may not be a programmable material, and as a result,select device116 may not be a memory device capable of storing information. For example, the switching material ofselect device116 may remain permanently amorphous and the I-V characteristic may remain the same throughout the operating life.

During programming of a memory cell, the state of the phase change memory material in the memory cell may be altered. This may be referred to as a “phase-change action”. A voltage potential is applied to a row interconnect material and a column interconnect material which generates a voltage potential betweenmemory element114 andselect device116. An electrical current flows through the phase change memory material in response to the applied voltage potential which results in heating of the phase change memory material. The phase change memory material may change state and resistance.

In one convention, the phase change memory material may be in an amorphous state considered the “reset” state. In a crystalline state, the phase change memory material may be considered to be in a “set” state. The resistance of phase change memory material in the amorphous state may be greater than the resistance of phase change memory material in the crystalline state. The claimed subject matter is not limited in such a way, as the opposite of this convention may apply.

Referring toFIGS. 2-41, portions of one or more memory cells104-112 are depicted at different stages of fabricating current-confining structures in memory cells according to one or more embodiments. In particular,FIGS. 2-11 show a fabrication process of a portion of a memory cell including confining current in an upperlocation memory element114. In multiple embodiments,FIGS. 12-19 show formation of a portion of a memory cell withmemory element114 at sub-critical dimension (sub-CD) andFIGS. 20-24 andFIGS. 25-27 illustrate other ways of formation ofsub-CD memory elements114. In multiple embodiments,FIGS. 28-35,FIGS. 36-38 andFIGS. 39-41 depict fabrication processes of a sub-CD heater electrode in contact withmemory element114. In one or more embodiments, damascene processing may be used in fabricating current-confining structures. Further, when referring to intermediate structures, these are generally structures for temporary and/or illustrative purposes and are not intended to refer to permanent structures.

According to one or more embodiments, current confinement may improve thermal efficiency of a phase-change action, which translates into lower power consumption. In one embodiment, upper chalcogenide may be confined in a row direction as well as a column direction. In one embodiment, minimizing a contact area between an electrode and a phase change memory material may reduce the power required to program a memory cell. The contact area may be defined as the surface in which the electrode interfaces with the phase change memory material. In one embodiment, minimizing a contact area between a heater electrode and the phase change memory material may lead to current reduction during programming. This also allows current confinement in structures in accordance with one or more embodiments.

Referring now toFIG. 2, a depiction of anintermediate structure200 during fabrication of a portion of amemory array102 ofFIG. 1 is shown in accordance with one embodiment.Intermediate structure200 includesrow stack structures202 that have been patterned and isolation trenches between therow stack structures202 filled withinsulator204. Conventional etching techniques may be used in patterning therow stack structures202.Intermediate structure200 may be formed above a substrate.

In a non-limiting example,insulator204 may include dielectric material or insulating film that may be formed in between the patternedrow stack structures202. In one embodiment, dielectric material may include silicon dioxide (SiO₂), silicon oxide (SiO), silicon nitride (Si₃N₄), or combinations thereof. In another embodiment, dielectric material may include a material selected with thermal conductivity κ values less than 1.0. In one embodiment,insulator204 may be formed using plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), spin-on, sol-gel, or other suitable processes. In one or more embodiments,insulator204 may be considered to be a sacrificial material and/or used as a mask.

According to one embodiment,row stack structure202 may include layers of arow interconnect material206, achalcogenide208 and amiddle electrode210.Row stack structure202 may further include a layer ofchemical barrier material214 located betweenrow interconnect material206 andchalcogenide208. In one embodiment, the layers ofrow interconnect material206,chalcogenide208 andmiddle electrode210 may be masked and dry etched to pattern therow stack structures202. In one example, an anisotropic etch may be used to pattern therow stack structures202.Sacrificial material212 may be incorporated on top ofrow stack structures202, which is self-aligned to row by patterning together.

In one embodiment, one or more layers ofrow stack structure202 may be applied using a deposition technique. Such deposition techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), laser assisted chemical vapor deposition, and atomic layer deposition (ALD), but the claimed subject matter is not limited in this respect. One or more of these deposition techniques may be selected for appropriate application of various different layers mentioned in this disclosure.

Row interconnect material

206 may include any suitable conductor. Examples ofrow interconnect material206 include copper, aluminum, copper alloys, and aluminum alloys. As another example,row interconnect material206 may be a polycrystalline film with cobalt silicide (CoSi₂) on the top surface. Therow interconnect material206 may correspond to row lines, such as122-124 ofFIG. 1, for addressing memory cells. A voltage potential between therow interconnect material206 and a column interconnect material, to be deposited in a subsequent stage of manufacture, may be used to program and read memory cells.

In one embodiment,row interconnect material206 may have a thickness ranging from about 100 Å to about 20,000 Å. In one embodiment,row interconnect material206 may have a thickness ranging from about 300 Å to about 5,000 Å. In one embodiment,row interconnect material206 may have a thickness of about 2,000 Å.

According to one embodiment,chalcogenide208 may be a memory chalcogenide or a switch chalcogenide. As mentioned above, memory chalcogenide may be programmable due to the ability to change phase whereas switch chalcogenide is not programmable due to its inability to change phase. Ifchalcogenide208 comprises memory chalcogenide, then a later formed chalcogenide in the memory cell comprises a switch chalcogenide, and vice versa, as will be further described below.

In one embodiment, there is flexibility to place memory chalcogenide and switch chalcogenide in either of lower and upper locations within the memory cell. The lower location refers to a position closer to rowinterconnect material206 and underlying substrate (not shown) of the memory cell, whereas the upper location refers to a position located above themiddle electrode210. In general, as used herein, “lower chalcogenide” refers to chalcogenide that is located closer to row interconnect material and “upper chalcogenide” refers to chalcogenide that is located closer to column interconnect material.

In one or more embodiments, if upper chalcogenide is fabricated with memory chalcogenide, the electrical current density may be preserved throughout the region near the memory chalcogenide. In one or more embodiments, if the upper chalcogenide is fabricated with switch chalcogenide, when active, the electrical current may be strictly confined within the switch chalcogenide.

Commonly, chalcogenide refers to alloys including at least one element from column VI of the Periodic Table of Elements. Examples of chalcogenide include, but are not limited to, compositions of the class of tellurium-germanium-antimony (Te_xGe_ySb_z). In one embodiment,chalcogenide208 includes Ge₂Sb₂Te₅.

In one embodiment,chalcogenide208 may be a switch chalcogenide comprising tellurium and/or selenium. In another embodiment, switch chalcogenide may comprise silicon (Si), tellurium (Te), arsenic (As), and germanium (Ge), or combinations of these elements. In other embodiments, a composition for switch chalcogenide may include an alloy of silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), and indium (In) or an alloy of Si, Te, As, Ge, and phosphorous (P), but the claimed subject matter is not limited in this respect.

According to one embodiment,chalcogenide208 may be deposited to a thickness in the range of about 10 Å to about 2,000 Å. In one embodiment, the thickness ofchalcogenide208 is in the range of about 100 Å to about 1,200 Å. In one embodiment, the thickness is on the order of about 600 Å.

Middle electrode

210 may be comprised of a thin film material having a film thickness ranging from about 20 Å to about 2,000 Å. In one embodiment, the thickness ofmiddle electrode210 may range from about 100 Å to about 1,000 Å. In another embodiment, the thickness ofmiddle electrode210 may be about 300 Å. Suitable materials formiddle electrode210 may include titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), carbon (C), silicon carbide (SiC), titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), polycrystalline silicon, tantalum nitride (TaN), some combination of these films, or other suitable conductors or resistive conductors compatible withchalcogenide208.

When referring to “middle electrode”, it should be understood thatmiddle electrode210 may be an intermediate or an adjacent electrode and not necessarily an electrode that is in the middle of the stack, electrodes, etc. Further,middle electrode210 may include one or more of top or bottom electrodes for memory chalcogenide and switch chalcogenide. The electrodes of the memory chalcogenide and switch chalcogenide may not be required to be identical in composition. In an example where memory chalcogenide is located in an upper location, an electrode on the bottom ofmemory element114 ofFIG. 1 and an electrode on the top ofselect device116 ofFIG. 1 may be considered together to composemiddle electrode210.

As non-limiting examples, the layer ofsacrificial material212 may include carbon and/or spin-on glass. Thesacrificial material212 may be an etch stop layer for chemical mechanical polishing (CMP). In another example, thesacrificial material212 may include SiN or polycrystalline silicon films. In one embodiment, the thickness of thesacrificial material212 may range from about 20 Å to about 4000 Å, and may depend on the desired thickness of chalcogenide that will be subsequently deposited in a trench caused by the vacancy ofsacrificial material212.

The layer ofchemical barrier214 located betweenrow interconnect material206 andchalcogenide208 may be a thin film for preventing a chemical reaction betweencolumn interconnect material206 andchalcogenide208.Chemical barrier214 may comprise Ti, TiN, TiW, C, SiC, TiAlN, TiSiN, polycrystalline silicon, TaN, some combination of these, or other suitable conductors or resistive conductors. The layer ofchemical barrier214 may be optional and if thechemical barrier214 is absent from therow stack structures202,chalcogenide208 may be applied onrow interconnect material206 and sandwiched betweenmiddle electrode210 androw interconnect material206.

Referring toFIG. 3, the structure ofFIG. 2, depicted as220, after thesacrificial material212 is removed in accordance with one embodiment. In one embodiment, thesacrificial material212 may be removed using a selective etch without removal of the underlyingmiddle electrode210 orinsulator204. In one embodiment, thesacrificial material212 being carbon is removed leaving behindtrenches222 self-aligned to rowstack structures202.

With reference toFIG. 4, the structure ofFIG. 3 after deposition of a layer of achalcogenide232 is depicted asstructure230 in accordance with one embodiment.Chalcogenide232 may fill intrenches222 completely and overlieinsulator204. In one embodiment,chalcogenide232 may be deposited to a thickness in the range of about 10 Å to about 2,000 Å. In one embodiment, the thickness ofchalcogenide208 is in the range of about 100 Å to about 1,200 Å. In one embodiment, the thickness is on the order of about 600 Å.Chalcogenide232 may be applied using a deposition technique such as PVD or CVD according to one embodiment.

Referring toFIG. 5 shows the structure ofFIG. 4, depicted asstructure240 after removingexcess chalcogenide232 in accordance with one embodiment. A chemical-mechanical polishing (CMP) process may be used to remove undesired chalcogenide. As the surface ofstructure240 is planarized during the CMP process,chalcogenide232 that is not in thetrenches222 is removed andchalcogenide242 is formed on top of and aligned with therow stack structure202.

Turning toFIG. 6, at250, once a planar surface has been obtained on the structure ofFIG. 5, a layer of achemical barrier252 may be applied to the planar surface of thestructure240. A layer ofcolumn interconnect material254 may be deposited on top of the layer ofchemical barrier252. The layer ofchemical barrier252 may be a thin film for preventing a chemical reaction betweenchalcogenide242 andcolumn interconnect material254.Chemical barrier252 may comprise Ti, TiN, TiW, C, SiC, TiAlN, TiSiN, polycrystalline silicon, TaN, some combination of these, or other suitable conductors or resistive conductors. In one embodiment,chemical barrier252 is optional and thecolumn interconnect material254 may be directly formed on the planar surface of thestructure240.

As non-limiting examples,column interconnect material254 may include suitable conductors such as copper, copper alloys, aluminum, and aluminum alloys, and polycrystalline film with cobalt silicide (CoSi₂).Column interconnect material254 may correspond to column lines, such as118-120 ofFIG. 1, for addressing memory cells for programming and reading.

In one embodiment,column interconnect material206 may have a thickness ranging from about 100 Å to about 20,000 Å. In one embodiment,column interconnect material206 may have a thickness ranging from about 300 Å to about 5,000 Å. In one embodiment,column interconnect material206 may have a thickness of about 2,000 Å.

After formingcolumn interconnect material254, column patterning may be performed to createcolumn stack structures256, which are more clearly shown inFIGS. 7-11. During column patterning,chemical barrier252 andcolumn interconnect material254 may be etched in a column-wise direction (y direction), thus formingcolumn stack structures256. In one embodiment, as shown at260,chalcogenide242 may also be etched and considered to be part ofcolumn stack structures256. In one embodiment,middle electrode210 may also be cut in a column-wise direction. For example, anisotropic etch is suitable for patterning in one or more embodiments.

FIGS. 7,8 and10 show cross-sections of the structure ofFIG. 6 through line A-A′ according to various embodiments.FIGS. 9 and 11 show top views of the various embodiments. It should be noted that although not shown in these figures, the structure ofFIG. 6 may be filled with an insulator in open or unfilled areas, for example, such as between

column stack structures

256 or260 so as to reduce current leakage. As a non-limiting example, the insulator may be a dielectric material.

FIG. 7 shows a cross-section of the structure ofFIG. 6 after column etching ofchalcogenide242 andmiddle electrode210 according to one embodiment.Chalcogenide242 may be confined to a cubical region with a smaller volume than prior to column etching. As a result, electrical current density may be preserved throughout the volume. In the embodiment ofFIG. 7,chalcogenide208 is not etched in a column-wise direction. The column etch process may be extended to etch intochalcogenide208, as shown inFIG. 8 in an embodiment where part ofchalcogenide208 is etched.FIG. 9 is a top view corresponding to both structures ofFIGS. 7-8 in accordance with various embodiments.

By etchingchalcogenide208 in embodiments shown inFIGS. 8 and 10, current that runs throughchalcogenide208 is said to be confined. Instead of spreading out like current normally does in phase change memory switch (PCMS) devices, the current travels mostly in the vertical direction (z direction) from therow interconnect material206 to thecolumn interconnect material254. The column etch process may extend down to thechemical barrier214 as shown inFIG. 9 and thechemical barrier214 may act as an etch stop. In one embodiment, current may travel through avertical stack262 of chalcogenide242 (upper chalcogenide),middle electrode210, and chalcogenide208 (lower chalcogenide), each having been etched in one or more of row and column directions.FIG. 11 is a top view of the structure ofFIG. 10 in accordance with one embodiment.

In accordance with one or more embodiments,FIGS. 9 and 11 show a portion ofmemory array102. From the top views, a cross-point PCMS arrangement of rows and columns ofmemory array102 include memory cells located at270 in each ofFIGS. 9 and 11. In one or more embodiments, memory cells may be stacked in the vertical direction to increase storage density.

In one or more embodiments, to increase current density during programming of the memory cell, a reduced size contact area may be formed between a memory chalcogenide and middle electrode for current confinement. For a smaller contact area, the lateral size of the memory chalcogenide may be reduced. In one embodiment, the memory chalcogenide may be formed such that the lateral size is below critical dimension (CD). CD may be defined as the minimum feature size or a target design rule, such as, for example, in photolithography. Fabricating components below critical dimension may be referred to as “sub-critical dimension”, “sub-lithographic”, “sub-lithographic CD” or simply “sub-CD”.

In one or more embodiments,FIGS. 12-19,FIGS. 20-24 andFIGS. 25-27 show processes of forming sub-CD chalcogenide.FIGS. 12-19 andFIGS. 25-27 illustrate how sub-CD chalcogenide may be formed at an upper location in one or more memory cells, using an additive process and a trimming process, respectively.FIGS. 20-24 illustrate a process of forming sub-CD chalcogenide at a lower location in one or more memory cells, utilizing trimming.

Referring now toFIG. 12, anintermediate structure300 during fabrication of a portion of a memory cell ofFIG. 1 in accordance with one or more embodiments is shown. In one embodiment,intermediate structure300 may be constructed as shown and described inFIG. 2 using the same or similar processes and materials.Intermediate structure300 may include row stack structures301 including layers ofrow interconnect material302, achemical barrier304, achalcogenide306, and amiddle electrode308.Sacrificial material310 may be incorporated on top of row stack structures301 and self-aligned to row stack structure301 by patterning together.Insulator312 may be deposited in between row stack structures301. In one embodiment,chalcogenide306 is switch chalcogenide.

Referring toFIG. 13,intermediate structure320 may be constructed as shown and described inFIG. 3 using the same or similar processes and materials.Sacrificial material310 may be selectively removed using an anisotropic etchprocess leaving trenches322 self-aligned to row stack structures301.

Turning toFIG. 14,intermediate structure330 is shown after depositinginsulator332 into thetrenches322 to create spacers insidetrenches322.Insulator332 may be comprised of silicon dioxide, silicon nitride, silicon oxide, or combinations thereof, as non-limiting examples. The layer ofinsulator332 may be a conformal layer deposited using CVD, HDPCVD or other thin-film deposition techniques. In one embodiment, the thickness ofinsulator332 is in the range of about 50 Å to about 1,000 Å. In one embodiment, the thickness is on the order of about 300 Å.

Referring toFIG. 15, as shown byintermediate structure340, a directional etch is applied tointermediate structure330 to removeinsulator332 in the vertical direction. By using an etching agent that is selective, the etching agent stops at themiddle electrode308. As depicted byspacer344, only the vertical layers of theinsulator332 lining the side walls oftrenches322 remain, andnew trenches342 are created. According to one embodiment, thetrenches342 are made to be narrow so that the memory chalcogenide that is filled in thetrenches342 may be as narrow as possible.

After creatingspacer344 in thetrenches342,FIGS. 16,17, and18 may use the same or similar processes and materials as shown atFIGS. 4,5, and6, respectively. InFIG. 16,memory chalcogenide352 may fill in thetrenches342 using CVD or HDPCVD, as an example. In one embodiment, in contrast to the embodiment shown atFIGS. 4,5, and6, a contact area betweenmemory chalcogenide352 andmiddle electrode308 formed withspacers344 is smaller and as a result, current can also be confined to a smaller volume. InFIG. 17, undesired chalcogenide may be removed by CMP, for example. Chalcogenide that is left in the trenches is depicted at362, and may be considered sub-CD. In one embodiment, the thickness ofchalcogenide362 may be in the range of about 50 Å to about 1,000 Å. In one embodiment, the thickness is on the order of about 300 Å.

Referring toFIG. 18, once a planar surface has been obtained after CMP, achemical barrier372 may be deposited on top of the planar surface and acolumn interconnect material374 may be deposited on top of thechemical barrier372 to formstructure370. In one embodiment,chemical barrier372 is optional and thecolumn interconnect material374 may be directly deposited onto the planarized surface. Column patterning may be done with etching in the column-wise direction (y direction), and thus creatingcolumn stack structures376. In one embodiment,column stack structure376 may includememory chalcogenide362 and may be patterned as well. Additional column etching may extend tomiddle electrode308.

FIG. 19 is a cross-section ofFIG. 18 taken through line B-B′ ofstructure370. The top view ofstructure370 is shown byFIG. 9. In one embodiment, similar to structure250 ofFIG. 6,structure370 has the option of further etching theswitch chalcogenide306 either partially, as shown in top viewFIG. 9 and cross-sectionFIG. 8, or completely, as shown in top viewFIG. 11.

Turning toFIG. 20, a trimming method for constructing a sub-CD memory chalcogenide is shown with anintermediate structure400 in the midst of a row stack structure patterning process.Intermediate structure400 may include aninterconnect material402 and achemical barrier404

overlying interconnect material

402, which have not been etched in the row direction (x direction), hence row stack structure is not yet defined.Chemical barrier404 may be an optional layer.Intermediate structure400 further includes a layer ofmemory chalcogenide406 on top of thechemical barrier404,middle electrode408 on top ofmemory chalcogenide406, andinsulator410 on top ofmiddle electrode408, which have gone through row patterning. As an etch mask,insulator410 may include a dielectric material such as silicon dioxide or a combination of several insulating films. During patterning,memory chalcogenide406 is etched and the sidewalls are exposed.

Referring now toFIG. 21, the patterning performed onmemory chalcogenide406 has allowed lateral access tomemory chalcogenide406. Using selective etching,memory chalcogenide406 may be etched laterally, as shown by the arrows. In one embodiment, vacuum conditions may be changed in the selective etching process in order to cutmemory chalcogenide406.Chemical barrier404 is not etched at this stage.

InFIG. 22, the rest ofrow stack structure422 includingchemical barrier404 androw interconnect material402 is patterned. Therow stack structure422 and layers ofmiddle electrode408 andinsulator410 are shown as anintermediate structure420.

InFIG. 23, according to one embodiment, cross-point PCMS cell process may occur, as described above, to constructstructure430. In one embodiment,intermediate structure420 may be filled in withadditional insulator410 using CVD or HDPCVD, for example. Theinsulator410 may replace the space that was vacated from the lateral etching of thememory chalcogenide406. In one embodiment, the contact area betweenmemory chalcogenide406 andmiddle electrode408 is maintained and smaller than CD in width.

Insulator

410 may be removed from the top ofintermediate structure420, for example, using CMP or isotropic etch processes, until the layer ofinsulator410 above therow stack structure422 is removed and/or whenmiddle electrode408 is reached. Once the surface ofintermediate structure420 is planarized andmiddle electrode408 is exposed at the surface, the process may proceed to deposition ofswitch chalcogenide432. Additionally, an optional layer ofchemical barrier434 may be deposited on top ofswitch chalcogenide432.Column interconnect material436 may be formed on top ofchemical barrier434. Ifchemical barrier434 is not used,column interconnect material436 may be deposited on top ofswitch chalcogenide432.

Column stack structures

438 and440 may be patterned in a column-wise direction.Middle electrode408 may be patterned with

column stack structures

438 and440.

FIG. 24 further shows a cross-section ofstructure430, taken through line C-C′, in accordance with one embodiment. The top view ofstructure430 is shown byFIG. 9. In one embodiment, similar to structure250 ofFIG. 6,structure430 has the option of further etching thememory chalcogenide406 either partially, as shown in top viewFIG. 9 and similar to cross-sectionFIG. 8, or completely (such as down to expose chemical barrier434) as shown in top viewFIG. 11.

Referring toFIGS. 25-27, an alternate method of constructingstructure370 ofFIG. 18, where memory chalcogenide is sub-CD, is shown using trimming. Similar toFIG. 18, anintermediate structure500 may include arow interconnect material502, an optional layer ofchemical barrier504, switchchalcogenide506,middle electrode508,memory chalcogenide510, andinsulator512. During a row patterning process,memory chalcogenide510 may be etched and the sidewalls are exposed. Both memory and switch chalcogenides are present in a row stack structure in one embodiment. With a chemically selective etch,memory chalcogenide510 may be etched laterally, as indicated by the arrows, according to one embodiment. The rest of therow stack structure520 may be etched vertically. Similar toFIG. 23, a cross-point PCMS cell process including insulator fill and column patterning, as described above, may occur following etching of the rest ofrow stack structure520 to constructstructure370 ofFIG. 18.

In one or more embodiments,FIGS. 28-35,FIGS. 36-38 andFIGS. 39-41 show processes of forming sub-CD middle electrode heaters.FIGS. 28-35 may use an additive process with a damascene approach to forming sub-CD middle electrode heaters.FIGS. 36-38 may use a trimming process to form the heaters.FIGS. 39-41 show another trimming process to form sub-CD heaters. Middle electrode heaters may also be referred to as “heaters” and “heater electrodes”.

In general, current flow between row interconnect material and column interconnect material results in electrical resistance heat developed by the heater electrode which heats memory chalcogenide adjacent to the heater electrode. As mentioned above, when memory chalcogenide is heated to a relatively higher temperature, the memory chalcogenide may amorphosize (set to “0”). When memory chalcogenide is heated to a relatively lower temperature, the memory chalcogenide may crystallize (set to “1”). In one or more embodiments, when using a sub-CD heater to heat the memory chalcogenide, a higher current density and increased uniformity of thermal profile within the memory chalcogenide may be achieved.

In forming sub-CD heaters,FIGS. 28 and 29 may use the same or similar processes and materials as shown atFIGS. 2 and 3, respectively.FIG. 28 shows anintermediate structure600 including patternedrow stack structures614 with layers ofrow interconnect material602,optional chemical barrier604, switchchalcogenide606, andmiddle electrode608.Sacrificial material610 overlyingmiddle electrode608 is also patterned.Insulator612 may fill in between the patternedrow stack structures614 to createintermediate structure600. AtFIG. 29, using an anisotropic etch process,sacrificial material610 is removed fromintermediate structure600 leavingtrenches622 self-aligned to rowstack structures614.

Turning toFIGS. 30 and 31, in the formation of spacers intrenches622,FIGS. 30 and 31 may use the same or similar processes and materials as shown atFIGS. 14 and 15, respectively. AtFIG. 30, aspacer632 may be deposited intrenches622 and aboveinsulator612 forming anintermediate structure630.FIG. 31 shows anintermediate structure640 after directional etching ofintermediate structure630 according to one embodiment. Anisotropic etching may remove a portion of thespacer632 that is above themiddle electrode608. A selective etching agent may removespacer632 without removingmiddle electrode608.Spacers634 remain and createnew trenches642.

Referring toFIG. 32,intermediate structure650 is shown after forming aheater electrode652 on top ofintermediate structure640 in accordance with one embodiment. As non-limiting examples, theheater electrode652 may be TiSiN, Ti, TiN, TiW, C, SiC, TiAlN, polycrystalline silicon, TaN, other suitable conductors, and combinations thereof. Theheater electrode652 may be a conformal layer introduced to the top ofintermediate structure640 using, for example, CVD or HDPCVD. Intrench642, a contact area is formed betweenheater electrode652 andmiddle electrode608 resulting in a contact area that is sub-CD.

Referring toFIG. 33, in accordance with one embodiment, anintermediate structure660 is formed after removingexcess heater electrode652. In one embodiment,heater electrode652 may be removed by CMP or isotropic etch.Heater electrode652 that is left in thetrenches642 is depicted at662. In one embodiment, the thickness ofheater electrode662 may be in the range of about 50 Å to about 1,000 Å. In one embodiment, the thickness is on the order of about 300 Å.

Referring toFIG. 34, once a planar surface has been obtained,memory chalcogenide672,chemical barrier674, andcolumn interconnect material676 may be deposited to the planar surface to formstructure670. In one embodiment,chemical barrier674 is optional and thecolumn interconnect material676 may be directly deposited ontomemory chalcogenide672. Column patterning may be done with anisotropic etching in the column-wise direction, and thus creatingcolumn stack structures678, as shown inFIG. 35.Column stack structures678 may further includememory chalcogenide672, which may be etched column-wise. Column etching may extend down tomiddle electrode608.

FIG. 35 is a cross-section ofFIG. 34 taken through line D-D′ ofstructure670. In one embodiment, the top view ofstructure670 is shown byFIG. 9. In one embodiment, similar to structure250 ofFIG. 6,structure670 has the option of further etching theswitch chalcogenide606 either partially, as shown in top viewFIG. 9 and similar to cross-sectionFIG. 8, or completely (such as down to expose chemical barrier604) as shown in top viewFIG. 11.

Turning toFIG. 36, a depiction of an alternate method, using trimming, to constructstructure670 using the same or similar materials of one or more embodiments above is shown. In one embodiment, anintermediate structure700 may include arow interconnect material702,chemical barrier704, switchchalcogenide706,middle electrode708,heater electrode710, andinsulator712.Chemical barrier704 may be optional in one embodiment. During a row patterning process,heater electrode710 may be etched and the sidewalls are exposed. InFIG. 37, a chemically selective etch may cutheater electrode710 laterally, as indicated by the arrows, according to one embodiment. Referring toFIG. 38, row patterning may continue after etchingheater electrode710 so that arow stack structure720 may be etched vertically. Similar toFIG. 23, a cross-point PCMS cell process including insulator fill and column patterning, as described above, may complete the trimming process of constructingstructure670.

Referring toFIG. 39, a depiction of an alternate method, using trimming, to construct anintermediate structure800 including a sub-CD heater using the same or similar materials of one or more embodiments above, is shown.Intermediate structure800 includesrow interconnect material802,chemical barrier804, switchchalcogenide806,middle electrode808,heater electrode810, andinsulator812.Chemical barrier804 may be optional in one embodiment. Row patterning forms rowstack structures814 in accordance with one embodiment.

InFIG. 40, for trimming purposes, a chemical/physical isotropic etch may be used to reduce the lateral dimension of theheater electrode810. In one embodiment, the etching creates a tapered profile on theheater electrode810. In one embodiment, the top surface area ofheater electrode810 is smaller than the bottom surface area ofheater electrode810. As shown,heater electrode810 has top surface area at sub-CD while the bottom surface area is at CD. A portion ofinsulator812 remains on top ofheater electrode810.

Referring toFIG. 41,additional insulator812 may be filled in between therow stack structures814. After filling in,insulator812 may be removed from the top ofintermediate structure830, for example, using CMP or isotropic etch processes, until theinsulator812 above therow stack structures814 are removed and/or whenheater electrodes822 are reached. Once the surface ofintermediate structure830 is planarized andheater electrode822 is exposed at the surface, the process may proceed to deposition ofmemory chalcogenide832. Additionally, an optional layer ofchemical barrier834 may be deposited on top ofmemory chalcogenide832.Column interconnect material836 may be formed on top ofchemical barrier834. Ifchemical barrier834 is not used,column interconnect material836 may be deposited on top ofmemory chalcogenide832.Column stack structure838 may be patterned in a column-wise direction.Column stack structure838 may further includememory chalcogenide832, which may be etched column-wise as well. Column etching may extend down toheater electrode822 andmiddle electrode808.

An identical cross-section ofFIG. 41 taken through line E-E′ ofstructure830 is shown inFIG. 35. In one embodiment, the top view ofstructure830 is shown byFIG. 9. In one embodiment, similar to structure250 ofFIG. 6,structure830 has the option of further etching theswitch chalcogenide806 either partially, as shown in top viewFIG. 9 and similar to cross-sectionFIG. 8, or completely (such as down to expose chemical barrier804) as shown in top viewFIG. 11.

Turning toFIG. 42, a portion of asystem900 in accordance with an embodiment of the present invention is described.System900 may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly.System900 may be used in any of the following systems: wireless personal area networks (WPAN), wireless local area networks (WLAN), and wide area networks (WAN) including, for example, 2G cellular networks, 3G networks, and 4G networks, although the scope of the claimed subject matter is not limited in this respect.

System

900 may include acontroller902, an input/output (I/O)device904, amemory906, and awireless interface908 coupled to each other via abus910. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.

Controller

902 may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like.Memory906 may be used to store messages transmitted to or bysystem900.Memory906 may also optionally be used to store instructions that are executed bycontroller902 during the operation ofsystem900, and may be used to store user data.Memory906 may be provided by one or more different types of memory. For example,memory906 may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a memory such asmemory100 discussed herein.

I/O device904 may be used by a user to generate a message. Other devices may include a keypad, display, microphone, mouse, camera, sensor, and other electronic devices.System900 may usewireless interface908 to transmit and receive messages to and from a wireless communication network with radio frequency (RF), microwave, or infrared signals. Examples ofwireless interface908 may include one or more antennae or wireless transceivers, although the scope of the present invention is not limited in this respect.

It is appreciated that fabrication of current-confining structures of PCMS cells has been explained with reference to one or more exemplary embodiments, and that the claimed subject matter is not limited to the specific details given above. References in the specification made to other embodiments fall within the scope of the claimed subject matter.

In one or more embodiments described above, regarding minimizing contact area, memory chalcogenide and middle electrode do not physically need to be in contact, electrical communication between a memory chalcogenide and a middle electrode may be sufficient. In one or more embodiments, electrical communication between a memory chalcogenide and a heater electrode may be sufficient.

The figures as shown and described above are not necessarily limited to the presented layers of materials. For example, a memory cell structure may include other materials and/or additional layers of electrodes, insulators, chemical barriers, etch stops, chalcogenide, etc. In another example, chemical barriers have been shown in each embodiment, but are not necessarily required in each embodiment. Further, the figures are not necessarily limited to the order in which processes occur. In one or more embodiments, the actual sequence may occur out of order with what is presented and may still be within the scope of the claimed subject matter.

Any reference to “up”, “down”, “row”, “column”, “lateral”, etc. was made to aid in illustrating one or more embodiments, and is not meant to be limiting in howmemory100 is to be oriented or utilized. In one example, references to “row” and “column” may be switched.

Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the claimed subject matter. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.

If the specification states a component, feature, structure, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.

Those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the claimed subject matter. Indeed, the claimed subject matter is not limited to the details described above. Rather, it is the following claims including any amendments thereto that define such scope and variations. Further, the order in which the claim elements are presented is not intended to be limiting to the scope of the claimed subject matter.

Claims

1. A method of fabricating a phase change memory cell, the method comprising:

patterning a row stack structure, the row stack structure including a row of an interconnect material, a first chalcogenide, and a middle electrode;

forming a sacrificial material;

forming an insulator to isolate the row stack structure from adjacent row stack structures;

etching the sacrificial material;

forming a second chalcogenide; and

patterning a column stack structure, the column stack structure orthogonal to the row stack structure.

2. The method ofclaim 1 wherein said etching the sacrificial material comprises leaving behind a trench self-aligned with the row stack structure and wherein the second chalcogenide fills the trench.

3. The method ofclaim 1 further comprising removing excess of the second chalcogenide.

4. The method ofclaim 1 wherein said patterning a column stack structure comprises forming one or more layers of a column interconnect material and a chemical barrier.

5. The method ofclaim 1 further comprising etching in a column-wise direction one or more of the second chalcogenide and the middle electrode with said patterning a column stack structure.

6. The method ofclaim 1 further comprising etching in a column-wise direction the first chalcogenide exposed between the column stack structure and an adjacent column stack structure.

7. The method ofclaim 6 wherein said etching comprises etching a portion of the first chalcogenide exposed between the column stack structure and adjacent column stack structure.

8. The method ofclaim 1 wherein the first chalcogenide is a memory chalcogenide and the second chalcogenide is a switch chalcogenide.

9. The method ofclaim 1 wherein the first chalcogenide is a switch chalcogenide and the second chalcogenide is a memory chalcogenide.

10. The method ofclaim 1 wherein said forming of a sacrificial material occurs on top of the second chalcogenide.

11. The method ofclaim 1 further comprising lateral etching of the second chalcogenide.

12. The method ofclaim 1 wherein the sacrificial material is carbon, spin-on glass, or insulator.

13. The method ofclaim 1 further comprising forming a spacer in a trench self-aligned with the row stack structure prior to said forming a second chalcogenide.

14. The method ofclaim 13 further comprising etching the spacer to expose the middle electrode.

15. The method ofclaim 14 wherein a contact area between the second chalcogenide and the middle electrode is sub-lithographic critical dimension.

16. The method ofclaim 13 wherein the spacer comprises silicon nitride, silicon dioxide, silicon oxide, or combinations thereof.

17. The method ofclaim 1 wherein said patterning of row stack structure comprises lateral etching of the first chalcogenide such that a contact area between the first chalcogenide and the middle electrode is sub-lithographic critical dimension.

18. The method ofclaim 1 further comprising column-wise etching of the first chalcogenide and the middle electrode.

19. A phase change memory comprising:

a row interconnect material;

a first chalcogenide above the row interconnect material;

a middle electrode above the first chalcogenide;

a second chalcogenide above the middle electrode; and

a column interconnect material above the second chalcogenide, the column interconnect material orthogonal to the row interconnect material,

wherein the middle electrode and one or more of the first chalcogenide and the second chalcogenide are arranged in a vertical stack after etching in row and column directions.

20. The phase change memory ofclaim 19 wherein a second chalcogenide comprises memory chalcogenide with a lateral dimension smaller than critical dimension.

21. The phase change memory ofclaim 20 further comprising a spacer for creating the memory chalcogenide.

22. The phase change memory ofclaim 19 wherein a first chalcogenide comprises memory chalcogenide with a lateral dimension smaller than critical dimension.

23. A method of fabricating a phase change memory cell, the method comprising:

patterning a row stack structure, the row stack structure comprising a row of an interconnect material, a first chalcogenide, and a middle electrode;

forming a sacrificial material;

etching the sacrificial material;

forming a heater electrode on the middle electrode; and

patterning a column stack structure,

wherein the column stack structure is orthogonal to the row stack structure, and

wherein the column stack structure comprises a second chalcogenide.

24. The method ofclaim 23 wherein the first chalcogenide comprises switch chalcogenide and the second chalcogenide comprises memory chalcogenide.

25. The method ofclaim 24 wherein a contact area between the heater electrode and the memory chalcogenide is sub-lithographic critical dimension.

26. The method ofclaim 23 further comprising over-etching a portion of the sacrificial material and a portion of the heater electrode to create a tapered profile on the heater electrode.

27. The method ofclaim 23 wherein a contact area between the heater electrode and the middle electrode is sub-lithographic critical dimension.

28. The method ofclaim 23 further comprising forming a spacer in a trench left by the sacrificial material after etching.

29. The method ofclaim 28 further comprising etching a portion of the spacer to expose the middle electrode.

30. The method ofclaim 23 further comprising etching the first chalcogenide exposed between the column stack structure and an adjacent column stack structure.