US20110121380A1 - Non-volatile electrically alterable memory cell for storing multiple data - Google Patents

Abstract

A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Description

CROSS REFERENCE TO RELATED APPLICATION
• The present application is a divisional application of copending U.S. patent application Ser. No. 11/348,556, entitled “Memory Array of Non-Volatile Electrically Alterable Memory Cells for Storing Multiple Data,” filed on Feb. 6, 2006, which is a divisional application of copending U.S. patent application Ser. No. 10/801,789, entitled “Non-Volatile Electrically Alterable Memory Cell For Storing Multiple Data And An Array Thereof,” filed on Mar. 16, 2004, and claims the benefit thereof and are both incorporated herein by reference.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to logic gate structures, and more particularly, to an electrically erasable and programmable read-only memory (EEPROM) and to Flash EEPROMs employing metal-oxide-semiconductor (MOS) floating gate structures.
• 2. Description of the Related Art
• Electrically erasable and programmable non-volatile semiconductor devices, such Flash EEPROMs are well known in the art. One type of Flash EEPROM employs metal-oxide-semiconductor (MOS) floating gate devices. Typically, electrical charge is transferred into an electrically isolated (floating) gate to represent one binary state while an uncharged gate represents the other binary state. The floating gate is generally placed above and between two regions (source and drain) spaced-apart from each other and separated from those regions by a thin insulating layer, such as a thin oxide layer. An overlying gate is disposed above the floating gate provides capacitive coupling to the floating gate, allowing an electric field to be established across the thin insulating layer. “Carriers” from a channel region under the floating gate are tunneled through the thin insulating layer into the floating gate to charge the floating gate. The presence of the charge in the floating gate indicates the logic state of the floating gate, i.e., 0 or 1.
• Several methods can be employed to erase the charge in a floating gate. One method applies ground potential to two regions and a high positive voltage to the overlying gate. The high positive voltage induces charge carriers, through the Fowler-Nordheim tunneling mechanism, on the floating gate to tunnel through an insulating layer that separates the overlying gate and the floating gate into the overlying gate. Another method applies a positive high voltage to a source region and grounds the overlying gate. The electric field across the layer that separates the source region and the floating gate is sufficient to cause the tunneling of electrons from the floating gate into the source region.
• Typically, one control gate and one floating gate form a memory cell and store only one piece of data. Accordingly, to store a large number of data, a large number of memory cells are needed. Another problem faced with traditional memory cells is miniaturization. Shrinking the scale of transistors has made it more difficult to program the floating gate devices, and reduces the ability of the floating gate devices to hold a charge. When the overlaying gate cannot induce enough voltage onto the floating gate, the floating gate cannot retain enough charge for a meaningful read-out. Therefore, the traditional transistor layout is reaching a limitation in miniaturization.
SUMMARY OF THE INVENTION
• In one aspect, the invention is an electrically alterable memory device. The memory device includes a semiconductor substrate and a semiconductor well. The semiconductor substrate is doped with a first dopant in a first concentration, and a semiconductor well, adjacent the semiconductor substrate, is doped with a second dopant that has an opposite electrical characteristic than the first dopant. The semiconductor well having a top side on which two spaced-apart diffusion regions are embedded. Each diffusion region is doped with the first dopant in a second concentration greater than the first concentration. The two diffusion regions includes a first diffusion region and a second diffusion region, and a first channel region is defined between the first diffusion region and the second diffusion region. The memory device also includes a first floating gate, a second floating gate, and a control gate. The first floating gate is disposed adjacent the first diffusion region and above the first channel region and separated therefrom by a first insulator region. The first floating gate has a first height and is made from a conductive material and capable of storing electrical charge. The second floating gate is disposed adjacent the second diffusion region and above the first channel region and separated therefrom by a second insulator region. The second floating gate has a second height and is made from a conductive material and capable of storing electrical charge. The control gate is disposed laterally between the first floating gate and the second floating gate. The control gate is separated from the first floating gate by a first vertical insulator layer and separated from the second floating gate by a second vertical insulator layer. The control gate is disposed above the first channel region and separated therefrom by a third insulator region. The control gate has a third height and is made from a conductive material.
• In another aspect, the invention is an electrically alterable memory string. The memory string includes a plurality of memory devices, each memory device having a control transistor capable of storing a plurality of data. The plurality of memory devices has a first end and a second end. A first select transistor connected to the first end, a second select transistor connected to the second end, and a connector connecting the first select transistor to a bit line.
• In another aspect, the invention is an electrically alterable non-volatile memory array. The memory array includes a plurality of memory strings, each memory string having a fast connector connected to a drain of a first select transistor in the memory string, a second connector connected to a gate of the first select transistor, a third connector connected to a gate of a memory cell transistor in the memory string, and a fourth connector connected to a gate of a second select transistor in the memory string. The plurality of memory strings are arranged in such way that the drain of the first select transistor in a fast memory string is connected to a source of the second select transistor in an adjacent second memory string. The memory array also includes a plurality of bit lines, wherein each bit line being connected to the first connector of every memory string, a plurality of first select lines, wherein each first select line being connected to the second connector of every memory string, a plurality of control lines, where each control line being connected to the third connector of every memory string, and a plurality of second select lines, wherein each second select line being connected to the fourth connector of every memory string.
• Other advantages and features of the present invention will become apparent after review of the hereinafter set forth Brief Description of the Drawings, Detailed Description of the Invention, and the Claims.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a top plan view of a plurality of memory strings according to one embodiment of the invention.
• FIG. 2A is a cross sectional view of the memory string taken along line2-2 ofFIG. 1.
• FIG. 2B is a cross sectional view of an alternative embodiment of the memory string taken along line2-2 ofFIG. 1.
• FIG. 3 is a cross sectional view of the memory string taken along line3-3 ofFIG. 1.
• FIG. 4 is a cross sectional view of the memory string taken along line4-4 ofFIG. 1.
• FIG. 5 is a top plan view of a plurality of memory strings according to one alternative embodiment of the invention.
• FIG. 6A is a cross sectional view of yet another alternative embodiment of the memory string taken along line6-6 ofFIG. 5.
• FIG. 6B is a cross sectional view of yet another alternative embodiment of the memory string taken along line6-6 ofFIG. 5.
• FIG. 6C is a cross sectional view of yet another alternative embodiment of the memory string taken along line6-6 ofFIG. 5.
• FIG. 7 is a schematic of a top plan of a plurality of memory cells according to one embodiment of the invention.
• FIG. 8 is a schematic of a top plan of a plurality of memory cells according to one alternative embodiment of the invention.
• FIG. 9 lists several combinations of operational voltages according to one embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
• Three electrically programmable and erasable non-volatile memory strings are shown inFIG. 1. Eachmemory string100 includes anactive region106 running vertically and a plurality ofcontrol gates102 running horizontally across multiple memory strings. The active region is heavily doped with a first dopant. The control gate is formed by polysilicon or other suitable material. A plurality of floatinggates104 are disposed adjacent to thecontrol gate102 and over theactive region106. Eachcontrol gate102 is surrounded by two floatinggates104 on two sides.
• The combination of two floatinggates104 surrounding onecontrol gate102 over one area of theactive region106 forms amemory cell103. Eachmemory cell103 stores two data, one on each floatinggate104. Eachmemory string100 may havemany memory cells103.
• Thememory cells103 on amemory string100 are delimited by a firstselect gate116 and a secondselect gate120. The firstselect gate116 and the secondselect gate120 run horizontally over allmemory strings100 and over theactive region106. The area of theactive region106 not covered by the floatinggates104, thecontrol gates102, and theselect gates114,116,118,120 are doped diffusion regions. Avertical connector121 connects theactive region106 to abit line110 that runs vertically through multiple memory strings100.
• Eachmemory string100 is connected to anadjacent memory string100 through theactive region106. The separation ofmemory cells103 in onememory string100 frommemory cells103 of anadjacent memory string100 may be accomplished through anisolation layer122, such as localized oxidation (LOCOS), recessed LOCOS, shallow trench isolation (STI), or full oxide isolation. A plurality ofmemory strings100 may form a high density memory array.
• FIG. 2A is across section view200 of amemory cell103 taken along line2-2 inFIG. 1. Thememory cell103 includes asemiconductor substrate202 and a well204 on the top of thesubstrate202. The substrate is doped with a first dopant, which can be either N type or P type. The well204 is a semiconductor doped with a second dopant with an electrical characteristic that is opposite of the first dopant. Two spaced-apartdiffusion regions106aand106b, which are part of theactive region106, are placed on the top side of thewell204. Thediffusion regions106a,106bare doped with the same dopant used for doping thesubstrate202 but doped with a concentration that is higher than that of thesubstrate202. Achannel region234 is defined between twodiffusion regions106a,106b. An insulatinglayer230 is placed on the top of the well204 and thediffusion regions106a,106b. The insulatinglayer230 may be formed by an insulating oxide material or other suitable insulating materials. ThoughFIG. 2A illustrates thediffusion regions106a,106bimplemented in a single well, it is understood that other implementations, such as twin wells, triple wells, or oxide isolation well may also be used. The separation of active devices may be accomplished through localized oxidation (LOCOS), recessed LOCOS, shallow trench isolation (STI), or full oxide isolation. A first floatinggate104aof polysilicon material is placed above thechannel region234 andadjacent diffusion region106a. The first floatinggate104amay overlap slightly with thediffusion region106a; however, excessive overlapping may reduce the length of thechannel region234. The first floatinggate104ais separated from thechannel region234 by atunnel channel214a(also known as tunnel oxide) of the insulatinglayer230. The thickness of thetunnel channel214ashould be thin enough to allow removal of electrons from the first floatinggate104aunder the Fowler-Nordheim tunneling mechanism, but thick enough to prevent the occurrence of a leakage current between the first floatinggate104aand thewell204. The length of thetunnel channel214aunder the first floatinggate104acan be smaller than one lambda, where the lambda is defined by the technology used. For example, if the technology uses 0.18 μm, then one lambda is defined as 0.18 μm.
• A second floatinggate104bof polysilicon material is placed above thechannel region234 andadjacent diffusion region106b. The second floatinggate104bmay overlap slightly with thediffusion region106b; however, excessive overlapping may reduce the length of thechannel region234. The second floatinggate104bis separated from thechannel region234 by atunnel channel214b(also known as tunnel oxide) of the insulatinglayer230. The thickness of thetunnel channel214bshould be thin enough to allow removal of electrons from the first floatinggate104bunder the Fowler-Nordheim tunneling mechanism, but thick enough to prevent the occurrence of a leakage current between the second floatinggate104band thewell204.
• Acontrol gate102 is placed above thechannel region234, laterally between the first floatinggate104aand the second floatinggate104b. Thecontrol gate102 is separated from the first floatinggate104aby a first vertical insulatinglayer212aand from the second floatinggate104bby a second vertical insulatinglayer212b. The insulatinglayers212a,212bcan be oxide-nitride-oxide or other suitable material. Thecontrol gate102 is separated from thechannel region234 by a separation channel216 (also known as separation oxide) of the insulatinglayer230. The thickness of theseparation channel216 should be thick enough to sustain the stress from the control gate's102 voltage variation. The voltage at thecontrol gate102 may vary during operation of thememory cell103 and cause stress on theseparation channel216, thus leading to the deterioration of theseparation channel216. Thecontrol gate102 may be formed by a polysilicon grown at a different stage as the floatinggates104a,104b. Thecontrol gate102 is connected to control gates in other memory cells in different memory strings. Thecontrol gate102 is surrounded by two floatinggates104a,104b.
• The fast floatinggate104ahas a first height measured from its bottom edge to its top edge and the second floatinggate104bhas second height also measured from its bottom edge to its top edge. Thecontrol gate102 has a third height measured from its bottom edge to its top edge. The first height, the second height, and the third height may be identical or may be different. The first height and the second height may be taller or shorter than the third height.
• The cross section view of one alternative embodiments of thememory cell103 taken along line2-2 inFIG. 1 is shown inFIG. 2B.FIG. 2B illustrates across section view300, where each floatinggate104aand104bsurrounds thecontrol gate102 on more than one lateral side. Because of greater exposure of the surface of a floatinggate104a,104bto thecontrol gate102, greater the coupling ratio between the control gate's voltage and the floating gate voltage can be achieved.
• Referring back toFIG. 2A, when a voltage is applied to thecontrol gate102, through a coupling effect, a voltage is induced on the floatinggates104a,104b. The voltage induced depends on a coupling ratio between thecontrol gate102 and the floatinggate104a. The coupling ratio is defined as the capacitance ratio between the capacitance between thecontrol gate102 and the floatinggate104aand the capacitance between the floatinggate104aand thesubstrate204.
• C(CG/FG)=capacitance between the control gate and the floating gate
• C(FG/Substrate)=capacitance between the floating gate and the substrate
• Gamma=coupling ratio
• $\mathrm{Gamma}=\frac{C\left(\frac{\mathrm{CG}}{\mathrm{FG}}\right)}{C\left(\frac{\mathrm{CG}}{\mathrm{FG}}\right)+C\left(\frac{\mathrm{FG}}{\mathrm{Substrate}}\right)}$
• When a V_CGis applied to the control gate, the voltage at the floating gate is:
• 
  V_FG=V_CG×Gamma
• The coupling effect depends on the thickness of thelayers212a,212bseparating thecontrol gate102 from the floatinggates104a,104band the area on each floatinggate104a,104bexposed to the coupling effect. The coupling effect can be easily increased by increasing the area of the floating gate210 exposed to the control gate212, and the area of the floating gate210 exposed to the control gate2′12 may be increased by increasing theheight234 of the control gate212 and theheight232 of the floating gate210. A capacitor is formed between thecontrol gate102 and each floatinggate104a,104b. When a floatinggate104a,104bis surrounded by acontrol gate102 in more than one lateral side, the coupling effect is increased and the capacitance between the floatinggate104a,104band thecontrol gate102 is increased. If thelayer212a,212bseparating thecontrol gate102 and the floatinggate104a,104bis too thin, a leakage current may occur between the floatinggate104a,104band thecontrol gate102 when the floatinggate104a,104bis charged with electrons. If thelayer212a,212bis too thick, the coupling ratio may be low, resulting in a low voltage in the floating gate. One workable coupling ratio is between 50%-80%, i.e., 10 V applied to thecontrol gate102 results in 5 V to 8 V induced in the floatinggate104a,104b. The combination of thecontrol gate102, the floatinggates104a,104b, and thediffusion regions106a,106bforms a control transistor. The control transistor is capable of holding two data independently, one in each floatinggate104a,104b. Each floatinggate104a,104bmay be independently programmed.
• The induction of voltage on the floatinggate104a,104bis important when erasing or programming amemory cell103. When programming the floatinggate104bof amemory cell103 of N-type diffusion, a positive high voltage (Vpp) between 4V and 11V is applied to thecontrol gate102, and thediffusion region106aand the well204 are left at 0 V. A positive high voltage between 4V and 11V is also applied to thediffusion region106b. The positive high voltage depends on the technology used. A voltage is induced to the floatinggates104a,104bby the Vpp at thecontrol gate102 through the coupling effect. When thecontrol gate102 is at the Vpp and inducing voltages onto the floatinggates104a,104b, thechannel234 between thediffusion regions106aand106bare conductive. With thechannel234 being conductive and thediffusion region106bat the Vpp, electrons flow between thediffusion regions106a,106b, and the phenomenon of impact ionization (several occurrences) occurs near thediffusion region106b. The impact ionization occurs when charge carriers moving toward thediffusion region106bgenerate electron-hole pairs from the lattice near the drain junction (diffusion region106b). The generated carriers look for high positive voltage and are injected into the floatinggate104b. The carriers emitted from thesource region106aexperience lateral electrical field between thediffusion regions106aand106b. The average carder energy is higher near the drain junction of thediffusion region106b. The impact ionization tends to occur near thediffusion region106b. Of free electrons, only lucky few will be injected into the floatinggate104b, and this is known as Lucky electron model. The amount of electrons injected into the floatinggate104bdepends on the positive high voltage applied to thecontrol gate102 and the duration of this positive high voltage. To program the floatinggate104a, the similar process may be used but the voltages at thediffusion regions106aand106bare reversed, i.e., a positive high voltage is applied to thediffusion region106awhile thediffusion region106band the well204 are at zero volt.
• A ramping positive high voltage (Vppr) may be applied to thecontrol gate102 to program a floatinggate104bin a memory cell of P-type diffusion. A positive high voltage between 4V and 11V is initially applied to thecontrol gate102, and this positive high voltage is gradually ramped down to 0V and then ramped up back to 4V-11V. A positive high voltage is applied to thediffusion region106aand 0V is applied to thediffusion region106b. When thecontrol gate102 is at the positive high voltage of 4V-11V, a voltage is induced onto the floatinggate104band thechannel234 between thediffusion regions106aand106bis turned off. Although the floatinggate104bis at a positive voltage level, no electrons are injected into the floatinggate104bbecause thechannel234 is off and there is no flow of electrons between thediffusion regions106aand106b. As the voltage at thecontrol gate102 ramps down, the potential difference between thecontrol gate102 and the well204 turns on the channel between thediffusion regions106aand106b, and electrons start to flow in thechannel234. The voltage at the floatinggate104balso drops as the voltage at thecontrol gate102 ramps down, but the voltage at the floatinggate104bis still sufficient to cause some high energy electrons (also known as hot electrons) to be injected into the floatinggate104b. When thecontrol gate102 reaches zero voltage, thechannel234 is turned on, but no electrons are injected into the floatinggate104bbecause the floatinggate104bis also at zero voltage. When the voltage at thecontrol gate102 starts to ramp up back to 4V-11V, the voltage at the floatinggate104balso ramps up, and high energy electrons from thechannel234 start to be injected into the floatinggate104bagain. When thecontrol gate102 is at positive high voltage of 4V-11V, thechannel234 is turned off, electrons stop flowing, and no more electrons are injected into the floatinggate104b. The number of electrons injected into the floatinggate104bdepends on the duration of the ramp down/up process and the concentration of dopants in the channel region. This voltage ramping process may be repeated for the floating gate to retain enough charge to represent a logic state properly. Once charges of electrons are inside of the floatinggate104b, the floatinggate104bmay hold the charges for years. The voltage ramping may also be used to program memory cells of N-type diffusion.
• The amount of charge injected into a floatinggate104a, determines the threshold voltage for the control transistor formed by thecontrol gate102, the floatinggates104a,104b, and thediffusion regions106a,106b. The floatinggate104amay hold different amount of charges, thus having different threshold voltages. In one embodiment of the invention, through repeating the voltage ramping process, the floatinggate104amay have four different levels of threshold voltages and capable of representing four logic states. The four logic states may be read and distinguished by measuring the current flowing between thediffusion regions106a,106b.
• A P-type diffusion memory cell may also be programmed with a different mechanism. Applying a negative voltage between −1V and −10V todiffusion region106b, a positive high voltage to thecontrol gate102, and a voltage between 0V and Vcc to the well204, charges can be programmed into floatinggate104b. The high positive voltage of thecontrol gate102 induces a voltage into the floatinggate104b. The difference of potential between the well204 and thediffusion region106bcauses a soft avalanche breakdown between thediffusion region106b(P-type) and the well204 (N-type). Some of the electrons from this soft breakdown are injected into the floatinggate104bbecause the floatinggate104bis at higher voltage.
• A negative voltage is applied between −4.5V and −10V to thecontrol gate102, a positive high voltage is applied to the well204 when it is desired to erase charges in thememory cell103 of N-type diffusion. The negative voltage at thecontrol gate103 is induced to the floatinggates104a,104b. The combination of an induced negative voltage at the floatinggates104a,104band positive high voltages at the well204 forces electrons out of the floatinggates104a,104band into the well204, thus removing the electrons from the floatinggates104a,104b. The electrons are removed through the Fowler-Nordheim tunneling mechanism.
• A negative voltage is applied between 4.5V and −10V to thecontrol gate102, a positive high voltage is applied to the well204 and thediffusion regions106a,106bwhen it is desired to erase charges in thememory cell103 of P-type diffusion. The mechanism to remove the electrons is similar to what has been described above for the N-type diffusion except that the positive high voltage is needed at thediffusion regions106aand106bbecause otherwise thechannel234 may be floating at an unknown voltage and impeding the exit of electrons from the floatinggates104a,104b.
• When it is desired to read the content from a floatinggate104aof amemory cell103, a voltage between 0V and Vcc is applied to thecontrol gate102, a voltage between 0 V to Vcc is applied todiffusion region106b, and 0V to −2V is applied to two select gates (not shown inFIG. 2A) in the memory string, one at each end of the memory string. The voltage at thecontrol gate102 turns on the portion of thechannel234 under it. The threshold voltage (Vt) for the floatinggate104bis lowered because of drain-induced barrier lowering (DIBL) and a depletion region is created under the floatinggate104b. If the floatinggate104ahas charge, the portion of thechannel234 under it will be on and a current flows fromdiffusion region106btodiffusion region106a. Thechannel234 under the floatinggate104aand thecontrol gate102 is on, the current passes under the floatinggate104aand thecontrol gate102, and then enter the depletion region under the floatinggate104b. The current will continue to flow through the depletion region under the floatinggate104atoward thediffusion region106a. Because the select gates are at 0V to −2V, the current resulting from the electron flow is sensed by a bit line and a sense-amplifier connected to the bit line. The data stored in the floatinggate104acomes out from the drain of the control transistor. When the floatinggate104ais programmed to store different levels of charge and thus with different levels of threshold voltage, the intensity of the current flowing betweendiffusion region106aanddiffusion region106bdepends on the threshold voltage of the floatinggate104a. The intensity of this current can be sensed by the sense-amplifier, thus the logic level of the floatinggate104adetermined.
• If the floatinggate104ais without charge, then the portion of thechannel234 under the floatinggate104awill not be turned on and there will be no current or small leakage current flowing betweendiffusion region106banddiffusion region106a. The leakage current should be different from the current flowing when the floatinggate104ais charged. If the floatinggate104ais not charged, then no channel is established between thediffusion regions106aand106band the sense-amplifier will not be able to detect any current. The absence of a current between thediffusion regions106aand106bindicates the floatinggate104ais without electrons. A floatinggate104awith electrons is assigned to a first logic state while a floatinggate104awithout electrons or with too few electrons is assigned to an opposite second logic state. Other operations not described here can be easily understood based on voltages listed inFIG. 9 and operations described above by those skilled in the art. When reading the content of a floatinggate104ain an N-type diffusion device, 0V is applied to106a, and 1V to 2.5V is applied to106b. The voltage in thediffusion region106bwill lower the threshold voltage of the floatinggate104bbecause of DIBL effect.
• FIG. 3 is across section view400 taken along line3-3 inFIG. 1.FIG. 3 illustrates a cross section view of amemory string100. Thememory string100 includes asubstrate202 doped with a first dopant, which can be either N type or P type, and a well204 doped with a second dopant with an electrical characteristic that is opposite of the first dopant. A plurality ofdiffusion regions106, which are part of theactive region106 inFIG. 1, are placed on the top side of thewell204. Thediffusion regions106 are doped with the same dopant used for doping thesubstrate202 but doped with a concentration that is higher than that of thesubstrate202. A plurality of control transistors are placed adjacent each other. Each control transistor includes acontrol gate102, two floatinggates104, and twodiffusion regions106, one diffusion region being the drain of the control transistor while the other diffusion region is the source. Two adjacent control transistors share onecommon diffusion region106. Each control transistor is a memory cell. There is oneselect transistor402 at one end of this “string” of memory cells and anotherselect transistor404 at the other end of the string of memory cells. There is avertical contact406 connecting onediffusion region106 at the end of the memory string to abit line108 inFIG. 1. Adiffusion region106 from onememory string100 is connected to adiffusion region106 of an adjacent memory string100 (shown inFIG. 1).FIG. 4 is across section view500 taken along line44 inFIG. 1. It is shown that memory strings represented by a floatinggate104 are separated from each other by isolation layers122.
• FIG. 5 is a top plan view of an alternative embodiment of the invention. In this embodiment thememory cells603 in onememory string600 are between twodiffusion regions106a,106b. Eachcontrol gate102 runs horizontally inFIG. 5 and across different memory strings600. Eachmemory string600 is delimited by two select gate transistors SG0a, SG1ain a manner similar as that depicted inFIG. 1. OneSTI612 separates one diffusion region of onememory string600 from a diffusion region for an adjacent memory string. Thediffusion region106ais connected to abit line602 through a buried contact and thediffusion region106bis connected to abit line604 also through a buried contact. When it is desirable to read a data from a floatinggate104bof amemory cell603, thecontrol gate102 for the selected memory cell is turned on. Abit line604 is connected to a source voltage. The voltage at thebit line604 is propagated through thediffusion region106bto thememory cell603. The read operation at thememory cell603 is similar to that described forFIG. 2. The data is read from the drain of the control gate transistor,bit line602. The program and ease operations for the embodiment ofFIG. 5 are same as those previously described forFIG. 2. For the embodiment ofFIG. 5, there is no need to turn on the control transistors of unselected memory cells. As matter of fact, the control transistors of unselected memory cells are turned off to prevent short betweendiffusion regions106aand106b.
• FIG. 6A is across section view700 taken along line6-6 inFIG. 5. The floatinggates104a,104bare surrounded by thecontrol gate102 from top and two lateral sides.FIG. 6B is across section view800 of an alternative embodiment taken along line6-6 inFIG. 5.FIG. 6C is across section view900 of yet another alternative embodiment taken along line6-6 inFIG. 5. It is also illustrated inFIG. 6C twooxidation sections612a,612b. Eachoxidation section612adisposed on the top of adiffusion region106a. Theoxidation section612 does not divide adiffusion region106 into two, but it does lessen the capacitance of thediffusion region106. When the capacitance of adiffusion region106 is smaller, the fast is the speed a data can be read out from amemory cell603.
• FIG. 7 is a schematic representation of part of amemory array1000 made from the memory strings100.Memory cells1002 in one memory string (running vertically inFIG. 7) are interconnected. The drain of one memory cell is connected to the source of an adjacent memory cell. Each memory string includes twoselect transistors1003,1005 one at each end of the memory string. One end of the memory string is connected to abit line1018 and also connected to an adjacent memory string. The memory strings are disposed parallel to each other and the resulting memory array are organized in rows and columns. Theselect transistors1003 of odd columns are controlled by oneselect line1004, while theselect transistors1003 of even columns are controlled by anotherselect line1006. Similarly, theselect transistors1005 of odd columns are controlled by oneselect line1016, while theselect transistors1005 of even columns are controlled by anotherselect line1014. The control transistors in one memory row are interconnected together and controlled by a control line. Data operations to one floating of a memory cell in one memory string is controlled by activating proper control line, select lines, and bit lines as described above forFIG. 2A. The activation of control lines and select lines depends on an X-address decoder (not shown) and the activation of bit lines depends on a Y-address decoder (not shown). Each bit line may be connected to a charging transistor and a discharging transistor (not shown) that are also controlled by the Y-address decoder.
• FIG. 8 is a schematic presentation of amemory array1100 made from memory strings600. One side of a control transistor of thememory cell1112 is connected to abit line1102, other side of the control transistor is connected to anotherbit line1104, and the gate of the control transistor is connected to acontrol gate line1106. Other select logics for enabling and selecting each memory cell are not shown inFIG. 8 but are easily understood by those skilled in the art.
• The thickness of each gate (control gate, and floating gate) depends on the manufacturing process; currently most common thickness is about 3000 Angstroms or 0.3 micron. The thickness of thetunnel channels214a,214bdepend also on manufacturing process. However, a preferred thickness for thetunnel channels214a,214bis between 70 Angstroms and 110 Angstroms. Similarly, the thickness of the insulating layer separating thecontrol gate102 from the well204 is between 150 Angstroms and 250 Angstroms. The materials and measurements mentioned heretofore are for illustration purposes and not intended to limit the scope of the present invention. It is recognized that as technology evolves, other suitable materials and manufacturing processes may be employed to realize the present invention. It is also understood that the structures disclosed heretofore can be easily implemented by any of existing semiconductor manufacturing processes known to those skilled in the art. It is also understood that the voltages illustrated inFIG. 9 is for illustration purposes, and other voltage combinations may be used. For example, voltages may be reduced for embodiments that have a large coupling ratio, and small voltages make manufacturing easier and enhance reliability.
• Although, the present application is described for Flash EEPROMs, it is understood that the invention is equally applicable for one-time-programmable (OTP) memories, multiple-time-programmable (MTP) memories, and other non-volatile memories.
• While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as set forth in the following claims. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims (10)

1. An electrically alterable memory device, comprising:

(a) a semiconductor substrate having a surface, comprising:

a first semiconductor layer of a first conductivity type at the surface of the semiconductor substrate, the first semiconductor layer having a first dopant concentration; and

a first diffusion region and a second diffusion region also provided at the surface of the semiconductor substrate spaced apart by a portion of the first semiconductor layer, thereby forming a channel region in the first semiconductor layer between the diffusion regions, each diffusion region being of a second conductivity type opposite to the first conductivity type and each diffusion region having a second dopant concentration greater than the first dopant concentration such that the first semiconductor layer and each diffusion region form a junction which breaks down according to a soft avalanche breakdown mechanism;

(b) a gate dielectric layer provided over the surface of the semiconductor substrate;

(c) a first floating gate and a second floating gate each comprising a conductive material, the floating gates respectively disposed at least in part overlapping the junctions, separated therefrom by the gate dielectric layer; and

(d) a control gate also comprising a conductive material, the control gate being disposed laterally between the first floating gate and the second floating gate and separated from each floating gate by an insulator layer having a thickness such that, when an electrical potential is imposed on the control gate, a portion of the electrical potential is capacitively coupled to the floating gates, and wherein the gate dielectric layer is of a thickness such that, when a soft avalanche break down occurs in a junction, electrical charge is injected by the capacitively coupled electrical potential into the corresponding overlapping floating gate.

2. The memory device ofclaim 1, wherein the gate dielectric layer allows tunneling of electrical charge between one of the floating gates and the channel region.

3. The memory device ofclaim 1, wherein the gate dielectric layer is between 70 Angstroms and 110 Angstroms thick.

4. The memory device ofclaim 1, wherein the insulator layer comprises a silicon dioxide having a thickness that is sufficiently thick to prevent current leakage between the control gate and each of the floating gates.

5. The memory device ofclaim 1, wherein the insulator layer comprises an oxide-nitride-oxide layer.

6. The memory device ofclaim 1, wherein each floating gate stores a predetermined amount of electrical charge controlled by the capacitively coupled electrical potential.

7. The memory device ofclaim 1, further comprising contacts to the first diffusion region and the second diffusion region, each contact being selectably coupled to a reference voltage or a variable voltage, so as to allow independent charging and discharging of the first floating gate and the second floating gate.

8. The memory device ofclaim 1, wherein the first and second diffusion regions are defined by a self-aligned process using the first and second floating gates, respectively.

9. The memory device ofclaim 1, wherein the first diffusion region and the second diffusion region are P-type.

10. The memory device ofclaim 9 wherein, when the soft avalanche breakdown mechanism occurs, the channel region is rendered non-conducting.

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