US20110042746A1 - Single transistor memory device having source and drain insulating regions and method of fabricating the same - Google Patents

Abstract

A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a divisional application of application Ser. No. 11/829,113 filed on Jul. 27, 2007, which claims priority from Korean Patent Application Nos. 10-2006-0107345 and 10-2006-0119087, filed on Nov. 1, 2006, and Nov. 29, 2006, respectively, the subject matters of which are hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a single transistor memory device having insulating regions associated with the source and drain regions, and a method of fabricating the same.
• 2. Description of the Related Art
• A conventional dynamic random access memory (DRAM) cell, which is a type of volatile memory, typically incorporates a capacitor, a transistor and interconnection units. In response to demands for electronic devices to be increasingly lightweight, small and thin, DRAM cells have become more highly integrated. That is, as many DRAM cells as possible are formed within a restricted space. However, the technology of highly integrating DRAM cells faces several limitations.
• For example, a typical DRAM cell capacitor includes upper and lower electrodes, and a capacitor dielectric layer. The upper and lower electrodes share an overlapping region, and the capacitor dielectric layer is positioned between the upper and lower electrodes. The capacitance of the capacitor is directly proportional to the size of the overlapping region, and inversely proportional to a thickness of the overlapping region. A minimum area for forming a capacitor is therefore required.
• A single transistor floating-body DRAM cell has been developed, which includes a floating body region for storing data. Because there is no capacitor, the single transistor floating-body DRAM cell may be more highly integrated than a common DRAM cell having a capacitor.
• A capacitor-less, single transistor DRAM cell is described, for example, in an article entitled “Scaled IT-bulk Devices Built with CMOS 90 nm Technology for Low-cost eDRAM Applications” by R. RANICA (IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39 (2005)).FIG. 1 herein is a cross-sectional view of a single transistor DRAM cell like that disclosed in the RANICA article.
• Referring toFIG. 1, a semiconductor substrate1 includes a deep n-well3 and a pocket p-well5 located in the deep n-well3. Anisolation layer7 is located within a predetermined region of the pocket p-well5, defining anactive layer5aof the pocket p-well5. Theisolation layer7 is in contact with the deep n-well3 through the pocket p-well5. As a result, theactive region5afunctions as an electrically floated bulk region, which is surrounded by theisolation layer7 and the deep n-well3.
• Source anddrain regions16sand16dare respectively located in both ends of thebulk region5a,and agate pattern10 is located on thebulk region5abetween the source anddrain regions16sand16d.Thegate pattern10 includes agate insulating layer8 and agate electrode9, which are sequentially stacked. Aspacer13 may be located on a sidewall of thegate pattern10. Thesource region16smay include a heavily-dopedsource region15sspaced apart from thegate pattern10, and a lightly-doped source region11sextending from the heavily-dopedsource region15s.Likewise, thedrain region16dmay include a heavily-dopeddrain region15dspaced apart from thegate pattern10, and a lightly-doped drain region11dextending from the heavily-dopeddrain region15d.The lightly-doped source anddrain regions11sand11dmay be located beneath thespacer13.
• According to RANICA, the source anddrain regions16sand16dare shallower in thickness than theactive region5a,i.e., the bulk region, as illustrated inFIG. 1. Thus, thebulk region5amay also extend under the source anddrain regions16sand16d.As a result, during a program operation, the number of holes stored in thebulk region5ais maximized. However, the holes stored in thebulk region5amay be recombined with electrons in the source anddrain regions16sand16dafter program operation, and erased in a short period of time. In other words, the single transistor DRAM cell illustrated inFIG. 1 has poor data retention characteristics.
• Furthermore, when the source anddrain regions16sand16dhave large junction areas, junction capacitances Cs and Cd of the source anddrain regions16sand16dalso increase. Thus, a loading capacitance of a bit line electrically connected to thedrain region16dincreases, which may lead to a decrease in a data sensing margin and operating speed of the single transistor DRAM cell.
• Another example of a single transistor floating-body DRAM device is disclosed in U.S. Patent Application Publication No. 2006/0049444, entitled “Semiconductor Device and Method of Fabricating the Same” by SHINO. According to SHINO, a floating body having a single crystal structure is located on a semiconductor substrate. The floating body has an expanded structure capable of storing excess holes, although the excess holes may be easily erased through source and drain regions.
SUMMARY OF THE INVENTION
• An aspect of the present invention provides a single transistor floating-body dynamic random access memory (DRAM) device, including a floating body located on a semiconductor substrate, the floating body having an excess carrier storage region, and a gate electrode located on the floating body. Source and drain regions are respectively located at both sides of the gate electrode, each of the source and drain regions contacting the floating body. Leakage shielding patterns are located between the floating body and the source and drain regions. The leakage shielding patterns may arranged at outer sides of the gate electrode, and may contact bottom surfaces of the source and drain regions. The leakage shielding patterns may include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.
• The floating body may be positioned between the source and drain regions, and may laterally extend under the leakage shielding patterns. The floating body may include a single crystal semiconductor layer having p-type impurity ions. A width of the excess carrier storage region of the floating body may be larger than a width of the gate electrode.
• The DRAM device may further include a buried insulating layer located between the semiconductor substrate and the floating body, and an isolation layer defining the floating body, where the leakage shielding patterns contact the isolation layer. Also, the semiconductor substrate may be configured to serve as a back gate electrode.
• Another aspect of the present invention provides a method of fabricating a single transistor floating-body DRAM device, including defining a floating body in a semiconductor substrate, forming a gate pattern on the floating body, and forming leakage shielding patterns in the floating body at both sides of the gate pattern. The floating body includes an excess carrier storage region, which may extend beneath the leakage shielding patterns and between the source and drain regions. Forming the leakage shielding patterns may include injecting oxygen ions into the floating body using the gate pattern as a mask to form temporary patterns, and annealing the temporary patterns. Forming the leakage shielding patterns may also include injecting germanium (Ge) ions into the floating body using the gate pattern as a mask to form temporary patterns, etching the temporary patterns to form gaps, and filling the gaps with an insulating layer.
• The method of fabricating the DRAM device may further include forming source and drain regions in the floating body above the gaps, and forming source and drain regions in contact with the leakage shielding patterns. Also, a gate dielectric layer may be formed on the floating body prior to forming the gate pattern. Forming the gate pattern may include sequentially stacking a gate electrode, a pad oxide layer and a mask nitride layer. Also, defining the floating body in the semiconductor substrate may include forming an isolation layer.
• Another aspect of the present invention provides a single transistor memory cell, including an active semiconductor pattern having a bulk region and an impurity region, stacked in sequence on a semiconductor substrate, and insulated from the semiconductor substrate. The memory cell also includes a recessed region passing through the impurity region, dividing the impurity region into a source region and a drain region, which are separated from each other, where the recessed region includes first and second sidewalls adjacent to the source and drain regions, respectively. A first insulating region is positioned between the source region and the bulk region, and separated from the first sidewall of the recessed region, and a second insulating region is positioned between the drain region and the bulk region, and separated from the second sidewall of the recessed region. Each of the first insulating region and the second insulating region may include one of an empty space or an insulating layer pattern. A gate electrode is positioned within the recessed region.
• A conductivity type of the impurity region may be different than a conductivity type of the bulk region. The bulk region may include a lower bulk region and an upper bulk region, the lower bulk region having a higher impurity concentration than the upper bulk region. In addition, the bulk region may include a first bulk region extending between the first insulating region and the first sidewall, and a second bulk region extending between the second insulating region and the second sidewall. Also, the gate electrode may include a projecting portion that extends above an upper surface of the impurity region, and a spacer may cover sidewalls of the projecting portion of the gate electrode. The first and second bulk regions may be aligned with the spacer. A gate insulating layer may be positioned between the gate electrode and the first and second sidewalls of the recessed region. Also, an insulating layer may cover the semiconductor substrate, the source and drain regions and the gate electrode. The memory cell may further include a back gate interconnection located on the insulating layer, and electrically connected to the semiconductor substrate through a back gate contact hole passing through the insulating layer.
• Yet another aspect of the present invention provides a method of fabricating a single transistor memory cell, including forming an active semiconductor pattern surrounded by an isolation layer on a semiconductor substrate, the active semiconductor pattern including a bulk region and an impurity region, which are sequentially stacked. The method further includes forming a gate pattern passing through the impurity region to divide the impurity region into a source region and a drain region, which are separated from each other, and forming spacers on sidewalls of the gate pattern. Sacrificial impurity ions are injected into the bulk region, using the gate pattern and the spacers as ion injection masks, to form first and second sacrificial impurity layers under the source and drain regions, respectively. The sacrificial impurity ions may be silicon germanium ions. The isolation layer is etched to expose the first and second sacrificial impurity layers, and the first and second sacrificial impurity layers are removed to form first and second undercut regions, exposing bottom surfaces of the source and drain regions, respectively. An insulating layer is formed on the semiconductor substrate having the first and second undercut regions.
• Forming the active semiconductor pattern may include preparing a silicon on insulator (SOI) substrate comprising a supporting substrate, a buried insulating layer and a semiconductor body layer, which are sequentially stacked; forming an isolation layer in contact with the buried insulating layer in a predetermined region of the semiconductor body layer to define an isolated semiconductor body pattern; and forming the impurity region in an upper portion of the semiconductor body pattern to define the bulk region under the impurity region. Also, forming the active semiconductor pattern may include preparing an SOI substrate having a supporting substrate, a buried insulating layer and a semiconductor body layer, which are sequentially stacked; forming the impurity layer in an upper portion of the semiconductor body layer to define the bulk layer under the impurity layer; and forming an isolation layer contacting the buried insulating layer in predetermined portions of the impurity layer and the bulk layer to define an isolated semiconductor body pattern comprising the bulk region and the impurity region.
• Forming the gate pattern may include forming a mask pattern covering the impurity region and the isolation layer, the mask pattern defining an opening over the impurity region; forming a recessed region by etching the impurity region and the bulk region using the mask pattern as an etch mask, the recessed region dividing the impurity region into the source and drain regions; forming a gate insulating layer covering a bottom surface and sidewalls of the recessed region; forming a gate electrode and a capping insulating layer pattern, which are sequentially stacked, on the gate insulating layer within the recessed region; and removing the mask pattern to expose the gate electrode and the capping insulating layer pattern.
• The first and second sacrificial impurity layers may be formed to have bottom surfaces above the bulk region, and may define a first bulk region between the first sacrificial impurity layer and the recessed region and a second bulk region between the second sacrificial impurity layer and the recessed region. The insulating layer may be formed to leave empty spaces in the first and second undercut regions, or to fill the first and second undercut regions. The method may further include patterning the insulating layer and forming a back gate contact hole to expose the semiconductor substrate, and forming a back gate interconnection electrically connected to the semiconductor substrate through the back gate contact hole.
BRIEF DESCRIPTION OF THE DRAWINGS
• The embodiments of the present invention will be described with reference to the attached drawings, not necessarily drawn to scale, in which:
• FIG. 1 is a cross-sectional view of a conventional single transistor memory cell;
• FIG. 2 is a cross-sectional view of a single transistor floating-body DRAM device, according to a first exemplary embodiment of the present invention;
• FIG. 3 is a cross-sectional view of a single transistor floating-body DRAM device, according to a second exemplary embodiment of the present invention;
• FIG. 4 is a plan view of a single transistor memory cell, according to a third exemplary embodiment of the present invention;
• FIG. 5 is a cross-sectional view taken along line I-I′ ofFIG. 4;
• FIG. 6 is a cross-sectional view illustrating a method of programming a single transistor memory cell, according to the third exemplary embodiment of the present invention;
• FIG. 7 is a cross-sectional view illustrating a method of erasing a single transistor memory cell, according to the third exemplary embodiment of the present invention;
• FIGS. 8 to 11 are cross-sectional views illustrating a method of fabricating a single transistor floating body DRAM device, according to the first exemplary embodiment of the present invention;
• FIGS. 12 to 15 are cross-sectional views illustrating a method of fabricating a single transistor floating body DRAM device, according to the second exemplary embodiment of the present invention; and
• FIGS. 16 to 24 are cross-sectional views illustrating a method of fabricating a single transistor memory cell, according to the third exemplary embodiment of the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
• The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention, however, may be embodied in various different forms, and should not be construed as being limited only to the illustrated embodiments. Rather, these embodiments are located as examples, to convey the concept of the invention to one skilled in the art. Accordingly, known processes, elements, and techniques are not described with respect to some of the embodiments of the present invention. Throughout the drawings and written description, like reference numerals will be used to refer to like or similar elements.
• In the drawings, the thickness of layers and regions may be exaggerated for clarity. Also, when a layer is described to be formed on other layer or on a substrate, this means that the layer may be formed on the other layer or on the substrate, or a third layer may be positioned between the layer and the other layer or the substrate.
• FIG. 2 is a cross-sectional view of a single transistor floating-body dynamic random access memory (DRAM) device, according to a first exemplary embodiment of the present invention.
• Referring toFIG. 2, a floatingbody55 is on asemiconductor substrate51. Agate electrode63 may be located on the floatingbody55, and source and drainregions73 may be positioned at both sides of thegate electrode63. The source and drainregions73 may be in contact with the floatingbody55.Leakage shielding patterns71′ may be located between the floatingbody55 and the source and drainregions73. An excesscarrier storage region55S may be included in the floatingbody55.
• Thesemiconductor substrate51 may be a single crystal silicon wafer, for example, and the floatingbody55 may be a semiconductor layer formed from single crystal silicon, for example. P- or n-type impurity ions may have been injected into the floatingbody55. Also, the impurity ions may show a graded ion profile in the floatingbody55. For example, the p-type impurity ions may gradually decrease in concentration toward a surface of the floatingbody55.
• Assuming that the floatingbody55 has p-type impurity ions, the device will be described below. A buried insulatinglayer52 may be positioned between thesemiconductor substrate51 and the floatingbody55. In this case, the buried insulatinglayer52 may cover thesemiconductor substrate51. The buried insulatinglayer52 may be an insulating layer, such as a silicon oxide layer. The buried insulatinglayer52 insulates the floatingbody55 from thesemiconductor substrate51.
• Anisolation layer53, defining the floatingbody55, is positioned on the buried insulatinglayer52, and may surround the floatingbody55. Theisolation layer53 may be an insulating layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.
• Agate dielectric layer61 may be positioned between the floatingbody55 and thegate electrode63. Thegate dielectric layer61 may be a silicon oxide layer or a high-k dielectric layer, for example.
• Amask nitride layer67 may be located on thegate electrode63. Apad oxide layer65 may be positioned between thegate electrode63 and themask nitride layer67. Thegate electrode63, thepad oxide layer65 and themask nitride layer67, which are sequentially stacked, may constitute a gate pattern. Thegate electrode63 may be formed from a conductive layer, such as a polysilicon layer, a metal silicide layer, a metal layer, or a combination thereof. Themask nitride layer67 may be a nitride layer, such as a silicon nitride layer. Thepad oxide layer65 may be a silicon oxide layer.
• The source and drainregions73 may include impurity ions with a different conductivity type from the floatingbody55. For example, when the floatingbody55 has the p-type impurity ions, the source and drainregions73 may include n-type impurity ions. The source and drainregions73 may be located at both sides of thegate electrode63. Also, the source and drainregions73 may be positioned to face each other over a space or distance, in which case, at least a portion of the floatingbody55 may be positioned between the source and drainregions73 within the space.
• Theleakage shielding patterns71′ may be located under the source and drainregions73. In this case, the floatingbody55 may extend beneath theleakage shielding patterns71′. Theleakage shielding patterns71′ may be arranged at outer sides of thegate electrode63. Theleakage shielding patterns71′ may be insulating layers, such as silicon oxide layers.
• As a result, the floatingbody55 may be positioned between the source and drainregions73 facing each other, and extend beneath theleakage shielding patterns71′. Also, the floatingbody55 may have a larger width than thegate electrode63. The excesscarrier storage region55S may likewise have a larger width than thegate electrode63.
• One of the source and drainregions73 is electrically connected to a source line S, and the other of the source and drainregions73 is electrically connected to a drain line D. Thegate electrode63 is electrically connected to a gate line G. Also, thesemiconductor substrate51 may be electrically connected to a back gate line BG. In an embodiment, the source line S may be connected to a ground terminal, the drain line D may be a bit line, and the gate line G may be a word line.
• Storing data, i.e., a write operation, in a floating body DRAM device according to the first exemplary embodiment of the present invention will now be explained. A gate program voltage higher than a threshold voltage (Vt) may be applied to thegate electrode63, and a bit program voltage may be applied to the drain line D. The source line S may be grounded. The bit program voltage may be a positive voltage.
• In this case, electron-hole pairs (EHP) are generated in the floatingbody55 by impact ionization. The electrons generated by impact ionization may flow through the drain line D, whereas the holes generated by impact ionization may be accumulated in the excesscarrier storage region55S. That is, excess holes are accumulated in the excesscarrier storage region55S. The excess holes accumulated in the excesscarrier storage region55S change the threshold voltage (Vt).
• However, a contact surface of the source and drainregions73 and floatingbody55 may be minimized by theleakage shielding patterns71′. In other words, theleakage shielding patterns71′ may serve to block a leakage path of the excess holes. Accordingly, theleakage shielding patterns71′ may serve to extend the time during which the excess holes are retained in the excesscarrier storage region55S. As a result, according to the first exemplary embodiment of the present invention, the retention time of the excess holes accumulated in the excesscarrier storage region55S is significantly increased.
• Furthermore, a back gate voltage may be applied to the back gate line BG, enabling thesemiconductor substrate51 to serve as a back gate, further extending the retention time of the excess holes.
• The erase operation of the floating body DRAM device may be performed by applying a gate program voltage higher than the threshold voltage (Vt) to thegate electrode63, and applying a bit erase voltage to the drain line D. The source line S may be grounded. The bit erase voltage may be a negative voltage. The excess holes accumulated in the excesscarrier storage region55S may be erased by the erase operation.
• A read operation of the floating body DRAM device may be performed by applying a gate read voltage lower than the gate program voltage to thegate electrode63, and applying a bit read voltage to the drain line D. The source line S may be grounded. An amount of current flowing between the source line S and the drain line D may be different depending on the existence or nonexistence of the excess holes. The data stored in the floating body DRAM device may be read out by sensing the amount of current flowing between the source line S and the drain line D.
• FIG. 3 is a cross-sectional view of a single transistor floating-body DRAM device according to a second exemplary embodiment of the present invention.
• Referring toFIG. 3, a floatingbody155 is on asemiconductor substrate151. Agate electrode163 may be located on the floatingbody155. Source anddrain regions173 may be located at both sides of thegate electrode163. The source and drainregions173 may be in contact with the floatingbody155.Leakage shielding patterns171′ may be positioned between the floatingbody155 and the source and drainregions173. An excesscarrier storage region155S may be located in the floatingbody155.
• Thesemiconductor substrate151 may be a single crystal silicon wafer, for example. The floatingbody155 may be a semiconductor layer, for example, formed of single crystal silicon. P-type impurity ions may be injected into the floatingbody155. The p-type impurity ions may decrease in concentration toward a surface of the floatingbody155.
• A buried insulatinglayer152 may be positioned between thesemiconductor substrate151 and the floatingbody155. Anisolation layer153 defining the floatingbody155 may be on the buried insulatinglayer152. Agate dielectric layer161 may be positioned between the floatingbody155 and thegate electrode163. Apad oxide layer165 and amask nitride layer167, which are sequentially stacked, may be located on thegate electrode163.
• The source and drainregions173 may have impurity ions with a different conductivity type from the floatingbody155. For example, when the floatingbody155 has the p-type impurity ions, the source and drainregions173 may include n-type impurity ions. The source and drainregions173 may be located at both sides of thegate electrode163, respectively. Also, the source and drainregions173 may be positioned to face each other over a space or distance. In this case, at least a portion of the floatingbody155 may be positioned between the source and drainregions173 within the space.
• An interlayer insulatinglayer177 covering sidewalls of the source and drainregions173 may be included above thesemiconductor substrate151. In an embodiment, top surfaces of the interlayer insulatinglayer177 and themask nitride layer167 may be exposed on the same plane. The interlayer insulatinglayer177 may be an insulating layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.
• The interlayer insulatinglayer177 may extend between the source and drainregions173 and the floatingbody155, and thus serve as theleakage shielding patterns171′, located under the source and drainregions173. In the depicted embodiment, the floatingbody155 may extend through theleakage shielding patterns171′. Theleakage shielding patterns171′ may be arranged on outer sides of thegate electrode163. Theleakage shielding patterns171′ may be formed of an insulating layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.
• As a result, the floatingbody155 may be positioned between the source and drainregions173 facing each other and extending beneath theleakage shielding patterns171′. The floatingbody155 may be larger in width than thegate electrode163. The excesscarrier storage region155S may likewise be larger in width than thegate electrode163.
• One of the source and drainregions173 is electrically connected to a source line S, and the other of the source and drainregions173 is electrically connected to a drain line D. Thegate electrode163 is electrically connected to a gate line G. Also, thesemiconductor substrate151 may be electrically connected to a back gate line BG. In an embodiment, the source line S may be connected to a ground terminal, the drain line D may be a bit line, and the gate line G may be a word line.
• A write operation in the floating body DRAM device according to the second exemplary embodiment of the present invention may include applying a gate program voltage higher than a threshold voltage (Vt) to thegate electrode163, and applying a bit program voltage to the drain line D. The source line S may be grounded. The bit program voltage may be a positive voltage.
• In this case, electron-hole pairs (EHPs) may be generated in the floatingbody155 by impact ionization. The electrons generated by the impact ionization may flow through the drain line D, whereas the holes generated by the impact ionization may be accumulated in the excesscarrier storage region155S. That is, excess holes are accumulated in the excesscarrier storage region155S. The excess holes accumulated in the excesscarrier storage region155S change the threshold voltage (Vt).
• However, a contact surface of the source and drainregions173 and the floatingbody155 may be minimized by theleakage shielding patterns171′. In other words, theleakage shielding patterns171′ may serve to block a leakage path of the excess holes. Accordingly, theleakage shielding patterns171′ extend the time during which the excess holes are retained in the excesscarrier storage region155S. As a result, according to the second exemplary embodiment of the present invention, the retention time of the excess holes accumulated in the excesscarrier storage region155S is significantly increased.
• FIG. 4 is a plan view of a single transistor memory cell according to a third exemplary embodiment of the present invention, andFIG. 5 is a cross-sectional view taken along line I-I′ ofFIG. 4.
• Referring toFIGS. 4 and 5, a buried insulatinglayer253 is stacked on asemiconductor substrate251, and anactive semiconductor pattern255ais on a portion of the buried insulatinglayer253. Thesemiconductor substrate251 may be formed, for example, from a supporting substrate of a silicon on insulator (SOI) substrate. Theactive semiconductor pattern255amay include abulk region255cand an impurity region (for providing asource region261sand adrain region261d,discussed below), which are sequentially stacked. The impurity region may have a different conductivity type from thebulk region255c.For example, when thebulk region255cis formed of p-type semiconductor, the impurity region may be formed of n-type semiconductor.
• A recessed region R passes through the impurity region and extends into thebulk region255c.The recessed region R divides the impurity region into asource region261sand adrain region261d,which are spaced apart from each other. In other words, a depth of the recessed region R may be greater than thicknesses of the impurity region, i.e., the source and drainregions261sand261d,and less than the total thickness of theactive semiconductor pattern255a.Also, the recessed region R includes first and second sidewalls SW1 and SW2, which are adjacent to the source and drainregions261sand261d, respectively.
• The recessed region R may contain aninsulated gate electrode269g,which is insulated from theactive semiconductor pattern255aby agate insulating layer267. That is, thegate insulating layer267 may be positioned between theinsulated gate electrode269gand inner walls of the first and second sidewalls SW1 and SW2 of the recessed region R. Furthermore, theinsulated gate electrode269gmay extend upwardly beyond the top surfaces of the source and drainregions261sand261d.In this case,spacers271 may be located on sidewalls of the projecting part of theinsulated gate electrode269g. Theactive semiconductor pattern255a,theinsulated gate electrode269g,thespacers271 and the buried insulatinglayer253 may be covered with an insulatinglayer277.
• A firstinsulating region277sof the insulatinglayer277 may be located between thesource region261sand thebulk region255c,and a secondinsulating region277dmay be located between thedrain region261dand thebulk region255c.The first and second insulatingregions277sand277dare in contact with bottom surfaces of the source and drainregions261sand261d,respectively. Also, the first and second insulatingregions277sand277dmay be spaced a specific distance D from the first and second sidewalls SW1 and SW2 of the recessed region R. Thus, afirst bulk region255b′ is located between the firstinsulating region277sand the first sidewall SW1, and asecond bulk region255b″ is located between the secondinsulating region277dand the second sidewall SW2. As a result, the first andsecond bulk regions255b′ and255b″ may have the same width as the specific distance D. When spacers271 are included, the first andsecond bulk regions255b′ and255b″ may be self-aligned with thespacers271 to have the same width as thespacers271.
• The first and second insulatingregions277sand277dmay be empty spaces or insulating layer patterns. Thebulk region255cincludes the first andsecond bulk regions255b′ and255b″, as well as abase bulk region259, which is located beneath the insulatingregions277sand277d,the first andsecond bulk regions255b′ and255b″ and the recessed region R.
• Thebulk region255cmay include lower and upper bulk regions. The lower bulk region may have a higher impurity concentration than the upper bulk region. The first and second insulatingregions277sand277dmay have the same thickness as the upper bulk region. In this case, top surfaces of the insulatingregions277sand277dmay be in contact with bottom surfaces of the source and drainregions261sand261d,and bottom surfaces of the insulatingregions277sand277dmay be in contact with a top surface of thebase bulk region259. In other words, the lower bulk region may correspond to thebase bulk region259 ofFIG. 5, and the upper bulk region may correspond to the first andsecond bulk regions255b′ and255b″ ofFIG. 5. Alternatively, the first and second insulatingregions277sand277dmay be thinner or thicker than the upper bulk region. In any case, the top surfaces of the first and second insulatingregions277sand277dare in contact with the bottom surfaces of the source and drainregions261sand261d.
• Aback gate interconnection281bmay be located on the insulatinglayer277. Theback gate interconnection281bmay be electrically connected to thesemiconductor substrate251 through a backgate contact plug279b,for example, filling a backgate contact hole278bpassing through the insulatinglayer277.
• FIG. 6 is a cross-sectional view illustrating a program operation which stores data “1” in the single transistor memory cell illustrated with reference toFIGS. 4 and 5. The single transistor memory cell illustrated inFIGS. 4 and 5 is assumed to be an n-channel MOS transistor cell, merely for the convenience of describing the operation, and it is thus understood that different types of transistor cells may be incorporated into the depicted embodiment without departing for the spirit and scope of the present invention.
• Referring toFIG. 6, the single transistor memory cell according to the third exemplary embodiment of the present invention may be programmed by several methods. For example, the single transistor memory cell shown inFIGS. 4 and 5 may be programmed by applying a source voltage V_Sof 0 volts to thesource region261s,and a first drain voltage V_D1having a positive pulse waveform to thedrain region261d.During application of the first drain voltage V_D1, a first gate voltage V_G1may be applied to thegate electrode269g,and a back gate voltage V_Bhaving a negative voltage may be applied to thesemiconductor substrate251.
• The first gate voltage V_G1may be a voltage corresponding to half of the drain voltage V_D. In this case, impact ionization occurs at a junction between thedrain region261dand thesecond bulk region255b″, thereby generating a large number of holes and electrons. The holes are stored in thebulk region255cto reduce a threshold voltage of the single transistor memory cell ofFIG. 6.
• In particular, when the back gate voltage V_Bis applied to thesemiconductor substrate251, most of the excess holes stored in thebulk region255care stored in the lower region of thebulk region255c(i.e., the base bulk region259) by an electric field caused by the back gate voltage V_B. Also, junction areas AS and AD of the source and drainregions261sand261dmay be significantly less than the junction areas of the source and drainregions16sand16d,for example, of the conventional single transistor memory cell illustrated inFIG. 1, due to the presence of the first and second insulatingregions277sand277d.Accordingly, even when the first drain voltage V_D1is changed to 0 volts after the program operation, recombination paths between the excess holes in thebulk region255cand the electrons in the source and drainregions261sand261dmay be significantly reduced, thereby increasing a holding time, i.e., a data retention time of the excess holes in thebulk region255c.As a result, retention characteristics of data “1” improve in accordance with the depicted embodiment.
• In another embodiment, the first gate voltage V_G1may be a negative voltage. In this case, holes may be induced into thesecond bulk region255b″ to cause band-to-band tunneling (BTBT) between thedrain region261dand thesecond bulk region255b″. During BTBT, a large amount of excess holes are stored in thebulk region255c.Thus, the program operation may be performed.
• Furthermore, when thebulk region255cincludes stacked, lower and upper bulk regions, as described above, the retention characteristics of data “1” are further improved. This is because most excess holes stored in thebulk region255cmay be stably stored in the lower bulk region having relatively larger volume and higher impurity concentration than the upper bulk region without application of the back gate voltage.
• FIG. 7 is a cross-sectional view illustrating an erase operation which stores data “0” in a single transistor memory cell according to a third exemplary embodiment of the present invention. Here, the single transistor memory cell is also assumed as an n-channel MOS transistor cell for convenience of the description.
• Referring toFIG. 7, the single transistor memory cell according to the third exemplary embodiment of the present invention may be erased by applying a source voltage V_Sof 0 volts to thesource region261s, and a second drain voltage V_D2having a negative pulse waveform to thedrain region261d. The second drain voltage V_D2may have a negative voltage during an erasing time T, and a voltage of 0 volts during an initial state before the erasing time T and during a holding state of data “0” after the erasing time T. Furthermore, a specific voltage, for example, a second gate voltage V_G2of 0 volts, may be applied to thegate electrode269gduring the erase operation.
• The holes in thebulk region255care injected into thedrain region261dduring the erasing time T, to increase a threshold voltage of the single transistor memory cell ofFIG. 7. Thus, the single transistor memory cell may have data corresponding to logic “0”.
• Subsequently, when the second drain voltage V_D2is changed to 0 volts after the erasing time T, a surface potential of thebulk region255c,i.e., a channel region, may be changed. In other words, when the channel region has a first surface potential during the erasing time T, the channel region may have a second surface potential different from the first surface potential after the erasing time T. In this case, a difference between the first and second surface potentials may change depending on magnitudes of junction capacitances Cs′ and Cd′ in the source and drainregions261sand261d,respectively. Particularly, as the source and drain junction capacitances Cs′ and Cd′ decrease, the difference between the first and second surface potentials also decreases.
• The source and drain junction capacitances Cs′ and Cd′ of the single MOS transistor according to the present invention are significantly smaller than the source and drain junction capacitances Cs and Cd of the conventional single transistor memory cell, for example, illustrated inFIG. 1, due to the presence of the first and second insulatingregions277sand277d. Accordingly, after the conventional single transistor memory cell ofFIG. 1 is erased, e.g., using the method described above with respect toFIG. 7, the channel region of the conventional single transistor memory cell may have a third surface potential higher than the second surface potential. It is therefore understood that the difference in threshold voltage before and after erasing the single transistor memory cell further increases, as the surface potential of the channel region after the erase operation decreases. As a result, the difference between the threshold voltage before and after erasing the single transistor memory cell according to the present embodiment may be higher than that of the conventional single transistor memory cell illustrated inFIG. 1. Thus, the single transistor memory cell of the present embodiment shows a larger sensing margin than the conventional single transistor memory cell illustrated inFIG. 1.
• Furthermore, after the erase operation, a specific voltage, for example, 0 volts, may be continuously applied to thegate electrode269g.In this case, thesecond bulk region255b″ may be fully or partially depleted. Accordingly, even when a positive voltage is applied to thedrain regions261d, the BTBT phenomenon between thesecond bulk region255b″ and thedrain region261dis effectively prevented.
• When the BTBT occurs at a junction of thedrain region261dafter the erase operation, excess holes are injected into thebulk region255c,and thus the single transistor memory cell ofFIG. 7 may be programmed again. However, according to the embodiment, the tunneling phenomenon of the erased single transistor memory cell is suppressed, as described above, thus improving the data retention characteristics of the erased single transistor memory cell. Particularly, when the width of thesecond bulk region255b″ is decreased, thesecond bulk region255b″ may be fully depleted. In this case, the BTBT at a junction of thedrain region261dmay be further suppressed.
• FIGS. 8 to 11 are cross-sectional views illustrating a method of fabricating a single transistor floating-body DRAM device, according to the first exemplary embodiment of the present invention.
• Referring toFIG. 8, a buried insulatinglayer52 may be formed on asemiconductor substrate51, to cover thesemiconductor substrate51. The buried insulatinglayer52 may be formed from a silicon oxide layer, for example. A floatingbody55 and anisolation layer53 may be formed on the buried insulatinglayer52.
• The floatingbody55 may be a semiconductor layer, for example, formed from single crystal silicon. P- or n-type impurity ions may be injected into the floatingbody55. The impurity ions may show a graded ion profile in the floatingbody55. For example, the p-type impurity ions may decrease in concentration toward a surface of the floatingbody55.
• Assuming that the floatingbody55 has the p-type impurity ions, the fabrication method will be described below. Theisolation layer53 may be formed to surround the floatingbody55. Theisolation layer53 may be an insulating layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. Theisolation layer53 may be formed by a well-known shallow trench isolation (STI) method. Alternatively, the floatingbody55 and theisolation layer53 may be formed using a silicon on insulator (SOI) wafer.
• Referring toFIG. 9, agate dielectric layer61 may be formed to cover at least a portion of the floatingbody55. Thegate dielectric layer61 may be a silicon oxide layer or a high-k dielectric layer, for example. In an embodiment, thegate dielectric layer61 may be formed to cover both the floatingbody55 and at least a portion of theisolation layer53.
• A gate pattern crossing the floatingbody55 may be formed on thegate dielectric layer61. The gate pattern may be formed from agate electrode63, apad oxide layer65, and amask nitride layer67, which are sequentially stacked on one another. Thegate electrode63 may be a conductive layer, formed from a polysilicon layer, a metal silicide layer, a metal later, or a combination thereof, for example. Themask nitride layer67 may be a nitride layer, formed from a silicon nitride layer, for example. Thepad oxide layer65 may be a silicon oxide layer, for example. When thegate electrode63 is formed from polysilicon, and themask nitride layer67 is formed from silicon nitride, thepad oxide layer65 may serve to relieve stress caused by a difference in thermal expansion coefficients between the polysilicon layer and the silicon nitride layer.
• Referring toFIG. 10, oxygen ions OX may be injected into the floatingbody55 using the gate pattern as an ion injection mask, thereby formingtemporary patterns71. The injection of the oxygen ions may be performed using various angles and energies.
• Thetemporary patterns71 may be formed at both sides of the gate pattern, and arranged at outer sides of the gate pattern. Furthermore, thetemporary patterns71 may be locally formed at a predetermined depth in the floatingbody55. That is, the floatingbody55 may be formed to remain beneath thetemporary patterns71. One surface of thetemporary patterns71 may be formed to be in contact with theisolation layer53. Themask nitride layer67 may serve to prevent the injection of the oxygen ions into thegate electrode63.
• Referring toFIG. 11, thesemiconductor substrate51 having thetemporary patterns71 may be annealed to formleakage shielding patterns71′. While annealing thesemiconductor substrate51, the oxygen ions in thetemporary patterns71 react with silicon, thus forming a silicon oxide layer. Thus, theleakage shielding patterns71′ may be formed from the silicon oxide layer. As a result, theleakage shielding patterns71′ are generally positioned the same as thetemporary patters71, e.g., arranged at outer sides of the gate pattern, and thus thegate electrode63.
• Impurity ions are injected into the floatingbody55 using the gate pattern as an ion injection mask, thereby forming source and drainregions73. When the floatingbody55 has p-type impurity ions, the source and drainregions73 may be formed by injecting n-type impurity ions.
• The source and drainregions73 may be formed at both sides of thegate electrode63, respectively. Also, the source and drainregions73 may be formed to face each other, over a distance or separation. In this case, at least a portion of the floatingbody55 may remain in the space between the source and drainregions73. The source and drainregions73 and the floatingbody55 may be in contact with each other.
• The source and drainregions73 may be formed on theleakage shielding patterns71′, and at least a portion of the floatingbody55 may remain under theleakage shielding patterns71′. As a result, the floatingbody55 may be positioned between the source and drainregions73, as well as beneath theleakage shielding patterns71′. The floatingbody55 may be formed to have a larger width than thegate electrode63.
• As described with reference toFIG. 2, an excesscarrier storage region55S may be formed in the floatingbody55. The excesscarrier storage region55S may also have a larger width than thegate electrode63.
• A contact surface of the source and drainregions73 and the floatingbody55 may be minimized by theleakage shielding patterns71′. That is, theleakage shielding patterns71′ serves to block a leakage path of the excess holes. Accordingly, theleakage shielding patterns71′ extends the time during which excess holes are retained in the excesscarrier storage region55S.
• Subsequently, a single transistor floating-body DRAM device may be formed by known fabrication process of a semiconductor device such as formation of a bit line and a plug.
• FIGS. 12 to 15 are cross-sectional views illustrating a method of fabricating a single transistor floating-body DRAM device, according to the second exemplary embodiment of the present invention.
• Referring toFIG. 12, a buried insulatinglayer152, a floatingbody155, and anisolation layer153 may be formed on asemiconductor substrate151 by the same method as described above with reference toFIG. 8. Agate dielectric layer161 covering the floatingbody155 may be formed. A gate pattern crossing the floatingbody155 may be formed on thegate dielectric layer161, as described above with reference toFIG. 9. The gate pattern may be formed from agate electrode163, apad oxide layer165, and amask nitride layer167, which are sequentially stacked.
• Germanium (Ge) ions are injected into the floatingbody155 using the gate pattern as an ion injection mask, thereby formingtemporary patterns171, as shown inFIG. 12. The injection of the Ge ions may be performed using various angles and energy. Thetemporary patterns171 may be formed at both sides of the gate pattern, in which case, thetemporary patterns171 may be arranged at outer sides of the gate pattern. Furthermore, thetemporary patterns171 may be locally formed at a predetermined depth in the floatingbody155, so that at least a portion of the floatingbody155 may remain under thetemporary patterns171. One side of thetemporary patterns171 may be formed to be in contact with theisolation layer153. Themask nitride layer167 prevents the injection of the Ge ions into thegate electrode163.
• Referring toFIG. 13, amask pattern175 is formed on thesemiconductor substrate151. Themask pattern175 may be formed to have anopening175H exposing theisolation layer153. Themask pattern175 may be formed from a photoresist layer or a hard mask layer, for example.
• Theisolation layer153 may be etched until thetemporary patterns171 are exposed using themask pattern175 as an etch mask. As a result, the floatingbody155 and thetemporary patterns171 may be exposed in theopening175H.
• Gaps171G may be formed by removing thetemporary patterns171. Thegaps171G may be formed by an isotropic etching process having an etch selectivity between thetemporary patterns171 and the floatingbody155.
• As described above, in thetemporary patterns171, the state that the Ge ions are injected into the single crystal silicon may be maintained. In this case, the single crystal silicon into which the Ge ions are injected may have an etch rate, for example, 100 times higher than the floatingbody155. Themask pattern175 may then be removed.
• Referring toFIG. 14, impurity ions may be injected into the floatingbody155 through thegaps171G, using the gate pattern as an ion injection mask, thereby forming the source and drainregions173. When the floatingbody155 has p-type impurity ions, the source and drainregions173 may be formed by injecting n-type impurity ions. The source and drainregions173 may be formed at both sides of thegate electrode163, respectively. Also, the source and drainregions173 may be formed to face each other over a space or distance. In this case, the floatingbody155 may remain in the space between the source and drainregions173, which face each other. As stated above, the floatingbody155 may remain under thegaps171G.
• Referring toFIG. 15, aninterlayer insulating layer177 is formed to cover thesemiconductor substrate151, filling thegaps171G. The interlayer insulatinglayer177 may be formed, for example, from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. A top surface of themask nitride layer167 may be exposed by planarizing the interlayer insulatinglayer177. In this case, top surfaces of the interlayer insulatinglayer177 and themask nitride layer167 may be exposed on substantially the same plane.
• The interlayer insulatinglayer177 filling thegaps171G serves asleakage shielding patterns171′. That is, theleakage shielding patterns171′ may be formed between the source and drainregions173 and the floatingbody155.
• Subsequently, the single transistor floating-body DRAM device may be fabricated by known fabrication processes of the semiconductor device, such as the formation of a bit line and a plug.
• As a result, theleakage shielding patterns171′ are formed beneath the source and drainregions173. The floatingbody155 may remain under theleakage shielding patterns171′. Theleakage shielding patterns171′ may be arranged at outer sides of thegate electrode163. That is, the floatingbody155 may be positioned between the source and drainregions173 facing each other, and formed to extend beneath theleakage shielding patterns171′. The floatingbody155 may have a larger width than thegate electrode163.
• As described with reference toFIG. 3, an excesscarrier storage region155S may be formed in the floatingbody155. The excesscarrier storage region155S may also be formed to have a larger width than thegate electrode163.
• A contact surface of the source and drainregions173 and the floatingbody155 may be minimized by theleakage shielding patterns171′. In other words, theleakage shielding patterns171′ serve to block a leakage path of the excess holes. Accordingly, theleakage shielding patterns171′ extend the time for which the excess holes are retained in the excesscarrier storage region155S.
• FIGS. 16 to 24 are cross-sectional views taken along line I-I′ ofFIG. 4 illustrating the method of fabricating a single transistor memory cell, according to the third exemplary embodiment of the present invention.
• Referring toFIGS. 4 and 16, anSOI substrate256 is prepared. TheSOI substrate256 may include a supportingsubstrate251, a buried insulatinglayer253 formed on the supportingsubstrate251, and asemiconductor body layer255 formed on the buried insulatinglayer253. The supportingsubstrate251 may be a semiconductor substrate, and thesemiconductor body layer255 may be a silicon layer, for example.
• Referring toFIGS. 4 and 17, anisolation layer257 is formed in a predetermined region of thesemiconductor body layer255, to form anactive region255r.Theisolation layer257 may be formed to be in contact with the buried insulatinglayer253. As a result, theactive region255rmay be electrically insulated from the supportingsubstrate251 by theisolation layer257 and the buried insulatinglayer253.
• Referring toFIGS. 4 and 18, first impurity ions are injected into a surface of theactive region255rto form animpurity region261. Theimpurity region261 may be formed to have a different conductivity type from theactive region255r.For example, when theactive region255ris a p-type, theimpurity region261 may be an n-type. Second impurity ions are injected into a lower portion of theactive region255rto form abulk region255c,which includes alower bulk region259 and anupper bulk region255b(between thelower bulk region259 and the impurity region261) defined by thelower bulk region259. Thelower bulk region259 may be formed to have the same conductivity type as theactive region255r.In this case, thelower bulk region259 may have a higher impurity concentration than theupper bulk region255b.Thebulk region255cand theimpurity region261 constitute anactive semiconductor pattern255a.
• Alternatively, theactive semiconductor pattern255amay be formed by a different method from that described above. For example, the process of forming thelower bulk region259 may be omitted. Also, before forming theisolation layer257, an impurity layer and a lower bulk layer may be respectively formed on an upper surface and in a lower region of thesemiconductor body layer255 to define an upper bulk layer between the impurity layer and the lower bulk layer. Then, theisolation layer257 may be formed in the impurity layer, the upper bulk layer and the lower bulk layer to define theactive semiconductor pattern255a.
• Referring toFIGS. 4 and 19, amask pattern266 is formed on the substrate having theactive semiconductor pattern255a.Themask pattern266 may be formed to define anopening266aover theactive semiconductor pattern255a.Themask pattern266 may also include at least two insulating layers. For example, themask pattern266 may be formed to include a padoxide layer pattern263 and a padnitride layer pattern265, which are sequentially stacked.
• Theactive semiconductor pattern255ais etched using themask pattern266 as an etch mask, to form a recessed region R passing through theimpurity region261. Accordingly, a recessed channel region is formed along a bottom surface and sidewalls of the recessed region R. The recessed region R may be formed deeper than the thickness of theimpurity region261, and shallower than the total thickness of theactive semiconductor pattern255a. As a result, the recessed region R divides theimpurity region261 into asource region261sand adrain region261d, which are spaced apart or separated from each other. The recessed region R may include a first sidewall SW1 adjacent to thesource region261s, and a second sidewall SW2 adjacent to thedrain region261d.
• Referring toFIGS. 4 and 20, agate insulating layer267 is formed on an inner wall of the recessed region R. Thegate insulating layer267 may be a thermal oxide layer, for example. A gate conductive layer filling the recessed region R and theopening266ais formed on the substrate having thegate insulating layer267 and then planarized to expose a top surface of themask pattern266. As a result, a gate conductive layer pattern is formed in the recessed region R and theopening266a.The gate conductive layer pattern may be further etched to form a recessedgate electrode269g.The gate conductive layer may be formed from a doped polysilicon layer, for example.
• A gate capping insulating layer is formed on the substrate having the recessedgate electrode269gand then planarized to expose a top surface of themask pattern266. As a result, a capping insulatinglayer pattern270 may be formed in theopening266aabove the recessedgate electrode269g.The gate capping insulating layer may be formed from a material having etch selectivity with respect to themask pattern266, for example, a silicon oxide layer. The gate electrode269gand the capping insulatinglayer pattern270 constitute agate pattern270g.
• Referring toFIGS. 4 and 21, at least a portion of themask pattern266, e.g., the padnitride layer pattern265, may be removed, thereby exposing upper sidewalls of thegate pattern270g.As a result, an upper region of thegate pattern270gmay project above theisolation layer257.Spacers271 may be formed on sidewalls of the projecting portion of thegate pattern270g.Thespacers271 may be formed of an insulating layer having an etch selectivity with respect to the capping insulatinglayer pattern270. For example, thespacers271 may be formed from a silicon nitride layer. During the formation of thespacers271, the pad oxide layer263 (FIG. 20) on the source and drainregions261sand261dmay be over-etched. In this case, the source and drainregions261sand261dmay be exposed.
• Referring toFIGS. 4 and 22,sacrificial impurity ions273 are injected into thebulk region255cusing thegate pattern270gand thespacers271 as ion injection masks, forming first and second sacrificial impurity layers273sand273dbeneath the source and drainregions261sand261d,respectively. A top surface of the firstsacrificial impurity layer273sis formed to contact a bottom surface of thesource region261s,and a top surface of the secondsacrificial impurity layer273dis formed to contact a bottom surface of thedrain region261d.As a result, afirst bulk region255b′ is defined between the firstsacrificial impurity layer273sand the recessed region R, and asecond bulk region255b″ is defined between the secondsacrificial impurity layer273dand the recessed region R. In the embodiment, the first andsecond bulk regions255b′ and255b″ may have the same width D as thespacers271 because they are self-aligned with thespacers271. The sacrificial impurity ions may be silicon germanium ions, for example. In this case, the first and second sacrificial impurity layers273sand273dmay be formed from silicon germanium layers.
• In alternative embodiments, the first and second sacrificial impurity layers273sand273dmay be the same or different from theupper bulk region255b(FIG. 21) in thickness. For example, the first and second sacrificial impurity layers273sand273d,as illustrated inFIG. 22 are depicted as having the same thickness as theupper bulk region255b.Also, the recessed region R may be formed to have the same depth as the total thickness of the source and drainregions261sand261dand theupper bulk region255b.In this case, the first andsecond bulk regions255b′ and255b″ may be theupper bulk region255bremaining under thespacers271, and thebulk region255cmay include the first andsecond bulk regions255b′ and255b″ and thelower bulk region259. However, in alternative embodiments of the present invention, the thicknesses of the first and second sacrificial impurity layers273sand273dand the depth of the recessed region R may vary, without departing for the spirit and scope of the present invention. For example, the first and second sacrificial impurity layers273sand273dmay be formed thinner or thicker than theupper bulk region255b,and the recessed region R may be formed to have a bottom surface higher or lower than the juncture between thelower bulk region259 and theupper bulk region255b.
• Referring toFIGS. 4 and 23, the isolation layer257 (FIG. 22) is etched to expose the first and second sacrificial impurity layers273sand273d. When the capping insulating layer pattern270 (FIG. 22) is formed of the same material layer as the isolation layer257 (for example, a silicon oxide layer), the capping insulatinglayer pattern270 may be removed during the etching of theisolation layer257. Then, the exposed sacrificial impurity layers273sand273dare likewise selectively removed. As a result, a firstundercut region275smay be formed under thesource region261s,and a secondundercut region275dmay be formed under thedrain region261d.
• Referring toFIGS. 4 and 24, an insulatinglayer277 is formed on the substrate having the undercutregions275sand275d.In the process, the insulatinglayer277 fills the undercutregions275sand275dto define first and second insulatingregions277sand277dunder the source and drainregions261sand261d,respectively. In other words, the firstinsulating region277smay be a first insulatinglayer pattern277sin the firstundercut region275s,and the secondinsulating region277dmay be a second insulatinglayer pattern277din the secondundercut region275d.Alternatively, the insulatinglayer277 may be formed to leave empty spaces in the undercutregions275sand275d,respectively. In this case, the firstinsulating region277smay be a first empty space in the firstundercut region275s,and the secondinsulating region277dmay be a second empty space in the secondundercut region275d.
• Subsequently, the insulatinglayer277 and the buried insulatinglayer253 may be patterned to form a backgate contact hole278b,asource contact hole278s,agate contact hole278gand adrain contact hole278d,which respectively expose the supportingsubstrate251, thesource region261s,thegate electrode269gand thedrain region261. A backgate contact plug279b, asource contact plug279s,a gate contact plug279gand adrain contact plug279dmay be formed in the contact holes278b,278s,278gand278d, respectively. A conductive layer, such as a metal layer, is formed on the substrate having the contact plugs279b,279s,279gand279d.The conductive layer is patterned to form aback gate interconnection281b, asource interconnection281s, agate interconnection281gand adrain interconnection281d,which are electrically connected to the contact plugs279b,279s,279gand279d,respectively.
• According to the embodiments described above, leakage shielding patterns are located under source and drain regions. The leakage shielding patterns may be arranged at outer sides of a gate electrode. A floating body may be located between the source and drain regions facing each other, and extend beneath the leakage shielding patterns. An excess carrier storage region may be located in the floating body.
• Accordingly, a contact surface of the source and drain regions and the floating body is minimized by the leakage shielding patterns. The leakage shielding patterns block a leakage path of the excess holes accumulated in the excess carrier storage region. Therefore, the retention time of the excess holes accumulated in the excess carrier storage region is significantly extended, as compared to the conventional art.
• Furthermore, insulating regions are located under source and drain regions on sides of a recessed channel region. Accordingly, a junction area of the source and drain regions significantly decreases, thus improving retention characteristics (e.g., of data “1”) of excess electric charges (e.g., excess holes) stored in a bulk region under the recessed channel region. Also, first and second bulk regions having fine widths between the insulating regions and the recessed channel region may be provided. Thus, when a certain voltage is applied to a gate electrode located in the recessed region, the first and second bulk regions may be fully or partially depleted. As a result, band-to-band tunneling is significantly suppressed at a junction between the source and drain regions, thus improving the retention characteristics (e.g., of data “0”). Also, the first and second bulk regions may be aligned with spacers formed on sidewalls of the gate electrode.
• While the present invention has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative.

Claims (10)

1. A single transistor floating-body dynamic random access memory (DRAM) device, comprising:

a floating body located on a semiconductor substrate, the floating body comprising an excess carrier storage region;

a gate electrode located on the floating body;

source and drain regions respectively located at both sides of the gate electrode, each of the source and drain regions contacting the floating body; and

leakage shielding patterns located between the floating body and the source and drain regions.

2. The device according toclaim 1, wherein the leakage shielding patterns are arranged at outer sides of the gate electrode.

3. The device according toclaim 1, wherein the leakage shielding patterns contact bottom surfaces of the source and drain regions.

4. The device according toclaim 3, wherein the floating body is positioned between the source and drain regions, and laterally extends under the leakage shielding patterns.

5. The device according toclaim 1, wherein the leakage shielding patterns comprise at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.

6. The device according toclaim 1, wherein a width of the excess carrier storage region is larger than a width of the gate electrode.

7. The device according toclaim 1, wherein the floating body comprises a single crystal semiconductor layer having p-type impurity ions.

8. The device according toclaim 1, further comprising:

a buried insulating layer located between the semiconductor substrate and the floating body.

9. The device according toclaim 1, further comprising:

an isolation layer defining the floating body, the leakage shielding patterns contacting the isolation layer.

10. The device according toclaim 1, wherein the semiconductor substrate is configured to serve as a back gate electrode.

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