US20110032932A2 - Apparatus and method for producing device identifiers for serially interconnected devices of mixed type - Google Patents

Abstract

A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application claims the benefit of priority from U.S. Provisional Patent Application No. 60/887,401 filed Jan. 31, 2007, the disclosure of which is expressly incorporated herein by reference in its entirety, and of U.S. Provisional Patent Application No. 60/868,773 filed Dec. 6, 2006, the disclosure of which is expressly incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
• The present invention relates generally to semiconductor device systems. More particularly, the present invention relates to apparatus and method for producing device identifiers for a serial interconnection configuration of devices of mixed type.
BACKGROUND OF THE INVENTION
• Current electronic equipment uses semiconductor devices, such as, for example, memory devices and processing devices. For example, mobile electronic products such as, for example, digital cameras, portable digital assistants, portable audio/video players and mobile terminals continue to require mass storage memories, preferably non-volatile memory with ever increasing capacities and speed capabilities. Non-volatile memory and hard disk drives are preferred since data is retained in the absence of power, thus extending battery life.
• While existing memory devices operate at speeds sufficient for most current consumer electronic equipment, such memory devices may not be adequate for use in future electronic products and other products where high data rates are desired. For example, a mobile multimedia device that records high definition moving pictures is likely to require a memory module with a greater programming throughput than one with current memory technology. While such a solution appears to be straightforward, there is a problem with signal quality at such high frequencies, which sets a practical limitation on the operating frequency of the memory. The memory communicates with other components using a set of parallel input/output (I/O) pins, the number of which depends on the desired configuration. The I/O pins receive command instructions and input data and provides output data. This is commonly known as a parallel interface. High speed operation may cause deleterious communication effects such as, for example, cross-talk, signal skew and signal attenuation, which degrade signal quality.
• In order to incorporate higher density and faster operation on the system boards, there are two design techniques possible: multi-drop and serial interconnection configurations. These design techniques may be used to overcome the density issue that determines the cost and operating efficiency of memory swapping between a hard disk and a memory system. However, multi-drop configurations have shortcomings relative to the serial interconnection of memory systems. For example, if the number of multi-drop memory systems increases, as a result of the loading effect of each pin, the delay time also increases so that the total performance of multi-drop is degraded by the multi-drop connection caused by the wire resistor-capacitor loading and the pin capacitance of the memory device. A serial link may provide a serial interconnection configuration to control command bits, address bits, and data bits effectively through the serial interconnection. In the serial interconnection configuration, each device is identified by a device identifier or a device address.
SUMMARY OF THE INVENTION
• In accordance with one aspect of the present invention, there is provided a method for producing a device identifier (ID) for a device, comprising: receiving a device type (DT) and an input ID; determining the DT of a device in response to the received DT; outputting an output ID in accordance with a determination result; and providing the output ID accompanying the received DT to an other device, the device and the other device being interconnected to each other.
• For example, the step of determining provides device type information (DTI) associated with the device. The received DT is compared with the provided DTI to provide the determination result.
• Advantageously, a calculation is performed based on the received ID and an altered (or calculated) ID is output. The altered ID or a non-altered ID is selected in response to the determination result. The selected ID is combined with the received DT. The combined ID and DT are provided to the other device interconnected to the device.
• The combined DT and ID may be further combined with an ID production command. The combined command, the DT and the ID may be transmitted in a packet basis to the other device.
• In accordance with another aspect of the present invention, there is provided an apparatus for use in a device, comprising: a receiver for receiving a device type (DT) and a device identifier (ID); a determiner for determining the DT of a device from the received DT; an ID provider for outputting an ID in accordance with the determination result; and an output provider for providing the outputted ID accompanying the received DT to another device.
• For example, in the determiner, device type information (DTI) of the device is provided and the received DT is compared with the provided DTI. The comparison is made by a DT match detector that detects a match between the received DT and the provided DTI. A match determination result is provided when there is a match between the received DT and the provided DTI. When there is a no-match, no match result is provided.
• Advantageously, the ID provider includes an arithmetic operator that performs a calculation of an ID based on the received ID and a value of one. In response to the determination result of a match or a no-match, the calculated ID or a non-calculated (i.e., the received ID) is selected as the new ID.
• The ID provider may output the provided new ID accompanying the received DT to an other device that is interconnected to the device. The device and the other devices are ones of a plurality of serially interconnected devices of mixed type.
• For example, the ID accompanying DT may be combined with an ID generation command. The combined ID, DT and ID generation command may be provided in a packet that is transmitted to the other device.
• In accordance with a further aspect of the present invention, there is provided an apparatus for assigning a device identifier at a first device coupled to a second device in a serial interconnection configuration of devices of mixed type, the first device having a serial input connection coupled to a serial output connection of a previous device in the serial interconnection configuration, the second device having a serial input connection coupled to a serial output connection of the first device. The apparatus comprises: a receiver for receiving a device identifier (ID) and a device type (DT), the ID and DT being provided through the serial input connection of the device; a determiner for determining the DT of the device from the received DT; an ID provider for outputting an ID in accordance with a determination result; and an output provider for providing the outputted ID accompanying the received DT to an other device.
• In accordance with yet a further aspect of the present invention, there is provided a method for assigning a device identifier (ID) for one of a plurality of devices of mixed type in a serial interconnection configuration, a first device having a serial input connection coupled to a serial output connection of a previous device, a second device having a serial input connection coupled to a serial output connection of the first device, the method being adopted to at least one of the devices. The method comprises: receiving an input ID and a device type (DT) through the serial input connection of a device; determining the DT of the device from the received DT; outputting an output ID in response to a determination result; and providing a combination of the received DT and the outputted ID.
• In accordance with yet a further aspect of the present invention, there is provided a method for assigning a device identifier (ID) for a plurality of devices of mixed type in a serial interconnection configuration, a first device having a serial input connection coupled to a serial output connection of a previous device, a second device having a serial input connection coupled to a serial output connection of the first device. The method comprises: receiving a device type (DT) and an input ID through the serial input connection; holding the received DT at a device; determining whether the received DT matches a reference DT associated with the device; obtaining a calculated ID or a non-calculated ID in response to a determination result; combining the received DT with the calculated or non-calculated ID; providing the combined DT and ID through the serial output connection of the device; and performing an ID assignment in response to the determination result at the device.
• In accordance with an embodiment, there is provided a plurality of devices of mixed type that is serially interconnected. The devices are, such as, for example, random access memories and Flash memories. Each device has device type information on its device type. A memory controller provides an ID generation command, a specific device type (DT) and a device identifier (ID) to a device that determines whether the provided DT matches the device's DT. If there is a match between them, an addition of ID is performed in the device to produce an ID. If there is no DT match, no addition is performed in the device (i.e., the ID production is skipped or bypassed). One of the added ID (the produced ID) and the fed ID (the non-calculated ID) is selected and the selected ID accompanying the fed DT is transferred to a next device in the serial interconnection configuration. Such a device type match determination and ID production or skip are performed in all devices of the serial interconnection configuration. With reference to a device type provided to the interconnected devices, IDs are sequentially generated. The generated ID and the provided DT and the ID generation command are combined and the combined data is transmitted as a packet.
• In accordance with an embodiment, there is provided an ID generation with skip function for serially interconnected devices of mixed type, in accordance with the device type. A combination of the device type number, the ID number and an ID generation command are is transferred as a packet. The devices may include random access memories such as DRAMs, SRAMs, MRAMs and Flash memories such as NAND-, NOR- and AND-types.
• Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
• Embodiments of the present invention will now be described, by way of example only, with reference to the attached figures, wherein:
• FIG. 1 is a block diagram illustrating a memory system including a plurality of memory devices in a serial interconnection configuration to which embodiments of the present invention are applied;
• FIG. 2A is a timing diagram of single data rate operation of memory devices;
• FIG. 2B is a timing diagram of double data rate operation of memory devices;
• FIG. 3 is a timing diagram illustrating signals and packets propagated through the interconnected devices shown inFIG. 1;
• FIG. 4 is a block diagram illustrating one of the devices ofFIG. 1;
• FIG. 5A is a block diagram illustrating a plurality of memory devices in a serial interconnection configuration to which embodiments of the present invention are applied;
• FIG. 5B is a schematic diagram illustrating a protocol conducted in the devices shown inFIG. 5A,
• FIG. 5C is a flow chart of an ID assigning method performed by each of the devices shown inFIG. 5B;
• FIG. 6A is a block diagram illustrating a memory system including a plurality of devices of mixed type in a serial interconnection configuration, in which embodiments of the present invention are implemented;
• FIG. 6B is a block diagram illustrating one of the devices shown inFIG. 6A;
• FIG. 6C is a block diagram illustrating an example of a device operation controller ofFIG. 6B;
• FIG. 6D is a block diagram illustrating an example of an ID generator ofFIG. 6B;
• FIG. 7A is a flow chart of operation performed by the serial interconnection configuration ofFIG. 6A;
• FIG. 7B is a flow chart of part of the operation shown inFIG. 7A;
• FIG. 8A is a block diagram illustrating the plurality of devices in the serial interconnection configuration shown inFIG. 6A, in which the ID generation of NAND memory devices is performed;
• FIG. 8B is a timing diagram of the ID generation in the serial interconnection configuration ofFIG. 8A;
• FIG. 9A is a block diagram illustrating the plurality of devices in the serial interconnection configuration shown inFIG. 6A, in which the ID generation of NOR memory devices is performed;
• FIG. 9B is a timing diagram of the ID generation in the serial interconnection configuration ofFIG. 9A;
• FIG. 10 is a block diagram illustrating another example of the ID generator, in which a generated ID is latched;
• FIG. 11 is a block diagram illustrating another example of the ID generator with a subtractor for ID generation;
• FIG. 12 is a block diagram illustrating a plurality of devices of mixed type in a serial interconnection configuration, in which embodiments of the present invention are implemented;
• FIG. 13A is a block diagram illustrating another example of a device operation controller ofFIG. 6B;
• FIG. 13B is a timing diagram of the ID generation with a latency adjustment achieved by the device operation controller shown inFIG. 13A; and
• FIG. 14 is a block diagram illustrating a plurality of devices in a serial interconnection configuration operating to generate an ID in dual links.
DETAILED DESCRIPTION
• In the following detailed description of embodiments of the present invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration of embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the present invention, and it is to be understood that other embodiments may be utilized and that logical, electrical, and other changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
• Generally, the present invention provides apparatus and method for producing device identifiers in serially interconnected devices.
• Some memory subsystems employ multiple memory devices, such as, for example, Flash memory devices, with serial interfaces. Here, the command string may be fed to all of the devices even though the command may only be performed on one of the devices. To select the device on which the command is to be performed, the command string may contain a device identifier (ID) or a device address that identifies the memory device to which the command is directed. Each device receiving the command string compares the ID contained in the command string to an ID associated with the device. If the two match, the device will assume that the command is directed to the device to execute the command.
• The above-described arrangement needs to assign an ID for each device. One technique that may be used to assign an ID for a device is to hardwire an internal unique ID into the device. One drawback with this approach, however, is that if large volumes of devices are used, the size of the ID may have to be quite large in order to ensure that each device contains a unique ID. Managing a large-sized ID may add significant complexity to the device, which in turn may increase the cost of producing the device. In addition, reclaiming IDs that are associated with devices that are no longer in use may further add to the complexity of this scheme.
• Another approach to assigning IDs to devices involves externally hardwiring an ID for each device. Here, the ID may be specified by wiring various pins on the device to certain states to assign an ID for the device. The device reads the wired state of the pins and assigns its ID from the read state. One drawback with this approach, however, is that external wiring is needed to assign the ID for each device. This may add to the complexity of, e.g., printed circuit boards (PCBs) that hold the memory devices. Another drawback with this approach is that it may require pins to be dedicated for the assignment of the ID. This may consume precious resources that may be otherwise better used. In addition, dedicating pins for the assignment of the ID may require a greater footprint for the device than if pins were not used to assign the ID.
• At least some of embodiments of the present invention address at least some of these shortcomings. At least some example embodiments automatically assign an ID for a device, for example, in a serial interconnection configuration, in a manner that does not require special internal or external hardwiring of the ID. According to an aspect of the techniques described herein, an input signal is transferred to a first device in an arrangement including multiple devices (e.g., a serial interconnection configuration) using inputs that are also used by the first device to input other information to the device (e.g., data, commands, control signals). A generator generates an ID in response to the input signal. A transmitter transfers an output signal associated with the ID to a second device through a serial output of the first device. The serial output may also be used by the first device to output other information (e.g., signals, data) to another device in the configuration.
• In an embodiment of the techniques described herein, a write ID operation is initiated at a device in a serial interconnection configuration of memory devices of mixed type to cause the device to produce an ID. A first device receives information on a device type (DT) and a first value by acquiring the state of one or more inputs of the first device. If the received DT matches the device type of the first device, it will generate an ID from the first value, which may include placing the first value in storage (e.g., an ID register) associated with the device. The first device generates a second value from the acquired state. The first device outputs a second value via an output of the first device to a second device in the serial interconnection configuration. The second device inputs the value output by the first device and repeats this process to generate an ID.
• Embodiments of the present invention will now be described in conjunction with the ID generation in a packet basis wherein during an ID generation operation, an ID generation command is serially transferred through the serial interconnection of devices. A device receives serial packet basis commands at the serial input thereof in response to clocks and interprets them for ID generation. A packet based ID generation is disclosed in U.S. patent application Ser. No. 11/529,293 filed Sep. 29, 2006 entitled “Packet Based ID Generation for Serially Interconnected Devices”, the content of which is entirely incorporated herein by reference.
• FIG. 1 shows a system that includes memory devices employing a serial interconnection configuration to which embodiments of the present invention are applied. The serial interconnection configuration includes a plurality of single port devices, which has inputs and outputs for various information or data. In this example, fourmemory devices1,2,3 and4 (120-1,120-2,120-3 and120-4) are serially interconnected. Each of the devices120-1-120-4 has a similar structure. Each device includes a serial input port (SIP) connection, a serial output port (SOP) connection, a chip select input (/CS) and a clock input (CLK). Amemory controller111 provides a group ofsignals113 containing information on chip select /SCS, serial input SI, clock SCLK and other control and data information that are provided to the devices. The memory devices may operate with either of a single data rate (SDR) interface or a double data rate (DDR) interface.
• FIG. 2A shows a relative timing sequence for an SDR operation of memory devices.FIG. 2A shows operation in one port. Referring toFIGS. 1 and 2A, the operation is that information transferred to the devices120-1-120-4 can be captured at different times of the clock signal SCLK fed to the CLK inputs of the devices. In an example of the SDR implementation, information fed to one of the devices at its SIP connection can be captured at the rising edge of the clock signal SCLK. In the SDR operation, the chip select signal /SCS is commonly connected to enable all devices at the same time, so that input data of the first device is transferable through the serial interconnection configuration. Alternatively, in the SDR operation, information fed to the device at the SIP connection may be captured at the falling edge of the clock signal SCLK.
• FIG. 2B shows a relative timing sequence for a DDR operation of memory devices.FIG. 2B shows operation in one port. In the DDR operation, both of the rising and falling edges of the clock signal SCLK can be used to capture information fed to the SIP connection.
• In both examples shown inFIGS. 2A and 2B, the chip select signal /SCS is commonly provided to the all devices to enable them at the same time, so that in response to the clock signal SCLK, input data fed to the first device may be propagated to the last device in the serial interconnection configuration with or without being altered by the devices thereof.
• In the particular example shown inFIG. 1, the system adopts the SDR implementation and the following description is based on the SDR operation.
• FIG. 3 shows signals and packets propagated through the devices120-1-120-4 shown inFIG. 1. Referring toFIGS. 1 and 3, the chip select signal /SCS is first asserted to select the devices. Thememory controller111 sends data and/or information to the devices in the serial interconnection configuration. The data and/or information in the serial input SI is propagated as packets through the interconnected devices with or without being altered by each of the devices. The propagation enables information to be clocked from the SOP connection ofdevice1,120-1, to the SIP connection ofdevice2,120-2, at one cycle after the information is clocked intodevice1,120-1. This process is repeated for successive devices in the serial interconnection configuration. In the example, the serial input SI1 as a packet todevice1, which is fed by thememory controller111, contains commands CMD and data or information on a device type DTsi and an initial ID number or value, ID0.Device1 outputs commands CMD and data on the device type, DTsi, and an altered or non-altered ID from the initial ID0, IDo1, as the serial output SO1 in a packet basis. The serial output SO1 is the serial input SI2 fed todevice2.Device2 can perform the same function of the ID production as that ofdevice1. Similarly, the successive devices can perform the same ID producing function.
• FIG. 4 shows one device120-irepresenting any one of the devices120-1-120-4 ofFIG. 1. Referring toFIGS. 1 and 4, the device120-iincludes adevice controller130 and amemory140 that is any type of memory, such as, for example, random access memory or Flash memory. For example, the random access memories are dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM) and the Flash memories are NAND-type, NOR-type, AND-type, and other type Flash memories.
• The device120-ihas the SIP connection, the SOP connection, the /CS input and the CLK input. The SIP connection is used to transfer information (e.g., command, address and data information) into the device120-i. The SOP connection is used to output information from the device120-i. The CLK input receives the clock signal SCLK. The /CS input receives the chip select signal /SCS, which enables operations at all devices simultaneously. Thedevice controller130 performs various control and process functions with access to thememory140 in response to the input signals (e.g., SI, SCLK), and provides serial output data to a next device120-(i+1).
• The SIP and SOP connections are connected between devices, such that the SOP connection of a previous device120-(i−1) is coupled to the SIP connection of the present device120-iin the serial interconnection configuration. For example, the SOP connection ofdevice1,120-1, is coupled to the SIP connection ofdevice2,120-2. The CLK input of each of four devices120-1-120-4 is fed with the clock signal SCLK from thememory controller111. The clock signal SCLK is distributed to all devices via a common link. The clock signal SCLK is used to capture information input to the device120-iat various registers contained therein. The /CS input is a conventional chip select input for selecting the device. The /CS input is coupled to a common link which enables the chip select signal /SCS to be asserted to all of the devices120-1-120-4 concurrently and consequently selects all of the devices. The SIP and SOP connections of the present device120-iare coupled with the SOP connection of the previous device120-(i−1) and the SIP connection of the next device120-(i+1) in the serial interconnection configuration, as described above.
• FIG. 5A shows a plurality of memory devices in a serial interconnection configuration to which embodiments of the present invention are applied. Referring toFIG. 5A, amemory controller151 provides a group of signals to an interconnected devices1-4 that have their own device type information (DTI) as reference device types DTref1-DTref4, respectively. Each of the device types may be the same as or different from another. The signals include a serial input SI containing commands CMD, a device type DTsi and an initial ID, ID0, which is fed todevice1.
• FIG. 5B shows a protocol conducted in the devices shown inFIG. 5A. Referring toFIGS. 5A and 5B, thememory controller151 sends the commands CMD, the device type DTsi and the initial ID0 as the SI todevice1. The commands CMD include an ID generation command IDGC (e.g., eight bits).Device1 determines whether its device type matches the received device type, DTsi, and outputs an output ID, IDo1, that is altered or non-altered in response to a device type match determination result. The CMD, the DTsi and the IDo1 are sent as the serial output todevice2 that can perform the same functions as those ofdevice1. Similarly, each of the other devices can perform the same functions of the DT match determination and the ID generation, in response to the serial input from a previous device as shown inFIG. 5C.
• Referring toFIGS. 5A-5C, a present device DVi receives the commands, the device type information DTsi and the ID information, IDii (step171) from a previous device DV(i−1) (or thememory controller151 if the device DVi is device1). The device type DTsi is device type information originally provided by thememory controller151 for device type match determination and propagated in the serial interconnection configuration. At the device DVi, the received DTsi is compared to a reference device type DTrefi that is associated with the device DVi (step172). In the example, the reference DT, DTrefi, is provided by storage means of the device DVi (not shown). If the received DTsi matches the reference DTrefi, the received ID, IDii, will be incremented by one, so that an altered ID (or a +1 ID) is generated as a new ID, IDj, (step173). If there is no-match between the DTsi and the DTrefi (NO at step172), the received ID, IDii, will be maintained as a new ID, IDj (step174). Thus, atstep174, the ID generation is skipped or bypassed. Afterstep173 or174, the new IDj is as an output ID, IDoi, combined with the received DTsi and the command CMD (step175). The combined CMD-DTsi-IDoi is fed by the device DVi as the SOi to a next device DV(i+1) (step176) and the DT determination and ID generation end at the device DVi (step177). The device DV(i+1) receives the IDoi accompanying the DTsi as the SIi and, in response to the SIi containing the CMD, the DTsi and the IDi, performs the device type match determination and ID generation operations. Thus, such operations of the device type match determination and ID generation are performed by all of devices1-4.
• FIG. 6A shows a system including a plurality of devices in a serial interconnection configuration and a memory controller, in which embodiments of the present invention are implemented. The device types are mixed and the memory devices included in the interconnection configuration are of any type of memories, such as, for example, random access memories (e.g., DRAMs, SRAMs, MRAMs) and the Flash memories (e.g., NAND-type, NOR-type, AND-type, other types). In this particular example shown inFIG. 6A, the serial interconnection configuration includes five memory devices of mixed type, which are three NAND Flash devices and two NOR Flash devices. Referring toFIG. 6A, five devices1-5 (410-1-410-5) are interconnected and they include memories420-1-420-5 therein. Each of the memories420-1,420-3 and420-5 is a NAND Flash memory. Each of the memories420-2 and420-4 is a NOR Flash memory. For example, a system implementing such an arrangement of different type or a mixed-device serial interconnection may require that only devices of a certain type (e.g., NAND Flash devices) be assigned IDs. Alternatively, the system may require that all devices be assigned IDs, but that all devices of the same type be assigned IDs in a consecutive sequence. In order to meet such requirements in a system implementing ID generation as described above, devices1-5,410-1-410-5, are provided with device controllers430-1-430-5, respectively. One of functions performed by the device controller is to assign an ID based on the device type.
• Amemory controller211 provides a group ofsignals213 containing information on the chip select /SCS, serial input SI, clock SCLK, reset RST and other control and data information. In the particular example shown inFIG. 6A, the chip select signal /SCS, the clock signal SCLK and the reset signal RST are commonly fed to all devices. The serial input SI1 is provided todevice1,410-1, anddevice1 outputs a serial output SO1 to a next device, i.e.,device2,410-2. Each of the devices performs similar functions and thus, the serial input SI is propagated through the interconnected devices with or without being altered. The serial input SI to and the serial output SO from each device transmitted as packets.
• The serial interconnection configuration shown inFIG. 6A includes NAND and NOR Flash devices only. It is noted that the interconnection configuration can include another type of memory devices, e.g., AND-type, DRAM, SRAM devices.
• FIG. 6B shows details of a device410-iwhich represents the devices410-1-410-5 shown inFIG. 6A. Referring toFIG. 6B, the device410-iincludes a memory420-iand a device controller430-iconnected thereto. The device controller430-iincludes adevice operation controller460, anID generator434 and anID register431. Thedevice operation controller460 receives the chip select signal /SCS, the clock signal SCLK, the serial input signal SIi and the reset signal RST and performs the functions of control and data processing. The serial input signal SIi fed to the SIP connection of the device410-icontains the commands and other signal data. In the example, the commands include an ID generation command IDGC of p-bits (e.g., p being eight). The SIi signal includes a device type DTsi and a device identifier (ID) IDii. The serial input SI includes other commands, but are not shown. In response to the ID generation command IDGC, thedevice operation controller460 provides a DTdetermination control signal421 to theID generator434 that determines whether a received device type matches a pre-defined device type. The received device type is the device type DTsi contained in the serial input SIi. The pre-defined device type is a reference DT, DTref, that is associated with the device410-i. In the example, the reference DT, DTref, is provided by storage means (not shown) of the device410-i.
• TheID generator434 generates an ID, IDj, based on the received ID, IDii, to produce an ID for an ID assignment, in response to the determination result. The produced ID is output through thedevice operation controller460 to a next device410-(i+1).
• FIG. 6C shows details of thedevice operation controller460 ofFIG. 6B. Referring toFIGS. 6B and 6C, thedevice operation controller460 includes apacket interpreter461 that receives the serial input signal SIi and the clock signal SCLK. Thepacket interpreter461 interprets the commands, and data information, and provides an interpretedcommand signal462 to a controller/processor463 that receives the chip select signal /SCS, the clock signal SCLK and the reset signal RST. The controller/processor463 provides the DTdetermination control signal421 to theID generator434 and an ID write enablesignal433 and aninternal reset signal438 to theID register431. The Controller/processor463 accesses the memory420-iand provides a processeddata signal425 to aselector456.
• In response to the interpretedcommand signal462, the controller/processor463 provides acommand signal427 containing a code of the ID generation command IDGC to adata combiner467 and adata selection signal423 to theselector456. The IDGC is p-bit serial data. The controller/processor463 receives the clock signal SCLK, a serialoutput ID signal481 containing the n-bit ID and a serial output DT signal487 containing the m-bit DT from theID generator434. Thedata combiner467 combines the ID generation command IDGC, the device type DTsi and the ID, IDj, and provides a data combination signal469 containing a combined IDGC-DT-ID to theselector456. Theselector456 also receives the processed data signal425 provided by the controller/processor463 accessing the memory420 (NAND or NOR Flash memory) of that device410-i. In response to thedata selection signal423 provided by the controller/processor463, theselector456 selects one of the combined IDGC-DT-ID and the processed data. A selected data is provided through abuffer458 to the next device410-(i+1).
• FIG. 6D shows details of theID generator434 shown inFIG. 6B. Referring toFIGS. 6A-6D, theID generator434 includes a device type number storage/provider442 of a one-time-programmable (OTP) element configured by a non-volatile memory. The OTP element stores a device type number as a device type reference (DTref) that is programmed to the device prior to ID generation. Table 1 shows an example of the definition of device types in serialized byte code.

  TABLE 1
  Device									Bit
  Type	HEX	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	0
  NAND	00h		0	0	0	0	0	0	0	0
  Flash
  (DTnd)
  NOR	01h	0	0	0	0	0	0	0	1
  Flash
  (DTnr)
  DRAM	02h		0	0	0	0	0	0	1	0
  (DTdm)
  SRAM	03h		0	0	0	0	0	0	1	1
  (DTsm)
  —	—	—	—	—	—	—	—	—	—
  —	—	—	—	—	—	—	—	—	—
  —	—	—	—	—	—	—	—	—	—
  MRAM	FFh		1	1	1	1	1	1	1	1
  (DTmm)

• The definitions of the device types in Table 1 can be changed. More device types can be added.
• TheID generator434 also includes aserial input buffer437 for receiving the serial input SIi through the SIP connection of the device410-i. The received SIi signal includes a value corresponding to a device type (DT), DTsi, which is a number of m-bits (e.g., eight bits). The received SIi signal also includes a value corresponding to an ID, IDii, which is a number of n-bits (e.g., eight bits). The clock signal SCLK is fed to aninput ID register440 and a device type (DT)clock generator441 that generates a DT register clock signal internally in response to the clock signal SCLK to provide it to aninput DT register439. Each of theinput ID register440 and the input DT register439 is a serial-to-parallel register that registers the input serial data therein in response to the input clocks. The m-bit DTsi is serially shifted into the input DT register439 in response to the DT register clock signal and held therein. The n-bit IDii is serially shifted into theinput ID register440 in response to the clock signal SCLK and held therein.
• The m-bit DTsi and n-bit IDii separately held in the input DT register439 andinput ID register440 are outputted in parallel as an m-bit DT signal445 and an n-bit ID signal435, respectively. TheID signal435 is fed to aselector452 and anadder450 that provides acalculation signal451 having a +1 operation value. The DT signal445 is fed to aDT comparator448 of m-bits that also receives an m-bit DT number, DTref, contained in a reference DT signal443 from the DT number storage/provider442. In response to the DTdetermination control signal421, at determination time Tdti, theDT comparator448 compares the received DTsi to the reference DT, DTref, to provide aDT match signal449. If the DTsi and the DTref are identical, theDT match signal449 will become “high,” indicating a match between the two numbers of the device types DTsi and DTref. Otherwise, theDT match signal449 will be “low,” indicating that the received DTsi specifies a type of device that is different from that of the present device410-i(i.e., no-match). The DT comparator448 outputs the “high” DT match signal having a pulse width Tm, when a device type match occurs. The time period Tm is selected as that the +1 operation is completed and the addition result is transferred to an output ID register (a parallel-to-serial register)454. TheDT match signal449 transits “low” in response to the trailing and falling edge of the DTdetermination control signal421. Theadder450 adds “1” to the IDii, thereby generating thecalculation signal451 containing an ID, IDii+1, for another device, in a sequence of IDs in the serial interconnection configuration. Theadder450 provides an appropriate function for ID generation when the selected sequence of ID numbers are consecutive integers from low to high.
• Alternatively, the sequence of ID numbers could be any other numeral sequence, provided that theadder450 is replaced with an alternative operator that enables the sequence. For example, theadder450 could be replaced with a subtractor that subtracts “1” from the ID, IDii, thereby enabling a sequence of consecutive integers from high to low. It will be described later with reference toFIG. 11.
• Theselector452 selects one of the two inputs (effectively “added (or altered) ID, IDii+1” and “non-added (or non-altered) ID, IDii”) according to theDT match signal449. If theDT match signal449 is “high” (corresponding to a match between DTsi and DTref), then theselector452 will select input “1”, which receives thecalculation signal451 of “added IDii+1” from theadder450. If theDT match signal449 is “low” (corresponding to a difference between DTsi and DTref), then theselector452 will select input “0”, which receives theID signal435 of “non-added IDii” from theinput ID register440. The selected output signal of n-bits from theselector452 is fed to theoutput ID register454 that is enabled to register the selected n-bit ID data (IDj) therein immediately before the expiration of the time period Tm, in response to an enable signal (not shown). Theoutput ID register454 outputs the registered data in a serial manner as the serialoutput ID signal481 that is fed to thedata combiner467.
• The DT signal445 containing the m-bit device type DTsi is fed from the input DT register439 to an output DT register485 (a parallel-to-serial register) that provides the serial output DT signal487 to thedata combiner467 in response to the clock signal SCLK. Thedata combiner467 combines the p-bit IDGC, the m-bit DT, DTsi, and the n-bit ID, IDo, all of them being serial data. The combined data signal (the data combination signal469) is fed from thedata combiner467 to theselector456. Theselector456 also receives the processed data signal425 provided by the controller/processor463 accessing the memory420-i(NAND or NOR Flash memory) of that device410-i. In response to thedata selection signal423, theselector456 selects one of the data combination signal469 containing the IDGC-DT-ID and the processeddata signal425. When thedata selection signal423 is “high” (an ID generation mode), theselector456 selects the data combination signal469 fed to its “1” input. When thedata selection signal423 is “low” (the normal mode), theselector456 selects the processed data signal425 fed to its “0” input. A selected signal from theselector456 is outputted through theserial output buffer458 to the next device410-(i+1) in the serial interconnection configuration. Thus, in the ID generation mode, the serial output SOi outputted through the SOP connection of the device410-icontains the ID generation command IDGC, the device type DTsi and the output IDoi. The SOi is provided to the next device410-(i+1).
• It is noted that theaforementioned selector452 is shown for selecting a single bit of IDii or a single bit ofIDii+1. Accordingly, there are n duplicate selectors to select the n-bit calculation signal451 or the n-bit ID signal435 and output the selected n-bit signal, in response to theDT match signal449.
• TheID generator434 provides theID signal435 containing the n-bit ID, IDii, to theID register431. In response to the ID write enablesignal433 from thedevice operation controller460 and theDT match signal449, theID register431 registers or latches the received ID, IDii, for the present device410-i. The registered ID is held until powered-off. TheID register431 is initially reset to the zero state by theinternal reset signal438 and thus, if no ID latch occurs, theID register431 will hold the zero state.
• With reference toFIG. 6A, for example, the above ID generation process is completed bydevice1's controller430-1 at device410-1 that is a NAND Flash memory device. The device controller430-1 outputs the resulting ID todevice2,410-2, that is a NOR Flash memory device. The device controller430-2 located at device410-2 performs a similar operation to that of the controller430-1 ofdevice1, transferring the resulting ID todevice3,410-3. This process is repeated for all devices410-1-410-5 in the serial interconnection configuration, until the ID has propagated through all devices.
• FIG. 7A shows an ID generation method with a skip or bypass function performed by the ID generator ofFIG. 6D. Referring toFIG. 7A, a device DVi receives an ID generation command IDGC, a device type DT and an ID (step511). In the example, “DVi” represents a given device to perform the operations of device type match determination and ID assignment. First to consider the operation ofdevice1, a device parameter “i” is determined to be “1” (step512). Then, operation starts at a present device DVi (step513). The operations of DT match determination and ID assignment are performed at the device DVi (step514). Upon completion of the operations ofstep514, the DT determination and ID generation operations end at the device DVi (step515). If the device DVi is not the last device (NO at step516), a given device DVi will be a next device DV(i+1) (i.e., the device parameter i is incremented to “i=i+1”). In this case, the serial output SOi from the present device DVi is the serial input SI to the next device DV(i+1) (step517). At the next device, the operations of steps513-515 are performed. Such a process is repeated until the last device completes it (YES at step516) and all of devices1-5 in the serial interconnection configuration performs the operations of the device type match determination and the ID assignment. After the operations are performed at the last device (YES at step516), successive operations are performed in the normal operation mode (step518). In this particular example shown in the figures, it is assumed that the memory controller211 (shown inFIG. 6A) is aware when the last device of the serial interconnection configuration completes the DT determination and ID assignment operations to move to the normal operation mode. Instep514, if there is a device type match between the received DT and a device type of the device DVi, an ID assignment and an ID generation for another device will be performed. If there is no-match, neither ID assignment nor ID generation for another device will be performed. Details of the operation of DT match determination and ID assignment performed atstep514 are shown inFIG. 7B.
• Referring toFIGS. 6C, 6D,7A and7B, in the example, a device DVi is given and then, the operations of DT match determination and ID assignment process start at the present device DVi (step513). The device DVi (e.g., device2) receives, from a previous device DV(i−1) (e.g., device1), an ID, IDii, and the received ID is held in theinput ID register440. Also, the device type DTsi for the device type match determination is received and is held in the input DT register439 (step521). Then, the held DTsi is compared with the reference DT, DTrefi, by theDT comparator448 whether there is a match between them (step522). If there is a match between DTsi and DTrefi (YES at step522), theDT match signal449 is “high” to indicate the generation of a new ID and the ID assignment (step523). In response to theDT match signal449 being “high”, the n-bit IDii contained in theID signal435 is registered or latched in theID register431 that has been enabled by the ID write enablesignal433. Thus, the received ID, IDii, is assigned to the present device DVi as an ID (step524). Upon completion ofstep524, the ID number or value is then altered by a “+1” operation (step525) by theadder450 and the altered or calculated ID is selected by theselector452, resulting in a new ID, IDj (=IDii+1).
• If the values of the DTsi and the DTref do not match (NO at step522), theDT match signal449 will be “low”. This signal indicates to the device not to latch the received ID number, IDii, with no adding operation. Thus, the received ID, IDii, is selected by theselector452 and is kept as a new ID, IDj (=IDii) (step527).
• After such a new ID is determined (step525 or527), the new ID, IDj, is fed from theselector452 to theoutput ID register454. The serial ID read from theID register454 is provided as an output IDoi contained in theoutput ID signal481 to thedata combiner467. The IDoi is combined with the serial DTsi read from theoutput DT register485 and further combined with the ID generation command IDGC by thedata combiner467. The resultant combination of IDGC, DTsi and IDoi is transferred to the next device DV(i+1) in the serial interconnection configuration (step526).
• FIG. 8A shows the plurality of devices in the serial interconnection configuration ofFIG. 6A, in which the ID generation of NAND memory devices is performed.FIG. 8B shows signal timings for the ID generation of NAND memory devices ofFIG. 8A.
• Referring toFIGS. 8A and 8B, the data on the SIP contains the command, DT and ID bits that are fed to the serial input port (SIP) ofdevice1,410-1. The serial input data to the SIP connection is processed and processed data is outputted as the serial output data from the SOP connection. Due to the nature of the serial interconnection configuration, an intended device for receipt of serial data needs to be identified for data processing. Such an identifier is attached to the serial data as an ID. The ID fordevice1,410-1, is provided by a memory controller such as thememory controller211 as shown inFIG. 6A. The ID fordevice1 might for example be ‘00h’. The size of the ID depends on the requirements of the system and the number of devices connected in the configuration. Then, device410-1 provides a serial output SO1 from its SOP connection, the SO1 being fed todevice2,410-2. Similarly, device410-2 provides a serial output SO2 todevice3,410-3. As such, each device receives serial input data from its SIP connection and provides a serial output SO to its neighboring device.
• Referring toFIGS. 6A-6D,7A,7B,8A and8B, thememory controller211 makes the chip select signal /SCS be “low” at time T1. Immediately thereafter, thememory controller211 sends the reset signal RST to all devices, so that in response to the internal reset signal438 provided by thedevice operation controller460, the ID registers431 of each device is reset. TheID register431 holds the reset state (e.g., ‘000’) until an assigned ID is registered or latched therein. Then, thememory controller211 provides the serial input SI contains a p-bit ID generation command IDGC, an m-bit device type DT, DTsi, and an n-bit identifier ID (initial ID0) todevice1,410-1. In the example, the initial ID, ID0, is a three-bit number ‘000’. Then,device1,410-1, performs the operations of the device type match determination and the ID assignment.
• In the example shown inFIG. 8A, the DT is DTnd for the NAND Flash memory and its DT number or code is ‘00h’ as shown in Table 1. The DT match signals449 indevices1,3 and5 (410-1,410-3 and410-5) (NAND Flash devices) become “high” at determination times Tdt1, Tdt3 and Tdt5, respectively. However, the DT match signals449 indevices2 and4 do not become “high”. Thus,devices2 and4 (NOR Flash devices) provide no “high” match signal. In response the “high” DT match signals449,devices1,3 and5 latch or register the IDs of ‘000’, ‘100’ and ‘010’, respectively, and generate new IDs with +1 operation.
• In the ID generation method shown inFIG. 7B, alternatively, steps524 and525 can be reversed, wherein the “new” ID number (resulting from the “+1” operation) is latched or registered in an ID register. As a result, an assigned ID to the device is the “new” ID number, instead of the received ID number. Accordingly, a memory controller may be configured to address the memory devices in the serial interconnection configuration according to the IDs generated at each device. This will be described later with reference toFIG. 10.
• When each device in the serial interconnection configuration has completed the process, all devices with a matching DT number have generated IDs (step525), and all other devices have refrained from generating IDs (step527). To generate IDs for these other devices, the process can be repeated for all devices, wherein the device type DTsi is replaced with a value matching the device type number of some or all of the other devices. For example, a first process, with the DTnd matching a NAND Flash device, could be completed at all devices, thereby assigning an ID at each NAND Flash device in the serial interconnection configuration. Afterwards, a second process, with the DTnd matching a NOR Flash device, could be completed at all devices, thereby assigning an ID at each NOR Flash device in the serial interconnection configuration. The process may be further repeated for other device types (e.g., DRAM, SRAM, MRAM) in the serial interconnection configuration. As a result, each device in the serial interconnection configuration can be uniquely identified in subsequent commands by specifying the ID and DT of that device.
• In a case where the stored reference device type DTref of the DT number storage/provider442 is selected for the NAND Flash memory, the device type DT is “00h” (see Table 1). In the process shown inFIGS. 7A and 7B, atstep522,devices1,3 and5 (410-1,410-3 and410-5) determine that the DTsi “match” the stored DTref (the positive determination) and thus, atstep525, the +1 operation is performed for generating a next ID. Indevices2 and4 (410-2 and410-4) that are NOR Flash memories, the DT (“01h”) do not match the selected stored DT (the negative determination at step522) and thus, no +1 operation is performed (step527). At the “no-match” devices, no ID registration (i.e., no ID latch) is performed and thus, the reset “zero state” is maintained in the ID registers. The resulting latched or registered IDs and generated or bypassed IDs are shown in Table 2.

  TABLE 2
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  410-1	NAND Flash	00h	000	001
  410-2	NORFlash	01h		000*	001
  410-3	NAND Flash	00h	001	010
  410-4	NORFlash	01h		000*	010
  410-5	NAND Flash	00h	010	011

• In Table 2, “000*” is the reset state, not a latched ID. If a different value or number is used for the reset state, the latched or registered initial ID (“000”) will be distinguishable from the reset state.
• FIG. 9A shows the plurality of devices in the serial interconnection configuration shown inFIG. 6A, in which the ID generation of NOR memory devices is performed.FIG. 9B is a timing diagram of the ID generation in the serial interconnection configuration ofFIG. 9A.
• Referring toFIGS. 6A-6D,7A,7B,9A and9B, each of five devices410-1-410-5 includes thedevice controller430 that provides a skip function of ID generation. The serially interconnected devices ofFIG. 9A perform operations with the stored DT of the DT number storage/provider442 being selected for the NOR Flash memory, DTnr, the number or code of which is ‘01 h’ as shown in Table 1.
• The DT match signals449 indevices2 and4 (410-2 and410-4) (NOR Flash devices) become “high” at determination times Tdt2 and Tdt4, respectively. In response to the “high” device type match signals,devices2 and4 latch or register the IDs ‘000’ and ‘100’ and generate new IDs with +1 operation. However, the DT match signals449 indevices1,3 and5 do not become “high”.
• In a case where the stored DT of the DT number storage/provider442 is selected for the NOR Flash memory, the DT is “01h” (see Table 1). In the process shown inFIG. 7B, atstep522,devices2 and4 (410-2 and410-4) determine that the DTsi “match” the stored DTref and thus, the +1 operation is performed for generating the next ID (step525). Indevices1,3 and5 (410-1,410-3 and410-5) that are NAND Flash memories, the DTsi (“00h”) does not match the selected stored DTref (the negative determination at step522) and thus, no +1 operation is performed (step527). The resulting latched or registered IDs and generated or bypassed IDs are shown in Table 3. In Table 3, “000*” is the reset state.

  TABLE 3
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  410-1	NAND Flash	00h	000*	000
  410-2	NORFlash	01h		000	001
  410-3	NAND Flash	00h	000*	001
  410-4	NORFlash	01h		001	010
  410-5	NAND Flash	00h	000*	010

• In the examples described above, the latched ID in theID register431 of a device is the ID previously generated in the device wherein the device type DT matches the reference device type DTref thereof. Thus, the assigned ID to the present device is the ID generated by theID generator434 of another device and received by the present device.
• Alternatively, a device latches an ID generated thereby before or simultaneously the generated ID is transferred to a next device. In the example, the assigned ID to a device is the ID generated by the device when the device type DT matches the reference device type DTref thereof. Such an example is shown inFIG. 10. An ID generator shown inFIG. 10 is similar to that ofFIG. 6D. A difference is that in anID generator541 ofFIG. 10, the added ID (IDii+1) by theadder450 is provided to theID register431 for registration or latch, instead of the non-calculated (non-altered) ID from theinput ID register440. In this example, the assigned ID is one generated by that device, not one generated by the previous or the other device. Therefore, the latched or registered IDs in the devices are different from ones shown in Tables 2 and 3
• Tables 4 and 5 show the latched or registered IDs and the generated or bypassed IDs in the serial interconnection configuration of devices shown inFIG. 6A with the ID generators as shown inFIG. 10, in the cases where the device types provided by the memory controller are the DTnd and DTnr for NAND and NOR Flash memories, respectively. In Tables 4 and 5, “000*” is the reset state, not a latched ID.

  TABLE 4
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  410-1	NAND Flash	00h	001	001
  410-2	NORFlash	01h		000*	001
  410-3	NAND Flash	00h	010	010
  410-4	NORFlash	01h		000*	010
  410-5	NAND Flash	00h	011	011

• TABLE 5
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  410-1	NAND Flash	00h	000*	000
  410-2	NORFlash	01h		001	001
  410-3	NAND Flash	00h	000*	001
  410-4	NORFlash	01h		010	010
  410-5	NAND Flash	00h	000*	010

• A general bit structure of the packet bits is “packet start+ID generation command+DT+ID+packet end”. In the example shown inFIG. 8A, the packets of the serial inputs are given by (ID being ‘MSB→LSB’):$\begin{array}{cc}\mathrm{SI}1\text{:}& \mathrm{Packet}\mathrm{including}\mathrm{the}\mathrm{ID}0\\ & =\mathrm{Packet}\mathrm{start}+\mathrm{IDGC}+\mathrm{DT}+‘000’+\mathrm{Packet}\mathrm{end}\\ \mathrm{SI}2\text{:}& \mathrm{Packet}\mathrm{including}\mathrm{the}\mathrm{ID}1\\ & =\mathrm{Packet}\mathrm{start}+\mathrm{IDGC}+\mathrm{DT}+‘001’+\mathrm{Packet}\mathrm{end}\\ \mathrm{SI}3\text{:}& \mathrm{ibid}.\\ \mathrm{SI}4\text{:}& \mathrm{Packet}\mathrm{including}\mathrm{the}\mathrm{ID}2\\ & =\mathrm{Packet}\mathrm{start}+\mathrm{IDGC}+\mathrm{DT}+‘010’+\mathrm{Packet}\mathrm{end}\\ \mathrm{SI}5\text{:}& \mathrm{ibid}.\\ \mathrm{SO}\text{:}& \mathrm{Packet}\mathrm{including}\mathrm{the}\mathrm{ID}3\\ & =\mathrm{Packet}\mathrm{start}+\mathrm{IDGC}+\mathrm{DT}+‘011’+\mathrm{Packet}\mathrm{end}.\end{array}$
• As such, the packet bit configuration of the serial input is a packet start, command, DT (device type values), ID values (several bits) and a packet end (optional). These information bits are required in the packets. Other information bits may be included in the packet depending on the system requirements. The number of bits of the information in the packet is varied depending on the system requirements. For example, each of the packet start and end includes four bits. The command includes any number of bits depending on the system requirement and memory operation modes. The DT includes, for example, eight bits representing the device type value. The ID includes, for example, eight bits representing the ID value.
• FIG. 11 shows another example of the ID generator. AnID generator545 shown inFIG. 11 is similar to that ofFIG. 6D. A difference is that theID generator545 has asubtractor550, instead of theadder450 ofFIG. 6D. Thesubtractor550 performs the subtraction of one from the received ID, IDii, to provide acalculation signal551 containing a subtracted ID, IDii−1 of n-bits to theselector452. With such a subtraction, consecutive IDs from high to low are generated. If an initial ID number provided by a memory controller is Q (an integer), IDs will be generated in consecutive numbers from Q to low by the devices including thesubtractors550. Each of thesubtractor550 ofFIG. 11 and theadder450 ofFIG. 6D performs an arithmetic operation for calculating an ID to be newly generated for another device. The arithmetic operation can be achieved by increment or decrement by one or any other number or value.
• FIG. 12 shows a plurality of devices of mixed type in a serial interconnection configuration, in which embodiments of the present invention are implemented. In this example, five devices are interconnected. Referring toFIG. 12, devices590-1-590-5 are a DRAM device, an SRAM device, an MRAM device, a NOR Flash memory device and a NAND Flash memory device, respectively. In a case where the device type DTsi provided by amemory controller591 is the DTdm for DRAMs, only the DRAM devices generate IDs and latch the IDs therein. Table 6 shows the latched or registered IDs and the generated or bypassed ID in the serial interconnection configuration of devices of mixed type shown inFIG. 12.

  TABLE 6
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  590-1	DRAM	02h		000	001
  590-2	SRAM	03h		000*	001
  590-3	MRAM	FFh		000*	001
  590-4	NORFlash	01h		000*	001
  590-5	NAND Flash	00h	000*	001

• Similarly, in a case where the device type DTsi provided by thememory controller591 is the DTsm for SRAMs, only the SRAM devices generate IDs and latch the IDs therein. Table 7 shows the latched or registered IDs and the generated or bypassed ID.

  TABLE 7
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  590-1	DRAM	02h		000*	000
  590-2	SRAM	03h		000	001
  590-3	MRAM	FFh		000*	001
  590-4	NORFlash	01h		000*	001
  590-5	NAND Flash	00h	000*	001

• In the cases where the device type DTsi provided by thememory controller591 are the DTsi is the DTmm for MRAMs, the DTnr for NOR Flash memories and the DTnd for NAND Flash memories, only the MRAM devices, NOR Flash memory devices and the NAND Flash memory devices, respectively, generate IDs and latch the IDs therein. Tables 8-10 show the latched or registered IDs and the generated or bypassed IDs in such three cases.

  TABLE 8
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  590-1	DRAM	02h		000*	000
  590-2	SRAM	03h		000*	000
  590-3	MRAM	FFh		000	001
  590-4	NORFlash	01h		000*	001
  590-5	NAND Flash	00h	000*	001

• TABLE 9
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  590-1	DRAM	02h		000*	000
  590-2	SRAM	03h		000*	000
  590-3	MRAM	FFh		000*	000
  590-4	NORFlash	01h		000	001
  590-5	NAND Flash	00h	000*	001

• TABLE 10
  		DT Number	Latched or	Generated or
  Device	Device Type	or Value	Registered ID	Bypassed ID
  590-1	DRAM	02h		000*	000
  590-2	SRAM	03h		000*	000
  590-3	MRAM	FFh		000*	000
  590-4	NORFlash	01h		000*	000
  590-5	NAND Flash	00h	000	001

• In Tables 6-10, “000*” is the reset state and it is not a latched initial ID. If a different value or number is used for the reset state, the latched or registered initial ID (“000”) will be distinguishable from the reset state.
• FIG. 13A shows another example of thedevice operation controller460 ofFIG. 6B. Referring toFIG. 13A, the device operation controller includes a latency adjuster471 having a delay element (e.g., one or more D-type flip-flops611) that provides a constant output latency. The data combination signal469 containing the combined IDGC-DT-ID is provided to the latency adjuster471 that performs a signal latency adjustment of the combined IDGC-DT-ID in response to the clock signal SCLK. Anoutput signal473 from the latency adjuster471 contains the IDGC-DT-ID with the adjusted latency and is provided to theselector456. In response to thedata selection signal423, theselector456 selects one of the combined IDGC-DT-ID and the processed data. A selected data is provided through thebuffer458 to the next device410-(i+1). Due to the adjusted latency, the ID generation processes between the present device410-I and the next device410-(i+1) are not overlapped. A packet interval between two serial inputs (e.g., SI1 and SI2) is adjusted to be non-overlapped. A time interval Tlt is adjusted by the latency adjuster471, as shown inFIG. 13B. In accordance with the adjusted latency, an output containing the IDGC, the DT and the ID is provided in a packet basis by one device to a next device. The two adjacent devices connected in the serial interconnection configuration are guaranteed enough time margin to perform the interpretation of packet based commands and the functions of the device type match determination and ID generation. The latency adjustment is optional and the system may not need such a latency adjuster.
• FIG. 14 shows a plurality of devices in a serial interconnection configuration operating to generate an ID at each device employing an example of ID generation logic for dual links. The connection of the memory devices is different from that ofFIG. 6A.FIG. 14 shows an example describing how to generate IDs with dual links of a serial interconnection configuration. In this example, serial inputs SI0 and S11 are fed into serial input port connections SIP0 and SIP1 of a device and serial outputs SO0 and SO1 are provided from serial output port connections SOP0 and SOP1 of that device. The transferring of the serial inputs SI0, SI1 and the serial outputs SO0, SO1 is separately controlled. Any serial input pin and one control pin can have the same functionality. Also, an ID generation logic may be possible for multiple links wherein a plurality of devices having multiple ports is interconnected.
• As described above, the embodiments operate with the SDR. The system and interconnected devices can operate with the DDR as shown inFIG. 2B.
• In the above-described examples, the bit structure of the ID stored in theID register431 of the devices410-iand transmitted in a packet is “MSB (Most Significant Bit)→LSB (Least Significant Bit)”. The bit structure of each of other data (e.g., “Packet Start”, “IDGC”, “DT”, “Packet End”) contained in the packet is also “MSB→LSB”. Alternatively, the bit structure of each data contained in a packet can be “LSB→MSB” and the ID bits of “LSB→MSB” can be stored in theID register431.
• There are variations to the above-described embodiments. The configuration of the devices120-1-120-4 inFIG. 1 may include both a serial interconnection (e.g., input SIP and output SOP) and conventional multi-drop connections (e.g., SCLK and /SCS). Thus, the configuration may be referred to as a hybrid of serial interconnection and multi-drop configurations, where the advantages of each may be realized. Alternatively, embodiments of the techniques described herein may be implemented in serial, parallel, multi-drop or other connections, and combinations thereof, between devices.
• In the above-described embodiments, the operation has been described based on the active “high” signals for the purpose of simplicity. The circuits may be designed to perform the operation based on the “low” active signals, in accordance with a design preference. As mentioned before, it can apply the serial Flash memory or a product with serial input bit stream control.
• In the embodiments described above, the device elements and circuits are connected to each other as shown in the figures, for the sake of simplicity. In practical applications of the present invention to apparatus, devices, elements, circuits, etc. may be connected directly to each other. As well, devices, elements, circuits etc. may be connected indirectly to each other through other devices, elements, circuits, etc., necessary for operation of the apparatus. Thus, in actual configuration, the circuit elements and devices are directly or indirectly coupled with or connected to each other.
• The embodiments described above are directed to systems including memory devices. The technique described above can be applied to systems including other semiconductor devices, such as, for example, data processing devices, which are distinguishable in accordance with predetermined data or information on their characteristics or types. Such systems can be included in electronic equipment or products.
• It will be apparent to those of ordinary skill in the art that the ID generators or producers, the controllers, the processors and the other device elements and the memory controllers may be achieved by hardware or software.
• The above-described embodiments of the present invention are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims (52)

1. A method for producing a device identifier (ID) for a device, comprising:

receiving a device type (DT) and an input ID;

determining the DT of the device in response to the received DT;

outputting an output ID in accordance with a determination result; and

providing the output ID accompanying the received DT to an other device, the devices being interconnected to each other.

2. The method ofclaim 1, wherein the step of determining comprises:

comparing the received DT with device type information (DTI) associated with the device to provide the determination result.

3. The method ofclaim 2, wherein the step of outputting comprises:

performing a calculation based on the received ID to provide an altered ID.

4. The method ofclaim 3, wherein the step of outputting further comprises:

selecting one of the altered ID and a non-altered ID in response to the determination result, the non-altered ID being the received ID, thereby outputting a selected ID as the output ID.

5. The method ofclaim 4, wherein the step of providing comprises:

combining the selected ID and the received DT, the combined ID and DT being provided to the other device.

6. The method ofclaim 5, further comprising:

sending the combined DT and ID in a packet.

7. The method ofclaim 6, wherein the step of receiving comprises:

receiving the DT and the input ID in a packet.

8. The method ofclaim 7, wherein:

the step of combining comprises combining an ID production command, the selected ID and the received DT;

the step of sending comprises sending the combined command, DT and ID in a packet; and

the step of receiving comprises receiving an ID production command, the DT and the input ID in a packet.

9. The method ofclaim 3, wherein the step of performing comprises:

adding a pre-determined value to the received ID to provide the altered ID.

10. The method ofclaim 3, wherein the step of performing comprises:

subtracting a pre-determined value from the received ID to provide the altered ID.

11. An apparatus for use in a device, comprising:

a receiver for receiving a device type (DT) and a device identifier (ID);

a determiner for determining the DT of the device from the received DT;

an ID provider for outputting an ID in accordance with a determination result; and

an output provider for providing the outputted ID accompanying the received DT to another device.

12. The apparatus ofclaim 11, further comprising:

a device type provider for providing device type information (DTI) associated with the device.

13. The apparatus ofclaim 12, wherein the determiner comprises:

a comparator for comparing the received DT with the provided DTI to provide the determination result.

14. The apparatus ofclaim 13, wherein the ID provider comprises:

an arithmetic operator for performing a calculation or non-calculation of the received ID with a pre-defined value to provide a calculated ID or a non-calculated ID as the outputted ID.

15. The apparatus ofclaim 14, wherein the comparator comprises:

a DT match detector for detecting a match between the received DT and the provided DTI, thereby providing a match determination result when there is a match therebetween,

the calculated ID being selected as the outputted ID in response to the match determination result,

the non-calculated ID being selected as the outputted ID in response to a no-match determination result.

16. The apparatus ofclaim 14, wherein the arithmetic operator comprises:

a calculator for calculating the received ID with the pre-defined value.

17. The apparatus ofclaim 16, wherein the calculator comprises:

an adder for adding one to the received ID.

18. The apparatus ofclaim 16, wherein the calculator comprises:

a subtractor for subtracting one from the received ID.

19. The apparatus ofclaim 14, wherein the output provider comprises:

an ID-device type provider for outputting the outputted ID accompanying the received DT to an other device, the device and the other device being interconnected to each other.

20. The apparatus ofclaim 19, wherein:

the outputted ID and the DT are provided in a parallel manner; and

the output provider comprises first and second holders,

the first holder registering the parallel ID and outputting the ID in a serial manner,

the second holder registering the parallel DT and outputting the DT in a serial manner.

21. The apparatus ofclaim 20, wherein the output provider further comprises:

a serial data combiner for combining the serial ID and DT to provide a combined serial ID and DT as the ID accompanying the received DT.

22. The apparatus ofclaim 21, wherein:

the device is one of a plurality of devices of mixed type, the devices being serially interconnected.

23. The apparatus ofclaim 21, wherein the serial data combiner comprises:

a data processor for combining an ID production command, the DT and the ID in a packet, the packet being sent to the other device.

24. The apparatus ofclaim 22, wherein the receiver comprises:

a packet receiver for receiving an ID production command, the DT and the input ID in a packet.

25. An apparatus for assigning a device identifier at a first device coupled to a second device in a serial interconnection configuration of devices of mixed type, the first device having a serial input connection coupled to a serial output connection of a previous device in the serial interconnection configuration, the second device having a serial input connection coupled to a serial output connection of the first device, the apparatus comprising:

a receiver for receiving a device identifier (ID) and a device type (DT), the ID and DT being provided through the serial input connection of the device;

a determiner for determining the DT of the device from the received DT;

an ID provider for outputting an ID in accordance with a determination result; and

an output provider for providing the outputted ID accompanying the received DT to an other device.

26. The apparatus ofclaim 25, wherein the ID provider comprises:

an arithmetic operator for performing arithmetic operation with the received ID and a pre-defined value to produce an ID.

27. The apparatus ofclaim 26, further comprising:

a device type provider for providing device type information (DTI) associated with the device.

28. The apparatus ofclaim 27, wherein the determiner comprises:

a comparator for comparing the received DT with the provided DTI to provide the determination result.

29. The apparatus ofclaim 28, wherein the ID provider further comprises:

a selector for selecting the received ID or the produced ID in response to the determination result, the selected ID being provided as the outputted ID.

30. The apparatus ofclaim 29, wherein the receiver comprises:

a serial to parallel holder for:

receiving the received ID and DT in a serial manner; and

outputting each of the registered ID and DT in a parallel manner,

the parallel ID being provided to the arithmetic operator and the selector.

31. The apparatus ofclaim 30, wherein the device type provider comprises:

a storage for storing the DTI on the type of the device and providing the DTI for the determination.

32. The apparatus ofclaim 31, wherein the output provider comprises:

a combiner for combining the received DT and the selected ID; and

a device type-ID provider for outputting the combined DT and ID.

33. The apparatus ofclaim 32, wherein the combiner comprises:

a parallel to serial holder for:

receiving the DT and ID in a parallel manner; and

outputting the parallel DT and ID in a serial manner; and

an output combiner for combining the serial DT and ID, the combined DT and ID being provided through the serial output connection of the device.

34. The apparatus ofclaim 32, wherein the combiner comprises:

a data combiner for combining an ID production command, the selected ID and the received DT.

35. The apparatus ofclaim 26, wherein the arithmetic operator comprises:

an adder for adding the pre-defined value to the received ID.

36. The apparatus ofclaim 26, wherein the arithmetic operator comprises:

a subtractor for subtracting the pre-defined value to the received ID.

37. A method for assigning a device identifier (ID) for one of a plurality of devices of mixed type in a serial interconnection configuration, a first device having a serial input connection coupled to a serial output connection of a previous device, a second device having a serial input connection coupled to a serial output connection of the first device, the method being adopted to at least one of the devices, the method comprising:

receiving an input ID and a device type (DT) through the serial input connection of the device;

determining the DT of the device from the received DT;

outputting an output ID in response to a determination result; and

providing a combination of the received DT and the outputted ID.

38. The method ofclaim 37, wherein the step of determining comprises:

match determining whether the received DT matches a reference DT associated with the device.

39. The method ofclaim 38, further comprising:

providing device type information (DTI) associated with the device as the reference DT.

40. The method ofclaim 39, wherein the step of match determining comprises:

comparing the received DT with the provided DTI to provide the determination result.

41. The method ofclaim 40, wherein the step of outputting comprises:

performing the calculation of the received ID with a pre-defined value.

42. The method ofclaim 41, wherein the step of outputting further comprises:

selecting one of the received ID and the calculated ID in response to the determination result, the selected ID being outputted through the output connection of the device.

43. The method ofclaim 42, wherein the step of providing the combination of DT and ID comprises:

combining the received DT and the selected ID; and

outputting the combined DT and ID to another device.

44. The method ofclaim 41, further comprising:

assigning the calculated ID for registration in the device.

45. The method ofclaim 41, further comprising:

assigning the received ID for registration in the device.

46. The method ofclaim 37, wherein the step of providing the combination of the DT and ID comprises:

combining the DT and the ID in a serial manner to provide the combined serial DT and ID, the combined serial ID and DT being provided through the serial output connection of the device.

47. The method ofclaim 46, further comprising:

combining an ID production command, the DT and the ID; and

sending the combined command, DT and ID in a packet to the other device.

48. The method ofclaim 37, wherein the step of receiving comprises:

receiving an ID production command, the DT and the input ID in a packet.

49. A method for assigning a device identifier (ID) for a plurality of devices of mixed type in a serial interconnection configuration, a first device having a serial input connection coupled to a serial output connection of a previous device, a second device having a serial input connection coupled to a serial output connection of the first device, the method comprising:

receiving a device type (DT) and an input ID through the serial input connection;

holding the received DT at a device;

determining whether the received DT matches a reference DT associated with the device;

obtaining a calculated ID or a non-calculated ID in response to a determination result;

combining the received DT with the calculated or non-calculated ID;

providing the combined DT and ID through the serial output connection of the device; and

performing an ID assignment in response to the determination result at the device.

50. The method ofclaim 49, wherein the step of providing the combined DT and ID comprises:

providing the ID accompanying the DT in a serial manner through the serial output connection to an other device.

51. The method ofclaim 50, further comprising:

providing an ID production command, the DT and the ID in a packet to the other device.

52. The method ofclaim 49, further comprising:

adjusting an output latency for avoiding overlap between the steps of receiving and providing.

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