US20100301329A1

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Publication number: US20100301329A1
Application number: US12/787,813
Authority: US
Inventors: Yuji Asano; Junichi Koezuka
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 2009-05-29
Filing date: 2010-05-26
Publication date: 2010-12-02
Also published as: CN101901838A; US20160035866A1; JP5564331B2; JP2016015505A; KR20100129185A; JP6053216B2; JP5801929B2; US9419113B2; CN101901838B; JP2011009724A; JP2014225674A

Abstract

An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. Another object is to provide a method for manufacturing the thin film transistor. A thin film transistor using an oxide semiconductor layer is formed in such a manner that buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, source and drain electrode layers are formed over the buffer layers, and the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween. In addition, the buffer layers are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer are obtained.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device including an oxide semiconductor, a display device including the semiconductor device, and a manufacturing method thereof.

2. Description of the Related Art

Various metal oxides are used for a variety of applications. Indium oxide is a well-known material and is used as a light-transmitting electrode material which is necessary for liquid crystal displays and the like.

Some metal oxides have semiconductor characteristics. As metal oxides exhibiting semiconductor characteristics, for example, tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like can be given. A thin film transistor in which such a metal oxide having semiconductor characteristics is used for a channel formation region has been disclosed (Patent Documents 1 to 4, and Non-Patent Document 1).

Further, not only single-component oxides but also multi-component oxides are known as metal oxides. For example, homologous compound, InGaO₃(ZnO)_m(m is a natural number) is known as a multi-component oxide including In, Ga and Zn (Non-Patent Documents 2 to 4).

In addition, it is confirmed that an oxide semiconductor including such an In—Ga—Zn-based oxide can be used for a channel layer of a transistor (Patent Document 5, andNon-Patent Documents 5 and 6).

In a conventional technique, amorphous silicon or polycrystalline silicon has been used for a thin film transistor (a TFT) provided for each pixel of an active matrix liquid crystal display. However, in place of these silicon materials, attention has been attracted to a technique for manufacturing a thin film transistor including the aforementioned metal oxide semiconductor. Examples of the techniques are disclosed inPatent Document 6 andPatent Document 7, in which a thin film transistor is manufactured with zinc oxide or an In—Ga—Zn—O-based oxide semiconductor for a metal oxide semiconductor film and is used as a switching element or the like of an image display device.

REFERENCES[Patent Documents]

[Patent Document 1] Japanese Published Patent Application No. S60-198861;

[Patent Document 2] Japanese Published Patent Application No. H8-264794;

[Patent Document 3] Japanese Translation of PCT International Application No. H11-505377;

[Patent Document 4] Japanese Published Patent Application No. 2000-150900;

[Patent Document 5] Japanese Published Patent Application No. 2004-103957;

[Patent Document 6] Japanese Published Patent Application No. 2007-123861; and

[Patent Document 7] Japanese Published Patent Application No. 2007-96055.

[Non-Patent Documents]

[Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, “A ferroelectric transparent thin-film transistor”,Appl. Phys. Lett.,17 Jun. 1996, Vol. 68 pp. 3650-3652;

[Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the In₂O₃—Ga₂ZnO₄—ZnO System at 1350° C.”,J. Solid State Chem.,1991, Vol. 93, pp. 298-315;

[Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In₂O₃(ZnO)_m(m=3, 4, and 5), InGaO₃(ZnO)₃, and Ga₂O₃(ZnO)_m(m=7, 8, 9, and 16) in the In₂O₃—ZnGa₂O₄—ZnO System”,J. Solid States Chem.,1995, Vol. 116, pp. 170-178;

[Non-Patent Document 4] M. Nakamura, N. Kimizuka, T. Mohri, and M. Isobe, “Syntheses and crystal structures of new homologous compounds, indium iron zinc oxides (InFeO3(ZnO)m) (m is a natural number) and related compounds”, KOTAI BUTSURI (SOLID STATE PHYSICS), 1993, Vol. 28, No. 5, pp. 317-327;

[Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor”,SCIENCE,2003, Vol. 300, pp. 1269-1272; and

[Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors”,NATURE,2004, Vol. 432 pp. 488-492.

SUMMARY OF THE INVENTION

An object of an embodiment of the present invention is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. Another object of an embodiment of the present invention is to provide a method for manufacturing the thin film transistor. Another object of an embodiment of the present invention is to provide a display device including the thin film transistor.

In order to achieve the above object, in an embodiment of the present invention, a thin film transistor using an oxide semiconductor layer is formed in such a manner that buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, source and drain electrode layers are formed over the buffer layers, and the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween. Further, in order to achieve the above object, in another embodiment of the present invention, the buffer layers over the oxide semiconductor layer are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer are obtained.

An embodiment of the present invention is a semiconductor device including a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, a first buffer layer and a second buffer layer over the oxide semiconductor layer, and source and drain electrode layers over the first buffer layer and the second buffer layer. The first buffer layer and the second buffer layer have higher conductivity than the oxide semiconductor layer and are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, and the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the first buffer layer and the second buffer layer interposed therebetween.

Note that it is preferable that the first buffer layer and the second buffer layer are formed using a non-single-crystal film formed from an oxide semiconductor. Alternatively, it is preferable that the first buffer layer and the second buffer layer are formed using a non-single-crystal film formed from an oxide semiconductor including nitrogen. It is preferable that the high-conductive oxide semiconductor layer is formed using a non-single-crystal film formed from an oxide semiconductor. Alternatively, it is preferable that the high-conductive oxide semiconductor layer is formed using a non-single-crystal film formed from an oxide semiconductor including nitrogen.

Further, the oxide semiconductor layer may be formed through heat treatment in a nitrogen atmosphere. Alternatively, the oxide semiconductor layer may be formed through heat treatment in an air atmosphere. The oxide semiconductor layer may include a region which is located between the first buffer layer and the second buffer layer and whose thickness is smaller than that of a region overlapping with the first buffer layer and the second buffer layer. A width in a channel direction of the gate electrode layer may be smaller than a width in the channel direction of the oxide semiconductor layer.

Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming a gate electrode layer over a substrate, forming a gate insulating layer over the gate electrode layer, forming a first oxide semiconductor film over the gate insulating layer using a sputtering method, subjecting the first oxide semiconductor film to heat treatment, forming a second oxide semiconductor film over the first oxide semiconductor film using a sputtering method, subjecting the second oxide semiconductor film to reverse sputtering treatment, subjecting the second oxide semiconductor film to heat treatment in a nitrogen atmosphere, etching the first oxide semiconductor film and the second oxide semiconductor film to form an oxide semiconductor layer and a first buffer layer, forming a conductive film over the oxide semiconductor layer and the first buffer layer, etching the conductive film and the first buffer layer to form source and drain electrode layers, a second buffer layer, and a third buffer layer, and subjecting the oxide semiconductor layer to heat treatment. The second buffer layer and the third buffer layer have higher conductivity than the oxide semiconductor layer.

Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps and the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the invention.

In this specification, a “semiconductor device” generally refers to a device which can function by utilizing semiconductor characteristics; an electrooptic device, a semiconductor circuit, and an electronic device are all included in semiconductor devices.

According to an embodiment of the present invention, in a thin film transistor using an oxide semiconductor layer, buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, and source and drain electrode layers are formed over the buffer layers, which results in that the oxide semiconductor layer can be electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween, contact resistance between the oxide semiconductor layer and the source and drain electrode layers can be reduced, and electric characteristics can be stabilized. In addition, the buffer layers are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer can be obtained.

By using the thin film transistor for a pixel portion and a driver circuit portion of a display device, the display device can have stable electric characteristics and high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 2A to 2C illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 3A to 3C illustrate the method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 4A and 4B illustrate the method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 5A and 5B illustrate the method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 6A to 6C illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 7 illustrates the method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 8 illustrates the method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 9 illustrates the method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 10 illustrates the method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 11 illustrates the method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS.12A1 and12A2 and FIGS.12B1 and12B2 illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 13A and 13B illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 14A to 14C illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 15A and 15B are block diagrams of a semiconductor device;

FIG. 16 illustrates a structure of a signal line driver circuit;

FIG. 17 is a timing chart showing operation of a signal line driver circuit;

FIG. 18 is a timing chart showing operation of a signal line driver circuit;

FIG. 19 is a diagram showing a structure of a shift register;

FIG. 20 illustrate a connection structure of a flip-flop inFIG. 19.

FIGS.21A1 and21A2 andFIG. 21B illustrate a semiconductor device according to an embodiment of the present invention;

FIG. 22 illustrates a semiconductor device according to an embodiment of the present invention;

FIG. 23 illustrates a semiconductor device according to an embodiment of the present invention;

FIG. 24 illustrates a pixel equivalent circuit of a semiconductor device according to an embodiment of the present invention;

FIGS. 25A to 25C each illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 26A and 26B illustrate a semiconductor device according to an embodiment of the present invention;

FIGS. 27A and 27B illustrate examples of usage patterns of electronic paper;

FIG. 28 is an external view of an example of an electronic book reader;

FIGS. 29A and 29B are external views illustrating an example of a television set and an example of a digital photo frame, respectively;

FIGS. 30A and 30B are external views illustrating examples of amusement machines;

FIGS. 31A and 31B are external views illustrating examples of mobile phones; and

FIGS. 32A and 32B illustrate a semiconductor device according to an embodiment of the present invention.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and the scope of the present invention. Therefore, the present invention to be disclosed is not interpreted as being limited to the description of Embodiments below. Note that in the structure of the present invention described below, reference numerals indicating the same portions and portions having a similar function are used in common in different drawings, and repeated descriptions thereof are omitted.

Embodiment 1

In this embodiment, a structure of a thin film transistor will be described with reference toFIGS. 1A and 1B.

A thin film transistor having a bottom-gate structure of this embodiment is illustrated inFIGS. 1A and 1B.FIG. 1A is a cross-sectional view, andFIG. 1B is a plan view.FIG. 1A is a cross-sectional view taken along line A1-A2 ofFIG. 1B.

In the thin film transistor illustrated inFIGS. 1A and 1B, agate electrode layer101 is provided over asubstrate100, agate insulating layer102 is provided over thegate electrode layer101, anoxide semiconductor layer103 is provided over thegate insulating layer102, buffer layers106aand106bare provided over theoxide semiconductor layer103, and source and drain electrode layers105aand105bare provided over the buffer layers106aand106b.In other words, theoxide semiconductor layer103 and the source and drain electrode layers105aand105bare electrically connected to each other with the buffer layers106aand106binterposed therebetween. Here, the buffer layers106aand106bhave higher conductivity than theoxide semiconductor layer103. In addition, theoxide semiconductor layer103 includes a region between the buffer layers106aand106b.The region has a thickness smaller than a region overlapping with the buffer layers106aand106b.

Thegate electrode layer101 can be formed with a single layer or a stacked layer using any of a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloy material including any of the metal materials as its main component; or a nitride including any of the metal materials as its component. Thegate electrode layer101 is preferably formed using a low-resistance conductive material such as aluminum or copper; however, since the low-resistance conductive material has disadvantages such as low heat resistance or a tendency to be corroded, it is preferably used in combination with a heat-resistant conductive material. As the heat-resistant conductive material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like is used.

For example, a stacked-layer structure of thegate electrode layer101 is preferably a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked. Alternatively, a three-layer structure in which a tungsten layer or a tungsten nitride layer, an aluminum-silicon alloy layer or an aluminum-titanium alloy layer, and a titanium nitride layer or a titanium layer are stacked is preferably used.

For theoxide semiconductor layer103, a non-single-crystal film formed from an In—Ga—Zn—O-based, In—Sn—Zn—O-based, Ga—Sn—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, In—Sn—O-based, Ga—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor.

Theoxide semiconductor layer103 includes at least an amorphous component. A crystal grain (a nanocrystal) is included in an amorphous structure in some cases. The crystal grain (nanocrystal) has a diameter of 1 nm to 10 nm, typically, approximately 2 nm to 4 nm Note that the crystal state is evaluated by X-ray diffraction (XRD) analysis.

The thickness of theoxide semiconductor layer103 is 10 nm to 300 nm, preferably 20 nm to 100 nm.

An insulating oxide may be included in theoxide semiconductor layer103. Here, as the insulating oxide, silicon oxide is preferable. Further, nitrogen may be added to the insulating oxide. In this case, theoxide semiconductor layer103 is preferably formed using a sputtering method using a target including SiO₂at 0.1% by weight to 30% by weight inclusive, more preferably at 1% by weight to 15% by weight inclusive.

The buffer layers106aand106bfunction as source and drain regions of the thin film transistor. In a manner similar to the case of theoxide semiconductor layer103, the buffer layers106aand106bcan be formed using a non-single-crystal film formed from an In—Ga—Zn—O-based, In—Sn—Zn—O-based, Ga—Sn—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, In—Sn—O-based, Ga—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor. In addition, the buffer layers106aand106bare preferably formed using a non-single-crystal film formed from an In—Ga—Zn—O—N-based, Ga—Zn—O—N-based, Zn—O—N-based, or Sn—Zn—O—N-based oxide semiconductor, which includes nitrogen. In addition, the non-single-crystal film may include insulating oxide such as silicon oxide.

In this specification, an In—Ga—Zn—O—N-based oxide semiconductor is an oxide semiconductor including at least In, Ga, Zn, and N. A Ga—Zn—O—N-based oxide semiconductor is an oxide semiconductor including at least Ga, Zn, and N. A Zn—O—N-based oxide semiconductor is an oxide semiconductor including at least Zn and N. A Sn—Zn—O—N-based oxide semiconductor is an oxide semiconductor including at least Sn, Zn, and N.

It is preferable that the buffer layers106aand106bare formed using a sputtering method in an atmosphere of a rare gas such as argon and a nitrogen gas. By forming the buffer layers106aand106bin this manner, the conductivity of the buffer layers106aand106bcan be increased. In addition, when reverse sputtering treatment and heat treatment in a nitrogen atmosphere are performed on the formed oxide semiconductor film, the conductivity of the buffer layers106aand106bcan be further increased. Here, an atmosphere including a nitrogen gas at 80 vol % to 100 vol % and a rare gas such as argon at 0 vol % to 20 vol % is preferably employed as the nitrogen atmosphere.

In addition, in the buffer layers106aand106b,the conductivity may be changed in stages or successively from a surface side toward the substrate side. Further, high resistance regions may be formed at edge portions of the buffer layers106aand106b.

The buffer layers106aand106binclude at least an amorphous component. A crystal grain (a nanocrystal) is included in an amorphous structure in some cases. The crystal grain (nanocrystal) has a diameter of 1 nm to 10 nm, typically, approximately 2 nm to 4 nm Note that the crystal state is evaluated by X-ray diffraction (XRD) analysis.

The thickness of the oxide semiconductor film used for the buffer layers106aand106bis 5 nm to 20 nm Needless to say, when the film includes a crystal grain, the diameter of the crystal grain does not exceed the thickness of the film.

The buffer layers106aand106bhaving higher conductivity than theoxide semiconductor layer103 are formed over theoxide semiconductor layer103, which results in that theoxide semiconductor layer103 can be electrically connected to the source and drain electrode layers105aand105bwith the buffer layers106aand 106binterposed therebetween. Thus, an ohmic contact is formed between theoxide semiconductor layer103 and the source and drain electrode layers105aand105b;accordingly, electric characteristics of the thin film transistor can be stabilized.

The source and drain electrode layers105aand105bcan be formed using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium; an alloy material including any of the metal materials as its main component; or nitride including any of the metal materials as its component. The source and drain electrode layers105aand105bare preferably formed using a low-resistance conductive material such as aluminum or copper; however, since the low-resistance conductive material has disadvantages such as low heat resistance or a tendency to be corroded, it is preferably used in combination with a heat-resistant conductive material. As the heat-resistant conductive material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like is used.

For example, it is preferable that the source and drain electrode layers105aand105bare formed with a three-layer structure in which a first conductive layer and a third conductive layer are formed using titanium that is a heat-resistant conductive material, and a second conductive layer is formed using an aluminum alloy including neodymium that has low resistance. By employing such a structure for the source and drain electrode layers105aand105b,generation of a hillock can be reduced while low resistance of aluminum is utilized. Note that the structure of the source and drain electrode layers105aand105bis not limited thereto. Alternatively, a single-layer structure, a two-layer structure, or a structure of four or more layers may be employed.

Further, although the thin film transistor having an inverted staggered structure illustrated inFIGS. 1A and 1B has thegate electrode layer101 having a width in a channel direction, which is smaller than that of theoxide semiconductor layer103, the thin film transistor described in this embodiment is not limited thereto. As illustrated inFIGS. 13A and 13B, agate electrode layer201 having a width in a channel direction, which is larger than that of theoxide semiconductor layer103 may be used. Note thatFIG. 13A is a cross-sectional view taken along line A1-A2 inFIG. 13B. By employing such a structure, theoxide semiconductor layer103 can be protected from light by thegate electrode layer201. Thus, reliability of the thin film transistor can be improved. Note that except thegate electrode layer201, reference numerals of parts of the thin film transistor illustrated inFIGS. 13A and 13B are the same as those used for the thin film transistor illustrated inFIGS. 1A and 1B.

With the above structure, in a thin film transistor using an oxide semiconductor layer, buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, and source and drain electrode layers are formed over the buffer layers, which results in that the oxide semiconductor layer can be electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween, contact resistance between the oxide semiconductor layer and the source and drain electrode layers can be reduced, and electric characteristics can be stabilized. In addition, by subjecting the buffer layers to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, the buffer layers having higher conductivity than the oxide semiconductor layer can be obtained.

Note that the structure described in this embodiment can be combined with any of the structures described in other embodiments as appropriate.

Embodiment 2

In this embodiment, a manufacturing process of a display device including the thin film transistor described inEmbodiment 1 will be described with reference toFIGS. 2A to 2C,FIGS. 3A to 3C,FIGS. 4A and 4B,FIGS. 5A and 5B,FIGS. 6A to 6C,FIG. 7,FIG. 8,FIG. 9,FIG. 10, andFIG. 11.FIGS. 2A to 2C,FIGS. 3A to 3C,FIGS. 4A and 4B,FIGS. 5A and 5B, andFIGS. 6A to 6C are cross-sectional views andFIG. 7,FIG. 8,FIG. 9,FIG. 10, andFIG. 11 are plan views. Note that A1-A2 and B1-B2 ofFIGS. 2A to 2C,FIGS. 3A to 3C,FIGS. 4A and 4B,FIGS. 5A and 5B, andFIGS. 6A to 6C correspond to cross sections taken along lines A1-A2 and B1-B2 ofFIG. 7,FIG. 8,FIG. 9,FIG. 10, andFIG. 11, respectively.

First, asubstrate100 is prepared. As thesubstrate100, the following can be used: an alkali-free glass substrate manufactured by a fusion method or a floating method, such as a barium borosilicate glass substrate, an aluminoborosilicate glass substrate, or an aluminosilicate glass substrate; a ceramic substrate; a heat-resistant plastic substrate that can resist a process temperature of this manufacturing process; or the like. Alternatively, a metal substrate such as a stainless steel alloy substrate which is provided with an insulating film over the surface may also be used. As thesubstrate100, a substrate having a size of 320 mm×400 mm, 370 mm×470 mm, 550 mm×650 mm, 600 mm×720 mm, 680 mm×880 mm, 730 mm×920 mm, 1000 mm×1200 mm, 1100 mm×1250 mm, 1150 mm×1300 mm, 1500 mm×1800 mm, 1900 mm×2200 mm, 2160 mm×2460 mm, 2400 mm×2800 mm, 2850 mm×3050 mm, or the like can be used.

Further, an insulating film may be provided as a base film over thesubstrate100. The base film may be formed with a single layer or a stacked layer using any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a silicon nitride oxide film by a CVD method, a sputtering method, or the like. In the case where a substrate including mobile ions, such as a glass substrate, is used as thesubstrate100, a film including nitrogen such as a silicon nitride film or a silicon nitride oxide film is used as the base film, whereby the mobile ions can be prevented from entering the oxide semiconductor layer.

A conductive film to be a gate wiring including thegate electrode layer101, acapacitor wiring108, and afirst terminal121 is formed over the entire surface of thesubstrate100 using a sputtering method or a vacuum evaporation method. Next, a photolithography process is performed and a resist mask is formed. Then, unnecessary portions are removed by etching, whereby wirings and an electrode (the gate wiring including thegate electrode layer101, thecapacitor wiring108, and the first terminal121) are formed. At this time, etching is preferably performed so that at least an edge portion of thegate electrode layer101 can be tapered in order to prevent disconnection. A cross-sectional view at this stage is illustrated inFIG. 2A. Note that a top view at this stage corresponds toFIG. 7.

The gate wiring including thegate electrode layer101, thecapacitor wiring108, and thefirst terminal121 in a terminal portion can be formed with a single layer or a stacked layer using the conductive material described inEmbodiment 1.

Here, thegate electrode layer101 may be formed so that a width in a channel direction of thegate electrode layer101 is larger than that of theoxide semiconductor layer103 which is to be formed in a later step. By forming thegate electrode layer101 in this manner, such a thin film transistor illustrated inFIGS. 13A and 13B can be formed. In such a transistor illustrated inFIGS. 13A and 13B, theoxide semiconductor layer103 can be protected from light by thegate electrode layer201.

Next, agate insulating layer102 is formed over the entire surface of thegate electrode layer101, thecapacitor wiring108, and thefirst terminal121. Thegate insulating layer102 is formed to a thickness of 50 nm to 250 nm by a CVD method, a sputtering method, or the like.

For example, thegate insulating layer102 is formed to a thickness of 100 nm using a silicon oxide film by a CVD method or a sputtering method. Needless to say, thegate insulating layer102 is not limited to such a silicon oxide film, and other insulating films such as a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, or a tantalum oxide film may be used to form a single-layer structure or a stacked-layer structure.

Alternatively, thegate insulating layer102 can be formed using a silicon oxide layer by a CVD method using an organosilane gas. As the organosilane gas, a silicon-containing compound such as tetraethoxysilane (TEOS) (chemical formula: Si(OC₂H₅)₄), tetramethylsilane (TMS) (chemical formula: Si(CH₃)₄), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (chemical formula: SiH(OC₂H₅)₃), or trisdimethylaminosilane (chemical formula: SiH(N(CH₃)₂)₃) can be used.

Alternatively, thegate insulating layer102 may be formed using one kind of oxide, nitride, oxynitride, and nitride oxide of aluminum, yttrium, or hafnium; or a compound including at least two or more kinds thereof.

Note that in this specification, oxynitride refers to a substance that includes more oxygen atoms than nitrogen atoms and nitride oxide refers to a substance that includes more nitrogen atoms than oxygen atoms. For example, a silicon oxynitride film means a film that includes more oxygen atoms than nitrogen atoms, and oxygen, nitrogen, silicon, and hydrogen at concentrations of 50 at. % to 70 at. %, 0.5 at. % to 15 at. %, 25 at. % to 35 at. %, and 0.1 at. % to 10 at. %, respectively, when they are measured by RBS (Rutherford Backscattering Spectrometry) and HFS (Hydrogen Forward Scattering). Further, a silicon nitride oxide film means a film that includes more nitrogen atoms than oxygen atoms and, in the case where measurements are performed using RBS and HFS, includes oxygen, nitrogen, silicon, and hydrogen at concentrations of 5 at. % to 30 at. %, 20 at. % to 55 at. %, 25 at. % to 35 at. %, and 10 at. % to 30 at. %, respectively. Note that percentages of nitrogen, oxygen, silicon, and hydrogen fall within the ranges given above, where the total number of atoms contained in the silicon oxynitride film or the silicon nitride oxide film is defined as 100 at. %.

Note that before an oxide semiconductor film to be theoxide semiconductor layer103 is formed, reverse sputtering by which plasma is generated by introduction of an argon gas into a chamber where thesubstrate100 is placed is preferably performed to remove powder substances (also referred to as particles or dust) which are generated at the time of film formation and attached to a surface of the gate insulating layer. By reverse sputtering, planarity of the surface of thegate insulating layer102 can be improved. The reverse sputtering refers to a method in which an RF power source is used for application of voltage to a substrate side in an argon atmosphere and plasma is generated in the vicinity of the substrate to modify a surface. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or the like may be used. Alternatively, an argon atmosphere to which oxygen, N₂O, or the like is added may be used. Further alternatively, an argon atmosphere to which Cl₂, CF₄, or the like is added may be used. After the reverse sputtering treatment, a firstoxide semiconductor film111 is formed without exposure to the air, whereby dust or moisture can be prevented from attaching to an interface between thegate insulating layer102 and theoxide semiconductor layer103.

Next, the firstoxide semiconductor film111 to be theoxide semiconductor layer103 is formed over thegate insulating layer102 using a sputtering method in an atmosphere of an oxygen gas and a rare gas such as argon. Alternatively, the film formation may be performed in an atmosphere including only a rare gas such as argon without an oxygen gas. As the firstoxide semiconductor film111, the oxide semiconductor to be theoxide semiconductor layer103, which is described inEmbodiment 1, can be used. Specifically, for example, the film formation is performed by sputtering with use of an oxide semiconductor target including In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1) of 8 inches in diameter, under the conditions that the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, the flow rate ratio of Ar:O₂in a deposition gas is 30:15 (sccm), and the deposition temperature is room temperature. As for the target, Ga₂O₃and ZnO in a pellet state may be disposed on a disk of 8 inches in diameter which includes In₂O₃. Note that a pulse direct current (DC) power source is preferable because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be uniform. The thickness of the firstoxide semiconductor film111 is set to 10 nm to 300 nm, preferably 20 nm to 100 nm.

The target may include insulating oxide so that the firstoxide semiconductor film111 includes the insulating oxide. Here, as the insulating oxide, silicon oxide is preferable. Further, nitrogen may be added to the insulating oxide. When the firstoxide semiconductor film111 is formed, it is preferable to use an oxide semiconductor target including SiO₂at 0.1% by weight to 30% by weight inclusive, preferably at 1% by weight to 15% by weight inclusive.

The firstoxide semiconductor film111 includes insulating oxide such as silicon oxide, whereby the oxide semiconductor to be formed is made amorphous easily. In addition, by inclusion of insulating oxide such as silicon oxide, crystallization of theoxide semiconductor layer103 can be suppressed when heat treatment is performed on the oxide semiconductor in a later step.

A chamber used for forming the firstoxide semiconductor film111 may be the same or different from the chamber in which the reverse sputtering has been performed.

Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating film is formed, and a DC sputtering method is mainly used in the case where a metal film is formed.

In addition, there are a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering method, and a sputtering apparatus used for an ECR sputtering method in which plasma generated with use of microwaves is used without using glow discharge.

Furthermore, as a deposition method by sputtering, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, and a bias sputtering method in which voltage is also applied to a substrate during deposition.

Next, the firstoxide semiconductor film111 is subjected to heat treatment. The heat treatment is performed at 200° C. to 600° C. inclusive, preferably 250° C. to 500° C. inclusive. For example, the heat treatment is performed on thesubstrate100 set in a furnace in a nitrogen atmosphere at 350° C. for about one hour. By this heat treatment, rearrangement at an atomic level of the firstoxide semiconductor film111 is performed and distortion in a crystal structure, which interrupts carrier movement, can be released. Accordingly, mobility of theoxide semiconductor layer103 can be improved. In addition, this heat treatment enables reduction in the amount of hydrogen that forms excess carriers in the firstoxide semiconductor film111. At this time, in the case where the heat treatment is performed in a nitrogen atmosphere, the conductivity of the firstoxide semiconductor film111 can be increased. When theoxide semiconductor layer103 is used as an active layer of the thin film transistor, the thin film transistor having large on current is obtained. Here, an atmosphere including a nitrogen gas at 80 vol % to 100 vol % and a rare gas such as argon at 0 vol % to 20 vol % is preferably employed as the nitrogen atmosphere. Alternatively, when the heat treatment is performed in an air atmosphere, the conductivity of the firstoxide semiconductor film111 can be reduced. When theoxide semiconductor layer103 is used as the active layer of the thin film transistor, the thin film transistor having small off is obtained. As the air atmosphere, an atmosphere including an oxygen gas at 15 vol % to 25 vol % and a nitrogen gas at 75 vol % to 85 vol % is preferably employed. The atmosphere at the heat treatment may be changed in accordance with usage of the oxide semiconductor layer. Note that a cross-sectional view at this state isFIG. 2B.

Next, a secondoxide semiconductor film113 to be the buffer layers106aand106bis formed over the firstoxide semiconductor film111 using a sputtering method in an atmosphere of a rare gas such as argon. It is preferable that the secondoxide semiconductor film113 is formed using a sputtering method in an atmosphere of a rare gas such as argon and a nitrogen gas. As a result, the conductivity of the buffer layers106aand106bcan be increased. Alternatively, the film formation may be performed in an atmosphere of a rare gas such as argon and an oxygen gas under the condition that the flow rate of a rare gas such as argon is higher than that of an oxygen gas. As the secondoxide semiconductor film113, the oxide semiconductor to be the buffer layers106aand106b,which is described inEmbodiment 1, can be used. Specifically, for example, the film formation is performed by sputtering with use of an oxide semiconductor target including In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1) of 8 inches in diameter, under the conditions that the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, the flow rate ratio of Ar:N₂in a deposition gas is 35:5 (sccm), and the deposition temperature is room temperature. As the target, Ga₂O₃and ZnO in a pellet state may be disposed on a disk of 8 inches in diameter which includes In₂O₃. Note that a pulse direct current (DC) power source is preferable because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be uniform. The thickness of the secondoxide semiconductor film113 is set to 5 nm to 20 nm

A chamber used for forming the secondoxide semiconductor film113 may be the same or different from the chamber in which the firstoxide semiconductor film111 has been formed. In addition, in formation of the secondoxide semiconductor film113, the same sputtering apparatus as that for forming the firstoxide semiconductor film111 can be used.

Next, the secondoxide semiconductor film113 is subjected to reverse sputtering treatment. The reverse sputtering refers to a method in which an RF power source is used for application of voltage to a substrate side in an argon atmosphere and plasma is generated in the vicinity of the substrate to modify a surface. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or the like may be used. Alternatively, an argon atmosphere to which oxygen, N₂O, or the like is added may be used. Further alternatively, an argon atmosphere to which Cl₂, CF₄, or the like is added may be used. In addition, it is preferable that pressure inside the chamber is set to 10⁻⁵Pa or less and impurities inside the chamber are removed in advance. By the reverse sputtering of the secondoxide semiconductor film113, the conductivity of the second oxide semiconductor film113 (the buffer layers106aand106b) can be increased. For example, an argon gas is introduced at a pressure of 0.6 Pa and a gas flow rate of approximately 50 sccm into the chamber where thesubstrate100 is set and reverse sputtering treatment is performed for approximately 3 minutes. Here, since the reverse sputtering treatment greatly affects a surface of the secondoxide semiconductor film113, the secondoxide semiconductor film113 has a structure in which the conductivity is changed in stages or successively from the surface toward the substrate side in some cases.

Further, by the reverse sputtering treatment, dust attached to the surface of the secondoxide semiconductor film113 can be removed. Furthermore, by the reverse sputtering treatment, the flatness of the surface of the secondoxide semiconductor film113 can be improved.

Thesubstrate100 is preferably processed without being exposed to the air during the period from the formation of the secondoxide semiconductor film113 up to the reverse sputtering treatment. Note that a chamber used for the reverse sputtering treatment may be the same or different from the chamber in which the secondoxide semiconductor film113 has been formed. The reverse sputtering treatment may be performed after heat treatment in a nitrogen atmosphere performed next. A cross-sectional view at this stage isFIG. 2C. A portion above a dashed line in the secondoxide semiconductor film113 is a mark of the reverse sputtering treatment.

Next, the secondoxide semiconductor film113 is subjected to heat treatment in a nitrogen atmosphere. The heat treatment is performed at 200° C. to 600° C. inclusive, preferably 250° C. to 500° C. inclusive. For example, the heat treatment is performed on thesubstrate100 set in a furnace in a nitrogen atmosphere at 350° C. for about one hour. By the heat treatment on the oxide semiconductor in a nitrogen atmosphere, the conductivity of the oxide semiconductor can be increased. Accordingly, the conductivity of the secondoxide semiconductor film113 can be increased. Therefore, the conductivity of the buffer layers106aand106bcan be improved. At this time, by subjecting the secondoxide semiconductor film113 to the heat treatment in a nitrogen atmosphere as described above, the conductivity of the secondoxide semiconductor film113 can be increased. Here, an atmosphere including a nitrogen gas at 80 vol % to 100 vol % and a rare gas such as argon at 0 vol % to 20 vol % is preferably employed as the nitrogen atmosphere. A cross-sectional view at this stage isFIG. 3A. The heat treatment in a nitrogen atmosphere progresses from the surface toward the substrate side of the secondoxide semiconductor film113. Therefore, the second oxide semiconductor film113 (the buffer layers106aand106b) may have a structure in which the conductivity is changed in stages or successively from the surface toward the substrate side of the secondoxide semiconductor film113 in some cases. In particular, when time for the heat treatment in a nitrogen atmosphere is not enough, difference in the conductivity between the surface and the inside of the secondoxide semiconductor film113 becomes large in some cases.

Next, a photolithography process is performed and a resist mask is formed over the secondoxide semiconductor film113. Then, the firstoxide semiconductor film111 and the secondoxide semiconductor film113 are etched. An acid-based etchant can be used for an etchant for the etching. Here, unnecessary portions are removed by wet etching using a mixed solution of phosphoric acid, acetic acid, nitric acid, and pure water (referred to as an aluminum mixed acid) so that the firstoxide semiconductor film111 and the secondoxide semiconductor film113 have an island shape. Thus, theoxide semiconductor layer103 and thebuffer layer106 are formed. Theoxide semiconductor layer103 and thebuffer layer106 are etched to have a tapered edge, whereby disconnection of a wiring due to a step shape can be prevented. A cross-sectional view at this stage isFIG. 3B. A plan view at this stage corresponds toFIG. 8.

Note that etching here is not limited to wet etching and dry etching may also be employed. As an etching apparatus used for the dry etching, an etching apparatus using a reactive ion etching method (an RIE method), or a dry etching apparatus using a high-density plasma source such as ECR (electron cyclotron resonance) or ICP (inductively coupled plasma) can be used. As a dry etching apparatus by which uniform electric discharge can be obtained over a wide area as compared to an ICP etching apparatus, there is an ECCP (enhanced capacitively coupled plasma) mode etching apparatus in which an upper electrode is grounded, a high-frequency power source at 13.56 MHz is connected to a lower electrode, and further a low-frequency power source at 3.2 MHz is connected to the lower electrode. This ECCP mode etching apparatus can be applied, for example, even when a substrate of the tenth generation with a side of longer than 3 m is used.

Here, the resist mask is formed over the secondoxide semiconductor film113, whereby the resist mask can be prevented from being in direct contact with the firstoxide semiconductor film111, and impurities can be prevented from entering the first oxide semiconductor film111 (the oxide semiconductor layer103) from the resist mask. In the case of using O₂ashing or a resist stripper for removal of the resist mask, the secondoxide semiconductor film113 is formed over the firstoxide semiconductor film111; thus, contamination of the first oxide semiconductor film111 (the oxide semiconductor layer103) can be prevented.

Next, a photolithography process is performed and a resist mask is formed. Then, unnecessary portions of thegate insulating layer102 are removed by etching, whereby a contact hole reaching the wiring or the electrode layer which is formed from the same material as thegate electrode layer101 is formed. The contact hole is provided for direct connection with a conductive film to be formed later. For example, a contact hole is formed when a thin film transistor whose gate electrode layer is in direct contact with the source or drain electrode layer in the driver circuit portion is formed, or when a terminal that is electrically connected to a gate wiring of a terminal portion is formed.

Next, aconductive film112 formed from a metal material is formed using a sputtering method or a vacuum evaporation method over theoxide semiconductor layer103, thebuffer layer106, and thegate insulating layer102. A cross-sectional view at this stage isFIG. 3C.

Theconductive film112 can be formed with a single layer or a stacked layer using the conductive material described inEmbodiment 1. For example, in theconductive film112, a first conductive layer and a third conductive layer may be formed using titanium that is a heat-resistant conductive material, and a second conductive layer may be formed using an aluminum alloy including neodymium. Theconductive film112 has such a structure, whereby low resistance of aluminum is utilized and generation of hillocks can be reduced.

Next, a photolithography process is performed and a resistmask131 is formed over theconductive film112. Then, unnecessary portions are removed by etching, whereby the buffer layers106aand106b,source and drain electrode layers105aand105b,and aconnection electrode120 are formed. Wet etching or dry etching is employed as an etching method at this time. For example, when in theconductive film112, the first and third conductive layers are formed using titanium and the second conductive layer is formed using an aluminum alloy including neodymium, wet etching can be performed using a hydrogen peroxide solution, heated hydrochloric acid, or a nitric acid solution including ammonium fluoride as an etchant. For example, theconductive film112 including the first conductive layer, the second conductive layer, and the third conductive layer can be etched collectively with use of KSMF-240 (manufactured by Kanto Chemical Co., Inc.). A cross-sectional view at this stage isFIG. 4A. Note that, inFIG. 4A, since wet etching allows the layers to be etched isotropically, the edge portions of the source and drain electrode layers105aand105bare recessed from the resistmask131.

Through this etching step, an exposed region of theoxide semiconductor layer103 is partly etched, so that theoxide semiconductor layer103 includes a region which is between the buffer layers106aand106 and whose thickness is smaller than that of a region overlapping with the buffer layers106aand106b.

Further, in this photolithography process, asecond terminal122 formed from the same material as that of the source and drain electrode layers105aand105bis left in the terminal portion. Note that thesecond terminal122 is electrically connected to a source wiring (a source wiring including the source and drain electrode layers105aand105b).

In the terminal portion, theconnection electrode120 is directly connected to thefirst terminal121 in the terminal portion through the contact hole formed in the gate insulating film. Note that although not illustrated here, a source wiring or a drain wiring, and a gate electrode of the thin film transistor in the driver circuit are directly connected through the same steps as the above-described steps.

In the above photolithography process, two masks are necessary in a step where theoxide semiconductor layer103 and thebuffer layer106 is etched to have an island shape and a step where the source and drain electrode layers105aand105bare formed. However, with use of a resist mask having regions with plural thicknesses (typically, two different thicknesses) which is formed using a multi-tone (high-tone) mask, the number of resist masks can be reduced, resulting in a simplified process and lower costs. A photolithography process using a multi-tone mask is described with reference toFIGS. 6A to 6C.

First, starting from the state illustrated inFIG. 3A, aconductive film112 is formed over the secondoxide semiconductor film113. Then, a resistmask132 having regions with a plurality of different thicknesses is formed over theconductive film112 as illustrated inFIG. 6A by light exposure using a multi-tone (high-tone) mask with which transmitted light has a plurality of intensity. The resistmask132 has a small thickness in a region that overlaps with part of thegate electrode layer101. Next, the firstoxide semiconductor film111, the secondoxide semiconductor film113, and theconductive film112 are etched and processed into an island shape using the resistmask132, whereby theoxide semiconductor layer103, thebuffer layer106, aconductive layer115, and asecond terminal124 are formed. A cross-sectional view at this stage corresponds toFIG. 6A.

Next, the resistmask132 is subjected to ashing to form the resistmask131. As illustrated inFIG. 6B, the resistmask131 is reduced in area and thickness by ashing, and the region thereof having a thin thickness is removed.

Lastly, thebuffer layer106, theconductive layer115, and thesecond terminal124 are etched using the resistmask131 to form the buffer layers106aand106b,the source and drain electrode layers105aand105b,and thesecond terminal122. The resistmask131 is reduced in area and thickness, whereby end portions of theoxide semiconductor layer103, the buffer layers106aand106b,the source and drain electrode layers105aand105b,and thesecond terminal122 are also etched. Therefore, the width in a channel direction of each of theoxide semiconductor layer103 and the buffer layers106aand106bis the approximately the same as that of the source and drain electrode layers. In addition, a layer formed of the first oxide semiconductor film and the second oxide semiconductor film is formed below thesecond terminal122. A cross-sectional view at this stage corresponds toFIG. 6C. Note that after a protectiveinsulating layer107 is formed in a later step, thegate insulating layer102 and the protective insulatinglayer107 are etched to form a contact hole, whereby a transparent conductive film is formed to connect thefirst terminal121 and an FPC to each other.

Next, the resistmask131 is removed and then heat treatment is performed. The heat treatment is performed at 200° C. to 600° C. inclusive, preferably 250° C. to 500° C. inclusive. For example, the heat treatment is performed on thesubstrate100 set in a furnace in a nitrogen atmosphere at 350° C. for approximately one hour. By this heat treatment, rearrangement at an atomic level of theoxide semiconductor layer103 which is exposed and located between the buffer layers106aand106bis performed and distortion in a crystal structure, which interrupts carrier movement, is released. Accordingly, mobility of theoxide semiconductor layer103 can be improved. In addition, this heat treatment enables reduction in the amount of hydrogen that forms excess carriers in theoxide semiconductor layer103. At this time, in the case where the heat treatment is performed in a nitrogen atmosphere, the conductivity of theoxide semiconductor layer103 can be increased. When theoxide semiconductor layer103 is used as the active layer of the thin film transistor, the thin film transistor having large on current is obtained. Here, an atmosphere including a nitrogen gas at 80 vol % to 100 vol % and a rare gas such as argon at 0 vol % to 20 vol % is preferably employed for the nitrogen atmosphere. Alternatively, heat treatment is performed in an air atmosphere, the conductivity of theoxide semiconductor layer103 can be reduced. When theoxide semiconductor layer103 is used as the active layer of the thin film transistor, the thin film transistor having small off current is obtained. As the air atmosphere, an atmosphere including an oxygen gas at 15 vol % to 25 vol % and a nitrogen gas at 75 vol % to 85 vol % is preferably employed. The atmosphere at the heat treatment may be changed in accordance with usage of the oxide semiconductor layer. A cross-sectional view at this stage isFIG. 4B. A plan view at this stage corresponds toFIG. 9.

Alternatively, at this time, the heat treatment is performed in an oxygen atmosphere, high-resistance regions are formed in exposed parts of the buffer layers106aand106b.

In this manner, the buffer layers106aand106bhaving higher conductivity than theoxide semiconductor layer103 are formed over theoxide semiconductor layer103 and the source and drain electrode layers105aand105bare formed over the

buffer layer

106aand106b,which results in that theoxide semiconductor layer103 and the source and drain electrode layers105aand105bare electrically connected to each other with the buffer layers106aand106binterposed therebetween. Thus, an ohmic contact is formed between theoxide semiconductor layer103 and the source and drain electrode layers105aand105band the contact resistance is reduced; accordingly electric characteristics of the thin film transistor can be stabilized. In addition, by subjecting the buffer layers106aand106bto reverse sputtering treatment and heat treatment in a nitrogen atmosphere, the buffer layers106aand106bcan have higher conductivity than theoxide semiconductor layer103.

Alternatively, the firstoxide semiconductor film111 is subjected to heat treatment, and after formation of the buffer layers106aand106band the source and drain

layers

105aand105b,theoxide semiconductor layer103 is subjected to heat treatment, whereby rearrangement at an atomic level of theoxide semiconductor layer103 is performed and electric characteristics of the thin film transistor whose active layer is theoxide semiconductor layer103 can be improved.

Through the above process, athin film transistor170 can be manufactured in which theoxide semiconductor layer103 serves as a channel formation region and the buffer layers106aand106bhaving higher conductivity than theoxide semiconductor layer103 are formed over theoxide semiconductor layer103.

Next, the protective insulatinglayer107 and aresin layer133 are formed to cover thethin film transistor170. First, the protective insulatinglayer107 is formed. A silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or the like obtained using a PCVD method, a sputtering method, or the like can be used for the protective insulatinglayer107. In particular, it is preferable to form a silicon nitride film with a high-density plasma apparatus. In the case of using a high-density plasma apparatus, the protective insulatinglayer107 can be formed dense as compared to the case of using a PCVD method. Such a protectiveinsulating layer107 can prevent moisture, hydrogen ions, OH⁻, and the like from entering theoxide semiconductor layer103 and the buffer layers106aand106b.

Next, a photolithography process is performed and a resist mask is formed. Then, the protective insulatinglayer107 is etched to form acontact hole125 reaching the source or drainelectrode layer105b.In addition, acontact hole126 reaching theconnection electrode120 and acontact hole127 reaching thesecond terminal122 are also formed by this etching.

Next, theresin layer133 is formed over the protective insulatinglayer107 in a pixel portion of the display device. Theresin layer133 is formed with a thickness ranging from 0.5 μm to 3 μm using polyimide, acrylic, polyamide, polyimideamide, resist, or benzocyclobutene, which is a photosensitive or non photosensitive organic material; or a stack of any of these materials. When photosensitive polyimide is deposited using a coating method, the number of steps can be reduced. Theresin layer133 is formed in the pixel portion of the display device through exposure to light, development, and baking; at this time, theresin layer133 is not formed in a portion overlapping with thecontact hole125 and a portion overlapping with thecapacitor wiring108. Theresin layer133 can prevent moisture, hydrogen, and the like from entering theoxide semiconductor layer103 and the buffer layers106aand106b.In addition, theresin layer133 enables formation of a planar pixel electrode which is provided over theresin layer133.

Next, a transparent conductive film is formed. The transparent conductive film is formed from indium oxide (In₂O₃), indium oxide-tin oxide alloy (In₂O₃—SnO₂, abbreviated to ITO), or the like using a sputtering method, a vacuum evaporation method, or the like. Such a material is etched with a hydrochloric acid-based solution. However, since a residue is easily generated particularly in etching ITO, indium oxide-zinc oxide alloy (In₂O₃—ZnO) may be used to improve etching processability.

Next, a photolithography process is performed and a resist mask is formed. Then, unnecessary portions are removed by etching to form apixel electrode layer110.

In this photolithography process, a storage capacitor is formed with thecapacitor wiring108 and thepixel electrode layer110, in which thegate insulating layer102 and the protective insulatinglayer107 in the capacitor portion are used as dielectrics.

In addition, in this photolithography process, thefirst terminal121 and thesecond terminal122 are covered with the resist mask, and transparent

conductive films

128 and129 formed in the terminal portion are left. The transparent

conductive films

128 and129 function as electrodes or wirings connected to an FPC. The transparentconductive film128 formed over theconnection electrode120 which is directly connected to thefirst terminal121 is a connection terminal electrode which functions as an input terminal of the gate wiring. The transparentconductive film129 formed over thesecond terminal122 is a connection terminal electrode which functions as an input terminal of the source wiring.

Subsequently, the resist mask is removed. A cross-sectional view at this stage isFIG. 5A. Note that a plan view at this stage corresponds toFIG. 10.

Although the protective insulatinglayer107 is formed and theresin layer133 is formed thereover in this embodiment, this embodiment is not limited thereto. As illustrated inFIG. 5B, after theresin layer133 is formed so as to cover thetransistor170, the protective insulatinglayer107 may be formed over theresin layer133. When the protective insulatinglayer107 and theresin layer133 are formed in this order, theresin layer133 can protect theoxide semiconductor layer103 and the buffer layers106aand106bfrom plasma damage which is caused in formation of the protective insulatinglayer107.

FIGS.12A1 and12A2 are respectively a cross-sectional view and a plan view of a gate wiring terminal portion at this stage. FIG.12A1 is a cross-sectional view taken along line C1-C2 of FIG.12A2. In FIG.12A1, a transparentconductive film155 formed over a protectiveinsulating layer154 is a connection terminal electrode which functions as an input terminal Furthermore, in FIG.12A1, in the terminal portion, thefirst terminal151 formed from the same material as the gate wiring and aconnection electrode153 formed from the same material as the source wiring are overlapped with each other with agate insulating layer152 interposed therebetween and are electrically connected. Further, theconnection electrode153 and the transparentconductive film155 are in direct contact with each other and are electrically connected through a contact hole formed in the protective insulatinglayer154.

Further, FIGS.12B1 and12B2 are respectively a cross-sectional view and a plan view of a source wiring terminal portion. FIG.12B1 is a cross-sectional view taken along line D1-D2 of FIG.12B2. In FIG.12B1, the transparentconductive film155 formed over the protective insulatinglayer154 is a connection terminal electrode which functions as an input terminal. Furthermore, in FIG.12B1, in the terminal portion, anelectrode156 formed from the same material as the gate wiring is located below and overlapped with asecond terminal150, which is electrically connected to the source wiring, with thegate insulating layer152 interposed therebetween. Theelectrode156 is not electrically connected to thesecond terminal150, and a capacitor to prevent noise or static electricity can be formed when the potential of theelectrode156 is set to a potential different from that of thesecond terminal150, such as floating, GND, or 0 V. Thesecond terminal150 is electrically connected to the transparentconductive film155 through the protective insulatinglayer154.

A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. Also in the terminal portion, the first terminal at the same potential as the gate wiring, the second terminal at the same potential as the source wiring, the third terminal at the same potential as the capacitor wiring, and the like are each arranged in plurality. The number of each of the terminals may be any number, and the number of the terminals may be determined by a practitioner as appropriate.

Thus, a pixel thin film transistor portion including thethin film transistor170 that is a bottom-gate n-channel thin film transistor, and a storage capacitor can be completed. By arranging the thin film transistor and the storage capacitor in each pixel of a pixel portion in which pixels are arranged in a matrix form, one of substrates for manufacturing an active matrix display device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the case of manufacturing an active matrix liquid crystal display device, an active matrix substrate and a counter substrate provided with a counter electrode are bonded to each other with a liquid crystal layer interposed therebetween. Note that a common electrode electrically connected to the counter electrode on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. The fourth terminal is provided so that the common electrode is set to a fixed potential such as GND or 0 V.

Further, this embodiment is not limited to a pixel structure ofFIG. 10, and an example of a plan view different fromFIG. 10 is illustrated inFIG. 11.FIG. 11 illustrates an example in which a capacitor wiring is not provided and a storage capacitor is formed with a pixel electrode layer and a gate wiring of an adjacent pixel which overlap with each other with a protective insulating layer and a gate insulating layer interposed therebetween. In this case, the capacitor wiring and the third terminal connected to the capacitor wiring can be omitted. Note that inFIG. 11, portions similar to those inFIG. 10 are denoted by the same reference numerals.

In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form are driven to form a display pattern on a screen. Specifically, voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, so that a liquid crystal layer provided between the pixel electrode and the counter electrode is optically modulated and this optical modulation is recognized as a display pattern by an observer.

In displaying moving images, a liquid crystal display device has a problem that a long response time of liquid crystal molecules themselves causes afterimages or blurring of moving images. In order to improve the moving-image characteristics of a liquid crystal display device, a driving method called black insertion is employed in which black is displayed on the whole screen every other frame period.

Further, there is another driving method which is so-called double-frame rate driving. In the double-frame rate driving, a vertical synchronizing frequency is set 1.5 times or more, preferably 2 times or more as high as a usual vertical synchronizing frequency, whereby moving image characteristics are improved.

Further alternatively, in order to improve the moving-image characteristics of a liquid crystal display device, a driving method may be employed, in which a plurality of LEDs (light-emitting diodes) or a plurality of EL light sources are used to form a surface light source as a backlight, and each light source of the surface light source is independently driven in a pulsed manner in one frame period. As the surface light source, three or more kinds of LEDs may be used and an LED emitting white light may be used. Since a plurality of LEDs can be controlled independently, the light emission timing of LEDs can be synchronized with the timing at which a liquid crystal layer is optically modulated. According to this driving method, LEDs can be partly turned off; therefore, an effect of reducing power consumption can be obtained particularly in the case of displaying an image having a large part on which black is displayed.

By combining these driving methods, the display characteristics of a liquid crystal display device, such as moving-image characteristics, can be improved as compared to those of conventional liquid crystal display devices.

The n-channel transistor obtained in this embodiment includes an oxide semiconductor layer for a channel formation region and has excellent dynamic characteristics; thus, any of these driving methods can be combined with each other.

In manufacturing a light-emitting display device, one electrode (also referred to as a cathode) of an organic light-emitting element is set to a low power supply potential such as GND or 0 V; thus, a terminal portion is provided with a fourth terminal for setting the cathode to a low power supply potential such as GND or 0 V. Also in manufacturing a light-emitting display device, a power supply line is provided in addition to a source wiring and a gate wiring. Accordingly, the terminal portion is provided with a fifth terminal electrically connected to the power supply line.

As described above, in the thin film transistor using the oxide semiconductor layer, the buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, and the source and drain electrode layers are formed over the buffer layers. Accordingly, the oxide semiconductor layer and the source and drain electrode layers can be electrically connected to each other with the buffer layers interposed therebetween, contact resistance between the oxide semiconductor layer and the source and drain electrode layers can be reduced, and electric characteristics can be stabilized. In addition, by subjecting the buffer layers to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, the buffer layers having higher conductivity than the oxide semiconductor layer can be obtained.

Embodiment 3

In this embodiment, an inverter circuit using two bottom-gate thin film transistors described inEmbodiment 1 will be described with reference toFIGS. 14A to 14C.

A driver circuit for driving a pixel portion is formed using an inverter circuit, a capacitor, a resistor, and the like. When the inverter circuit is formed using two n-channel TFTs in combination, there are an inverter circuit having a combination of an enhancement type transistor and a depletion type transistor (hereinafter, referred to as an EDMOS circuit) and an inverter circuit having a combination of two enhancement type TFTs (hereinafter, referred to as an EEMOS circuit). Note that an n-channel TFT whose threshold voltage is positive is referred to as an enhancement type transistor, and an n-channel TFT whose threshold voltage is negative is referred to as a depletion type transistor, throughout this specification.

The pixel portion and the driver circuit are formed over one substrate. In the pixel portion, on and off of voltage application to a pixel electrode are switched by enhancement type transistors arranged in matrix. The enhancement type transistors arranged in the pixel portion include an oxide semiconductor.

A cross-sectional structure of the inverter circuit of the driver circuit (EDMOS circuit) is illustrated inFIG. 14A. Note that inFIG. 14A, the inverted staggered thin film transistor illustrated inFIGS. 1A and 1B is used as a firstthin film transistor430aand a secondthin film transistor430b.However, a thin film transistor that can be used for the inverter circuit described in this embodiment is not limited to this structure.

In the firstthin film transistor430aillustrated inFIG. 14A, a firstgate electrode layer401ais provided over asubstrate400, agate insulating layer402 is provided over the firstgate electrode layer401a,a firstoxide semiconductor layer403ais provided over thegate insulating layer402, first buffer layers404aand404bare provided over the firstoxide semiconductor layer403a,and afirst wiring405aand asecond wiring405bare provided over the first buffer layers404aand404b.The firstoxide semiconductor layer403ais electrically connected to thefirst wiring405aand thesecond wiring405bwith the first buffer layers404aand404binterposed therebetween. Similarly, in the secondthin film transistor430b,a secondgate electrode layer401bis provided over thesubstrate400, thegate insulating layer402 is provided over the secondgate electrode layer401b,a secondoxide semiconductor layer403bis provided over thegate insulating layer402, second buffer layers406aand406bare provided over the secondoxide semiconductor layer403b,and thesecond wiring405band athird wiring405care provided over the second buffer layers406aand406b.The secondoxide semiconductor layer403bis electrically connected to thesecond wiring405band thethird wiring405cwith the second buffer layers406aand406binterposed therebetween. Here, thesecond wiring405bis directly connected to the secondgate electrode layer401bthrough acontact hole414 formed in thegate insulating layer402. Note that as for the structures and materials of the respective portions, the thin film transistor described inEmbodiment 1 is to be referred to.

Thefirst wiring405ais a power supply line at a ground potential (a ground power supply line). This power supply line at a ground potential may be a power supply line to which a negative voltage VDL is applied (a negative power supply line). Thethird wiring405cis a power supply line to which a positive voltage V_DDis applied (a positive power supply line).

As illustrated inFIG. 14A, thesecond wiring405bwhich is electrically connected to both thefirst buffer layer404band thesecond buffer layer406ais directly connected to the secondgate electrode layer401bof the secondthin film transistor430bthrough thecontact hole414 formed in thegate insulating layer402. By the direct connection, favorable contact can be obtained, which leads to a reduction in contact resistance. Since thesecond wiring405bcan be directly connected to the secondgate electrode layer401bat the same time as formation of thesecond wiring405b,favorable contact can be obtained without influence of heat treatment after formation of thesecond wiring405b.Further, in comparison with the case where the secondgate electrode layer401band thesecond wiring405bare connected to each other through another conductive film, for example, a transparent conductive film, reduction in the number of contact holes and reduction in an area occupied by the driver circuit due to the reduction in the number of contact holes can be achieved.

Further,FIG. 14C is a plan view of the inverter circuit (EDMOS circuit) of the driver circuit. InFIG. 14C, a cross section taken along the chain line Z1-Z2 corresponds toFIG. 14A.

Further, an equivalent circuit of the EDMOS circuit is illustrated inFIG. 14B. The circuit connection ofFIGS. 14A and 14C corresponds to that illustrated inFIG. 14B. An example in which the firstthin film transistor430ais an enhancement type n-channel transistor and the secondthin film transistor430bis a depletion type n-channel transistor is illustrated.

In order to manufacture an enhancement type n-channel transistor and a depletion type n-channel transistor over one substrate, for example, the first buffer layers404aand404band the firstoxide semiconductor layer403aare formed using materials or conditions which are different from those for the second buffer layers406aand406band the secondoxide semiconductor layer403b.Alternatively, an EDMOS circuit may be formed in such a manner that gate electrodes are provided over and under the oxide semiconductor layer to control the threshold value and a voltage is applied to the gate electrodes so that one of the TFTs is normally on while the other TFT is normally off.

Alternatively, without being limited to the EDMOS circuit, an EEMOS circuit can be manufactured in such a manner that the firstthin film transistor430aand the secondthin film transistor430bare enhancement type n-channel transistors. In that case, thethird wiring405cand the secondgate electrode layer401bare connected to each other instead of the connection between thesecond wiring405band the secondgate electrode layer401b.

In the thin film transistor used in this embodiment, the buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, and the source and drain electrode layers are formed over the buffer layers. Accordingly, the oxide semiconductor layer can be electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween, contact resistance between the oxide semiconductor layer and the source and drain electrode layers can be reduced, and electric characteristics can be stabilized. Accordingly, circuit characteristics of the inverter circuit described in this embodiment can be improved.

With use of the inverter circuit described in this embodiment for a driver circuit portion, a display device having stable electric characteristics and high reliability can be provided.

Embodiment 4

In this embodiment, a thin film transistor having a structure different from the thin film transistors described inEmbodiment 1 will be described with reference toFIGS. 32A and 32B.

A thin film transistor having a bottom gate structure of this embodiment is illustrated inFIGS. 32A and 32B.FIG. 32A is a cross-sectional view, andFIG. 32B is a plan view.FIG. 32A is a cross-sectional view taken along line A1-A2 ofFIG. 32B.

The high-conductiveoxide semiconductor layer300 is formed using the same material as that for the buffer layers106aand106b.In a manner similar to the case of the buffer layers106aand106b,the high-conductiveoxide semiconductor layer300 can be formed using a non-single-crystal film formed from an In—Ga—Zn—O-based, In—Sn—Zn—O-based, Ga—Sn—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, In—Sn—O-based, Ga—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor. In addition, the high-conductiveoxide semiconductor layer300 is preferably formed using a non-single-crystal film formed from an In—Ga—Zn—O—N-based, Ga—Zn—O—N-based, Zn—O—N-based, or Sn—Zn—O—N-based oxide semiconductor, which includes nitrogen. In addition, the non-single-crystal film may include insulating oxide such as silicon oxide.

It is preferable that the high-conductiveoxide semiconductor layer300 is formed using a sputtering method in an atmosphere of a nitrogen gas and a rare gas such as argon in a manner similar to the case of the buffer layers106aand106b.When the conductiveoxide semiconductor layer300 is formed in such a manner, conductivity of the high-conductiveoxide semiconductor layer300 can be increased. In addition, when reverse sputtering treatment and heat treatment in a nitrogen atmosphere are performed on the formed oxide semiconductor film, the conductivity of the high-conductiveoxide semiconductor layer300 can be further increased. Here, an atmosphere including a nitrogen gas at 80 vol % to 100 vol % and a rare gas such as argon at 0 vol % to 20 vol % is preferably employed as the nitrogen atmosphere.

Further, the high-conductiveoxide semiconductor layer300 may have a structure in which the conductivity is changed in stages or successively from the surface toward the substrate side of the high-conductiveoxide semiconductor layer300 in some cases.

The high-conductiveoxide semiconductor layer300 includes at least an amorphous component. A crystal grain (a nanocrystal) is included in an amorphous structure in some cases. The crystal grains (nanocrystals) each have a diameter of approximately 1 nm to 10 nm, typically, approximately 2 nm to 4 nm Note that the crystal state is evaluated by X-ray diffraction (XRD) analysis.

It is preferable that the thickness of an oxides semiconductor film for the high-conductiveoxide semiconductor layer300 is 5 nm to 20 nm Needless to say, when the film includes a crystal grain, the diameter of the crystal grain does not exceed the thickness of the film.

By employing a stacked-layer structure of the high-conductiveoxide semiconductor layer300 and theoxide semiconductor layer103 for an active layer of the thin film transistor, drain current flows mainly through the high-conductiveoxide semiconductor layer300, which has higher conductivity, when the thin film transistor is turned on, and the field effect mobility can be increased. Further, drain current flows mainly through the region having a smaller thickness of theoxide semiconductor layer103 between the buffer layers106aand106bwhen the thin film transistor is turned off; thus, off current can be prevented from flowing through the high-conductiveoxide semiconductor layer300, which has high conductivity, whereby increase in off current can be suppressed.

Note that, as for a structure and materials of parts other than the high-conductiveoxide semiconductor layer300 of the thin film transistor of this embodiment,Embodiment 1 is to be referred to.

A manufacturing process of the thin film transistor described this embodiment is substantially similar to the manufacturing process of the thin film transistor described inEmbodiment 2. First, steps up to formation of thegate insulating layer102 are performed in the method described inEmbodiment 2.

Next, a high-conductive oxide semiconductor film for forming the high-conductiveoxide semiconductor layer300 is formed over thegate insulating layer102. The high-conductive oxide semiconductor film is formed in a manner similar to that of the secondoxide semiconductor film113 for forming the buffer layers106aand106bin an atmosphere of a rare gas such as argon with use of a sputtering method. It is preferable that the high-conductive oxide semiconductor film is formed using a sputtering method in an atmosphere of a rare gas such as argon and a nitrogen gas. Accordingly, the conductivity of the high-conductiveoxide semiconductor layer300 can be increased. Alternatively, the film formation may be performed in an atmosphere of a rare gas such as an argon gas and an oxygen gas under the condition that the flow rate of a rare gas such as an argon gas is higher than that of an oxygen gas. As the high-conductive oxide semiconductor film, the oxide semiconductor to be the high-conductiveoxide semiconductor layer300 can be used. The target may include insulating oxide so that the high-conductive oxide semiconductor film includes the insulating oxide. Here, as the insulating oxide, silicon oxide is preferable. Further, nitrogen may be added to the insulating oxide. As a specific example, the formation method of the secondoxide semiconductor film113 described inEmbodiment 2 is to be referred to.

Next, the high-conductive oxide semiconductor film is subjected to reverse sputtering treatment. Note that the reverse sputtering is a method in which voltage is applied to a substrate side in an argon atmosphere with use of an RF power source without applying voltage to a target side, so that plasma is generated to modify the surface of the substrate. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or the like may be used. Alternatively, an argon atmosphere to which oxygen, N₂O, or the like is added may be used. Further alternatively, an argon atmosphere to which Cl₂, CF₄, or the like is added may be used. Further, the pressure in the chamber is preferably set to 10⁻⁵Pa or lower in advance so that an impurity in the chamber is removed. For example, an argon gas is introduced at a pressure of 0.6 Pa and a gas flow rate of approximately 50 sccm into the chamber where thesubstrate100 is set and reverse sputtering treatment is performed for approximately 3 minutes.

Next, the high-conductive oxide semiconductor film is subjected to heat treatment in a nitrogen atmosphere. The heat treatment is performed at 200° C. to 600° C. inclusive, preferably 250° C. to 500° C. inclusive. For example, the heat treatment is performed on thesubstrate100 set in a furnace in a nitrogen atmosphere at 350° C. for approximately one hour. Here, an atmosphere including a nitrogen gas at 80 vol % to 100 vol % and a rare gas such as argon at 0 vol % to 20 vol % is preferably employed as the nitrogen atmosphere. The heat treatment in a nitrogen atmosphere progresses from the surface toward the inside of the high-conductive oxide semiconductor film. Therefore, the high-conductive oxide semiconductor film (the high-conductive oxide semiconductor layer300) may have a structure in which the conductivity is changed in stages or successively from the surface toward the substrate side of the high-conductive oxide semiconductor film in some cases. In particular, when time for the heat treatment in a nitrogen atmosphere is not enough, the conductivity of the high-conductive oxide semiconductor film is not increased sufficiently in some cases.

Next, a firstoxide semiconductor film111 is formed over the high-conductive oxide semiconductor film. Steps after this step are performed in accordance with the manufacturing steps of the thin film transistor described inEmbodiment 2 to manufacture a thin film transistor. Note that the high-conductiveoxide semiconductor layer300 is formed in such a manner that the high-conductive oxide semiconductor film is etched at the same time as etching of the firstoxide semiconductor film111 and the secondoxide semiconductor film113.

In the thin film transistor used in this embodiment, the buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, and the source and drain electrode layers are formed over the buffer layers. Accordingly, the oxide semiconductor layer and the source and drain electrode layers can be electrically connected to each other with the buffer layers interposed therebetween, contact resistance between the oxide semiconductor layer and the source and drain electrode layers can be reduced, and electric characteristics can be stabilized. In addition, the buffer layers are subjected to reverse sputtering and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer can be obtained. By employing the stacked-layer structure of the high-conductiveoxide semiconductor layer300 and theoxide semiconductor layer103 for the active layer of the thin film transistor, the conductivity can be increased when the thin film transistor is turned on, and increase of off current can be suppressed when the thin film transistor is turned off.

Embodiment 5

In this embodiment, an example will be described below, in which at least part of a driver circuit and a thin film transistor arranged in a pixel portion are formed over one substrate in a display device which is one example of a semiconductor device.

The thin film transistor to be arranged in the pixel portion is formed in accordance withEmbodiment 2. Further, the thin film transistor described in any ofEmbodiments 1 to 4 is an n-channel TFT, and thus part of a driver circuit that can include an n-channel TFT among driver circuits is formed over the same substrate as the thin film transistor of the pixel portion.

FIG. 15A illustrates an example of a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device. The display device illustrated inFIG. 15A includes, over asubstrate5300, apixel portion5301 having a plurality of pixels each provided with a display element, a scan-line driver circuit5302 that selects each pixel, and a signalline driver circuit5303 that controls a video signal input to a selected pixel.

Thepixel portion5301 is connected to the signalline driver circuit5303 by a plurality of signal lines S1 to Sm (not shown) which extend in a column direction from the signalline driver circuit5303, and to the scanline driver circuit5302 by a plurality of scan lines G1 to Gn (not shown) that extend in a row direction from the scanline driver circuit5302. Thepixel portion5301 includes a plurality of pixels (not illustrated) arranged in a matrix form by the signal lines S1 to Sm and the scan lines G1 to Gn. Then, each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scan line Gi (any one of the scan lines G1 to Gn).

In addition, the thin film transistor described in any ofEmbodiments 1 to 4 is an n-channel TFT, and a signal line driver circuit including the n-channel TFT is described with reference toFIG. 16.

The signal-line driver circuit illustrated inFIG. 16 includes adriver IC5601, switch groups5602_1 to5602_M, afirst wiring5611, asecond wiring5612, athird wiring5613, and wirings5621_1 to5621_M. Each of the switch groups5602_1 to5602_M is connected to thefirst wiring5611, thesecond wiring5612, and thethird wiring5613, and the wirings5621_1 to5621_M are connected to the switch groups5602_1 to5602_M, respectively.

Thedriver IC5601 is connected to thefirst wiring5611, thesecond wiring5612, thethird wiring5613, and the wirings5621_1 to5621_M. Each of the switch groups5602_1 to5602_M is connected to thefirst wiring5611, thesecond wiring5612, and thethird wiring5613, and the wirings5621_1 to5621_M are connected to the switch groups5602_1 to5602_M, respectively. Each of the wirings5621_1 to5621_M is connected to three signal lines (a signal line Sm-2, a signal line Sm-1, and a signal line Sm (m=3M)) via the firstthin film transistor5603a,the secondthin film transistor5603b,and the thirdthin film transistor5603c.For example, the wiring5621_J of the J-th column (one of the wirings5621_1 to5621_M) is connected to a signal line Sj-2, a signal line Sj-1, and a signal line Sj (j=3J) via the firstthin film transistor5603a,the secondthin film transistor5603b,and the thirdthin film transistor5603cwhich are included in the switch group5602_J.

A signal is input to each of thefirst wiring5611, thesecond wiring5612, and thethird wiring5613.

Note that thedriver IC5601 is preferably formed using a single crystal semiconductor. Further, the switch groups5602_1 to5602_M are preferably formed over the same substrate as the pixel portion is. Therefore, thedriver IC5601 and the switch groups5602_1 to 5602_M are preferably connected through an FPC or the like. Alternatively, thedriver IC5601 may be formed by providing a single crystal semiconductor layer over the same substrate as the pixel portion using a method such as bonding.

Next, operation of the signal-line driver circuit illustrated inFIG. 16 is described with reference to a timing chart ofFIG. 17.FIG. 17 illustrates the timing chart where the scan line Gi in the i-th row is selected. A selection period of the scan line Gi of the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal-line driver circuit inFIG. 16 operates similarly to that inFIG. 17 even when a scan line of another row is selected.

Note that the timing chart ofFIG. 17 illustrates the case where the wiring5621_J in the J-th column is connected to the signal line Sj-2, the signal line Sj-1, and the signal line Sj through the firstthin film transistor5603a,the secondthin film transistor5603b,and the thirdthin film transistor5603c.

The timing chart ofFIG. 17 illustrates timing when the scan line Gi in the i-th row is selected, timing5703aof on/off of the firstthin film transistor5603a,

timing

5703bof on/off of the secondthin film transistor5603b,

timing

5703cof on/off of the thirdthin film transistor5603c,and a signal5721_J input to the wiring5621_J in the J-th column.

In the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, different video signals are input to the wirings5621_1 to5621_M. For example, a video signal input to the wiring5621_J in the first sub-selection period T1 is input to the signal line Sj-2, a video signal input to the wiring5621_J in the second sub-selection period T2 is input to the signal line Sj-1, and a video signal input to the wiring5621_J in the third sub-selection period T3 is input to the signal line Sj. In addition, the video signals input to the wiring5621_J in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 are denoted by Data_j-2, Data_j-1, and Data_j.

As described above, in the signal-line driver circuit ofFIG. 16, one gate selection period is divided into three; thus, video signals can be input to three signal lines through one wiring5621 in one gate selection period. Therefore, in the signal-line driver circuit ofFIG. 16, the number of connections between the substrate provided with thedriver IC5601 and the substrate provided with the pixel portion can be reduced to approximately one third of the number of signal lines. The number of connections is reduced to approximately one third of the number of signal lines, so that the reliability, yield, and the like of the signal-line driver circuit ofFIG. 16 can be improved.

Note that there are no particular limitations on the arrangement, the number, a driving method, and the like of the thin film transistors, as long as one gate selection period is divided into a plurality of sub-selection periods and video signals are input to a plurality of signal lines from one wiring in the respective sub-selection periods as illustrated inFIG. 17.

For example, when video signals are input to three or more signal lines from one wiring in three or more sub-selection periods, it is only necessary to add a thin film transistor and a wiring for controlling the thin film transistor. Note that when one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes shorter. Therefore, one gate selection period is preferably divided into two or three sub-selection periods.

As another example, as shown in a timing chart ofFIG. 18, one selection period may be divided into a pre-charge period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. Further, the timing chart ofFIG. 18 shows timing when the scan line Gi in the i-th row is selected, timing5803aof on/off of the firstthin film transistor5603a,

timing

5803bof on/off of the secondthin film transistor5603b,

timing

As described above, in the signal-line driver circuit ofFIG. 16, to which the timing chart ofFIG. 18 is applied, a signal line can be pre-charged by providing a pre-charge selection period before sub-selection periods. Thus, a video signal can be written to a pixel at a high speed. Note that portions inFIG. 18 similar to those inFIG. 17 are denoted by the same reference numerals, and detailed description of the same portions and portions having similar functions is omitted.

Further, a structure of a scan line driver circuit is described. The scan line driver circuit includes a shift register and a buffer. Additionally, the scan line driver circuit may include a level shifter in some cases. In the scan line driver circuit, when the clock signal (CLK) and the start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scan line. Gate electrodes of transistors in pixels of one line are connected to the scan line. Since the transistors in the pixels of one line have to be turned on all at once, a buffer which can supply a large current to a thin film transistor in each pixel is used.

One mode of the shift register used for part of the scan-line driver circuit is described with reference toFIG. 19 andFIG. 20.

FIG. 19 illustrates a circuit configuration of the shift register. The shift register illustrated inFIG. 19 includes a plurality of flip-flops, flip-flops5701_1 to5701_—n.The shift register is operated with input of a first clock signal, a second clock signal, a start pulse signal, and a reset signal.

Connection relations of the shift register inFIG. 19 are described. The flip-flop5701_1 of a first stage is connected to afirst wiring5711, asecond wiring5712, afourth wiring5714, afifth wiring5715, a seventh wiring5717_1, and a seventh wiring5717_2. The flip-flop5717_2 of a second stage is connected to athird wiring5713, thefourth wiring5714, thefifth wiring5715, the seventh wiring5717_1, the seventh wiring5717_2, and a seventh wiring5717_3.

The flip-flop5701_—nof an n-th stage is connected to one of thesecond wiring5712 and thethird wiring5713, thefourth wiring5714, thefifth wiring5715, a seventh wiring5717n-1, the seventh wiring5717_—n,and asixth wiring5716.

Note that thefirst wiring5711, thesecond wiring5712, thethird wiring5713, and thesixth wiring5716 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Thefourth wiring5714 and thefifth wiring5715 may be referred to as a first power supply line and a second power supply line, respectively.

In addition, the flip-flop illustrated inFIG. 20 includes afirst wiring5501, asecond wiring5502, athird wiring5503, afourth wiring5504, a fifth wiring5505, and asixth wiring5506.

Note that all thin film transistors here are enhancement-mode n-channel transistors; however, the present invention is not limited thereto. For example, the driver circuit can be operated using depression-mode n-channel transistors.

Next, connection structures of the flip-flop shown inFIG. 20 are described below.

A first electrode (one of a source electrode and a drain electrode) of the first thin film transistor5571 is connected to thefourth wiring5504. A second electrode (the other of the source electrode and the drain electrode) of the first thin film transistor5571 is connected to thethird wiring5503.

A first electrode of the secondthin film transistor5572 is connected to thesixth wiring5506. A second electrode of the secondthin film transistor5572 is connected to thethird wiring5503.

A first electrode of the thirdthin film transistor5573 is connected to the fifth wiring5505, and a second electrode of the thirdthin film transistor5573 is connected to a gate electrode of the secondthin film transistor5572. A gate electrode of the thirdthin film transistor5573 is connected to the fifth wiring5505.

A first electrode of the fourththin film transistor5574 is connected to thesixth wiring5506. A second electrode of the fourththin film transistor5574 is connected to a gate electrode of the secondthin film transistor5572. A gate electrode of the fourththin film transistor5574 is connected to a gate electrode of the first thin film transistor5571.

A first electrode of the fifththin film transistor5575 is connected to the fifth wiring5505. A second electrode of the fifththin film transistor5575 is connected to the gate electrode of the first thin film transistor5571. A gate electrode of the fifththin film transistor5575 is connected to thefirst wiring5501.

A first electrode of the sixththin film transistor5576 is connected to thesixth wiring5506. A second electrode of the sixththin film transistor5576 is connected to the gate electrode of the first thin film transistor5571. A gate electrode of the sixththin film transistor5576 is connected to the gate electrode of the secondthin film transistor5572.

A first electrode of the sevenththin film transistor5577 is connected to thesixth wiring5506. A second electrode of the sevenththin film transistor5577 is connected to the gate electrode of the first thin film transistor5571. A gate electrode of the sevenththin film transistor5577 is connected to thesecond wiring5502.

A first electrode of the eighththin film transistor5578 is connected to thesixth wiring5506. A second electrode of the eighththin film transistor5578 is connected to the gate electrode of the secondthin film transistor5572. A gate electrode of the eighththin film transistor5578 is connected to thefirst wiring5501.

Note that thefirst wiring5501, thesecond wiring5502, thethird wiring5503, and thefourth wiring5504 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fifth wiring5505 and thesixth wiring5506 may be referred to as a first power supply line and a second power supply line, respectively.

In the flip-flop5701_—iof the i-th stage, thefirst wiring5501 inFIG. 20 is connected to the seventh wiring5717_—i−1 inFIG. 19. Thesecond wiring5502 inFIG. 20 is connected to the seventh wiring5717_—i+1 inFIG. 19. Thethird wiring5503 inFIG. 20 is connected to the seventh wiring5717_—i.Thesixth wiring5506 inFIG. 20 is connected to thefifth wiring5715.

If the “i” is an odd number, thefourth wiring5504 inFIG. 20 is connected to thesecond wiring5712 inFIG. 19; if the “i” is an even number, thefourth wiring5504 inFIG. 20 is connected to thethird wiring5713 inFIG. 19. In addition, the fifth wiring5505 inFIG. 20 is connected to thefourth wiring5714 inFIG. 19.

Note that in the flip-flop5701_1 of the first stage, thefirst wiring5501 inFIG. 20 is connected to thefirst wiring5711 inFIG. 19. In addition, in the flip-flop5701_—nof the n-th stage, thesecond wiring5502 inFIG. 20 is connected to thesixth wiring5716 inFIG. 19.

In addition, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in any ofEmbodiments 1 to 4. The n-channel TFT described in any ofEmbodiments 1 to 4 has a high mobility, and thus a driving frequency of a driver circuit can be increased. Further, in the case of the n-channel TFT described in any ofEmbodiments 1 to 4, since parasitic capacitance is reduced by using an oxide semiconductor layer typified by an In—Ga—Zn—O-based non-single-crystal film, frequency characteristics (also referred to as f characteristics) is favorable. For example, the scan-line driver circuit including the n-channel TFT described inEmbodiments 1 to 4 can operate at high speed; therefore, it is possible to increase the frame frequency or to achieve insertion of a black screen, for example.

In addition, when the channel width of the transistor in the scan line driver circuit is increased or a plurality of scan line driver circuits are provided, for example, higher frame frequency can be realized. When a plurality of scan line driver circuits are provided, a scan line driver circuit for driving scan lines of even-numbered rows is provided on one side and a scan line driver circuit for driving scan lines of odd-numbered rows is provided on the opposite side; thus, an increase in frame frequency can be realized. Furthermore, the use of the plurality of scan line driver circuits for output of signals to the same scan line is advantageous in increasing the size of a display device.

Further, when an active matrix light-emitting display device which is an example of a semiconductor device is manufactured, a plurality of thin film transistors are arranged in at least one pixel, and thus a plurality of scan line driver circuits are preferably arranged.FIG. 15B illustrates an example of a block diagram of an active matrix light-emitting display device.

The light-emitting display device illustrated inFIG. 15B includes, over asubstrate5400, apixel portion5401 including a plurality of pixels each provided with a display element, a first scan-line driver circuit5402 and a second scan-line driver circuit5404 that selects a pixel, and a signal-line driver circuit5403 that controls a video signal input to the selected pixel.

In the case where the video signal input to a pixel of the light-emitting display device illustrated inFIG. 15B is a digital signal, the pixel is put in a light-emitting state or a non-light-emitting state by switching on/off of a transistor. Thus, grayscale can be displayed using an area grayscale method or a time grayscale method. An area grayscale method refers to a driving method in which one pixel is divided into a plurality of subpixels and the respective subpixels are driven independently based on video signals so that grayscale is displayed. Further, a time grayscale method refers to a driving method in which a period during which a pixel emits light is controlled so that grayscale is displayed.

Since the response time of a light-emitting element is higher than that of a liquid crystal element or the like, the light-emitting element is more suitable for a time grayscale method than the liquid crystal element. Specifically, in the case of displaying with a time grayscale method, one frame period is divided into a plurality of subframe periods. Then, in accordance with video signals, the light-emitting element in the pixel is brought into a light-emitting state or a non-light-emitting state in each subframe period. By dividing one frame period into a plurality of subframe periods, the total length of time, in which a pixel actually emits light in one frame period, can be controlled by video signals so that grayscale can be displayed.

Note that in the example of the light-emitting display device illustrated inFIG. 15B, when two switching TFTs are arranged in one pixel, the first scan-line driver circuit5402 generates a signal which is input to a first scan line serving as a gate wiring of one of the two switching TFTs, and the second scan-line driver circuit5404 generates a signal which is input to a second scan line serving as a gate wiring of the other of the two switching TFTs. However, one scan-line driver circuit may generate both the signal which is input to the first scan line and the signal which is input to the second scan line. In addition, for example, there is a possibility that a plurality of scan lines used for controlling the operation of the switching element are provided in each pixel, depending on the number of the switching TFTs included in one pixel. In this case, one scan line driver circuit may generate all signals that are input to the plurality of scan lines, or a plurality of scan line driver circuits may generate signals that are input to the plurality of scan lines.

Also in the light-emitting display device, a part of a driver circuit that can include n-channel TFTs among driver circuits can be formed over the same substrate as the thin film transistors of the pixel portion. In addition, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in any ofEmbodiments 1 to 4.

Through the above process, a display device having stable electric characteristics and high reliability as a semiconductor device can be manufactured.

Embodiment 6

The thin film transistor described in any ofEmbodiments 1 to 4 can be manufactured, and the thin film transistor can be used for a pixel portion and further for a driver circuit, so that a semiconductor device having a display function (also referred to as a display device) can be manufactured. Further, part or whole of a driver circuit can be formed over the same substrate as a pixel portion, using the thin film transistor described in any ofEmbodiments 1 to 4, whereby a system-on-panel can be obtained.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by a current or a voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like. Furthermore, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

In addition, the display device includes a panel in which the display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel. The display device also relates to an element substrate, which corresponds to an embodiment before the display element is completed in a manufacturing process of the display device, and the element substrate is provided with means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state after only a pixel electrode of the display element is formed, a state after a conductive film to be a pixel electrode is formed and before the conductive film is etched to form the pixel electrode, or any of other states.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Further, the “display device” includes the following modules in its category: a module including a connector such as a flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP) attached; a module having a TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.

The appearance and cross section of a liquid crystal display panel which is one mode of a semiconductor device will be described in this embodiment with reference to FIGS.21A1 and21A2 andFIG. 21B. FIGS.21A1 and21A2 are each a plan view of a panel in which

thin film transistors

4010 and4011 and aliquid crystal element4013, which are formed over afirst substrate4001, are sealed between thefirst substrate4001 and asecond substrate4006 with asealant4005. The

thin film transistors

4010 and4011 are thin film transistors having stable electric characteristics and high reliability, which are described any ofEmbodiments 1 to 4 and include the oxide semiconductor layer typified by an In—Ga—Zn—O-based non-single-crystal film.FIG. 21B is a cross-sectional view taken along line M-N of FIGS.21A1 and21A2.

Thesealant4005 is provided so as to surround apixel portion4002 and a scanline driver circuit4004 which are provided over thefirst substrate4001. Thesecond substrate4006 is provided over thepixel portion4002 and the scanline driver circuit4004. Therefore, thepixel portion4002 and the scanline driver circuit4004 are sealed together with aliquid crystal layer4008, by thefirst substrate4001, thesealant4005, and thesecond substrate4006. A signalline driver circuit4003 that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region that is different from the region surrounded by thesealant4005 over thefirst substrate4001.

Note that the connection method of a driver circuit which is separately formed is not particularly limited, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG.21A1 illustrates an example of mounting the signalline driver circuit4003 with a COG method, and FIG.21A2 illustrates an example of mounting the signalline driver circuit4003 with a TAB method.

Thepixel portion4002 and the scanline driver circuit4004 provided over thefirst substrate4001 include a plurality of thin film transistors.FIG. 21B illustrates thethin film transistor4010 included in thepixel portion4002 and thethin film transistor4011 included in the scanline driver circuit4004. Over the

thin film transistors

4010 and4011, insulating

layers

4020 and4021 are provided.

As the

thin film transistors

4010 and4011, thin film transistors having stable electric characteristics and high reliability which are described in any ofEmbodiments 1 to 4 and include the oxide semiconductor layer typified by an In—Ga—Zn—O-based non-single-crystal film, can be used. In this embodiment, the

thin film transistors

4010 and4011 are n-channel thin film transistors.

Apixel electrode layer4030 included in theliquid crystal element4013 is electrically connected to thethin film transistor4010. Acounter electrode layer4031 of theliquid crystal element4013 is provided for thesecond substrate4006. A portion where thepixel electrode layer4030, thecounter electrode layer4031, and theliquid crystal layer4008 overlap with one another corresponds to theliquid crystal element4013. Note that thepixel electrode layer4030 and thecounter electrode layer4031 are provided with an insulatinglayer4032 and an insulatinglayer4033 respectively which each function as an alignment film, and theliquid crystal layer4008 is sandwiched between thepixel electrode layer4030 and thecounter electrode layer4031 with the insulating

layers

4032 and4033 therebetween.

Note that thefirst substrate4001 and thesecond substrate4006 can be formed of glass, metal (typically, stainless steel), ceramic, or plastic. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. In addition, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

Reference numeral

4035 denotes a columnar spacer obtained by selectively etching an insulating film and is provided to control the distance between thepixel electrode layer4030 and the counter electrode layer4031 (a cell gap). Alternatively, a spherical spacer may also be used. In addition, thecounter electrode layer4031 is electrically connected to a common potential line formed over the same substrate as thethin film transistor4010. With use of the common connection portion, thecounter electrode layer4031 and the common potential line can be electrically connected to each other by conductive particles arranged between a pair of substrates. Note that the conductive particles are included in thesealant4005.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase is generated within an only narrow range of temperature, liquid crystal composition containing a chiral agent at 5 wt % or more so as to improve the temperature range is used for theliquid crystal layer4008. The liquid crystal composition which includes liquid crystal exhibiting a blue phase and a chiral agent have such characteristics that the response time is 10 μs to 100 μs, which is short, the alignment process is unnecessary because the liquid crystal composition has optical isotropy, and viewing angle dependency is small.

Although the example of a transmissive liquid crystal display device is described in this embodiment, one embodiment of the present invention can also be applied to a reflective liquid crystal display device and a transflective liquid crystal display device.

While an example of the liquid crystal display device in which the polarizing plate is provided on the outer side of the substrate (on the viewer side) and the coloring layer and the electrode layer used for a display element are provided on the inner side of the substrate in that order is described in this embodiment, the polarizing plate may be provided on the inner side of the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing process. Further, a light-blocking film serving as a black matrix may be provided.

In this embodiment, in order to reduce the unevenness of the surface of the thin film transistors and to improve the reliability of the thin film transistors, the thin film transistors which are obtained in any ofEmbodiments 1 to 4 are covered with protective films or insulating layers (the insulatinglayers4020 and4021) which function as planarizing insulating films. Note that the protective film is provided to prevent entry of contaminant impurities such as organic substance, metal, or moisture existing in air and is preferably a dense film. The protective film may be formed with a single layer or a stacked layer of any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, aluminum oxynitride film, and/or an aluminum nitride oxide film using a sputtering method. Although an example in which the protective film is formed using a sputtering method is described in this embodiment, the present invention is not limited to this method and a variety of methods may be employed.

The insulatinglayer4020 having a layered structure can be formed as the protective film. Here, a silicon oxide film is formed using a sputtering method, as a first layer of the insulatinglayer4020. The use of a silicon oxide film as a protective film has an effect of preventing hillock of an aluminum film which is used as the source and drain electrode layers.

Further, as a second layer of the protective film, an insulating layer is formed. Here, a silicon nitride film is formed using a sputtering method, as a second layer of the insulatinglayer4020. The use of the silicon nitride film as the protective film can prevent mobile ions of sodium or the like from entering a semiconductor region so that variation in electrical characteristics of the TFT can be suppressed.

Further, after the protective film is formed, the oxide semiconductor layer may be annealed (at 300° C. to 400° C.).

The insulatinglayer4021 is formed as the planarizing insulating film. As the insulatinglayer4021, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the insulatinglayer4021 may be formed by stacking a plurality of insulating films formed of these materials.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may include as a substituent an organic group (for example, an alkyl group or an aryl group) or a fluoro group. In addition, the organic group may include a fluoro group.

A formation method of the insulatinglayer4021 is not particularly limited, and the following method can be employed depending on the material: a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (an ink-jet method, screen printing, offset printing, or the like), a doctor knife, a roll coater, a curtain coater, a knife coater, or the like. In the case of forming the insulatinglayer4021 with use of a material solution, annealing (300° C. to 400° C.) may be performed on the oxide semiconductor layer at the same time as a baking step. When the baking of the insulatinglayer4021 and the annealing of the oxide semiconductor layer are performed at the same time, a semiconductor device can be manufactured efficiently.

Thepixel electrode layer4030 and thecounter electrode layer4031 can be formed using a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like.

Conductive compositions including a conductive high molecule (also referred to as a conductive polymer) can be used for thepixel electrode layer4030 and thecounter electrode layer4031. The pixel electrode formed using the conductive composition preferably has a sheet resistance of less than or equal to 10000 ohms per square and a transmittance of greater than or equal to 70% at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule included in the conductive composition is preferably less than or equal to 0.1·Ωcm.

As the conductive high molecule, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given.

Further, a variety of signals and potentials are supplied to the signalline driver circuit4003 which is formed separately, the scanline driver circuit4004, or thepixel portion4002 from anFPC4018.

In this embodiment, aconnection terminal electrode4015 is formed from the same conductive film as that of thepixel electrode layer4030 included in theliquid crystal element4013, and aterminal electrode4016 is formed from the same conductive film as that of the source and drain electrode layers of the

thin film transistors

4010 and4011.

Theconnection terminal electrode4015 is electrically connected to a terminal included in theFPC4018 via an anisotropicconductive film4019

Note that FIGS.21A1 and21A1 andFIG. 21B illustrate an example in which the signalline driver circuit4003 is formed separately and mounted on thefirst substrate4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 22 illustrates an example in which a liquid crystal display module is formed as a semiconductor device by using aTFT substrate2600 formed using the TFT described in any ofEmbodiments 1 to 4.

FIG. 22 illustrates an example of a liquid crystal display module, in which theTFT substrate2600 and acounter substrate2601 are fixed to each other with asealant2602, and apixel portion2603 including a TFT or the like, adisplay element2604 including a liquid crystal layer, and acoloring layer2605 are provided between the substrates to form a display region. Thecoloring layer2605 is necessary to perform color display. In the RGB system, respective coloring layers corresponding to colors of red, green, and blue are provided for respective pixels. Polarizing

plates

2606 and2607 and adiffusion plate2613 are provided outside theTFT substrate2600 and thecounter substrate2601. A light source includes acold cathode tube2610 and areflective plate2611, and acircuit substrate2612 is connected to awiring circuit portion2608 of theTFT substrate2600 by aflexible wiring board2609 and includes an external circuit such as a control circuit or a power source circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate therebetween.

The liquid crystal display module can employ a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, or the like.

Through the above process, a liquid crystal display panel having stable electric characteristics and high reliability as a semiconductor device can be manufactured.

Embodiment 7

In this embodiment, an example of electronic paper will be described as a semiconductor device to which the thin film transistor described in any ofEmbodiments 1 to 4 is applied.

FIG. 23 illustrates active matrix electronic paper as an example of a semiconductor device. Athin film transistor581 used for the semiconductor device can be manufactured by application of the thin film transistor described in any one ofEmbodiments 1 to 4.

The electronic paper inFIG. 23 is an example of a display device using a twisting ball display system. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

Thethin film transistor581 sealed between asubstrate580 and asubstrate596 is a thin film transistor with a bottom-gate structure, and a source or drain electrode layer thereof is in contact with afirst electrode layer587 through an opening formed in insulating

layers

583,584, and585, whereby thethin film transistor581 is electrically connected to thefirst electrode layer587. Between thefirst electrode layer587 and asecond electrode layer588,spherical particles589 each having ablack region590a,awhite region590b,and acavity594 around the regions which is filled with liquid are provided. A space around thespherical particles589 is filled with afiller595 such as a resin (seeFIG. 23). In this embodiment, thefirst electrode layer587 corresponds to a pixel electrode, and thesecond electrode layer588 corresponds to a common electrode. Thesecond electrode layer588 is electrically connected to a common potential line provided over the same substrate as thethin film transistor581. A common connection portion described inEmbodiment 2 is used, whereby thesecond electrode layer588 provided on asubstrate596 and the common potential line can be electrically connected to each other through the conductive particles arranged between a pair of substrates.

Further, instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of approximately 10 μm to 200 μm in which transparent liquid, positively charged white microparticles, and negatively charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move to opposite sides, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is generally called electronic paper. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.

In this way, an electrophoretic display element utilizes a so-called dielectrophoretic effect by which a substance having a high dielectric constant moves to a high-electric field region. An electrophoretic display device using an electrophoretic display element does not need to use a polarizer, which is required in a liquid crystal display device.

A solution in which the above microcapsules are dispersed in a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Furthermore, by using a color filter or particles that have a pigment, color display can also be achieved.

In addition, if a plurality of the above microcapsules is arranged as appropriate over an active matrix substrate so as to be interposed between two electrodes, an active matrix display device can be completed, and display can be performed by application of an electric field to the microcapsules. For example, the active matrix substrate obtained with the thin film transistor described in any ofEmbodiments 1 to 4 can be used.

Note that the microparticles may be formed using a single material selected from a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, or a magnetophoretic material or formed of a composite material of any of these.

Through this process, electronic paper having stable electric characteristics and high reliability as a semiconductor device can be manufactured.

Embodiment 8

In this embodiment, an example of a light-emitting display device will be described as the semiconductor device to which the thin film transistor described in any ofEmbodiments 1 to 4 is applied. As a display element included in a display device, a light-emitting element utilizing electroluminescence is described here. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The carriers (electrons and holes) are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that an example of an organic EL element as a light-emitting element is described here.

FIG. 24 illustrates an example of a pixel structure to which digital time grayscale driving can be applied, as an example of a semiconductor device to which one embodiment of the present invention is applied.

A structure and operation of a pixel to which digital time grayscale driving can be applied are described. Here, an example is described in which one pixel includes two n-channel transistors each of which is described in any ofEmbodiments 1 to 4 and each of which includes the oxide semiconductor layer typified by an In—Ga—Zn—O-based non-single-crystal film in a channel formation region.

Apixel6400 includes aswitching transistor6401, adriver transistor6402, a light-emittingelement6404, and acapacitor6403. A gate of theswitching transistor6401 is connected to ascan line6406, a first electrode (one of a source electrode and a drain electrode) of theswitching transistor6401 is connected to asignal line6405, and a second electrode (the other of the source electrode and the drain electrode) of theswitching transistor6401 is connected to a gate of thedriver transistor6402. The gate of thedriver transistor6402 is connected to apower supply line6407 via thecapacitor6403, a first electrode of thedriver transistor6402 is connected to thepower supply line6407, and a second electrode of thedriver transistor6402 is connected to a first electrode (pixel electrode) of the light-emittingelement6404. A second electrode of the light-emittingelement6404 corresponds to acommon electrode6408. Thecommon electrode6408 is electrically connected to a common potential line provided over the same substrate, and the connection portion may be used as a common connection portion.

The second electrode (common electrode6408) of the light-emittingelement6404 is set to a low power supply potential. Note that the low power supply potential is a potential satisfying the low power supply potential<a high power supply potential with reference to the high power supply potential that is set to thepower supply line6407. As the low power supply potential, GND, 0 V, or the like may be employed, for example. A potential difference between the high power supply potential and the low power supply potential is applied to the light-emittingelement6404 and current is supplied to the light-emittingelement6404, so that the light-emittingelement6404 emits light. Here, in order to make the light-emittingelement6404 emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is a forward threshold voltage or higher of the light-emittingelement6404.

Note that gate capacitor of thedriver transistor6402 may be used as a substitute for thecapacitor6403, so that thecapacitor6403 can be omitted. The gate capacitor of thedriver transistor6402 may be formed between the channel region and the gate electrode.

In the case of a voltage-input voltage driving method, a video signal is input to the gate of thedriver transistor6402 so that thedriver transistor6402 is in either of two states of being sufficiently turned on or turned off. That is, thedriver transistor6402 operates in a linear region. Since thedriver transistor6402 operates in the linear region, a voltage higher than the voltage of thepower supply line6407 is applied to the gate of thedriver transistor6402. Note that a voltage higher than or equal to (voltage of the power supply line+Vth of the driver transistor6402) is applied to thesignal line6405.

In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel structure as inFIG. 24 can be used by changing signal input.

In the case of performing analog grayscale driving, a voltage higher than or equal to (forward voltage of the light-emittingelement6404+Vth of the driver transistor6402) is applied to the gate of thedriver transistor6402. The forward voltage of the light-emittingelement6404 indicates a voltage at which a desired luminance is obtained, and includes at least forward threshold voltage. The video signal by which thedriver transistor6402 operates in a saturation region is input, so that current can be supplied to the light-emittingelement6404. In order for thedriver transistor6402 to operate in the saturation region, the potential of thepower supply line6407 is set higher than the gate potential of thedriver transistor6402. When an analog video signal is used, it is possible to feed current to the light-emittingelement6404 in accordance with the video signal and perform analog grayscale driving.

Note that the present invention is not limited to the pixel structure shown inFIG. 24. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added to the pixel shown inFIG. 24.

Next, a structure of a light emitting element will be described with reference toFIGS. 25A to 25C. Here, a cross-sectional structure of a pixel will be described by taking an n-channel driving TFT as an example. Driving

TFTs

7001,7011, and7021 used for the semiconductor devices illustrated inFIGS. 25A to 25C can be manufactured similarly to the thin film transistors described in any ofEmbodiments 1 to 4 and are thin film transistors having stable electric characteristics and high reliability, in which an oxide semiconductor layer typified by an In—Ga—Zn—O-based non-single-crystal film is used.

In order to extract light emitted from the light-emitting element, at least one of an anode and a cathode is required to transmit light. A light-emitting element can have a top emission structure, in which light emission is extracted through the surface opposite to the substrate; a bottom emission structure, in which light emission is extracted through the surface on the substrate side; or a dual emission structure, in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure of the present invention can be applied to a light-emitting element having any of these emission structures.

A light emitting element having a top emission structure is described with reference toFIG. 25A.

FIG. 25A is a cross-sectional view of a pixel in the case where theTFT7001 serving as a driver TFT is an n-channel TFT and light generated in a light-emittingelement7002 is emitted to pass through ananode7005. InFIG. 25A, acathode7003 of the light-emittingelement7002 and theTFT7001, which is the driving TFT, are electrically connected to each other, and a light-emittinglayer7004 and theanode7005 are sequentially stacked over thecathode7003. Thecathode7003 can be formed using a variety of conductive materials as long as they have a low work function and reflect light. For example, Ca, Al, MgAg, AlLi, or the like is desirably used. The light-emittinglayer7004 may be formed using a single layer or a plurality of layers stacked. When the light-emittinglayer7004 is formed using a plurality of layers, the light-emittinglayer7004 is formed by stacking an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer in this order over thecathode7003. It is not necessary to form all of these layers. Theanode7005 is made of a light-transmitting conductive material such as indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

The light-emittingelement7002 corresponds to a region where the light-emittinglayer7004 is sandwiched between thecathode7003 and theanode7005. In the case of a pixel shown inFIG. 25A, light which is emitted from thelight emitting element7002 is emitted to theanode7005 side as indicated by an arrow.

Next, a light emitting element having a bottom emission structure is described with reference toFIG. 25B.FIG. 25B is a cross-sectional view of a pixel in the case where the drivingTFT7011 is of an n-type and light is emitted from a light-emittingelement7012 to acathode7013 side. InFIG. 25B, thecathode7013 of the light-emittingelement7012 is formed over a light-transmittingconductive film7017 which is electrically connected to thedriver TFT7011, and a light-emittinglayer7014 and ananode7015 are stacked in this order over thecathode7013. A light-blockingfilm7016 for reflecting or blocking light may be formed to cover theanode7015 when theanode7015 has a light-transmitting property. Thecathode7013 can be formed using any of a variety of conductive materials as long as it has a low work function similarly toFIG. 25A. Thecathode7013 is formed to have a thickness that can transmit light (preferably, approximately 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm can be used as thecathode7013. Then, thelight emitting layer7014 may be formed using either a single layer or a stacked layer of a plurality of layers similarly toFIG. 25A. Although theanode7015 is not required to be transmit light, a light-transmitting conductive material can be used to form theanode7015 similarly toFIG. 25A. As the light-blockingfilm7016, a metal or the like that reflects light can be used for example; however, it is not limited to a metal film. For example, a resin or the like to which black pigments are added can also be used.

The light-emittingelement7012 corresponds to a region where the light-emittinglayer7014 is sandwiched between thecathode7013 and theanode7015. In the case of a pixel shown inFIG. 25B, light which is emitted from thelight emitting element7012 is emitted to thecathode7013 side as indicated by an arrow.

Description is made on a light emitting element having the dual emission structure with reference toFIG. 25C. InFIG. 25C, acathode7023 of a light-emittingelement7022 is formed over a light-transmittingconductive film7027 which is electrically connected to adriver TFT7021, and a light-emittinglayer7024 and ananode7025 are stacked in this order over thecathode7023. Thecathode7023 can be formed using any of a variety of conductive materials as long as it has a low work function similarly toFIG. 25A. Thecathode7023 is formed to have a thickness that can transmit light. For example, a film of Al having a thickness of 20 nm can be used as thecathode7023. Then, thelight emitting layer7024 may be formed using either a single layer or a stacked layer of a plurality of layers similarly toFIG. 25A. A light-transmitting conductive material can be used to form theanode7025 as in the case ofFIG. 25A.

The light-emittingelement7022 corresponds to a region where thecathode7023, the light-emittinglayer7024, and theanode7025 overlap with one another. In the case of the pixel shown inFIG. 25C, light which is emitted from thelight emitting element7022 is emitted to both theanode7025 side and thecathode7023 side as indicated by arrows.

Note that, although the organic EL elements are described here as the light-emitting elements, an inorganic EL element can also be provided as a light-emitting element.

In this embodiment, the example is described in which a thin film transistor (a driving TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element; however, a structure may be employed in which a TFT for current control is connected between the driving TFT and the light-emitting element.

The semiconductor device described in this embodiment is not limited to the structures illustrated inFIGS. 25A to 25C, and can be modified in various ways based on the spirit of techniques according to the present invention.

Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) which corresponds to one embodiment of the semiconductor device to which the thin film transistor described in any ofEmbodiments 1 to 4 is applied is described with reference toFIGS. 26A and 26B.FIG. 26A is a plan view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed between the first substrate and a second substrate with a sealant, andFIG. 26B is a cross-sectional view taken along H-I ofFIG. 26A.

Asealant4505 is provided so as to surround apixel portion4502, signal

line driver circuits

4503aand4503b,and scan

line driver circuits

4504aand4504bwhich are provided over afirst substrate4501. In addition, asecond substrate4506 is provided over thepixel portion4502, the signal

line driver circuits

4503aand4503b,and the scan

line driver circuits

4504aand4504b.Accordingly, thepixel portion4502, the signal

line driver circuits

4503aand4503b,and the scan

line driver circuits

4504aand4504bare sealed together with afiller4507, by thefirst substrate4501, thesealant4505, and thesecond substrate4506. It is preferable that a panel be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the panel is not exposed to the outside air, in this manner.

Thepixel portion4502, the signal-

line driver circuits

4503aand4503b,and the scan-

line driver circuits

4504aand4504bprovided over thefirst substrate4501 each include a plurality of thin film transistors, and athin film transistor4510 included in thepixel portion4502 and athin film transistor4509 included in the signal-line driver circuit4503aare illustrated as an example inFIG. 26B.

As the

thin film transistors

4509 and4510, thin film transistors having stable electric characteristics and high reliability, which are described in any ofEmbodiments 1 to 4 and include the oxide semiconductor layer typified by an In—Ga—Zn—O-based non-single-crystal film, can be used. In this embodiment, the

thin film transistors

4509 and4510 are n-channel thin film transistors.

Moreover,reference numeral4511 denotes a light-emitting element. Afirst electrode layer4517 which is a pixel electrode included in the light-emittingelement4511 is electrically connected to a source electrode layer or a drain electrode layer of thethin film transistor4510. Note that a structure of the light-emittingelement4511 is a stacked-layer structure of thefirst electrode layer4517, theelectroluminescent layer4512, and thesecond electrode layer4513, but there is no particular limitation on the structure. The structure of the light-emittingelement4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emittingelement4511, or the like.

Apartition4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that thepartition4520 be formed using a photosensitive material and an opening be formed over thefirst electrode layer4517 so that a sidewall of the opening is formed as an inclined surface with continuous curvature.

Theelectroluminescent layer4512 may be formed with a single layer or a plurality of layers stacked.

A protective film may be formed over thesecond electrode layer4513 and thepartition4520 in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emittingelement4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal

line driver circuits

4503aand4503b,the scan

line driver circuits

4504aand4504b,or thepixel portion4502 from

FPCs

4518aand4518b.

In this embodiment, aconnection terminal electrode4515 is formed from the same conductive film as thefirst electrode layer4517 included in the light-emittingelement4511, and aterminal electrode4516 is formed from the same conductive film as the source and drain electrode layers included in the

thin film transistors

4509 and4510.

Theconnection terminal electrode4515 is electrically connected to a terminal included in theFPC4518avia an anisotropicconductive film4519.

As thesecond substrate4506 located in the direction in which light is extracted from the light-emittingelement4511 needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used for thesecond substrate4506.

As thefiller4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used for thefiller4507.

In addition, if needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

The signal

line driver circuits

4503aand4503band the scanning

line driver circuits

4504aand4504bmay be mounted as driver circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared. In addition, only the signal-line driver circuit or only part thereof, or only the scan-line driver circuit or only part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated inFIGS. 26A and 26B.

Through this process, a light-emitting display device (display panel) having stable electric characteristics and high reliability as a semiconductor device can be manufactured.

Embodiment 9

A semiconductor device to which the thin film transistor described in any ofEmbodiments 1 to 4 is applied can be applied as electronic paper. Electronic paper can be used for electronic appliances of a variety of fields as long as they can display data. For example, electronic paper can be applied to an e-book reader (electronic book), a poster, an advertisement in a vehicle such as a train, or displays of various cards such as a credit card. Examples of such electronic devices are illustrated inFIGS. 27A and 27B andFIG. 28.

FIG. 27A illustrates aposter2631 formed using electronic paper. In the case where an advertising medium is printed paper, the advertisement is replaced by hands; however, by using the electronic paper, the advertising display can be changed in a short time. Furthermore, stable images can be obtained without display defects. Note that the poster may have a configuration capable of wirelessly transmitting and receiving data.

FIG. 27B illustrates anadvertisement2632 in a vehicle such as a train. In a case where an advertising medium is paper, a man replaces advertising, but in a case where it is electronic paper, much manpower is not needed and replacement of advertising can be conducted in short time. Furthermore, stable images can be obtained without display defects. Note that the advertisement in a vehicle may have a configuration capable of wirelessly transmitting and receiving data.

FIG. 28 illustrates an example of anelectronic book2700. For example, thee-book reader2700 includes two housings, ahousing2701 and ahousing2703. Thehousing2701 and thehousing2703 are combined with ahinge2711 so that thee-book reader2700 can be opened and closed with thehinge2711 as an axis. With such a structure, thee-book reader2700 can operate like a paper book.

Adisplay portion2705 and adisplay portion2707 are incorporated in thehousing2701 and thehousing2703, respectively. Thedisplay portion2705 and thedisplay portion2707 may display one image or different images. When the display portions display different images, text can be displayed on the right display portion (thedisplay portion2705 inFIG. 28) and an image can be displayed on the left display portion (thedisplay portion2707 inFIG. 28), for example.

Further,FIG. 28 illustrates an example where thehousing2701 is provided with an operation portion and the like. For example, thehousing2701 is provided with apower switch2721, anoperation key2723, aspeaker2725, and the like. With theoperation key2723, pages can be turned. Note that a keyboard, a pointing device, and the like may be provided on the same surface as the display portion of the housing. Furthermore, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing. Moreover, thee-book reader2700 may have a function of an electronic dictionary.

Thee-book reader2700 may have a configuration capable of wirelessly transmitting and receiving data. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.

Embodiment 10

The semiconductor device including the thin film transistor described in any ofEmbodiments 1 to 4 can be applied to a variety of electronic devices (including game machines). Examples of electronic devices are a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone handset (also referred to as a mobile phone or a mobile phone device), a portable game console, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like.

FIG. 29A illustrates an example of atelevision device9600. In thetelevision set9600, adisplay portion9603 is incorporated in ahousing9601. Thedisplay portion9603 can display images. Here, thehousing9601 is supported by astand9605.

Thetelevision set9600 can be operated with an operation switch of thehousing9601 or a separateremote controller9610. Channels and volume can be controlled with anoperation key9609 of theremote controller9610 so that an image displayed on thedisplay portion9603 can be controlled. Furthermore, theremote controller9610 may be provided with adisplay portion9607 for displaying data output from theremote controller9610.

Note that thetelevision set9600 is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. Moreover, when the display device is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed.

FIG. 29B illustrates an example of adigital photo frame9700. For example, in thedigital photo frame9700, adisplay portion9703 is incorporated in ahousing9701. Thedisplay portion9703 can display a variety of images. For example, thedisplay portion9703 can display data of an image taken with a digital camera or the like and function as a normal photo frame.

Note that thedigital photo frame9700 is provided with an operation portion, an external connection portion (a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like), a recording medium insertion portion, and the like. Although these components may be provided on the surface on which the display portion is provided, it is preferable to provide them on the side surface or the back surface for the design of thedigital photo frame9700. For example, a memory storing data of an image taken with a digital camera is inserted in the recording medium insertion portion of the digital photo frame, whereby the image data can be transferred and then displayed on thedisplay portion9703.

Thedigital photo frame9700 may be configured to transmit and receive data wirelessly. The structure may be employed in which desired image data is transferred wirelessly to be displayed.

FIG. 30A illustrates a portable game machine including ahousing9881 and ahousing9891 which are jointed with aconnector9893 so as to be able to open and close. Adisplay portion9882 and adisplay portion9883 are incorporated in thehousing9881 and thehousing9891, respectively. The portable game machine illustrated inFIG. 30A additionally includes aspeaker portion9884, a storagemedium inserting portion9886, anLED lamp9890, an input means (operation keys9885, aconnection terminal9887, a sensor9888 (including a function of measuring force, displacement, position, speed, acceleration, angular speed, the number of rotations, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, tilt angle, vibration, smell, or infrared ray), and a microphone9889), and the like. Needless to say, the structure of the portable game machine is not limited to the above, and may be any structure as long as a semiconductor device according to one embodiment of the present invention is provided. Moreover, another accessory may be provided as appropriate. The portable game machine illustrated inFIG. 30A has a function of reading out a program or data stored in a storage medium to display it on the display portion and a function of sharing information with another portable game machine by wireless communication. The functions of the portable game machine illustrated inFIG. 30A are not limited to these, and the portable game machine can have a variety of functions.

FIG. 30B illustrates an example of aslot machine9900 which is a large-sized game machine. In theslot machine9900, adisplay portion9903 is incorporated in ahousing9901. In addition, theslot machine9900 includes an operation means such as a start lever or a stop switch, a coin slot, a speaker, and the like. Needless to say, the structure of theslot machine9900 is not limited to the above, and may be any structure as long as at least a semiconductor device according to one embodiment of the present invention is provided. Moreover, another accessory may be provided as appropriate.

FIG. 31A illustrates an example of amobile phone1000. Themobile phone1000 includes adisplay portion1002 incorporated in ahousing1001, anoperation button1003, anexternal connection port1004, aspeaker1005, amicrophone1006 and the like.

When thedisplay portion1002 of themobile phone1000 illustrated inFIG. 31A is touched with a finger or the like, data can be input into themobile phone1000. Furthermore, operations such as making calls and composing mails can be performed by touching thedisplay portion1002 with a finger or the like.

There are mainly three screen modes of thedisplay portion1002. The first mode is a display mode mainly for displaying images. The second mode is an input mode mainly for inputting data such as text. The third mode is a display-and-input mode in which two modes of the display mode and the input mode are combined.

For example, in a case of making a call or composing a mail, a text input mode mainly for inputting text is selected for thedisplay portion1002 so that text displayed on a screen can be input. In that case, it is preferable to display a keyboard or number buttons on almost all area of the screen of thedisplay portion1002.

When a detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, is provided inside themobile phone1000, display in the screen of thedisplay portion1002 can be automatically switched by determining the installation direction of the mobile phone1000 (whether themobile phone1000 is placed horizontally or vertically for a landscape mode or a portrait mode).

The screen modes are switched by touching thedisplay portion1002 or operating theoperation button1003 of thehousing1001. Alternatively, the screen modes may be switched depending on the kind of the image displayed on thedisplay portion1002. For example, when a signal of an image displayed on the display portion is a signal of moving image data, the screen mode is switched to the display mode. When the signal is a signal of text data, the screen mode is switched to the input mode.

Further, in the input mode, when input by touching thedisplay portion1002 is not performed for a certain period while a signal detected by the optical sensor in thedisplay portion1002 is detected, the screen mode may be controlled so as to be switched from the input mode to the display mode.

Thedisplay portion1002 may function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken when thedisplay portion1002 is touched with a palm or a finger, whereby personal identification can be performed. Further, by providing a backlight or a sensing light source which emits a near-infrared light in the display portion, an image of a finger vein, a palm vein, or the like can be taken.

FIG. 31B illustrates another example of a mobile phone. The mobile phone inFIG. 31B has adisplay device9410 in ahousing9411, which includes adisplay portion9412 andoperation buttons9413, and acommunication device9400 in ahousing9401, which includesoperation buttons9402, anexternal input terminal9403, amicrophone9404, aspeaker9405, and a light-emittingportion9406 that emits light when a phone call is received. Thedisplay device9410 which has a display function can be detached from or attached to thecommunication device9400 which has a phone function by moving in two directions represented by arrows. Thus, thedisplay device9410 and thecommunication device9400 can be attached to each other along their short sides or long sides. In addition, when only the display function is needed, thedisplay device9410 can be detached from thecommunication device9400 and used alone. Images or input information can be transmitted or received by wireless or wire communication between thecommunication device9400 and thedisplay device9410, each of which has a rechargeable battery.

Example 1

In this example, evaluation results of the conductivity of an oxide semiconductor which is used for the oxide semiconductor layer and the buffer layer in any of the above embodiments will be described.

In this example, an In—Ga—Zn—O-based non-single-crystal film (hereinafter referred to as an IGZO film) formed using a sputtering method in an atmosphere of an argon gas and an oxygen gas and an In—Ga—Zn—O—N-based non-single-crystal film (hereinafter referred to as an IGZON film) formed using a sputtering method in an atmosphere of an argon gas and a nitrogen gas were each formed over a glass substrate. The IGZO film and the IGZON film, which had been formed, were subjected to reverse sputtering treatment, heat treatment in an air atmosphere, and heat treatment in a nitrogen atmosphere. After each heat treatment, the sheet resistance values of the IGZO film and the IGZON film were measured and the conductivity thereof was calculated. Each step of this example is described in detail below.

First, the glass substrates were cleaned with pure water. Note that product name EAGLE 2000 (manufactured by Corning Inc., alkali-free glass) was used for the glass substrate. Next, the IGZO film and the IGZON film were each formed over the glass substrate. The IGZO film was formed using a target of an oxide semiconductor of In₂O₃:Ga₂O₃:ZnO=1:1:1 under conditions where the distance between the substrate and the target was 60 mm, the pressure was 0.4 Pa, direct current (DC) power was 0.5 kW, the film thickness was 50 nm, the flow rate ratio of film formation gasses of Ar:O₂was 30:15 (sccm), and the film formation temperature was room temperature. The IGZON film was formed under conditions similar to those of the IGZO film except that the flow rate ratio of film formation gases of Ar to N₂was 35:5 (sccm). Note that the IGZO film and the IGZON film were each formed to a thickness of approximately 50 nm, and the actual thickness was measured by an ellipsometer after the formation. Then, the sheet resistance values of the IGZO film and the IGZON film were measured by a sheet resistance measuring apparatus. Note that conductivity can be obtained by a sheet resistance value and a film thickness.

Next, the IGZO film and the IGZON were subjected to reverse sputtering treatment under conditions where an Ar gas flow rate was 50 sccm, the pressure was 0.6 Pa, direct current (DC) power was 0.2 kW, and treatment time was 3 minutes. After the reverse sputtering, the sheet resistance values of the IGZO film and the IGZON film were measured and the conductivity thereof was calculated.

Next, the IGZO film and the IGZON film were repeatedly subjected to heat treatment in an air atmosphere (hereinafter referred to as air baking) under conditions where a treatment temperature was 350° C. and treatment time was 1 hour, and heat treatment in a nitrogen atmosphere (hereinafter referred to as nitrogen baking) under the same conditions of a treatment temperature and treatment time. The heat treatments were performed in two ways, a process A and a process B. In the process A, after the reverse sputtering treatment, air baking, nitrogen baking, second air baking, and second nitrogen baking were performed in this order. In the process B, after the reverse sputtering treatment, nitrogen baking, air baking, and second nitrogen baking were performed in this order. In other words, the first air baking in the process A was omitted in the process B.

TABLE 1

	Conductivity of	Conductivity of
Process A	IGZO film (S/cm)	IGZON film (S/cm)

Directly after	<<0.01	<<0.01
film formation
After reverse	1.72	3.49
sputtering
After air baking	<<0.01	<<0.01
After nitrogen baking	<<0.01	1.82
After air baking	<<0.01	<<0.01
After nitrogen baking	<<0.01	1.65

TABLE 2

	Conductivity of	Conductivity of
Process B	IGZO film (S/cm)	IGZON film (S/cm)

Directly after	<<0.01	<<0.01
film formation
After reverse	1.72	3.49
sputtering
After nitrogen baking	139	290
After air baking	<<0.01	<<0.01
After nitrogen baking	0.15	65.2

Table 1 shows the conductivity of the IGZO film and the IGZON film in the process A, and Table 2 shows the conductivity of the IGZO film and the IGZON film in the process B. The unit for the conductivity is S/cm both in Table 1 and in Table 2. Note that the conductivity of a film whose sheet resistance value is too high to be measured by the sheet resistance measuring apparatus is represented as <<0.01 S/cm.

In each of Table 1 and Table 2, when the IGZO film and the IGZON film which were formed through the same process are compared to each other, the conductivity of the IGZON film is higher than that of the IGZO film. In addition, after the reverse sputtering treatment, the conductivity of the IGZO film and the IGZON film is increased. The conductivity of the IGZO film and the IGZON film is reduced after the air baking and increased after the nitrogen baking. In particular, the conductivity of the IGZO film and the IGZON film after the first nitrogen baking in the process B shown in Table 2 is greatly high as compared to that of the others.

When the conductivity of the IGZO film and the IGZON film after the first nitrogen baking in the process A shown in Table 1 and that of the IGZO film and the IGZON film after the second nitrogen baking in the process B shown in Table 2 are compared to each other, the conductivity of each of the IGZO film and the IGZON film in the latter case is higher than that in the former case, even though the conductivity becomes 0.01 S/cm or less after the air baking in both the processes A and B. This shows that the conductivity of the IGZO film and the IGZON film is decreased when the atmosphere of the first heat treatment after the film formation is an air atmosphere, and increased when the atmosphere is a nitrogen atmosphere. Furthermore, the following is presumed: even when heat treatments in different atmospheres are performed a plurality of times after the film formation, effect of subsequent heat treatment in a different atmosphere is lowered depending on the atmosphere of the first heat treatment after the film formation.

Accordingly, in any of the above embodiments, an In—Ga—Zn—O—N-based non-single-crystal film formed in an atmosphere of an argon gas and a nitrogen gas is preferable as the buffer layer. In addition, the In—Ga—Zn—O—N-based non-single-crystal film which is subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere is preferable. By using such a film, the conductivity of the buffer layer can be increased, an ohmic contact can be formed between the oxide semiconductor layer and the source and drain electrode layers, and electric characteristics of the thin film transistor can be stabilized. In the case where the oxide semiconductor layer is subjected to heat treatment in an air atmosphere, it is preferable that the oxide semiconductor layer is subjected to the heat treatment in a nitrogen atmosphere in advance of the heat treatment in an air atmosphere. Alternatively, when an In—Ga—Zn—O-based non-single-crystal film which is formed in an atmosphere of an argon gas and an oxygen gas and subjected to heat treatment in an air atmosphere is used as the oxide semiconductor layer, the conductivity of the oxide semiconductor layer can be reduced and off current can be reduced. Further alternatively, when an In—Ga—Zn—O-based non-single-crystal film which is formed in an atmosphere of an argon gas and an oxygen gas and subjected to heat treatment in a nitrogen atmosphere is used, the conductivity of the oxide semiconductor layer can be increased and on current can be increased. Accordingly, an atmosphere of heat treatment for the oxide semiconductor layer may be changed depending on a purpose.

This application is based on Japanese Patent Application serial no. 2009-131161 filed with Japan Patent Office on May 29, 2009, the entire contents of which are hereby incorporated by reference.