US20100190306A1 - Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan⁻¹(W2/T)<α≦tan⁻¹(W1/T), where W1 is an interval between a first portion and a fourth portion and an interval between a third portion and a sixth portion; W2 is an interval between a second portion and a fifth portion; T is a total film thickness of the silicon oxide film and the silicon nitride film. When the implant angle α is controlled within that range, impurity ions are implanted into a second side surface and a fifth side surface through a silicon oxide film.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of U.S. application Ser. No. 11/767,734, filed Jun. 25, 2007, which is a divisional of U.S. application Ser. No. 11/292,360 filed Dec. 2, 2005, which is a divisional of U.S. application Ser. No. 10/730,099, filed Dec. 9, 2003, now U.S. Pat. No. 6,998,319 each of which is hereby incorporated by reference. This application is based upon and claims the benefit of priority from the prior Japanese patent application No. 2003-143438 filed May 21, 2003.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to methods of manufacturing semiconductor devices, and more particularly to a method of manufacturing a semiconductor device having a DRAM capacitor.
• 2. Description of the Background Art
• A conventional method of manufacturing a semiconductor device having a DRAM capacitor has the following steps, which are carried out in the following order: (a) partially forming an element isolating insulation film in an upper surface of a silicon substrate, (b) ion-implanting an impurity in a direction perpendicular to the upper surface of the silicon substrate to form a doped channel region, a channel cut region, and a well region, all of which are of p-type, within the silicon substrate that is in an element forming region, (c) forming a gate insulating film on the upper surface of the silicon substrate that is within the element forming region using a thermal oxidation technique, (d) forming a gate electrode on the gate insulating film, (e) forming a source region and a drain region, both of which are of n-type, in the upper surface of the silicon substrate, the source region and drain region forming a pair such as to sandwich a channel forming region below the gate electrode, (f) forming a first interlayer dielectric film entirely, (g) forming a first contact plug connected to the drain region in the first interlayer dielectric film, (h) forming a bit line connected to the first contact plug, (i) forming a second interlayer dielectric film entirely, (j) forming a second contact plug connected to the source region in the first and second interlayer dielectric films, (k) forming a third interlayer dielectric film entirely, (j) forming a capacitor lower electrode connected to the second contact plug in the third interlayer dielectric film, (m) forming a capacitor dielectric film on the capacitor lower electrode, and (n) forming a capacitor upper electrode on the capacitor dielectric film.
• Japanese Patent Application Laid-Open Nos. 10-65153, 9-237829, and 8-250583, for example, disclose methods of manufacturing a semiconductor device including the step of forming a doped channel region in a silicon substrate.
• According to the conventional methods of manufacturing a semiconductor device, however, the gate insulating film is formed after the doped channel region is formed. For this reason, part of the impurity contained in the doped channel region is absorbed into the gate insulating film by the heat treatment for forming the gate insulating film. As a result, the impurity concentration of the doped channel region becomes lower than a desired value, thereby reducing the threshold voltage of a memory cell transistor. This tendency is particularly noticeable in a boundary portion between the element isolating insulation film and the doped channel region, and a considerable reduction in the threshold voltage of memory cell transistors occurs when the width of the doped channel region becomes narrower than a certain value (the phenomenon known as “inverse narrow width effect”).
• It is possible to compensate the reduction in the impurity concentration by ion-implanting a p-type impurity at a higher concentration than a desired value when forming doped channel regions. However, since the high-concentration p-type impurity is implanted into the regions in which n-type source and drain regions are to be formed, the following problems arise.
• Because the impurity concentration in the source and drain regions reduces, the contact resistance between the source region and the second contact plug increases. As a consequence, the performance of memory cell transistors degrades, leading to the problem of deteriorating data write characteristics.
• In addition, electric field strength becomes high in the boundary portion between the source region and the channel forming region and in the boundary portion between the source region and the element isolating insulation film. As a result, junction leakage current increases, leading to the problem of deteriorating device characteristics (for example, refresh characteristics) of DRAMs.
SUMMARY OF THE INVENTION
• It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device that is capable of suppressing reduction in a impurity concentration in a doped channel region, which is caused by formation of a gate insulating film, without deteriorating write characteristics and refresh characteristics.
• According to a first aspect of the present invention, a method of manufacturing a semiconductor device includes the following steps (a) through (k). The step (a) is to form a first substantially H-shaped mask material and a second substantially H-shaped mask material on a main surface of a semiconductor substrate, the first mask material having a first portion, a second portion, and a third portion connected in that order along a first direction in plan view and wherein a dimension of the second portion with respect to a second direction in plan view that is perpendicular to the first direction is smaller than dimensions of the first and third portions with respect to the second direction, the second mask material having a fourth portion, a fifth portion, and a sixth portion connected in that order along the first direction and wherein a dimension of the fifth portion with respect to the second direction is smaller than dimensions of the fourth and sixth portions with respect to the second direction, so that the first and fourth portions, the second and fifth portions, and the third and sixth portions are each mutually spaced apart and aligned along the second direction. The step (b) is to etch the semiconductor substrate using the first and second mask materials as etch masks, to form in the main surface a recessed portion having a first side surface, a second side surface, and a third side surface that are defined by the semiconductor substrate below the first to third portions, and a fourth side surface, a fifth side surface, and a sixth side surface that are defined by the semiconductor substrate below the fourth to sixth portions. The step (c) is to implant impurity ions in the second direction from diagonally above, with the first and second mask materials being formed on the main surface, to form first doped channel regions of a first conductive type only in the second and fifth side surfaces among the first to sixth side surfaces. The step (d) is performed after the step (c). The step (d) is to form an element isolating insulation film by filling the recessed portion to define respective portions of the semiconductor substrate where the first and second mask materials are formed in the step (a) as a first element forming region and a second element forming region. The step (e) is to form second doped channel regions of the first conductive type respectively within the main surface that is in the first and second element forming regions. The step (f) is performed after the step (c). The step (f) is to remove the first and second mask materials. The step (g) is performed after the step (f). The step (g) is to form an insulating film on the main surface that is in the first and second element forming regions. The step (h) is to form a conductive film on a structure obtained by the step (g). The step (i) is to pattern the conductive film to form a gate electrode above the main surface on which the second and fifth portions are formed in the step (a), the gate electrode extending along the second direction. The step ( ) is to form first source-drain regions of a second conductive type being different from the first conductive type, in the main surface in which the first and fourth portions are formed in the step (a). The step (k) is to form second source-drain regions of the second conductive type in the main surface in which the third and sixth portions are formed in the step (a).
• It is possible to suppress reduction in the impurity concentration in the doped channel regions, which arises from formation of the gate insulating film.
• According to a second aspect of the present invention, a method of manufacturing a semiconductor device includes the following steps (a) through (k). The step (a) is to form a first mask material, a second mask material, and a third mask material on a main surface of a semiconductor substrate, the first mask material having a first portion, a second portion, and a third portion connected in that order along a first direction in plan view, the second mask material having a fourth portion, a fifth portion, and a sixth portion connected in that order along the first direction, and the third mask material having a seventh portion, an eighth portion, and a ninth portion connected in that order along the first direction, so that the third, fourth and ninth portions are mutually spaced apart and aligned in that order along a second direction in plan view that is perpendicular to the first direction, that the second and eighth portions are mutually spaced apart and aligned along the second direction, and that the second and fifth portions are not aligned along the second direction. The step (b) is to etch the semiconductor substrate using the first to third mask materials as an etch mask to form in the main surface a recessed portion having a first side surface, a second side surface, and a third side surface that are defined by the semiconductor substrate below the first to third portions, respectively, a fourth side surface, a fifth side surface, and a sixth side surface that are defined by the semiconductor substrate below the fourth to sixth portions, respectively, and a seventh side surface, an eighth side surface, and a ninth side surface that are defined by the semiconductor substrate below the seventh to ninth portions. The step (c) is to implant impurity ions in the second direction from diagonally above, with the first to third mask materials being formed on the main surface, to form first doped channel regions of a first conductive type only in the second side surface of the second and third side surfaces, only in the fifth side surface of the fourth and fifth side surfaces, and only in the eighth side surface of the eighth and ninth side surfaces. The step (d) is performed after the step (c). The step (d) is to form an element isolating insulation film by filling the recessed portion to define respective portions of the semiconductor substrate where the first to third mask materials are formed in the step (a) as a first element forming region, a second element forming region, and a third element forming region. The step (e) is to form second doped channel regions of the first conductive type within the main surface that is in the first to third element forming regions, respectively. The step (f) is performed after the step (c). The step (f) is to remove the first to third mask materials. The step (g) is performed after the step (f). The step (g) is to form an insulating film on the main surface that is in the first to third element forming regions. The step (h) is to form a conductive film on a structure obtained by the step (g). The step (i) is to pattern the conductive film to form a gate electrode above the main surface on which the second, fifth, and eighth portions are formed in the step (a), the gate electrode extending along the second direction. The step (j) is to form first source-drain regions of a second conductive type being different from the first conductive type, in the main surface in which the first, sixth, and seventh portions are formed in the step (a). The step (k) is to form second source-drain regions of the second conductive type in the main surface in which the third, forth, and ninth portions are formed in the step (a).
• It is possible to suppress reduction in the impurity concentration in the doped channel regions, which arises from formation of the gate insulating film.
• According to a third aspect of the present invention, a method of manufacturing a semiconductor device includes the following steps (a) through (e). The step (a) is to form an insulating film on a main surface of a semiconductor substrate. The step (b) is to form a conductive film on the insulating film. The step (c) is to implant ions of an impurity into the main surface through the conductive film and the insulating film to form doped channel regions. The step (d) is to pattern the conductive film to form a gate electrode. The step (e) is to introduce an impurity into the main surface that is exposed from the gate electrode to form source-drain regions.
• It is possible to suppress reduction in the impurity concentration in the doped channel regions, which arises from formation of the gate insulating film.
• These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a top plan view showing a structure of a semiconductor device according to a first preferred embodiment of the present invention;
• FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device shown inFIG. 1;
• FIG. 3 is a cross-sectional view showing, in order of manufacturing steps, a method of manufacturing the semiconductor device according to the first preferred embodiment of the present invention;
• FIG. 4 is a top plan view showing a formation pattern of a silicon nitride film, corresponding toFIG. 1;
• FIGS. 5 through 11 are cross-sectional views showing, in order of manufacturing steps, the method of manufacturing the semiconductor device according to the first preferred embodiment of the present invention;
• FIG. 12 is a top plan view showing a structure of a semiconductor device according to a second preferred embodiment of the present invention;
• FIG. 13 is a cross-sectional view showing a cross-sectional structure concerning a position along the line XIII-XIII shown inFIG. 12;
• FIG. 14 is a top plan view showing a formation pattern of a silicon nitride film, corresponding to a portion ofFIG. 12;
• FIGS. 15 through 19 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing the semiconductor device according to the second preferred embodiment of the present invention;
• FIGS. 20 and 21 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a third preferred embodiment of the present invention;
• FIGS. 22 and 23 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a fourth preferred embodiment of the present invention;
• FIG. 24 is a top plan view showing a structure of a semiconductor device according to a fifth preferred embodiment of the present invention;
• FIG. 25 is a cross-sectional view showing a cross-sectional structure concerning a position along the line XXV-XXV shown inFIG. 24;
• FIGS. 26 and 27 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing the semiconductor device according to the fifth preferred embodiment of the present invention;
• FIGS. 28 through 31 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a sixth preferred embodiment of the present invention;
• FIGS. 32 through 35 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a seventh preferred embodiment of the present invention; and
• FIG. 36 is a top plan view showing a structure of a semiconductor device according to an eighth preferred embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTSFirst Preferred Embodiment
• FIG. 1 is a top plan view showing a structure of a semiconductor device according to a first preferred embodiment of the present invention. Element forming regions AR1 and AR2 having a substantially H-shaped upper surface structure are defined by an element isolatinginsulation film4. The element forming regions AR1 and AR2 are spaced apart from each other and aligned along a Y direction.
• In the element forming region AR1, a first transistor is formed that has asource region1S, adrain region1D, a dopedchannel region1C, and agate structure3. Likewise, in the element forming region AR2, a second transistor is formed that has asource region2S, adrain region2D, a dopedchannel region2C, and thegate structure3. In the example shown inFIG. 1, thegate structure3 that the first transistor has and thegate structure3 that the second transistor has are connected to each other. The first and second transistors are, for example, memory cell transistors of a DRAM, transistors constituting a peripheral circuit thereof, or transistors constituting a logic circuit thereof. In the following, an example in which the first and second transistors are both N-channel MOSFETs is described.
• Thesource region1S, the dopedchannel region1C, and thedrain region1D are aligned in that order along an X direction. Likewise, thesource region2S, the dopedchannel region2C, and thedrain region2D are aligned in that order along the X direction. Thesource region1S and thesource region2S, the dopedchannel region1C and the dopedchannel region2C, and thedrain region1D and thedrain region2D, are each mutually spaced apart and aligned along the Y direction. An interval W1 between the dopedchannel region1C and the dopedchannel region2C is wider than an interval W2 between thesource region1S and thesource region2S and the interval W2 between thedrain region1D and thedrain region2D.
• FIG. 2 depicts cross-sectional views showing a cross-sectional structure of the semiconductor device shown inFIG. 1. InFIG. 2, views (A), (B), and (C) show the cross-sectional structures taken along the lines IIA-IIA, IIB-IIB, and IIC-IIC shown inFIG. 1, respectively.
• FIGS. 3 and 5 to11 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to the first preferred embodiment. The views (A) to (C) in each of the figures correspond to the views (A) to (C) ofFIG. 2, respectively.
• First, referring toFIG. 3, a silicon oxide film and a silicon nitride film are formed in that order entirely on an upper surface of an n-type silicon substrate10. It should be noted, however, that a silicon oxynitride film may be formed in place of the silicon oxide film. Alternatively, in place of the silicon nitride film, a polysilicon film or a layered film of a silicon nitride film and a polysilicon film may be formed. Next, by patterning these films, asilicon oxide film20 and asilicon nitride film21 are formed. Subsequently, using thesilicon nitride film21 as an etch mask, thesilicon substrate10 is etched away by a predetermined film thickness using an anisotropic dry etching technique. This forms a recessedportion22 in the upper surface of thesilicon substrate10. Then, using an oxidation furnace or a single wafer-type lamp oxidation apparatus, asilicon oxide film13 having a film thickness of about several nanometers to several tens of nanometers is formed on the side surfaces and the bottom surface of the recessedportion22 by a thermal oxidation technique at about 900 to 1150° C. This recovers crystal defects in thesilicon substrate10 that are produced by damages arising from the etching for forming the recessedportion22.
• FIG. 4 is a top plan view showing a formation pattern of thesilicon nitride film21 corresponding toFIG. 1. Thesilicon nitride film21 that corresponds to the element forming region AR1 (denoted byreference character21ainFIG. 4) has afirst portion211, asecond portion212, and athird portion213, which are connected in that order along the X direction. Thesilicon nitride film21ahas a substantially H-shaped upper surface structure, and the dimension of thesecond portion212 with respect to the Y direction is smaller than the dimensions of thefirst portion211 and thethird portion213 with respect to the Y direction. Likewise, thesilicon nitride film21 that corresponds to the element forming region AR2 (denoted byreference character21binFIG. 4) has afourth portion214, afifth portion215, and asixth portion216, which are connected in that order along the X direction. Thesilicon nitride film21bhas a substantially H-shaped upper surface structure, and the dimension of thefifth portion215 with respect to the Y direction is smaller than the dimensions of thefourth portion214 and thesixth portion216 with respect to the Y direction. Thefirst portion211 and thefourth portion214, thesecond portion212 and thefifth portion215, and thethird portion213 and thesixth portion216 are each mutually spaced apart and aligned along the Y direction. The recessedportion22 has first to sixth side surfaces10A1 to10A6 defined by thesilicon substrate10 below the first tosixth portions211 to216.
• Subsequent toFIG. 3, referring toFIG. 5,ions231,232 of a p-type impurity such as B, BF2, or In are implanted at a concentration of about 1E11/cm2 to 1E14/cm2 in the Y direction from diagonally above, with thesilicon oxide film20 and thesilicon nitride film21 having been formed. The ion implantation is sequentially carried out in opposing directions +Y and −Y, as indicated by arrows Y1 and Y2 inFIG. 1.
• As for implant angle α of the ion implantation (that is, an angle formed by an implant direction of theimpurity ions231 and232 and a direction of the normal to the upper surface of the silicon substrate10), an implant angle is adopted that falls within a range that satisfies the relationship tan−1(W2/T)<α≦tan−1(W1/T), where W2 represents an interval between thefirst portion211 and thefourth portion214 and an, internal between thethird portion213 and thesixth portion216 shown inFIG. 4, W1 is an interval between thesecond portion212 and thefifth portion215, and T is a total film thickness of thesilicon oxide film20 and thesilicon nitride film21.
• When the implant angle α is controlled within that range, theimpurity ions231 and232 are implanted through thesilicon oxide film13 in the second side surface10A2 and thefifth side surface10A5 shown inFIG. 4. As a result, as shown in view (A) ofFIG. 5, p-type dopedchannel regions51 and52 are formed within the upper surface of thesilicon substrate10 that is in the element forming regions AR1 and AR2, respectively. On the other hand, due to the shadowing effect of thesilicon oxide film20 and thesilicon nitride film21, theimpurity ions231 and232 are not implanted to the first side surface10A1, thethirdside surface10A3, the fourth side surface10A4, and the sixth side surface10A6 that are shown inFIG. 4. As a result, as shown in view (B) ofFIG. 5, the dopedchannel regions51 and52 are not formed.
• Next, referring toFIG. 6, asilicon oxide film24 having such a film thickness that it can completely fill up the recessedportion22 is entirely formed by a coating technique or a CVD technique using high density plasma. Thesilicon oxide film24 may be doped with impurity such as F, P, or B.
• Then, referring toFIG. 7, thesilicon oxide film24 is polished by a CMP technique until an upper surface of thesilicon nitride film21 is exposed.
• Subsequently, referring toFIG. 8, in order to adjust the height of an upper surface of the element isolatinginsulation film4, thesilicon oxide film24 is removed by a desired film thickness using an aqueous solution of HF or the like. Next, thesilicon nitride film21 is removed using a hot phosphoric acid solution.
• Then, referring toFIG. 9, in order to form a CMOS transistor, an impurity such as B is ion-implanted into thesilicon substrate10 through thesilicon oxide film20, thereby forming a p-type well region11.Reference numeral11 inFIG. 9 represents a location in which the impurity concentration shows a peak in the well region. Subsequently, in order to improve isolation breakdown voltage, a p-typechannel cut region12 is formed by ion-implanting an impurity such as B, BF2, or In into thesilicon substrate10 through thesilicon oxide film20. Next, in order to adjust the threshold voltage of the transistors, an impurity such as B,BF2, or In is ion-implanted at a concentration of about 1E11/cm 2 to 1E14/cm 2 into thesilicon substrate10 through thesilicon oxide film20. Thus, p-type dopedchannel regions11C and2C are formed in the upper surface of thesilicon substrate10. Thereafter, the impurities that have been ion-implanted in thesilicon substrate10 are activated by carrying out a heat treatment at about 800 to 1100° C. using a lamp annealing technique.
• Next, referring toFIG. 10, thesilicon oxide film20 is removed using an aqueous solution of HF or the like. Thus, the upper surface of thesilicon substrate10 that is in the element forming regions AR1 and AR2 is exposed. Also, a portion of thesilicon oxide film24 is removed to form asilicon oxide film14, thus forming a trench-shaped element isolatinginsulation film4 having thesilicon oxide films13 and14. Subsequently, using an oxidation furnace at about 700 to 850°, or a lamp oxidation apparatus at about 900 to 1100° C., silicon oxide films151 and152 functioning as gate insulating films are formed on the upper surface of thesilicon substrate10 that is in the element forming regions AR1 and AR2. It should be noted that a silicon oxynitride film, or a layered film of a silicon oxide film and a silicon oxynitride film may be formed in place of the silicon oxide films151 and152. Then, by a CVD technique or the like, aconductive film16 is formed on the silicon oxide films151 and152 and on the element isolatinginsulation film4. Theconductive film16 is a polysilicon film, a metal film (W, Ti, Al, Cu, or the like), a metal silicide film, a metal nitride film, or a layered film thereof. Next, using a CVD technique or the like, asilicon nitride film17 is formed on theconductive film16. It should be noted that a silicon oxide film, or a layered film of a silicon oxide film and a silicon nitride film may be formed in place of thesilicon nitride film17.
• Next, referring toFIG. 11, thesilicon nitride film17 is patterned by a photolithography technique and an anisotropic dry etching technique. Then, using thesilicon nitride film17 as an etch mask, theconductive film16 is etched by an anisotropic dry etching technique. The portion of theconductive film16 that has not been etched away functions as a gate electrode. Next, using a lamp oxidation technique or a normal thermal oxidation technique, theconductive film16 is oxidized or nitrided in a mixed gas atmosphere of O2, NO, N2O, NH3, H2, etc., to form an insulating film18.
• Subsequently, using thesilicon nitride film17 as an implant mask, an impurity such as P, As, or Sb is ion-implanted so as to form n-type source regions1S and2S and n-type drain regions1D,2D in the upper surfaces of thesilicon substrate10. With the manufacturing steps thus described, the structure shown inFIG. 2 is obtained.
• As described above, in the method of manufacturing the semiconductor device according to the first preferred embodiment, the silicon oxide films151 and152, which function as the gate insulating films, are formed in the step shown inFIG. 10, after the doped channel regions51 and52 are formed in the step shown inFIG. 5 and then the dopedchannel regions1C and2C are formed in the step shown inFIG. 9. Therefore, even if part of the impurity contained in the doped channel regions51,52,1C and2C are absorbed in the gate insulating films because of the heat treatment for forming the gate insulating films, it is possible to suppress reduction in the impurity concentration in the doped channel regions in comparison with the conventional manufacturing methods in which the doped channel regions51 and52 are not formed. As a consequence, reduction in the threshold voltages of the first and second transistors can be suppressed.
• Moreover, as shown inFIG. 1, the doped channel regions51 and52 are formed under thegate structure3 and in the boundary portions between the element isolatinginsulation film4 and the dopedchannel regions1C and2C; therefore, the inverse narrow width effect is effectively prevented from occurring.
• Furthermore, in the step shown inFIG. 5, the p-type impurity ions231,232 are implanted in the Y direction from diagonally above, and in addition, the implant angle .alpha. of the ion implantation is controlled within the range tan.sup.−1(W2/T)<α≦tan−1(W1/T); therefore, of the first to sixth side surfaces10A1 to10A6 shown inFIG. 4, only in thesecondside surface10A2 and thefifth side surface10A5, the doped channel regions51 and52 are formed in a self-aligned manner. Consequently, reduction in the impurity concentrations in the n-type source regions1S and2S as well as thedrain regions1D and2D because of the formation of the p-type doped channel regions5₁and5₂can be appropriately avoided.
Second Preferred Embodiment
• The second preferred embodiment describes an example in which the invention according to the foregoing first preferred embodiment is applied to DRAM memory cells.
• FIG. 12 depicts a top plan view showing a structure of a semiconductor device according to a second preferred embodiment of the present invention.FIG. 13 depicts a cross-sectional view showing a cross-sectional structure concerning a position along the line XIII-XIII shown inFIG. 12. Referring toFIG. 12, a plurality of element forming regions AR (represented byreference characters AR11,AR12,AR21,AR31, andAR32 inFIG. 12) are defined by the element isolatinginsulation film4. The element formingregion AR11 and the element formingregion AR31 both of which belong to a common column in a memory cell array, and the element formingregion AR12 and the element formingregion AR32, both of which belong to another common column, are each mutually spaced apart and aligned along the Y direction. The element formingregion AR11 and the element formingregion AR12, both of which belong to a common row, and the element formingregion AR3, and the element formingregion AR32, both of which belong to a common row, are each mutually spaced apart and aligned along the X direction. The element formingregion AR21 is formed so that it is staggered with respect to the element forming region AR11 by half of the formation pitch of the element forming regions AR along the X direction. That is, a so-called half pitch cell is constructed.
• Referring toFIGS. 12 and 13, in each one of the element forming regions AR, two memory cell transistors are formed sharing adrain region56D. On thedrain region56D, acontact plug32 is formed that is connected to abit line48. Contact plugs30 and31 respectively connected topolysilicon films52 and53, which function as capacitor lower electrodes, are formed onrespective source regions5S and6S. Since the half pitch cell is constructed, thesource regions5S and6S formed in the element forming regions AR that belong to different rows are mutually spaced apart at an interval W2 and aligned along the Y direction. Thedrain regions56D as well as dopedchannel regions38,44 formed in the element forming regions AR that belong to different rows are mutually spaced apart at an interval W1 that is wider than the interval W2 and aligned along the Y direction.
• In each of the element forming regions AR, doped channel regions5, which correspond to the doped channel regions51 and52 of the foregoing first preferred embodiment, are formed. As in the step shown inFIG. 5, the doped channel regions5 are formed by implanting p-type impurity ions231,232 in the Y direction from diagonally above so that an implant angle α of the ion implantation controlled within a range tan−1(W2/T)<α≦tan−1(W1/T). Thus, the doped channel regions5 are formed in the dopedchannel regions38 and44 and in thedrain region56D, but are not formed in thesource regions5S and6S. In the second preferred embodiment, for one example, the interval W1 is about 370 nm, the interval W2 is about 110 nm, and the film thickness T is about 120 nm.
• FIGS. 15 through 19 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing the semiconductor device according to the second preferred embodiment. First, memory cell transistors shown inFIG. 15 are formed through similar manufacturing steps to those in the foregoing first preferred embodiment.
• FIG. 14 is a top plan view showing a formation pattern of asilicon nitride film21 when forming the element isolatinginsulation film4, corresponding to a portion ofFIG. 12. Thesilicon nitride film21 corresponding to the element forming region AR11 (denoted byreference character21ainFIG. 14) has afirst portion211, asecond portion212, and athird portion213, which are connected in that order along the X direction. Likewise, thesilicon nitride film21 that corresponds to the element forming region AR21 (denoted byreference character21binFIG. 14) has afourth portion214, afifth portion215, and asixth portion216, which are connected in that order along the X direction. Likewise, thesilicon nitride film21 that corresponds to the element forming region AR31 (denoted byreference character21cinFIG. 14) has aseventh portion217, aneighth portion218, and aninth portion219, which are connected in that order along the X direction.
• Thethird portion213, thefourth portion214, and theninth portion219 correspond to thesource regions5S and6S. Thesecond portion212, thefifth portion215, and theeighth portion218 correspond to the dopedchannel regions38 and44. Thefirst portion211, thesixth portion216, and theseventh portion217 correspond to thedrain region56D.
• Thethird portion213, thefourth portion214, and theninth portion219 are spaced apart from each other and aligned in that order along the Y direction. Thesecond portion212 and theeighth portion218 are spaced apart from each other and are aligned along the Y direction. Thefirst portion211 and theseventh portion217 are spaced apart from each other and are aligned along the Y direction. Thesecond portion212 and thefifth portion215 are not aligned along the Y direction, and thefirst portion211 and thesixth portion216 are not aligned along the Y direction either. The recessedportion22 has first to ninth side surfaces10A1 to10A9 that are defined by thesilicon substrate10 below the first toninth portions211 to219, respectively.
• In a similar manner to the manufacturing step shown inFIG. 5, the doped channel regions5 are formed by implanting p-type impurity ions231,232 in the Y direction from diagonally above while an implant angle α of the ion implantation is controlled within a range tan−1(W2/T)<α≦tan−1 (W1/T), with thesilicon oxide film20 and thesilicon nitride film21 having been formed. As a result, the doped channel regions5 are formed, of the second side surface10A2 and the third side surface10A3, only in the second side surface10A2, of the fourth side surface10A4 and the fifth side surface10A5, only in the fifth side surface10A5, and of the eighth side surface10A8 and the ninth side surface10A9, only in the eighth side surface10A8.
• Referring toFIG. 15, after a transistor structure similar to that ofFIG. 2 is obtained, a silicon nitride film is entirely formed by a CVD technique. Next, the silicon nitride film is etched back by an anisotropic dry etching technique, thereby formingsidewalls37 and43. This providesgate structures35 and36 havingsilicon oxide films33 and39,conductive films34 and40,silicon nitride films35 and41, insulatingfilms36 and42, and thesidewalls37 and43, respectively.
• Next, referring toFIG. 16, asilicon oxide film44 doped with an impurity such as B or P is entirely formed by a coating technique or a CVD technique so as to cover thegate structures35 and36. Subsequently, annealing is performed in an O2, N2, or H2 atmosphere. Then, contact holes respectively connected to thesource regions5S,6S and thedrain region56D are formed in thesilicon oxide film44 by a photolithography technique and an anisotropic dry etching technique. Thereafter, contact plugs30 to32 respectively connected to thesource regions5S,6S and thedrain region56D are formed by filling up the contact holes with a polysilicon film doped with an impurity such as P, As, or Sb.
• Next, referring toFIG. 17, asilicon oxide film45 is entirely formed by a CVD technique. Then, a contact hole connected to thecontact plug32 is formed in thesilicon oxide film45 by a photolithography technique and an anisotropic dry etching technique. Thereafter, abit line48 connected to thecontact plug32 is formed by filling up the contact hole with abarrier metal film46 of TiN, TaN, WN, TiSi2, COSi2 or the like, and ametal film47 of W, Ti, Cu, Al, or the like.
• Subsequently, referring toFIG. 18, asilicon oxide film49 is entirely formed by a CVD technique. Then, contact holes respectively connected to the contact plugs30 and31 are formed in thesilicon oxide films45 and49 by a photolithography technique and an anisotropic dry etching technique. Next, contact plugs50 and51 respectively connected to the contact plugs30 and31 are formed by filling the contact holes with a polysilicon film doped with an impurity such as P, As, or Sb. Depending upon the material of which a later-formed capacitor lower electrode is formed, the material of the contact plugs50 and51 may be Ti, W, TiN, WN, TaN, or the like.
• Then, referring toFIG. 19, asilicon oxide film56 is entirely formed by a CVD technique. Thereafter, recesses respectively connected to contactplugs50 and51 are formed in thesilicon oxide film56 by a photolithography technique and an anisotropic dry etching technique. Subsequently, a polysilicon film doped with an impurity such as P, As, or Sb is entirely formed by a CVD technique. Then, the polysilicon film is polished by a CMP technique until an upper surface of thesilicon oxide film56 is exposed. This formspolysilicon films52 and53 respectively connected to the contact plugs50 and51. Thepolysilicon films52 and53 function as capacitor lower electrodes. It should be noted, however, that a metal film of Ti, W, TiN, WN, Pt, Ru, or the like may be formed in place of thepolysilicon films52 and53.
• Next, thesilicon oxide film56 is removed by an etching technique using HF. It should be noted, however, that a lower portion of thesilicon oxide film56 may be left unremoved in order to prevent thepolysilicon films52 and53 from collapsing due to mechanical stress during the process. Subsequently, an insulatingfilm54 of SiO2, Si3N4, Ta2O5, Al2O3, HfO, or the like is entirely formed. The insulatingfilm54 functions as a capacitor dielectric film. Then, aconductive film55 of polysilicon, Ti, W, TiN, WN, Pt, Ru, or like is entirely formed. Theconductive film55 functions as a capacitor upper electrode. With the manufacturing steps described above, a structure shown inFIG. 13 is obtained.
• Thus, with the method of manufacturing the semiconductor device according to the second preferred embodiment, it is possible to suppress reduction in the threshold voltage of memory cell transistors and the occurrence of the inverse narrow width effect, for the same reasons as those in the foregoing first preferred embodiment.
• Moreover, because the doped channel regions5 are not formed in thesource regions5S and6S, the n-type source regions5S and6S do not suffer from reduction in the impurity concentration arising from the formation of the p-type doped channel regions5. Therefore, the contact resistance between therespective source regions5S,6S and the contact plugs30,31 do not increase, and consequently, degradation in data write characteristics can be avoided. Furthermore, degradation in refresh characteristics can be avoided because the electric field strength of thesource regions5S and6S does not become high.
Third Preferred Embodiment
• FIGS. 20 and 21 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a third preferred embodiment of the present invention. First, a structure shown inFIG. 8 is obtained through the manufacturing steps similar to those in the foregoing first preferred embodiment. Next, thesilicon oxide film20 is removed using an aqueous solution of HF or the like. Then, referring toFIG. 20, thesilicon oxide films151 and152 functioning as the gate insulating film are formed on the upper surface of thesilicon substrate10 that is in the element forming regions AR1 and AR2. Subsequently, theconductive film16 is formed on thesilicon oxide films151 and152 as well as on the element isolatinginsulation film4 by a CVD technique or the like. Thereafter, thesilicon nitride film17 is formed on theconductive film16 by a CVD technique or the like.
• Next, referring toFIG. 21, an impurity such as B is ion-implanted intosilicon substrate10 through thesilicon nitride film17, theconductive film16, and thesilicon oxide film151 and152. This forms a p-type well region11. Then, an impurity such as B, BF2, or In is ion-implanted into thesilicon substrate10 through thesilicon nitride film17, theconductive film16, and thesilicon oxide films151 and152. This forms the p-typechannel cut region12. Subsequently, an impurity such as B, BF2, or In is ion-implanted into thesilicon substrate10 through thesilicon nitride film17, theconductive film16, and thesilicon oxide films151 and152. This forms the p-type dopedchannel regions1C and2C. Thereafter, the above-mentioned impurities that have been ion-implanted in thesilicon substrate10 are activated by carrying out a heat treatment.
• Next, thesilicon nitride film17 is patterned by a photolithography technique and an anisotropic dry etching technique. Subsequently, using thesilicon nitride film17 as an etch mask, theconductive film16 is etched by an anisotropic dry etching technique. Then, an insulating film18 is formed by oxidizing theconductive film16 with a lamp oxidation technique or the like. Thereafter, the n-type source regions1S and2S as well as the n-type drain regions1D and2D are formed in the upper surface of thesilicon substrate10 by ion-implanting an impurity such as P, As, or Sb using thesilicon nitride film17 as an implant mask. With the manufacturing steps described above, a structure shown inFIG. 2 is obtained.
• As described above, in the method of manufacturing the semiconductor device according to the third preferred embodiment, thesilicon oxide films151 and152, which function as the gate insulating films, are formed in the manufacturing step shown inFIG. 20. Thereafter, the dopedchannel regions1C and2C are formed in the manufacturing step shown inFIG. 21. Consequently, the impurity contained in the dopedchannel regions1C and2C is not absorbed in the gate insulating films by the heat treatment for forming the gate insulating films. As a result, it is possible to avoid the reduction in threshold voltage and the occurrence of the inverse narrow width effect that are caused by reduction in the impurity concentration in the dopedchannel regions1C and2C.
• Accordingly, when forming the dopedchannel regions1C and2C, it is unnecessary to ion-implant a p-type impurity at a higher concentration than a desired value; therefore, it is possible to avoid degradations in data write characteristics and refresh characteristics.
• It should be noted that in the third preferred embodiment, the above-described advantageous effects may be obtained even without forming the dopedchannel regions51 and52, but it is more effective if the dopedchannel regions51 and52 are formed.
Fourth Preferred Embodiment
• FIGS. 22 and 23 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a fourth preferred embodiment of the present invention. First, a structure shown inFIG. 15 is obtained through the manufacturing steps similar to those in the foregoing second preferred embodiment. Next, referring toFIG. 22, asilicon oxide film44 is entirely formed by a CVD technique or the like so as to cover thegate structures35 and36. Subsequently, contact holes60,62, and61 respectively connected to thesource regions5S and6S and thedrain region56D are formed in thesilicon oxide film44 by a photolithography technique and an anisotropic dry etching technique.
• Next, referring toFIG. 23, aphotoresist63 having such a pattern that portions thereof that are above the contact holes60 and62 are opened is formed by a photolithography technique. Then, using thephotoresist63 as an implant mask, an impurity such as P, As, or Sb is ion-implanted at a concentration of about 1E12/cm2 to 1E14/cm2. This forms n-type impurity-introducedregions100 in the respective upper surfaces of thesource regions5S and6S. Next, thephotoresist63 is removed. Then, contact plugs30 to32 are formed by filling the contact holes60 to62 with a polysilicon film doped with an impurity such as P, As, or Sb. From this point on, the processes that follow the step shown inFIG. 17 are performed, thus completing a semiconductor device.
• As described above, with the method of manufacturing the semiconductor device according to the fourth preferred embodiment, the electric field strength of thesource regions5S and6S can be further lowered in comparison with the second preferred embodiment by forming the impurity-introducedregions100 in the upper surfaces of thesource regions5S and6S. As a consequence, device characteristics such as refresh characteristics and hot carrier characteristics can be further improved, which accordingly enhances device reliability. Moreover, since the impurity-introducedregions100 are formed only in thesource regions5S and6S, degradation in short channel characteristics of the memory cell transistors can be avoided.
Fifth Preferred Embodiment
• FIG. 24 is a top plan view showing a structure of a semiconductor device according to a fifth preferred embodiment of the present invention.FIG. 25 is a cross-sectional view showing a cross-sectional structure concerning a position along the line XXV-XXV shown inFIG. 24. Referring toFIG. 24, a plurality of element forming regions AR (denoted by reference characters ARa to ARe inFIG. 24) are defined by the element isolatinginsulation film4. The element forming region ARa and the element forming region ARb, which belong to a common row in a memory cell array, and the element forming region ARd and the element forming region ARe, which belong to a common row, are each mutually spaced apart and aligned along the X direction. Referring toFIGS. 24 and 25, in each of the element forming regions AR, impurity-introducedregions70 and73 are formed in ends of thesource regions5S and6S with respect to the X direction. It should be noted that the doped channel regions5 may be formed in each of the element forming regions AR, as in the foregoing second preferred embodiment.
• FIGS. 26 and 27 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing the semiconductor device according to the fifth preferred embodiment of the present invention. First, referring toFIG. 26, thesilicon oxide film20 and thesilicon nitride film21 are formed in a similar manner to the foregoing first preferred embodiment. In addition, a recessedportion22ais formed in the upper surface of thesilicon substrate10 by overetching in the etching for patterning thesilicon oxide film20 and thesilicon nitride film21.
• Next, referring toFIG. 27, with thesilicon oxide film20 and thesilicon nitride film21 having been formed,ions76 and77 of an n-type impurity such as P, As, or Sb are implanted at a concentration of about 1E12/cm2 to 1E14/cm2, in the X direction from diagonally above. The ion implantation is sequentially carried out in opposing directions +X and −X, as indicated by arrows X1 and X2 inFIG. 24.
• As for implant angle .beta. of the ion implantation (that is, an angle formed by an implant direction of theimpurity ions76,77 and a direction of the normal to the upper surface of the silicon substrate10), an implant angle is adopted that satisfies the relationship tan−1 (V/U)≦beta≦tan−1 (V/T), where V is the interval between thesilicon nitride films21 adjacent to each other along the X direction, T is the total film thickness of thesilicon oxide film20 and thesilicon nitride film21, U is the depth from the upper surface of thesilicon nitride film21 to the bottom surface of the recessedportion22a. For one example, the interval V is about 390 nm, and the depth U is about 170 nm.
• When the implant angle .beta. is controlled within that range, theimpurity ions76 and77 are implanted into portions of the side surfaces of the recessedportion22athat are perpendicular to the X direction. For example, of the side surface of the recessedportion22athat corresponds to the third side surface10A3 shown inFIG. 14,impurity ions76 and77 are implanted into a portion perpendicular to the X direction. As result, as shown inFIG. 27, n-type impurity-introducedregions70 and73 are formed within the upper surface of thesilicon substrate10 that is in the element forming regions ARd and ARe, respectively. Meanwhile, because the ion implantation is performed in the X direction from diagonally above,impurity ions76 and77 are not implanted in portions of the side surfaces of the recessedportion22athat are perpendicular to the Y direction.
• Thereafter, the recessedportion22 is formed and the asilicon oxide film13 is formed on the side surfaces and the bottom surface of the recessedportion22, followed by performing the processes subsequent to the manufacturing step shown inFIG. 6, as in the second preferred embodiment; thus, a semiconductor device is completed.
• As described above, in the method of manufacturing the semiconductor device according to the fifth preferred embodiment, the impurity-introducedregions70 and73 are respectively formed within the upper surface of thesilicon substrate10 that is in the element forming regions AR. Therefore, even if crystal defects are caused in thesilicon substrate10 due to damages arising from, for example, the etching for forming the recessedportion22, the crystal defects can be covered by the impurity-introducedregions70 and73. As a result, leakage current resulting from the crystal defects can be suppressed, and refresh characteristics can therefore be improved.
• Moreover, the impurity-introducedregions70 and73 are formed only in portions of thesource regions5S and6S that are in the vicinity of their interfaces with the element isolatinginsulation film4, and therefore, it is possible to avoid degradation in short channel characteristics of memory cell transistors.
Sixth Preferred Embodiment
• FIGS. 28 through 31 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a sixth preferred embodiment of the present invention.FIGS. 28 to 31 show a structure of a memory cell array section in thesilicon substrate10, in which a memory cell array is formed, and a structure of a peripheral circuit section therein, in which a peripheral circuit is formed. The following describes an example in which p-channel MOSFETs are formed in the peripheral circuit section.
• First, referring toFIG. 28, thesilicon oxide film20, thesilicon nitride film21, the recessedportion22, and thesilicon oxide film13 are formed in the memory cell array section and the peripheral circuit section in a similar manner to the foregoing first preferred embodiment. In addition, the dopedchannel regions51 and52 are formed in the memory cell array section. Next, a photoresist80 that covers the peripheral circuit section is formed by a photolithography technique. Then, using the photoresist80 as an implant mask, ions of an impurity such as B or In are implanted into thesilicon substrate10 in a direction perpendicular to the upper surface of thesilicon substrate10 through the recessedportion22 and thesilicon oxide film13. This forms a p-typechannel cut region81 in the bottom surface of the recessedportion22 that is in the memory cell array section.
• Next, referring toFIG. 29, after removing the photoresist80, the manufacturing steps shown inFIGS. 6 through 8 are carried out in a similar manner to those in the foregoing first preferred embodiment. Specifically, asilicon oxide film24 having such a film thickness that it can completely fill up the recessedportion22 is entirely formed, and subsequently, thesilicon oxide film24 is polished until the upper surface of thesilicon nitride film21 is exposed; thereafter, thesilicon oxide film24 is removed to a desired film thickness, and then, thesilicon nitride film21 is removed.
• Then, referring toFIG. 30, aphotoresist82 that covers the peripheral circuit section is formed by a photolithography technique. Thereafter, the p-type dopedchannel regions1C and2C as well as the p-type well region11 are formed within thesilicon substrate10 that is in the memory cell array section by implanting ions of a p-type impurity, using thephotoresist82 as an implant mask.
• Next, referring toFIG. 31, after removing thephotoresist82, aphotoresist83 that covers the memory cell array section is formed by a photolithography technique. Then, n-type dopedchannel regions86, an n-typechannel cut region85, and an n-type well region84 are formed in thesilicon substrate10 that is in the peripheral circuit section by ion-implanting an n-type impurity using thephotoresist83 as an implant mask.
• After removing thephotoresist83, the processes subsequent to the manufacturing step shown inFIG. 10 are performed in a similar manner to the foregoing second preferred embodiment, thus completing a semiconductor device.
• As described above, in the method of manufacturing the semiconductor device according to the sixth preferred embodiment, the channel cutregions81 are formed only within the bottom surface of the recessedportion22 in the memory cell array section. In other words, the p-type channel cutregions81 are not formed in portions below the n-type source regions5S and6S. For this reason, the electric field strength of thesource regions5S and6S is further relaxed in comparison with the foregoing second preferred embodiment, and therefore, it becomes possible to improve refresh characteristics.
• Further, the peripheral circuit section is covered by the photoresist80 when performing the ion implantation for forming the channel cutregions81. Therefore, it is possible to avoid formation of unnecessary channel cutregions81 within thesilicon substrate10 that is in the peripheral circuit section.
Seventh Preferred Embodiment
• FIGS. 32 through 35 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a seventh preferred embodiment of the present invention. First, referring toFIG. 32, thesilicon oxide film20, thesilicon nitride film21, the recessedportion22, and thesilicon oxide film13 are formed in the memory cell array section and the peripheral circuit section, in a similar manner to the foregoing first preferred embodiment. In addition, the dopedchannel regions51 and52 are formed in the memory cell array section. Next, an impurity such as B or In is ion-implanted into thesilicon substrate10 in a direction perpendicular to the upper surface of thesilicon substrate10 through the recessedportion22 and thesilicon oxide film13. This forms p-type channel cutregions81 and90 within the bottom surface of the recessedportion22 that is in the memory cell array section and in the peripheral circuit section.
• Next, referring toFIG. 33, the manufacturing steps shown inFIGS. 6 through 8 are carried out in a similar manner to that in the foregoing first preferred embodiment. Specifically, asilicon oxide film24 having such a film thickness that it can completely fill up the recessedportion22 is entirely formed. Then, thesilicon oxide film24 is polished until the upper surface of thesilicon nitride film21 is exposed; thereafter thesilicon oxide film24 is removed to a desired film thickness, and then, thesilicon nitride film21 is removed.
• Subsequently, referring toFIG. 34, aphotoresist91 that covers the peripheral circuit section is formed by a photolithography technique. Then, the p-type dopedchannel regions1C,2C, and the p-type well region11 are formed within thesilicon substrate10 that is in the memory cell array section, by ion-implanting a p-type impurity using thephotoresist91 as an implant mask.
• Then, referring toFIG. 35, after removing thephotoresist91, aphotoresist92 that covers the memory cell array section is formed by a photolithography technique. Next, by ion-implanting an n-type impurity using thephotoresist92 as an implant mask, an n-type dopedchannel region86, an n-typechannel cut region93, and an n-type well region84 within thesilicon substrate10 that is in the peripheral circuit section. In the ion implantation for forming the channel cutregions93, the impurity concentration is set to be about two times the normal concentration. Thereby, the p-type channel cutregions90 are cancelled out by the n-type channel cutregions93.
• After removing thephotoresist92, the processes subsequent to the manufacturing steps shown inFIG. 10 are performed in a similar manner to those in the foregoing second preferred embodiment, thus completing a semiconductor device.
• As described above, with the method of manufacturing a semiconductor according to the seventh preferred embodiment, the electric field strength of thesource regions5S and6S can be relaxed for the same reasons as in the foregoing sixth preferred embodiment, and therefore, refresh characteristics can be improved.
• In addition, the photoresist80 shown inFIG. 28 is unnecessary, and consequently, the number of required photomasks can be reduced in comparison with the foregoing sixth preferred embodiment.
Eighth Preferred Embodiment
• FIG. 36 is a top plan view showing a structure of a semiconductor device according to an eighth preferred embodiment of the present invention. Thesilicon substrate10 has a memorycell array section95 and aperipheral circuit section96. InFIG. 36, the boundary between the memorycell array section95 and theperipheral circuit section96 is denoted by ahypothetical line97. In the memorycell array section95, a plurality of element forming regions AR are defined by the element isolatinginsulation film4, and two memory cells are provided in each one of the element forming regions AR. In the eighth preferred embodiment, among a plurality of memory cells that constitute the memory cell array, at least a plurality of memory cells that are arranged in an outermost periphery of the memory cell array are set as dummy cells. Those memory cells that are set as dummy cells do not function as DRAM cells because the contact plugs30 to32 are not formed therein.
• In the method of manufacturing the semiconductor device according to the second preferred embodiment, locations in which the doped channel regions5 are to be formed are determined by utilizing the shadowing effect of thesilicon nitride film21 formed on the element forming regions AR adjacent to each other along the Y direction. For this reason, the shadowing effect of thesilicon nitride film21 cannot be utilized for the element forming regions AR11, AR12, and AR13 that are located on ends along the Y direction in the memorycell array section95, and consequently, the doped channel regions5 cannot be formed at desired locations. Therefore, it is essential that the memory cells formed in the element forming regions AR11, AR12, and AR13 be set as dummy cells.
• Likewise, in the method of manufacturing the semiconductor device according to the foregoing fifth preferred embodiment, the impurity-introducedregions70 and73 are formed by the ion implantation in the X direction from diagonally above. For this reason, it may be possible that, due to the structure of theperipheral circuit section96 or the like, the impurity-introducedregions70 and73 are not formed for the element forming regions AR11, AR31, and AR51 that locate on ends with respect to the X direction in the memorycell array section95. Therefore, it is inevitable that, of the two memory cells formed in each of the element forming regions AR11, AR31, and AR51, one that is at the outermost periphery side be set as a dummy cell.
• Thus, in the method of manufacturing the semiconductor device according to the eighth preferred embodiment, at least a plurality of memory cells that are arranged in the outermost periphery of the memory cell array are set as dummy cells. This makes it possible to avoid beforehand degradation in performance and reliability of a semiconductor device caused by the doped channel regions5 or the impurity-introducedregions70 and73 being not formed in desired locations.
• While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous other modifications and variations can be devised without departing from the scope of the invention.

Claims (7)

1. A method of manufacturing a semiconductor device having transistor formed on an element forming region defined by a trench isolation region, comprising:

(a) forming a first insulating film on a main surface of a semiconductor substrate;

(b) forming a conductive film on said first insulating film;

(c) implanting first impurity ions into said main surface through said conductive film and said first insulating film to form doped channel regions of a first conductivity type;

(d) patterning said conductive film to form a gate electrode; and

(e) implanting second impurity ions into said main surface that is exposed from said gate electrode to form source and drain regions of a second conductivity type.

2. The method according toclaim 1, further comprising:

(f) forming a second insulating film on said conductive film, said step (f) being performed between said steps (b) and (c);

(g) patterning said second insulating film, said step (g) being performed between said steps (c) and (d), wherein:

in said step (c), said first impurity ions are implanted into said main surface through said second insulating film, said conductive film and said first insulating film, and

in said step (d), said conductive film is patterned by an etch technique using said second insulating film patterned in said step (g) as an etch mask.

3. The method according toclaim 1, wherein:

in said step (a), said first insulating film is formed using a lump oxidation apparatus at about 900 to 1100° C.

4. The method according toclaim 1, further comprising:

(h) forming a trench in said main surface;

(i) forming a thermal oxidation film on side surfaces and a bottom surface of said trench by a thermal oxidation technique at about 900 to 1150° C., using a single wafer-type lamp oxidation apparatus; and

(j) forming a third insulation film to fill said trench;

wherein said steps (h), (i) and (j) are performed before said step (a) to form said trench isolation region.

5. The method according toclaim 1, wherein said step (c) further includes:

(c-1) implanting third impurity ions into said main surface deeper than a bottom of said trench isolation region through said conductive film and said first insulating film to form channel well regions of said first conductivity type;

(c-2) implanting fourth impurity ions into said main surface so as to contact said bottom of said trench isolation region through said conductive film and said first insulating film to form channel cut regions of said first conductivity type.

6. The method according toclaim 5, wherein in said step (c) said first, second and third impurity ions are implanted substantially in a same region in plane view.

7. The method according toclaim 1, further comprising:

(k) forming an interlayer insulation film after said step (e);

(l) forming a contact hole connected to said source and drain regions in said interlayer insulation film;

(m) forming a conductive plug in said contact hole;

(n) forming a lower electrode of a capacitor over said conductive plug,

(o) forming a dielectric film on said lower electrode; and

(p) forming an upper electrode of said capacitor on said dielectric film.

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