US20100187643A1 - Method for tuning the threshold voltage of a metal gate and high-k device - Google Patents
Method for tuning the threshold voltage of a metal gate and high-k deviceDownload PDFInfo
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- US20100187643A1 US20100187643A1US12/359,434US35943409AUS2010187643A1US 20100187643 A1US20100187643 A1US 20100187643A1US 35943409 AUS35943409 AUS 35943409AUS 2010187643 A1US2010187643 A1US 2010187643A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
- H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
Definitions
- the present inventionrelates generally to a semiconductor device and method of forming the same and, more specifically, to metal gate and high dielectric constant (high-k) devices.
- achieving a desired work function of a gate material for n-FET and p-FET CMOS devices to meet an operating voltage requirementis achieved by heavy doping of poly-Si, an acceptor dopant for p-FET and a donor for n-FET.
- a high-k dielectric/metal gate stackdifferent metal gate materials which possess the desired work function are used for n-FET and p-FET devices. Since the work function of the metal gate material depends on the high-k gate dielectric and processing conditions, selection of suitable gate materials presents a challenge for process integration. Metal gate work function may also be adjusted by placing cap layers between the metal gate and the high-k gate dielectric.
- the position of the cap layers after thermal processingdetermines the work function and threshold voltage (Vt) of the device. Diffusion of the cap layer through the thin high-k gate dielectric into an interfacial layer during anneals causes degradation of carrier mobility. Attempts to limit diffusion by nitridation of the high-k gate dielectric had limited success.
- a method of forming a deviceincludes depositing an interfacial layer on top of a substrate.
- the methodincludes depositing a high-k dielectric layer on top of the interfacial layer.
- the methodincludes depositing a metal film on top of the high-k dielectric layer.
- the methodincludes depositing a cap layer on top of the metal film.
- the methodfurther includes depositing a metal gate layer on top of the cap layer.
- the methodalso includes performing an activation anneal.
- a devicein a further aspect of the invention, includes a substrate.
- the deviceincludes an interfacial layer on top of the substrate.
- the deviceincludes a high-k dielectric layer on top of the interfacial layer.
- the deviceincludes a metal film on top of the high-k dielectric layer.
- the devicefurther includes a cap layer on top of the metal film.
- the devicealso includes a metal gate layer on top of the cap layer.
- FIG. 1shows a starting structure and processing steps in accordance with an embodiment of the invention
- FIGS. 2-4show processing steps and intermediate structures in accordance with an embodiment of the invention.
- FIG. 5shows processing steps and a final structure in accordance with an embodiment of the invention.
- FIG. 1shows a starting structure and processing steps in accordance with an embodiment of the invention.
- a substrate 100is cleaned by conventional processes.
- Substrate 100may be a Si wafer.
- An interfacial layer 110is formed on substrate 100 .
- Interfacial layer 110may be formed by thermal oxidation or any known or later developed processes.
- Interfacial layer 110may include, but is not limited to: oxide, nitride and oxynitride.
- Interfacial layer 110may be formed with or without subsequent nitridation.
- Interfacial layer 110may have a thickness of approximately 1 nm to 7 nm.
- a high-k dielectric layer 120is deposited on top of interfacial layer 110 .
- High-k dielectric layer 120may be deposited by thermal oxidation or any known or later developed processes.
- High-k dielectric layer 120may include, but is not limited to: zirconium oxide (ZrO2), hafnium oxide (HfO2), zirconium silicate (ZrSiO4) and hafnium silicate (HfSiO4).
- High-k dielectric layer 120may be approximately 1 nm to 7 nm thick.
- Metal film 130is deposited on top of high-k dielectric layer 120 .
- Metal film 130may be deposited by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or any known or later developed processes.
- Metal film 130may be approximately 0.1 nm to 10 nm thick.
- Metal film 130may include, but is not limited to: ruthenium (Ru), tungsten (W), tantalum (Ta), titanium (Ti), tantalum nitride (TaN) and titanium nitride (TiN).
- Cap layer 140is deposited on top of metal film 130 .
- Cap layer 140may be deposited by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or any known or later developed processes.
- Cap layer 140may have a thickness of approximately 0.1 nm to 5 nm.
- Cap layer 140may include, but is not limited to metal oxides (MOx), metal nitrides (MNx) and pure metals.
- MOxmay include, but is not limited to: tantalum oxide (TaOx) and titanium oxide (TiOx).
- MNxmay include, but is not limited to tantalum nitride (TaNx) and titanium nitride (TiNx).
- Pure metalsmay include, but are not limited to: tungsten (W), tantalum (Ta) and titanium (Ti).
- FIG. 5shows processing steps and a final structure in accordance with an embodiment of the invention.
- a metal gate layer 150is deposited on top of cap layer 140 .
- Metal gate layer 150may be deposited by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or any known or later developed processes.
- Metal gate layer 150has a thickness of approximately 0.1 nm to 10 nm.
- Metal film 130 and metal gate layer 150may be the same or different.
- a gateis comprised of metal film 130 , cap layer 140 and metal gate layer 150 .
- Poly-Simay be deposited on top of the gate (not shown).
- the gatemay be patterned. Spacers 160 may be formed along with active device regions (not shown). Thermal processing leads to diffusion of cap layer 140 .
- the optimum location of species of a cap layer with respect to gate dielectricleads to setting up a desired work function of the metal gate and thus desired threshold voltage (Vt) of the device
- the thickness of metal film 130 and cap layer 140may be tuned so that a target concentration of a cap layer material is present at an interface of metal film 130 and high-k dielectric layer 120 after activation anneal without allowing the cap layer material to diffuse close to the Si in substrate 100 .
- the target concentrationmay be approximately 0.1% to 10%.
- the formerwill lead to desired threshold voltage (Vt).
- Vtthreshold voltage
- placing the cap layer 140 away from the interface of metal film 130 and high-k dielectric layer 120allows for the deposition of thicker cap layers then currently employed, making the process more manufacturable.
- the method as described aboveis used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chipscan be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chipis mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chipis then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end productcan be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
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Abstract
Description
- The present invention relates generally to a semiconductor device and method of forming the same and, more specifically, to metal gate and high dielectric constant (high-k) devices.
- In devices with poly-Si gates, achieving a desired work function of a gate material for n-FET and p-FET CMOS devices to meet an operating voltage requirement is achieved by heavy doping of poly-Si, an acceptor dopant for p-FET and a donor for n-FET. In a high-k dielectric/metal gate stack, different metal gate materials which possess the desired work function are used for n-FET and p-FET devices. Since the work function of the metal gate material depends on the high-k gate dielectric and processing conditions, selection of suitable gate materials presents a challenge for process integration. Metal gate work function may also be adjusted by placing cap layers between the metal gate and the high-k gate dielectric. The position of the cap layers after thermal processing determines the work function and threshold voltage (Vt) of the device. Diffusion of the cap layer through the thin high-k gate dielectric into an interfacial layer during anneals causes degradation of carrier mobility. Attempts to limit diffusion by nitridation of the high-k gate dielectric had limited success.
- In a first aspect of the invention, a method of forming a device includes depositing an interfacial layer on top of a substrate. The method includes depositing a high-k dielectric layer on top of the interfacial layer. The method includes depositing a metal film on top of the high-k dielectric layer. The method includes depositing a cap layer on top of the metal film. The method further includes depositing a metal gate layer on top of the cap layer. The method also includes performing an activation anneal.
- In a further aspect of the invention, a device includes a substrate. The device includes an interfacial layer on top of the substrate. The device includes a high-k dielectric layer on top of the interfacial layer. The device includes a metal film on top of the high-k dielectric layer. The device further includes a cap layer on top of the metal film. The device also includes a metal gate layer on top of the cap layer.
- The present invention is described in the detailed description below, in reference to the accompanying drawings that depict non-limiting examples of exemplary embodiments of the present invention.
FIG. 1 shows a starting structure and processing steps in accordance with an embodiment of the invention;FIGS. 2-4 show processing steps and intermediate structures in accordance with an embodiment of the invention; andFIG. 5 shows processing steps and a final structure in accordance with an embodiment of the invention.FIG. 1 shows a starting structure and processing steps in accordance with an embodiment of the invention. Asubstrate 100 is cleaned by conventional processes.Substrate 100 may be a Si wafer. Aninterfacial layer 110 is formed onsubstrate 100.Interfacial layer 110 may be formed by thermal oxidation or any known or later developed processes.Interfacial layer 110 may include, but is not limited to: oxide, nitride and oxynitride.Interfacial layer 110 may be formed with or without subsequent nitridation.Interfacial layer 110 may have a thickness of approximately 1 nm to 7 nm.- Referring to
FIG. 2 , a high-kdielectric layer 120 is deposited on top ofinterfacial layer 110. High-kdielectric layer 120 may be deposited by thermal oxidation or any known or later developed processes. High-kdielectric layer 120 may include, but is not limited to: zirconium oxide (ZrO2), hafnium oxide (HfO2), zirconium silicate (ZrSiO4) and hafnium silicate (HfSiO4). High-kdielectric layer 120 may be approximately 1 nm to 7 nm thick. - Referring to
FIG. 3 , ametal film 130 is deposited on top of high-kdielectric layer 120.Metal film 130 may be deposited by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or any known or later developed processes.Metal film 130 may be approximately 0.1 nm to 10 nm thick.Metal film 130 may include, but is not limited to: ruthenium (Ru), tungsten (W), tantalum (Ta), titanium (Ti), tantalum nitride (TaN) and titanium nitride (TiN). - Referring to
FIG. 4 , acap layer 140 is deposited on top ofmetal film 130.Cap layer 140 may be deposited by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or any known or later developed processes.Cap layer 140 may have a thickness of approximately 0.1 nm to 5 nm.Cap layer 140 may include, but is not limited to metal oxides (MOx), metal nitrides (MNx) and pure metals. MOx may include, but is not limited to: tantalum oxide (TaOx) and titanium oxide (TiOx). MNx may include, but is not limited to tantalum nitride (TaNx) and titanium nitride (TiNx). Pure metals may include, but are not limited to: tungsten (W), tantalum (Ta) and titanium (Ti). FIG. 5 shows processing steps and a final structure in accordance with an embodiment of the invention. Ametal gate layer 150 is deposited on top ofcap layer 140.Metal gate layer 150 may be deposited by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or any known or later developed processes.Metal gate layer 150 has a thickness of approximately 0.1 nm to 10 nm.Metal film 130 andmetal gate layer 150 may be the same or different. A gate is comprised ofmetal film 130,cap layer 140 andmetal gate layer 150. Poly-Si may be deposited on top of the gate (not shown). The gate may be patterned.Spacers 160 may be formed along with active device regions (not shown). Thermal processing leads to diffusion ofcap layer 140. The optimum location of species of a cap layer with respect to gate dielectric leads to setting up a desired work function of the metal gate and thus desired threshold voltage (Vt) of the device without compromising carrier mobility.- The thickness of
metal film 130 andcap layer 140 may be tuned so that a target concentration of a cap layer material is present at an interface ofmetal film 130 and high-kdielectric layer 120 after activation anneal without allowing the cap layer material to diffuse close to the Si insubstrate 100. The target concentration may be approximately 0.1% to 10%. The former will lead to desired threshold voltage (Vt). The latter will eliminate degradation of carrier mobility. Additionally, placing thecap layer 140 away from the interface ofmetal film 130 and high-k dielectric layer 120 allows for the deposition of thicker cap layers then currently employed, making the process more manufacturable. - The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (25)
1. A method of forming a device, comprising:
depositing an interfacial layer on top of a substrate;
depositing a high-k dielectric layer on top of the interfacial layer;
depositing a metal film on top of the high-k dielectric layer;
depositing a cap layer on top of the metal film;
depositing a metal gate layer on top of the cap layer; and
performing an activation anneal, wherein the thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer after the performing step without allowing the cap layer material to diffuse close to the substrate, wherein the target concentration is approximately 0.1% to 10%.
2. A method according toclaim 1 , wherein the interfacial layer is deposited by thermal oxidation.
3. A method according toclaim 2 , wherein the interfacial layer is selected from the group consisting of: oxide, nitride and oxynitride.
4. A method according toclaim 3 , wherein the interfacial layer has a thickness of approximately 1 nm to 7 nm.
5. A method according toclaim 1 , wherein the high-k dielectric layer is deposited by thermal oxidation.
6. A method according toclaim 5 , wherein the high-k dielectric layer is selected from the group consisting of: zirconium oxide (ZrO2), hafnium oxide (HfO2), zirconium silicate (ZrSiO4) and hafnium silicate (HfSiO4).
7. A method according toclaim 6 , wherein the high-k dielectric layer has a thickness of approximately 1 nm to 7 nm.
8. A method according toclaim 1 , wherein the metal film has a thickness of approximately 0.1 nm to 10 nm.
9. A method according toclaim 8 , wherein the metal film is deposited by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
10. A method according toclaim 9 , wherein the metal film is selected from the group consisting of: ruthenium (Ru), tungsten (W), tantalum (Ta), titanium (Ti), tantalum nitride (TaN) and titanium nitride (TiN).
11. A method according toclaim 1 , wherein the cap layer is deposited on top of the metal film by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
12. A method according toclaim 11 , wherein the cap layer is selected from the group consisting of: metal oxides (MOx), metal nitrides (MNx) and pure metals.
13. A method according toclaim 12 , wherein the cap layer has a thickness of approximately 0.1 nm to 5 nm.
14. A method according toclaim 1 , wherein the metal gate layer is deposited by physical vapor deposition (PVD), metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
15. A method according toclaim 14 , wherein the metal gate layer has thickness of approximately 0.1 nm to 10 nm.
16. A method according toclaim 15 , wherein the metal film and the metal gate layer are the same material.
17. (canceled)
18. A device, comprising:
a substrate;
an interfacial layer on top of the substrate;
a high-k dielectric layer on top of the interfacial layer;
a metal film on top of the high-k dielectric layer;
a cap layer on top of the metal film; and
a metal gate layer on top of the cap layer, wherein a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer, wherein the target concentration is approximately 0.1% to 10%.
19. A device according toclaim 18 , wherein the interfacial layer is selected from the group consisting of: oxide, nitride and oxynitride.
20. A device according toclaim 18 , wherein the high-k dielectric layer is selected from the group consisting of: zirconium oxide (ZrO2), hafnium oxide (HfO2), zirconium silicate (ZrSiO4) and hafnium silicate (HfSiO4).
21. A device according toclaim 18 , wherein the metal film is selected from the group consisting of: ruthenium (Ru), tungsten (W), tantalum (Ta), titanium (Ti), tantalum nitride (TaN) and titanium nitride (TiN).
22. A device according toclaim 18 , wherein the cap layer is selected from the group consisting of: metal oxides (MOx), metal nitrides (MNx) and pure metals.
23. A device according toclaim 18 , wherein metal film and the metal gate layer are the same material.
24. A device according toclaim 18 , wherein the interfacial layer has a thickness of approximately 1 nm to 7 nm, the high-k dielectric layer has a thickness of approximately 1 nm to 7 nm, the metal film has a thickness of approximately 0.1 nm to 10 nm, the cap layer has a thickness of approximately 0.1 nm to 5 nm and the metal gate layer has thickness of approximately 0.1 nm to 10 nm.
25. (canceled)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/359,434US7754594B1 (en) | 2009-01-26 | 2009-01-26 | Method for tuning the threshold voltage of a metal gate and high-k device |
| TW099101612ATW201044465A (en) | 2009-01-26 | 2010-01-21 | Method for tuning the threshold voltage of a metal gate and high-k device |
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| US12/359,434US7754594B1 (en) | 2009-01-26 | 2009-01-26 | Method for tuning the threshold voltage of a metal gate and high-k device |
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| US20100187643A1true US20100187643A1 (en) | 2010-07-29 |
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| US8420473B2 (en) | 2010-12-06 | 2013-04-16 | International Business Machines Corporation | Replacement gate devices with barrier metal for simultaneous processing |
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- 2009-01-26USUS12/359,434patent/US7754594B1/ennot_activeExpired - Fee Related
- 2010
- 2010-01-21TWTW099101612Apatent/TW201044465A/enunknown
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| US8367496B2 (en) | 2009-06-18 | 2013-02-05 | International Business Machines Corporation | Scavanging metal stack for a high-k gate dielectric |
| US9105745B2 (en) | 2009-06-18 | 2015-08-11 | International Business Machines Corporation | Fabrication of low threshold voltage and inversion oxide thickness scaling for a high-k metal gate p-type MOSFET |
| US8420473B2 (en) | 2010-12-06 | 2013-04-16 | International Business Machines Corporation | Replacement gate devices with barrier metal for simultaneous processing |
| CN102842618A (en)* | 2011-06-24 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| WO2012174770A1 (en)* | 2011-06-24 | 2012-12-27 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| US8673701B2 (en) | 2011-06-24 | 2014-03-18 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor structure and method for manufacturing the same |
| US8853751B2 (en) | 2012-06-28 | 2014-10-07 | International Business Machines Corporation | Reducing the inversion oxide thickness of a high-K stack fabricated on high mobility semiconductor material |
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Also Published As
| Publication number | Publication date |
|---|---|
| US7754594B1 (en) | 2010-07-13 |
| TW201044465A (en) | 2010-12-16 |
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