US20100181626A1 - Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates - Google Patents

Abstract

A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap.

Description

• This application claims the benefit of U.S. Provisional Application No. 61/146,202 filed on Jan. 21, 2009, entitled “Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates,” which application is hereby incorporated herein by reference.
CROSS-REFERENCE TO RELATED APPLICATION
• This application relates to commonly-assigned U.S. patent application Ser. No. 12/341,674, filed Dec. 22, 2008, and entitled “N-FET with a Highly Doped Source/Drain and Strain Booster,” which application is hereby incorporated herein by reference.
TECHNICAL FIELD
• This invention relates generally to integrated circuit devices, and more particularly to CMOS devices and methods for forming the same.
BACKGROUND
• Germanium is a commonly known semiconductor material. The electron mobility and hole mobility of germanium are greater than that of silicon, hence making germanium an excellent material in the formation of integrated circuits. However, in the past, silicon gained more popularity since its oxide (silicon oxide) is readily usable in the gate dielectric of metal-oxide-semiconductor (MOS) transistors. The gate dielectrics of the MOS transistors can be conveniently formed by thermal oxidation of silicon substrates. The oxide of germanium, on the other hand, is soluble in water, and hence is not suitable for the formation of gate dielectrics. Particularly, germanium oxides can easily evaporate at temperatures higher than about 430° C., and germanium may easily diffuse to neighboring silicon layers. This poses problems since the manufacturing processes of the MOS transistors often involve annealing temperatures of about 600° C. or above.
• With the use of high-k dielectric materials in the gate dielectrics of MOS transistors, the convenience provided by silicon oxide is no longer a dominating advantage, and hence germanium is reexamined for use in integrated circuits. However, a further challenge faced by the semiconductor industry is that it is difficult to integrate PMOS devices formed on germanium layers or substrates with NMOS devices that are formed on high-electron-mobility materials. Research has been conducted to solve this problem. For example, in one of the proposed solutions, a germanium layer or a compound semiconductor layer formed of group III and group V elements (also known as III-V materials) may be formed on a silicon substrate. A III-V region may further be formed on top of the germanium layer or the compound semiconductor layer for an NMOS device, while a germanium region may be formed on top of the germanium layer or the compound semiconductor layer for a PMOS device. In another proposed solution, a germanium layer is formed on a silicon substrate. A silicon region is then formed on the germanium layer for an NMOS device, and a germanium region is formed on the germanium layer for a PMOS device. However, these solutions face problems such as lattice mismatch between substrates and the materials grown thereon, and increased manufacturing cost due to increased process steps. What is needed, therefore, is a method for overcoming the above-described shortcomings in the prior art.
SUMMARY OF THE INVENTION
• In accordance with one aspect of the present invention, a semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap.
• In accordance with another aspect of the present invention, a semiconductor structure includes a germanium substrate including a top layer formed of substantially pure germanium, wherein the top layer has a first region and a second region. A PMOS device includes a first silicon cap over the first region of the germanium substrate, and a first gate dielectric over the first silicon cap. An NMOS device includes a second silicon cap over the second region of the germanium substrate, and a second gate dielectric over the second silicon cap. A first thickness of the first silicon cap is less than a second thickness of the second silicon cap. The second thickness is less than about 22 mono-layers of silicon (ML).
• In accordance with yet another aspect of the present invention, a method of forming a semiconductor structure includes providing a germanium substrate including a first region and a second region; forming a first silicon cap over the first region of the germanium substrate; and forming a second silicon cap over the second region of the germanium substrate. A first thickness of the first silicon cap is less than a second thickness of the second silicon cap.
• In accordance with yet another aspect of the present invention, a method of forming a semiconductor structure includes providing a germanium substrate including a first region and a second region; masking the second region; selectively growing a first silicon cap from the first region of the germanium substrate; oxidizing a top layer of the first silicon cap to form a silicon oxide layer, wherein the first silicon cap has a first thickness after the step of oxidizing; and selectively growing a second silicon cap from the second region of the germanium substrate. The second silicon cap has a second thickness different from the first thickness. The method further includes forming an NMOS device including forming a first gate dielectric over a thicker silicon cap among the first silicon cap and the second silicon cap; and forming a PMOS device including forming a second gate dielectric over a thinner silicon cap among the first silicon cap and the second silicon cap.
• The advantageous features of the embodiments of the present invention include improved performance for both PMOS and NMOS devices. Adverse effects such as the segregation and the oxidation of germanium are reduced due to the formation of silicon caps.
BRIEF DESCRIPTION OF THE DRAWINGS
• For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
• FIGS. 1 through 12B illustrate cross-sectional views of embodiments of the present invention.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
• The making and using of the embodiments of the present invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
• A method for forming a complementary metal-oxide-semiconductor (CMOS) device is provided. The intermediate stages of manufacturing embodiments of the present invention are illustrated. Throughout various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.
• Referring toFIG. 1,semiconductor substrate20 is provided.Semiconductor substrate20 may be formed of a germanium-containing semiconductor material, which may be expressed as Si_1-xGe_x, wherein x is the atomic percentage of germanium. The materials ofsemiconductor substrate20 may also be pure germanium or substantially pure germanium, for example, with a germanium atomic percentage greater than about 95 percent, or even greater than about 99 percent. Further,semiconductor substrate20 may be a bulk substrate or have a layered structure such as germanium-on-silicon, germanium-on-insulator, or the like.Semiconductor substrate20 includesPMOS region100 andNMOS region200, which may be defined by insulation regions such as shallow trench isolation (STI)region22.
• Referring toFIG. 2,mask layer24, which may comprise silicon oxide or silicon nitride, is formed. In an embodiment,mask layer24 comprises silicon oxide, and may be formed using a chemical vapor deposition (CVD) method. In alternative embodiments,mask layer24 comprises silicon nitride and may be formed using, for example, low-pressure chemical vapor deposition (LPCVD). In yet other embodiments,mask layer24 is formed by thermal nitridation of silicon or plasma anodic nitridation.
• Referring toFIG. 3, the portion ofmask layer24 inNMOS region200 is removed, while the portion ofmask layer24 inPMOS region100 remains un-removed. The removal step may be performed by masking the portion ofmask layer24 inPMOS region100, for example, using a photo resist (not shown), and performing a wet etch on the exposed portion ofmask layer24. The etchant may include hot H₃PO₄ifmask layer24 is formed of silicon nitride. Otherwise, if mask layer is formed of silicon oxide, HF may be used.
• Referring toFIG. 4,silicon cap26 is formed on the exposed surface ofsubstrate20, for example, using selective epitaxial growth (SEG), wherein nosilicon cap26 is formed onmask layer24.Silicon cap26 may include pure silicon or substantially pure silicon, for example, with a silicon atomic percentage greater than about 95 percent, or even greater than about 99 percent, although it may comprise a small amount of other elements, such as germanium. In an embodiment, thickness Tn ofsilicon cap26 is less than about 22 mono-layers (ML, or in other words, includes fewer than about 22 mono-layers of silicon atoms), which is about 18 Å. Thickness Tn may also be between about 12 ML and about 22 ML, although other thicknesses may also be used. It is realized that 22 ML is roughly the maximum thickness of silicon that may be epitaxially grown on germanium without causing relaxation. If the thickness ofsilicon cap26 is greater than about 22 ML, due to the lattice mismatch between silicon and germanium, silicon relaxation may occur, and dislocations will be generated.
• InFIG. 5, a thermal oxidation is performed onsilicon cap26, so that a top layer ofsilicon cap26 is oxidized to formsilicon oxide layer28, although other methods such as deposition may also be used to formsilicon oxide layer28. The lower portion ofsilicon cap26 remains un-oxidized. The oxidation may include, for example, low temperature plasma oxidation, with the temperature being lower than about 300° C. As a result, the amount ofsilicon cap26 consumed in the oxidation may be as few as several mono-layers.
• Referring toFIG. 6, the portion ofmask layer24 inPMOS region100 is removed, followed by the epitaxial growth ofsilicon cap30 onsemiconductor substrate20 inPMOS region100, as shown inFIG. 7.Silicon cap30 may be formed of essentially the same material assilicon cap26, for example, pure silicon or substantially pure silicon. In an embodiment,silicon cap30 has thickness Tp between about 4 ML and about 12 ML, although other thicknesses may also be used.Silicon oxide layer28 is then removed, resulting in the structure as shown inFIG. 8.
• In the structure shown inFIG. 8, silicon caps30 and26 are formed inPMOS region100 andNMOS region200, respectively. The resulting thickness Tn′ ofsilicon cap26 may be between about 8 ML and about 16 ML. Preferably, thickness Tn′ is greater than thickness Tp. In an embodiment, the thickness difference Tn′ Tp may be between about 2 Ml and about 12 ML.
• FIG. 9 illustrates the formation ofgate dielectric layer36. In an embodiment,gate dielectric layer36 is formed of a high-k dielectric material. The exemplary high-k materials may have a k value greater than about 4.0, or even greater than about 7.0, and may include aluminum-containing dielectrics such as Al₂O₃, HfAlO, HfAlON, AlZrO, Hf-containing materials such as HfO₂, HfSiO_x, HfAlO_x, HfZrSiO_x, HfSiON, and other materials such as LaAlO₃and ZrO₂.Gate dielectric layer36 may also include oxides, nitrides, oxynitrides, multi-layers thereof, and combinations thereof.
• In an embodiment in which high-k dielectric materials are used, silicon oxide (SiO₂)interlayer37 may be formed between silicon caps30 and26 and the overlying high-k dielectric material. In the process steps subsequent to the step as shown inFIG. 9, the thicknesses of silicon caps30 and26 may be further reduced. For example, SiO₂interlayer37 may be formed by thermally oxidizing silicon caps30 and26, which may cause the thicknesses of silicon caps30 and26 to be further reduced, for example, by about 2 ML to about 6 ML. As a result, as shown inFIG. 9, the resulting thickness Tp′ ofsilicon cap30 may be between about 2 ML and about 8 ML, and the resulting thickness Tn″ ofsilicon cap26 may be between about 4 ML and about 14 ML, which thicknesses Tp′ and Tn″ are the final thicknesses of silicon caps30 and26, respectively. The thickness difference Tn″−Tp′ may be between about 2 ML and about 12 ML.
• Next, as shown inFIG. 10,gate electrode layer38 is formed. In an embodiment,gate electrode layer38 comprises polysilicon. In other embodiments,gate electrode layer38 may be formed of metals, metal nitrides, metal silicides, or the like. In yet other embodiments,gate electrode layer38 may includefirst portion38₁inPMOS region100 andsecond portion38₂inNMOS region200.First portion38₁ofgate electrode layer38 may have a work function suitable for forming PMOS devices, which work function is preferably between about 4.9 eV and about 5.2 eV, and may be a valence band-edge work function (close to the valence band of silicon, which is about 5.2 eV). The exemplary materials include tungsten-containing materials such as tungsten and tungsten nitride, ruthenium-containing materials such as ruthenium and ruthenium oxide, molybdenum-containing materials such as molybdenum and molybdenum nitride, or combinations thereof. Thesecond portion38₂ofgate electrode layer38 may have a work function suitable for forming NMOS devices, which work function is preferably between about 4.0 eV and about 4.4 eV, and may be a conduction band-edge work function (close to the conduction band of silicon, which is about 4.1 eV). The exemplary materials include tantalum-containing materials such as TaC, TaN, TaSiN, and combinations thereof.Hard mask layer40, which may be formed of silicon nitride, is then formed.
• Next, as shown inFIG. 11,hard mask layer40,gate electrode layer38, andgate dielectric layer36 are patterned, forminggate stacks150 and250.Gate stack150 includesgate dielectric136,gate electrode138 andhard mask140.Gate stack250 includesgate dielectric236,gate electrode238 andhard mask240.
• FIG. 12A illustrates the formation of the remaining components ofPMOS device160 andNMOS device260. Lightly doped source/drain (LDD)regions162 and262 are formed. As is known in the art,LDD regions162 and262 may be formed by implanting n-type and p-type impurities intoPMOS region100 andNMOS region200, respectively. Due to the masking ofgate stacks150 and250,LDD regions162 and262 are substantially aligned to the edges ofgate stacks150 and250, respectively.
• Gate spacers164 and264 are formed on sidewalls ofgate stacks150 and250, respectively. Preferably,gate spacers164 and264 are formed by depositing one or more spacer layer(s) (not shown), and removing horizontal portions of the spacer layer(s) by etching. In an embodiment, the spacer layers include a nitride layer on a liner oxide layer. The spacer deposition methods may include PECVD, LPCVD, sub-atmospheric CVD (SACVD), and the like.
• FIG. 12A also illustrates the formation of deep source/drain regions166 and266. The formation processes for deep source/drain regions166 and266 are well known in the art, and thus are not repeated herein. Source/drain silicide regions (not shown) may then be formed on source/drain regions166 and266, and ongate electrodes138 and238 ifgate electrodes138 and238 are formed of polysilicon.
• In the resulting structure,PMOS device160 andNMOS device260 include silicon caps30 and26, respectively. However,silicon cap26 is thicker thansilicon cap30. An advantageous feature of silicon caps30 and26 is thatgermanium substrate20 is separated fromgate dielectrics136 and236 bysilicon caps30 and26, respectively, so that the likelihood of generating germanium oxide is substantially eliminated, and hence the traps that may be generated due to the germanium oxide are also eliminated. Reducing the thickness Tp ofsilicon cap30 can result in the desirable reduction of equivalent oxide thickness (EOT) forPMOS device160. On the other hand, the EOT ofNMOS device260 is substantially unaffected by the thickness ofsilicon cap26. Accordingly,silicon cap26 may be thicker thansilicon cap30 to take advantage of reduced diffusion of germanium to the surface ofsilicon cap26 without incurring the increase in EOT ofNMOS device260.
• It is realized that the steps discussed in the preceding paragraphs may be performed in different orders. For example,silicon cap26 may be formed after the formation ofsilicon cap30. Accordingly,silicon oxide layer28 will be formed onsilicon cap30 and acts as a mask for selectively growingsilicon cap26. Further, other methods may also be used to differentiate the thicknesses of silicon caps26 and30, which methods are also in the scope of the embodiments of the present invention. For example, a silicon cap that has a thickness essentially the same as thickness Tp′ (FIG. 12A) may be formed in bothPMOS region100 andNMOS region200. ThePMOS region100 is then masked, for example, by a silicon oxide layer (not shown), and an additional epitaxial growth may then be performed to increase the thickness ofsilicon cap26 to thickness Tn″. One skilled in the art will realize the process details.
• FIG. 12B illustrates an alternative embodiment, whereinSiGe stressors268 are formed insemiconductor substrate20 inNMOS region200.SiGe stressors268 form portions of source/drain regions266 ofNMOS device260. In an embodiment, the germanium atomic percentage inSiGe stressors268 is less than the germanium atomic percentage insemiconductor substrate20, and henceSiGe stressors268 may incur a tensile stress in the channel region ofNMOS device260. Further,SiGe stressors268 may advantageously result in an increased solubility of the source/drain impurities in source/drain regions266. In an embodiment,SiGe stressors268 have a germanium atomic percentage between about 15 percent and about 85 percent, although different percentages are also usable.
• Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the invention.

Claims (19)

1. A semiconductor structure comprising:

a germanium substrate comprising a first region and a second region;

a first silicon cap over the first region of the germanium substrate; and

a second silicon cap over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap.

2. The semiconductor structure ofclaim 1 further comprising:

a PMOS device comprising a first gate dielectric over the first silicon cap; and

an NMOS device comprising a second gate dielectric over the second silicon cap.

3. The semiconductor structure ofclaim 2, wherein the NMOS device further comprises a silicon germanium stressor in the germanium substrate and adjacent the second gate dielectric, and wherein the silicon germanium stressor has a germanium atomic percentage less than an atomic percentage of the germanium substrate.

4. The semiconductor structure ofclaim 2, wherein the first gate dielectric and the second gate dielectric comprise high-k dielectric materials.

5. The semiconductor structure ofclaim 2, wherein the first silicon cap contacts both the germanium substrate and the first gate dielectric, and the second silicon cap contacts both the germanium substrate and the second gate dielectric.

6. The semiconductor structure ofclaim 1, wherein portions of the germanium substrate adjoining the first silicon cap and the second silicon cap are formed of substantially pure germanium.

7. The semiconductor structure ofclaim 1, wherein the first thickness is less than the second thickness by a difference between than about 2 mono-layers of silicon (ML) and about 12 ML.

8. The semiconductor structure ofclaim 1, wherein the first thickness is between about 2 ML and about 8 ML, and the second thickness is between about 4 ML and about 14 ML.

9. The semiconductor structure ofclaim 1, wherein the second thickness is less than about 22 ML.

10. The semiconductor structure ofclaim 1, wherein the first silicon cap and the second silicon cap are formed of substantially pure silicon.

11. A semiconductor structure comprising:

a germanium substrate comprising a top layer formed of substantially pure germanium, wherein the top layer comprises a first region and a second region;

a PMOS device comprising:

a first silicon cap over the first region of the germanium substrate; and

a first gate dielectric over the first silicon cap; and

an NMOS device comprising:

a second silicon cap over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap, and wherein the second thickness is less than about 22 mono-layers of silicon (ML); and

a second gate dielectric over the second silicon cap.

12. The semiconductor structure ofclaim 11, wherein a first bottom of the first silicon cap is substantially level with a second bottom of the second silicon cap.

13. The semiconductor structure ofclaim 11, wherein the first thickness is less than the second thickness by a difference between about 2 ML and about 12 ML.

14. The semiconductor structure ofclaim 11, wherein the first thickness is between about 2 ML and about 8 ML.

15. The semiconductor structure ofclaim 11, wherein the second thickness is between about 4 ML and about 14 ML.

16. The semiconductor structure ofclaim 11, wherein the NMOS device further comprises a silicon germanium stressor adjacent the second gate dielectric and in the germanium substrate, wherein the silicon germanium stressor has a germanium atomic percentage less than an atomic percentage of the germanium substrate.

17. The semiconductor structure ofclaim 11, wherein the first gate dielectric and the second gate dielectric comprise high-k dielectric materials.

18. The semiconductor structure ofclaim 11, wherein the first silicon cap and the second silicon cap are formed of substantially pure silicon.

19. The semiconductor structure ofclaim 11, wherein the first silicon cap adjoins the germanium substrate and the first gate dielectric, and the second silicon cap adjoins the germanium substrate and the second gate dielectric.

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