US20100148332A1 - Semiconductor apparatus and manufacturing method thereof - Google Patents
Semiconductor apparatus and manufacturing method thereofDownload PDFInfo
- Publication number
- US20100148332A1 US20100148332A1US12/639,421US63942109AUS2010148332A1US 20100148332 A1US20100148332 A1US 20100148332A1US 63942109 AUS63942109 AUS 63942109AUS 2010148332 A1US2010148332 A1US 2010148332A1
- Authority
- US
- United States
- Prior art keywords
- wiring substrate
- semiconductor chip
- resin
- adhesive layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01088—Radium [Ra]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present disclosurerelates to a semiconductor apparatus and a manufacturing method thereof, and more particularly to a resin-sealed semiconductor apparatus in which a semiconductor chip is received between stacked wiring substrates and a gap between the wiring substrates is filled with a resin, and a manufacturing method of the semiconductor apparatus.
- a resin-sealed semiconductor apparatusconstructed by stacking and connecting a second wiring substrate on a first wiring substrate on which a semiconductor chip is mounted by flip chip bonding through a bump electrode and filling a gap between the wiring substrates with a molding resin.
- the semiconductor chipis thinned to 100 ⁇ m or less by grinding in order to achieve thinning of the whole apparatus.
- a minute crackoften occurs in a grinding surface (upper surface) of the semiconductor chip and in order to remove the crack, polishing processing is performed on the grinding surface of the semiconductor chip.
- a buffingthat is a polishing using a polishing cloth, which is provided with diamond or polishing paste such as aluminum oxide and the like, or which is soaked into slurry
- polishing processingis performed as the polishing processing.
- the molding resinis formed on a mirror surface of the semiconductor chip, it is difficult to obtain high adhesion properties by an anchor effect and there is a problem of forming the molding resin in a state of low adhesion properties with respect to the semiconductor chip. As a result of that, when moisture absorbed by the semiconductor apparatus vaporizes and volume expansion is caused, peeling occurs at an interface between the molding resin and the semiconductor chip with low adhesion properties and thus, there is fear of leading to destruction of the semiconductor apparatus.
- Exemplary embodiments of the present inventionprovide a semiconductor apparatus capable of obtaining sufficient reliability by improving adhesion properties in a semiconductor apparatus of a structure in which a thinned semiconductor chip is mounted between wiring substrates and is sealed with a resin, and a manufacturing method of the semiconductor apparatus.
- a semiconductor apparatuscomprises:
- a semiconductor chipwhich is mounted on the first wiring substrate by flip chip bonding and received between the first wiring substrate and the second wiring substrate, an upper surface of the semiconductor chip being subject to a mirror treatment;
- a semiconductor chip, an upper surface of which is subject to the mirror treatmentis first mounted on a first wiring substrate by flip chip bonding.
- the semiconductor chipis obtained by dicing a silicon wafer after a back surface of the silicon wafer in which an element forming region is disposed in the front surface side is ground to make the silicon wafer thin and mirror treatment is performed.
- the mirror treatmentis performed in order to remove a minute crack occurring by grinding. In this manner, the semiconductor chip, the upper surface of which is subject to mirror treatment, is obtained.
- an anchor effectbecomes resistant to working, so that adhesion properties of a layer (a molding resin etc.) formed on the semiconductor chip become worse. Because of this, an adhesive layer is formed on the upper surface (mirror surface) of the semiconductor chip in the invention.
- a coupling material or a resin without including a mold release materialis suitably used as the adhesive layer.
- a second wiring substrateis stacked on the first wiring substrate through a bump electrode and the semiconductor chip is received in a receiving part between the first wiring substrate and the second wiring substrate.
- itmay be constructed so that a gap occurs between the adhesive layer on the semiconductor chip and a lower surface of the second wiring substrate or the adhesive layer on the semiconductor chip makes contact with the lower surface of the second wiring substrate.
- a gap between the first wiring substrate and the second wiring substrateis filled with a molding resin and the semiconductor chip is sealed with the resin.
- a gapis disposed between the adhesive layer on the semiconductor chip and the lower surface of the second wiring substrate in the case of stacking the second wiring substrate, it is sealed with the resin so that the molding resin is interposed between the adhesive layer and the second wiring substrate.
- the adhesive layeris disposed on the semiconductor chip, so that even when the upper surface of the semiconductor chip is a mirror surface without having the anchor effect, the molding resin formed on its surface is formed with sufficient adhesion properties. Or, when the adhesive layer on the semiconductor chip makes contact with the second wiring substrate, the second wiring substrate is arranged with sufficient adhesion properties by the adhesive layer on the semiconductor chip.
- FIGS. 1A to 1Care sectional views showing a manufacturing method of a semiconductor apparatus of the related art.
- FIGS. 2A to 5are sectional views showing a manufacturing method of a semiconductor apparatus of a first embodiment of the invention.
- FIGS. 6A to 7Bare sectional views showing a manufacturing method of a semiconductor apparatus of a second embodiment of the invention.
- FIGS. 1A to 1Care sectional views showing a manufacturing method of a semiconductor apparatus of the related art.
- flip chip bonding between a wiring layer (not shown) of a first wiring substrate 100 and a connection electrode 220 of a semiconductor chip 200is first made.
- the semiconductor chip 200is thinned to a thickness of 100 ⁇ m or less and polishing processing of its upper surface is performed.
- a gap between the lower side of the semiconductor chip 200 and an upper surface of the first wiring substrate 100is filled with an under fill resin 300 .
- a second wiring substrate 400is stacked and connected on the first wiring substrate 100 through bump electrodes 240 arranged so as to surround a receiving part A of the semiconductor chip 200 .
- a height of the bump electrode 240is set higher than a height of the semiconductor chip 200 and the semiconductor chip 200 is received in the receiving part A between the first wiring substrate 100 and the second wiring substrate 400 .
- a gap between the first and the second wiring substrates 100 and 400is filled with a resin by a transfer molding construction method using a molding mold. Consequently, as shown in FIG. 1C , the semiconductor chip 200 received between the first and the second wiring substrates 100 and 400 is sealed with a molding resin 260 .
- external connection terminals 280are disposed by installing solder balls etc. in a wiring layer (not shown) of the lower surface side of the first wiring substrate 100 . Consequently, a resin-sealed semiconductor apparatus 5 of the related art is obtained.
- the semiconductor chip 200is obtained by dicing a silicon wafer after a back surface of the silicon wafer in which an element forming region is disposed in the front surface side is ground by a grinder to make the silicon wafer thin to a necessary thickness.
- polishing processingis performed by wet polishing etc. after the back surface of the silicon wafer is ground. Consequently, the semiconductor chip 200 , the upper surface of which is subject to polishing processing as described above, is obtained.
- the upper surface of the semiconductor chip 200becomes a mirror surface and smoothness is high, so that sufficient adhesion properties of the molding resin 260 by an anchor effect are not obtained and there is a problem of low adhesion properties between the semiconductor chip 200 and the molding resin 260 .
- the upper surface of the semiconductor chip 200is smooth, a contact area of the molding resin 260 per unit area becomes small, so that the anchor effect becomes weak.
- the molding resin 260has lower adhesion properties to the semiconductor chip 200 (silicon) than other resins such as the under fill resin 300 since the molding resin 260 includes a mold release material (wax) in order to be easily detached from the molding mold.
- the semiconductor apparatus 5When the semiconductor apparatus 5 absorbs moisture, moisture tends to gather at an interface with which a material with low adhesion properties makes contact. Then, the moisture evaporates (vaporizes) by heating treatment such as a step of making connection to a mounting substrate by reflow heating of the external connection terminals 280 and thereby, volume expansion is caused and force of pushing up a film is applied. At this time, it is in a state of low adhesion properties between the semiconductor chip 200 and the molding resin 260 , so that peeling occurs at its interface and thus, the semiconductor apparatus 5 may be destroyed.
- the second wiring substrate 400is present on the semiconductor chip 200 , so that the ashing treatment cannot be performed sufficiently with respect to the upper surface of the semiconductor chip 200 and it is difficult to adopt a technique for improving adhesion properties by the ashing treatment.
- a manufacturing method of a semiconductor apparatus of the present embodiment described belowcan solve the trouble described above.
- FIGS. 2 to 5are sectional views showing a manufacturing method of a semiconductor apparatus of a first embodiment of the invention.
- a first wiring substrate 10 as shown in FIG. 2Ais first prepared.
- a through hole THis disposed in a core substrate 12 made of an insulating material such as a glass epoxy resin.
- Wiring layers 20 mutually connected through a through electrode 14 with which the inside of the through hole TH is filledare respectively formed on the sides of both surfaces of the core substrate 12 .
- the wiring layers 20may be mutually connected through a through hole plated layer (through electrode) disposed on an inner wall of the through hole TH of the core substrate 12 and a hole of the through hole TH may be filled with a resin.
- a through hole plated layerthrough electrode
- solder resists 16 in which opening parts 16 a are disposed on connection parts of the wiring layers 20are respectively formed on the sides of both surfaces of the core substrate 12 .
- a contact part(not shown) is disposed by, for example, forming a Ni/Au plated layer in the connection part of the wiring layer 20 .
- the wiring layers 20 of one layerare respectively formed on both surfaces of the core substrate 12 , but the number of stacks of the wiring layer formed on the core substrate 12 can be set arbitrarily. Also, a coreless wiring substrate without having the core substrate 12 may be used.
- connection electrode 32 of a semiconductor chip 30(LSI chip) and the connection part of the wiring layer 20 of the upper surface side of the first wiring substrate 10 is made.
- a gap between the semiconductor chip 30 and the first wiring substrate 10is filled with an under fill resin 18 .
- the semiconductor chip 30is obtained by dicing a silicon wafer after a back surface of the silicon wafer in which an element forming region is disposed in the front surface side is ground by a grinder to make the silicon wafer thin to a necessary thickness.
- An upper surface of the semiconductor chip 30 of FIG. 2Bcorresponds to the grinding surface side of the back surface of the silicon wafer.
- the reason why the upper surface of the semiconductor chip 30 becomes a mirror surfaceis because a minute crack often occurs in the grinding surface (upper surface) of the thinned semiconductor chip 30 and, for example, when the semiconductor chip 30 is mounted, the crack advances and destruction may be caused as described in the related art. Because of that, in the semiconductor chip 30 , polishing processing of the grinding surface (upper surface) is performed and the minute crack is removed.
- Surface roughness (Ra) of the grinding surface (upper surface) of the semiconductor chip 30 obtained based on grinding of the silicon wafer by the grinderis about 0.1 mm (100 ⁇ m).
- surface roughness (Ra) of the mirror surface (upper surface) of the semiconductor chip 30 obtained based on polishing processing of its grinding surface after the silicon wafer is ground by the grinderbecomes 8 to 12 ⁇ m (about 10 ⁇ m).
- a difference between the surface roughnesses (Ra) of the mirror surface on which polishing processing is performed and the grinding surface by the grinderis about 10 times and it is understood that the surface is remarkably smoothed by performing the polishing processing.
- polishing processing of the upper surface of the semiconductor chip 30is performed and the surface roughness (Ra) becomes small, so that an anchor effect becomes resistant to working in the case of sealing the semiconductor chip 30 with a molding resin and adhesion force of the molding resin reduces.
- an adhesive layer 40is formed on the upper surface of the semiconductor chip 30 as shown in FIG. 3A .
- a suitable material of the adhesive layer 40there is the same resin as the under fill resin used in a step of FIG. 2C .
- a mold release material (wax)is not included in the under fill resin, so that sufficient adhesion properties to the semiconductor chip 30 (silicon) are obtained.
- a resin without including the mold release material (wax)is applied to the upper surface of the semiconductor chip 30 and heating treatment is performed in an atmosphere of temperature of 150 to 200° C. and the resin is cured and thereby, the adhesive layer 40 is obtained.
- the resin without including the mold release material used as the adhesive layer 40has good adhesion properties to the semiconductor chip (silicon) from the standpoint of having a lower content rate of a filler than the molding resin described below.
- 20 to 40% (for example, 30%) fillers with a diameter of about 5 ⁇ mare contained in resin without including the mold release material used as the adhesive layer 40 .
- the adhesive layer 40there is a coupling material. Since a silane coupling material etc. have an organic functional group and a hydrolyzable group in one molecule, an inorganic substance (the semiconductor chip 30 ) can be coupled to an organic substance (the molding resin described below) and adhesion properties between their substances can be improved.
- the silane coupling material etc.are applied to the upper surface of the semiconductor chip 30 and heating treatment is performed for 0.5 hour in an atmosphere of temperature of 80° C. and thereafter, heating treatment is performed for 2 hours in an atmosphere of temperature of 200° C. and the silane coupling material etc. are cured and thereby, the adhesive layer 40 is obtained.
- the adhesive layer 40may be obtained by applying a resin without including a mold release material after surface treatment of the upper surface of the semiconductor chip 30 is performed by a coupling material.
- the coupling material and the resin without including the mold release materialare given as the adhesive layer 40 , but various adhesive (gluing) materials capable of adhesion between the semiconductor chip 30 and the molding resin can be used as long as a material without losing reliability of the semiconductor apparatus finally obtained is used.
- a second wiring substrate 50 as shown in FIG. 3Bis prepared.
- the second wiring substrate 50has a structure similar to that of the first wiring substrate 10 . That is, a through hole TH is disposed in a core substrate 52 and the inside of the through hole TH is filled with a through electrode 54 . Wiring layers 60 mutually connected through the through electrode 54 are respectively formed on the sides of both surfaces of the core substrate 52 . Further, solder resists 56 in which opening parts 56 a are disposed on connection parts of the wiring layers 60 are respectively formed on the sides of both surfaces of the core substrate 52 .
- various wiring substratessuch as a coreless wiring substrate can be used while the number of stacks of the wiring layer can be set arbitrarily like the first wiring substrate 10 .
- a conductive ball 62 xis installed on the connection part of the wiring layer 60 of the lower surface peripheral edge side of the second wiring substrate 50 .
- the conductive ball 62 xis constructed by covering an outer surface of a copper ball 62 a with a solder layer 62 b . Since the semiconductor chip 30 is received in a receiving part constructed of the first wiring substrate 10 and the second wiring substrate 50 , a height (diameter) of the conductive ball 62 x is set higher than a height (the total thickness of the semiconductor chip 30 and the connection electrode 32 ) of the semiconductor chip 30 .
- the conductive ball 62 x of the lower surface side of the second wiring substrate 50is arranged on the connection part of the wiring layer 20 of the peripheral edge side of the first wiring substrate 10 . Further, the conductive ball 62 x is bonded to the wiring layers 20 , 60 of the first and second wiring substrates 10 , 50 by melting the solder layer 62 b by reflow heating. Or, the conductive ball 62 x may be installed on the side of the first wiring substrate 10 and the second wiring substrate 50 may be arranged on the conductive ball 62 x.
- the wiring layer 20 of the first wiring substrate 10is electrically connected to the wiring layer 60 of the second wiring substrate 50 by a bump electrode 62 as shown in FIG. 3C .
- the semiconductor chip 30is received in a receiving part A surrounded by the bump electrodes 62 between the first wiring substrate 10 and the second wiring substrate 50 .
- the first embodimentis in a state of disposing a gap d between an upper surface of the adhesive layer 40 on the semiconductor chip 30 and a lower surface of the second wiring substrate 50 .
- a stacked wiring member 2constructed by stacking the second wiring substrate 50 on the first wiring substrate 10 on which the semiconductor chip 30 is mounted by flip chip bonding is obtained.
- a molding mold 70basically constructed by a lower mold 72 and an upper mold 74 is prepared as shown in FIG. 4 .
- the molding mold 70is a metal mold for being filled with a molding resin by a transfer molding construction method.
- a recessed part 72 a corresponding to the first wiring substrate 10 of the stacked wiring member 2is disposed in the upper surface side of the lower mold 72 .
- a recessed part 74 a corresponding to the second wiring substrate 50 of the stacked wiring member 2is disposed in the lower surface side of the upper mold 74 .
- the stacked wiring member 2is arranged in the recessed part 72 a of the lower mold 72 and the upper mold 74 is arranged on the lower mold 72 so as to receive the second wiring substrate 50 of the stacked wiring member 2 in the recessed part 74 a of the upper mold 74 .
- the receiving part A between the first wiring substrate 10 and the second wiring substrate 50becomes a cavity C filled with a resin.
- a gapis disposed between the lower mold 72 and the upper mold 74 in the outside of one end of the stacked wiring member 2 and the gap forms a resin supply part B (a molding gate) connected to the cavity C. It is constructed so that a melted resin passes through the resin supply part B and flows into the cavity C.
- the transfer molding construction method using such a molding mold 70the melted resin is allowed to flow into the side of the cavity C through the resin supply part B.
- the upper mold 74 and the lower mold 72are detached from the stacked wiring member 2 and a gate resin part formed in the resin supply part B is broken off and thereby, the gate resin part is separated from the resin with which the inside of the cavity C is filled.
- a gap between the first wiring substrate 10 and the second wiring substrate 50is filled with a molding resin 76 and the semiconductor chip 30 is sealed with the resin as shown in FIG. 5 .
- a mold release material(wax) is included in the molding resin 76 used by the transfer molding construction method in order to be easily detached from the molding mold 70 . Therefore, when the molding resin 76 is directly formed on the mirror surface in the case of performing polishing processing of the upper surface of the semiconductor chip 30 , adhesion properties are low and peeling at its interface tends to occur.
- the mold release materialthere is a natural material or a chemical synthetic material.
- the natural materialfor example, there is carnauba wax obtained by using wax present on a surface of a leaf of a palm plant as a raw material.
- fillerswith a diameter of about 30 ⁇ m are contained in the molding resin 76 and adhesion properties to the semiconductor chip 30 tend to be low from the standpoint of a small resin component.
- the adhesive layer 40is disposed on the upper surface of the semiconductor chip 30 , so that the molding resin 76 is formed on the adhesive layer 40 with sufficient adhesion properties. As a result of that, the molding resin 76 is formed with sufficient adhesion properties to the semiconductor chip 30 by a function of the adhesive layer 40 .
- external connection terminals 78are disposed by, for example, installing solder balls in the connection parts of the wiring layer 20 of the lower surface side of the first wiring substrate 10 .
- connection electrode 32 of the semiconductor chip 30is mounted on the wiring layer 20 of the upper surface side of the first wiring substrate 10 described in FIG. 2A by flip chip bonding in the semiconductor apparatus 1 of the first embodiment.
- a gap between the lower portion of the semiconductor chip 30 and the upper surface of the first wiring substrate 10is filled with the under fill resin 18 .
- Polishing processing of the upper surface of the semiconductor chip 30is performed and surface roughness (Ra) of its mirror surface becomes about 10 ⁇ m and the surface is smoothed.
- the adhesive layer 40is formed on the upper surface (mirror surface) of the semiconductor chip 30 .
- a coupling material or a resin without including a mold release materialis used as the adhesive layer 40 .
- the second wiring substrate 50 described in FIG. 3Bis stacked and arranged on the first wiring substrate 10 through the bump electrode 62 .
- the wiring layer 20 of the first wiring substrate 10is electrically connected to the wiring layer 60 of the second wiring substrate 50 through the bump electrode 62 .
- a height of the bump electrode 62is set higher than a height of the semiconductor chip 30 , and the semiconductor chip 30 is received between the first and second wiring substrates 10 , 50 .
- a gap between the first and second wiring substrates 10 , 50is filled with the molding resin 76 and the semiconductor chip 30 is sealed with the molding resin 76 .
- the adhesive layer 40is formed on the upper surface (mirror surface) of the semiconductor chip 30 and the top of the adhesive layer 40 is filled with the molding resin 76 . That is, the molding resin 76 is interposed between an upper surface of the adhesive layer 40 on the semiconductor chip 30 and a lower surface of the second wiring substrate 50 .
- the molding resin 76is formed with sufficient adhesion properties to the semiconductor chip 30 through the adhesive layer 40 .
- the semiconductor apparatus 1absorbs moisture and the moisture gathered at an interface between different materials evaporates (vaporizes) by heating treatment and thereby volume expansion is caused, the semiconductor chip 30 , the adhesive layer 40 and the molding resin 76 adhere mutually by high adhesion force, so that peeling is prevented from occurring at their interfaces.
- FIGS. 6 and 7are sectional views showing a manufacturing method of a semiconductor apparatus of a second embodiment of the invention.
- the second embodimentis characterized in that a semiconductor chip is made to adhere to a second wiring substrate directly by an adhesive layer without interposing a molding resin between an upper surface (mirror surface) of the semiconductor chip and a lower surface of the second wiring substrate.
- the same structural body as that of FIG. 2C of the first embodiment described aboveis prepared as shown in FIG. 6A . That is, after a semiconductor chip 30 is mounted in a first wiring substrate 10 by flip chip bonding, a gap between a lower portion of the semiconductor chip 30 and an upper surface of the first wiring substrate 10 is filled with an under fill resin 18 .
- an adhesive material 40 ais applied to an upper surface (mirror surface) of the semiconductor chip 30 as shown in FIG. 6B .
- the adhesive material 40 athe resin without including the mold release material (wax) described in the first embodiment is suitably used.
- a second wiring substrate 50 in which conductive balls 62 x are installed on the lower surface sideis stacked and connected on the first wiring substrate 10 like the step of FIG. 3B of the first embodiment.
- the application amount (volume) of the adhesive material 40 a or a diameter of the conductive ball 62 x installed on the second wiring substrate 50is adjusted so that a gap does not occur by making contact between the adhesive material 40 a on the semiconductor chip 30 and a lower surface of the second wiring substrate 50 .
- the adhesive material 40 amay be formed using a coupling material as a main material.
- a coupling materialfor example, an adhesive in which the coupling material is included is used and its application amount (volume) or a diameter of the conductive ball 62 x installed on the second wiring substrate 50 is adjusted.
- the uncured adhesive material 40 a on the semiconductor chip 30is pushed in a lateral direction by the second wiring substrate 50 and flows and a gap between the upper surface (mirror surface) of the semiconductor chip 30 and the lower surface of the second wiring substrate 50 is filled with the adhesive material 40 a.
- an adhesive layer 40is obtained by heat-treating and curing the adhesive material 40 a . Also at the same time, a wiring layer 20 of the first wiring substrate 10 is electrically connected to a wiring layer 60 of the second wiring substrate 50 through a bump electrode 62 .
- a gapis not disposed between the second wiring substrate 50 and the adhesive layer 40 on the semiconductor chip 30 , and the semiconductor chip 30 is received in a receiving part A between the first and second wiring substrates 10 , 50 in a state of filling a gap between the second wiring substrate 50 and an upper surface of the semiconductor chip 30 with the adhesive layer 40 .
- the receiving part A (cavity) between the first and second wiring substrates 10 , 50is filled with a molding resin 76 by a transfer molding construction method similar to that of the first embodiment.
- the receiving partis filled with the molding resin 76 so as to surround the semiconductor chip 30 and the adhesive layer 40 .
- the second embodimenthas an effect similar to that of the first embodiment.
- a gap between the adhesive layer 40 on the semiconductor chip 30 and the solder resist 56 of the lower surface of the second wiring substrate 50is filled with the molding resin 76 .
- adhesion properties between the semiconductor chip 30 and the molding resin 76are improved by the adhesive layer 40 , but the case where adhesion properties between the molding resin 76 and the solder resist 56 of the second wiring substrate 50 are not always obtained sufficiently depending on their materials is assumed.
- filling with the adhesive layer 40is performed without interposing the molding resin 76 between the upper surface (mirror surface) of the semiconductor chip 30 and the lower surface side of the second wiring substrate 50 .
- the solder resist 56is arranged with sufficient adhesion properties to the semiconductor chip 30 by the adhesive layer 40 and a strength of adhesion between first and second wiring substrates 10 , 50 can be reinforced.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
- This application claims priority to Japanese Patent Application No. 2008-321038, filed Dec. 17, 2008, in the Japanese Patent Office. The Japanese Patent Application No. 2008-321038 is incorporated by reference in its entirety.
- The present disclosure relates to a semiconductor apparatus and a manufacturing method thereof, and more particularly to a resin-sealed semiconductor apparatus in which a semiconductor chip is received between stacked wiring substrates and a gap between the wiring substrates is filled with a resin, and a manufacturing method of the semiconductor apparatus.
- There are various semiconductor apparatuses. Description in which plural substrates, on each of which an electronic component is mounted, are stacked on a substrate, on which an electronic component is mounted through a solder ball, and a gap between the substrates is sealed with a resin is made in Patent Reference 1.
- Also, description in which one wiring substrate is stacked and connected on the other wiring substrate by a solder ball and a first electronic component is mounted on one wiring substrate and a second electronic component is received in an opening part of the other wiring substrate and a gap between a pair of the wiring substrates is sealed with a resin is made in
Patent Reference 2. - Also, description in which a second substrate is stacked and connected on a first substrate on which a semiconductor chip is mounted through a solder ball and a gap between the first and second substrates is filled with a molding resin is made in Patent Reference 3.
- [Patent Reference 1] JP-A-2003-347722
- [Patent Reference 2] JP-A-2008-159956
- [Patent Reference 3] WO 2007/069606 A1
- As described in a column of a related art described below, there is a resin-sealed semiconductor apparatus constructed by stacking and connecting a second wiring substrate on a first wiring substrate on which a semiconductor chip is mounted by flip chip bonding through a bump electrode and filling a gap between the wiring substrates with a molding resin.
- In such a semiconductor apparatus, the semiconductor chip is thinned to 100 μm or less by grinding in order to achieve thinning of the whole apparatus. As a result of this, a minute crack often occurs in a grinding surface (upper surface) of the semiconductor chip and in order to remove the crack, polishing processing is performed on the grinding surface of the semiconductor chip. For example, a buffing (that is a polishing using a polishing cloth, which is provided with diamond or polishing paste such as aluminum oxide and the like, or which is soaked into slurry) is performed as the polishing processing.
- Since the molding resin is formed on a mirror surface of the semiconductor chip, it is difficult to obtain high adhesion properties by an anchor effect and there is a problem of forming the molding resin in a state of low adhesion properties with respect to the semiconductor chip. As a result of that, when moisture absorbed by the semiconductor apparatus vaporizes and volume expansion is caused, peeling occurs at an interface between the molding resin and the semiconductor chip with low adhesion properties and thus, there is fear of leading to destruction of the semiconductor apparatus.
- Exemplary embodiments of the present invention provide a semiconductor apparatus capable of obtaining sufficient reliability by improving adhesion properties in a semiconductor apparatus of a structure in which a thinned semiconductor chip is mounted between wiring substrates and is sealed with a resin, and a manufacturing method of the semiconductor apparatus.
- A semiconductor apparatus according to the exemplary embodiment of the present invention, comprises:
- a first wiring substrate;
- a second wiring substrate which is stacked and connected on the first wiring substrate through a bump electrode;
- a semiconductor chip which is mounted on the first wiring substrate by flip chip bonding and received between the first wiring substrate and the second wiring substrate, an upper surface of the semiconductor chip being subject to a mirror treatment;
- an adhesive layer which is formed on the upper surface of the semiconductor chip; and
- a molding resin which is filled in a gap between the first wiring substrate and the second wiring substrate.
- In the case of manufacturing a semiconductor apparatus of the invention, a semiconductor chip, an upper surface of which is subject to the mirror treatment, is first mounted on a first wiring substrate by flip chip bonding. The semiconductor chip is obtained by dicing a silicon wafer after a back surface of the silicon wafer in which an element forming region is disposed in the front surface side is ground to make the silicon wafer thin and mirror treatment is performed. The mirror treatment is performed in order to remove a minute crack occurring by grinding. In this manner, the semiconductor chip, the upper surface of which is subject to mirror treatment, is obtained.
- In the semiconductor chip in which mirror treatment is performed, an anchor effect becomes resistant to working, so that adhesion properties of a layer (a molding resin etc.) formed on the semiconductor chip become worse. Because of this, an adhesive layer is formed on the upper surface (mirror surface) of the semiconductor chip in the invention. As the adhesive layer, a coupling material or a resin without including a mold release material is suitably used.
- Then, a second wiring substrate is stacked on the first wiring substrate through a bump electrode and the semiconductor chip is received in a receiving part between the first wiring substrate and the second wiring substrate. At this time, it may be constructed so that a gap occurs between the adhesive layer on the semiconductor chip and a lower surface of the second wiring substrate or the adhesive layer on the semiconductor chip makes contact with the lower surface of the second wiring substrate.
- Further, a gap between the first wiring substrate and the second wiring substrate is filled with a molding resin and the semiconductor chip is sealed with the resin. When a gap is disposed between the adhesive layer on the semiconductor chip and the lower surface of the second wiring substrate in the case of stacking the second wiring substrate, it is sealed with the resin so that the molding resin is interposed between the adhesive layer and the second wiring substrate.
- In the semiconductor apparatus of the invention, the adhesive layer is disposed on the semiconductor chip, so that even when the upper surface of the semiconductor chip is a mirror surface without having the anchor effect, the molding resin formed on its surface is formed with sufficient adhesion properties. Or, when the adhesive layer on the semiconductor chip makes contact with the second wiring substrate, the second wiring substrate is arranged with sufficient adhesion properties by the adhesive layer on the semiconductor chip.
- Therefore, even when moisture absorbed by the semiconductor apparatus vaporizes and volume expansion is caused, an interface of the upper surface side of the semiconductor chip has sufficient adhesion properties, so that peeling is prevented from occurring at their interfaces. Consequently, reliability of the semiconductor apparatus can be improved.
- As mentioned above, in the present invention, it is possible to obtain sufficient reliability by improving adhesion properties in a semiconductor apparatus of a structure in which a thinned semiconductor chip is mounted between wiring substrates and is sealed with a resin.
- Other features and advantages may be apparent from the following detailed description, the accompanying drawings and the claims.
FIGS. 1A to 1C are sectional views showing a manufacturing method of a semiconductor apparatus of the related art.FIGS. 2A to 5 are sectional views showing a manufacturing method of a semiconductor apparatus of a first embodiment of the invention.FIGS. 6A to 7B are sectional views showing a manufacturing method of a semiconductor apparatus of a second embodiment of the invention.- Embodiments of the invention will hereinafter be described with reference to the accompanying drawings.
- A problematical point of a related art related to the invention will be described before the embodiments of the invention are described.
FIGS. 1A to 1C are sectional views showing a manufacturing method of a semiconductor apparatus of the related art. - As shown in
FIG. 1A , flip chip bonding between a wiring layer (not shown) of afirst wiring substrate 100 and aconnection electrode 220 of asemiconductor chip 200 is first made. Thesemiconductor chip 200 is thinned to a thickness of 100 μm or less and polishing processing of its upper surface is performed. - Thereafter, a gap between the lower side of the
semiconductor chip 200 and an upper surface of thefirst wiring substrate 100 is filled with anunder fill resin 300. Then, as shown inFIG. 1B , asecond wiring substrate 400 is stacked and connected on thefirst wiring substrate 100 throughbump electrodes 240 arranged so as to surround a receiving part A of thesemiconductor chip 200. A height of thebump electrode 240 is set higher than a height of thesemiconductor chip 200 and thesemiconductor chip 200 is received in the receiving part A between thefirst wiring substrate 100 and thesecond wiring substrate 400. - Then, a gap between the first and the
second wiring substrates FIG. 1C , thesemiconductor chip 200 received between the first and thesecond wiring substrates molding resin 260. - Thereafter, external connection terminals280 are disposed by installing solder balls etc. in a wiring layer (not shown) of the lower surface side of the
first wiring substrate 100. Consequently, a resin-sealed semiconductor apparatus5 of the related art is obtained. - In the resin-sealed semiconductor apparatus5, thinning of the whole apparatus is desired, so that it is necessary to set the
semiconductor chip 200 as thin as possible. Thesemiconductor chip 200 is obtained by dicing a silicon wafer after a back surface of the silicon wafer in which an element forming region is disposed in the front surface side is ground by a grinder to make the silicon wafer thin to a necessary thickness. - At this time, a minute crack often occurs in a grinding surface of the
semiconductor chip 200 and as thesemiconductor chip 200 is thinned, the crack advances in a mounting step etc. and thesemiconductor chip 200 may be destroyed. - As this countermeasure, polishing processing is performed by wet polishing etc. after the back surface of the silicon wafer is ground. Consequently, the
semiconductor chip 200, the upper surface of which is subject to polishing processing as described above, is obtained. - In the semiconductor apparatus5 (
FIG. 1C ) of the related art, the upper surface of thesemiconductor chip 200 becomes a mirror surface and smoothness is high, so that sufficient adhesion properties of themolding resin 260 by an anchor effect are not obtained and there is a problem of low adhesion properties between thesemiconductor chip 200 and themolding resin 260. As the upper surface of thesemiconductor chip 200 is smooth, a contact area of themolding resin 260 per unit area becomes small, so that the anchor effect becomes weak. - Also, this results from the fact that the
molding resin 260 has lower adhesion properties to the semiconductor chip200 (silicon) than other resins such as the underfill resin 300 since themolding resin 260 includes a mold release material (wax) in order to be easily detached from the molding mold. - When the semiconductor apparatus5 absorbs moisture, moisture tends to gather at an interface with which a material with low adhesion properties makes contact. Then, the moisture evaporates (vaporizes) by heating treatment such as a step of making connection to a mounting substrate by reflow heating of the external connection terminals280 and thereby, volume expansion is caused and force of pushing up a film is applied. At this time, it is in a state of low adhesion properties between the
semiconductor chip 200 and themolding resin 260, so that peeling occurs at its interface and thus, the semiconductor apparatus5 may be destroyed. - When the
semiconductor chip 200 is sealed with themolding resin 260 in a state of exposing the upper surface of the semiconductor chip200 (in the absence of the second wiring substrate400), a method for improving adhesion properties of themolding resin 260 by ashing treatment of the upper surface of thesemiconductor chip 200 can be adopted. - However, in the related art, the
second wiring substrate 400 is present on thesemiconductor chip 200, so that the ashing treatment cannot be performed sufficiently with respect to the upper surface of thesemiconductor chip 200 and it is difficult to adopt a technique for improving adhesion properties by the ashing treatment. - A manufacturing method of a semiconductor apparatus of the present embodiment described below can solve the trouble described above.
FIGS. 2 to 5 are sectional views showing a manufacturing method of a semiconductor apparatus of a first embodiment of the invention. In the manufacturing method of the semiconductor apparatus of the first embodiment, afirst wiring substrate 10 as shown inFIG. 2A is first prepared. In thefirst wiring substrate 10, a through hole TH is disposed in acore substrate 12 made of an insulating material such as a glass epoxy resin. Wiring layers20 mutually connected through a throughelectrode 14 with which the inside of the through hole TH is filled are respectively formed on the sides of both surfaces of thecore substrate 12.- Or, the wiring layers20 may be mutually connected through a through hole plated layer (through electrode) disposed on an inner wall of the through hole TH of the
core substrate 12 and a hole of the through hole TH may be filled with a resin. - Further, solder resists16 in which opening
parts 16aare disposed on connection parts of the wiring layers20 are respectively formed on the sides of both surfaces of thecore substrate 12. A contact part (not shown) is disposed by, for example, forming a Ni/Au plated layer in the connection part of thewiring layer 20. - In an example of
FIG. 2A , the wiring layers20 of one layer are respectively formed on both surfaces of thecore substrate 12, but the number of stacks of the wiring layer formed on thecore substrate 12 can be set arbitrarily. Also, a coreless wiring substrate without having thecore substrate 12 may be used. - Then, as shown in
FIG. 2B , flip chip bonding between aconnection electrode 32 of a semiconductor chip30 (LSI chip) and the connection part of thewiring layer 20 of the upper surface side of thefirst wiring substrate 10 is made. Further, as shown inFIG. 2C , a gap between thesemiconductor chip 30 and thefirst wiring substrate 10 is filled with an underfill resin 18. - As described in the related art mentioned above, the
semiconductor chip 30 is obtained by dicing a silicon wafer after a back surface of the silicon wafer in which an element forming region is disposed in the front surface side is ground by a grinder to make the silicon wafer thin to a necessary thickness. - After the silicon wafer is thinned to a thickness of 100 μm or less (for example, 50 to 60 μm), polishing processing of its grinding surface is performed by wet polishing etc. An upper surface of the
semiconductor chip 30 ofFIG. 2B corresponds to the grinding surface side of the back surface of the silicon wafer. - The reason why the upper surface of the
semiconductor chip 30 becomes a mirror surface is because a minute crack often occurs in the grinding surface (upper surface) of the thinnedsemiconductor chip 30 and, for example, when thesemiconductor chip 30 is mounted, the crack advances and destruction may be caused as described in the related art. Because of that, in thesemiconductor chip 30, polishing processing of the grinding surface (upper surface) is performed and the minute crack is removed. - Surface roughness (Ra) of the grinding surface (upper surface) of the
semiconductor chip 30 obtained based on grinding of the silicon wafer by the grinder is about 0.1 mm (100 μm). On the other hand, surface roughness (Ra) of the mirror surface (upper surface) of thesemiconductor chip 30 obtained based on polishing processing of its grinding surface after the silicon wafer is ground by the grinder becomes 8 to 12 μm (about 10 μm). - Thus, a difference between the surface roughnesses (Ra) of the mirror surface on which polishing processing is performed and the grinding surface by the grinder is about 10 times and it is understood that the surface is remarkably smoothed by performing the polishing processing.
- In the embodiment, polishing processing of the upper surface of the
semiconductor chip 30 is performed and the surface roughness (Ra) becomes small, so that an anchor effect becomes resistant to working in the case of sealing thesemiconductor chip 30 with a molding resin and adhesion force of the molding resin reduces. - Hence, in the embodiment, an
adhesive layer 40 is formed on the upper surface of thesemiconductor chip 30 as shown inFIG. 3A . As a suitable material of theadhesive layer 40, there is the same resin as the under fill resin used in a step ofFIG. 2C . - Unlike a molding resin described below, a mold release material (wax) is not included in the under fill resin, so that sufficient adhesion properties to the semiconductor chip30 (silicon) are obtained. Such a resin without including the mold release material (wax) is applied to the upper surface of the
semiconductor chip 30 and heating treatment is performed in an atmosphere of temperature of 150 to 200° C. and the resin is cured and thereby, theadhesive layer 40 is obtained. - Also, the resin without including the mold release material used as the
adhesive layer 40 has good adhesion properties to the semiconductor chip (silicon) from the standpoint of having a lower content rate of a filler than the molding resin described below. For example, 20 to 40% (for example, 30%) fillers with a diameter of about 5 μm are contained in resin without including the mold release material used as theadhesive layer 40. In addition, in the embodiment, it is not always necessary to use a resin containing a filler as theadhesive layer 40. - Also, as a suitable material of the
adhesive layer 40, there is a coupling material. Since a silane coupling material etc. have an organic functional group and a hydrolyzable group in one molecule, an inorganic substance (the semiconductor chip30) can be coupled to an organic substance (the molding resin described below) and adhesion properties between their substances can be improved. - The silane coupling material etc. are applied to the upper surface of the
semiconductor chip 30 and heating treatment is performed for 0.5 hour in an atmosphere of temperature of 80° C. and thereafter, heating treatment is performed for 2 hours in an atmosphere of temperature of 200° C. and the silane coupling material etc. are cured and thereby, theadhesive layer 40 is obtained. - In addition, the
adhesive layer 40 may be obtained by applying a resin without including a mold release material after surface treatment of the upper surface of thesemiconductor chip 30 is performed by a coupling material. - The coupling material and the resin without including the mold release material are given as the
adhesive layer 40, but various adhesive (gluing) materials capable of adhesion between thesemiconductor chip 30 and the molding resin can be used as long as a material without losing reliability of the semiconductor apparatus finally obtained is used. - Then, a
second wiring substrate 50 as shown inFIG. 3B is prepared. Thesecond wiring substrate 50 has a structure similar to that of thefirst wiring substrate 10. That is, a through hole TH is disposed in acore substrate 52 and the inside of the through hole TH is filled with a throughelectrode 54. Wiring layers60 mutually connected through the throughelectrode 54 are respectively formed on the sides of both surfaces of thecore substrate 52. Further, solder resists56 in which openingparts 56aare disposed on connection parts of the wiring layers60 are respectively formed on the sides of both surfaces of thecore substrate 52. - Also in the
second wiring substrate 50, various wiring substrates such as a coreless wiring substrate can be used while the number of stacks of the wiring layer can be set arbitrarily like thefirst wiring substrate 10. - Further, a conductive ball62xis installed on the connection part of the
wiring layer 60 of the lower surface peripheral edge side of thesecond wiring substrate 50. The conductive ball62xis constructed by covering an outer surface of a copper ball62awith asolder layer 62b. Since thesemiconductor chip 30 is received in a receiving part constructed of thefirst wiring substrate 10 and thesecond wiring substrate 50, a height (diameter) of the conductive ball62xis set higher than a height (the total thickness of thesemiconductor chip 30 and the connection electrode32) of thesemiconductor chip 30. - Then, the conductive ball62xof the lower surface side of the
second wiring substrate 50 is arranged on the connection part of thewiring layer 20 of the peripheral edge side of thefirst wiring substrate 10. Further, the conductive ball62xis bonded to the wiring layers20,60 of the first andsecond wiring substrates solder layer 62bby reflow heating. Or, the conductive ball62xmay be installed on the side of thefirst wiring substrate 10 and thesecond wiring substrate 50 may be arranged on the conductive ball62x. - Consequently, the
wiring layer 20 of thefirst wiring substrate 10 is electrically connected to thewiring layer 60 of thesecond wiring substrate 50 by abump electrode 62 as shown inFIG. 3C . At the same time, thesemiconductor chip 30 is received in a receiving part A surrounded by thebump electrodes 62 between thefirst wiring substrate 10 and thesecond wiring substrate 50. The first embodiment is in a state of disposing a gap d between an upper surface of theadhesive layer 40 on thesemiconductor chip 30 and a lower surface of thesecond wiring substrate 50. - In this manner, a
stacked wiring member 2 constructed by stacking thesecond wiring substrate 50 on thefirst wiring substrate 10 on which thesemiconductor chip 30 is mounted by flip chip bonding is obtained. - Then, a
molding mold 70 basically constructed by alower mold 72 and anupper mold 74 is prepared as shown inFIG. 4 . Themolding mold 70 is a metal mold for being filled with a molding resin by a transfer molding construction method. A recessedpart 72acorresponding to thefirst wiring substrate 10 of the stackedwiring member 2 is disposed in the upper surface side of thelower mold 72. Also, a recessedpart 74acorresponding to thesecond wiring substrate 50 of the stackedwiring member 2 is disposed in the lower surface side of theupper mold 74. - Then, the stacked
wiring member 2 is arranged in the recessedpart 72aof thelower mold 72 and theupper mold 74 is arranged on thelower mold 72 so as to receive thesecond wiring substrate 50 of the stackedwiring member 2 in the recessedpart 74aof theupper mold 74. - By pinching the stacked
wiring member 2 by thelower mold 72 and theupper mold 74 in this manner, the receiving part A between thefirst wiring substrate 10 and thesecond wiring substrate 50 becomes a cavity C filled with a resin. Also, a gap is disposed between thelower mold 72 and theupper mold 74 in the outside of one end of the stackedwiring member 2 and the gap forms a resin supply part B (a molding gate) connected to the cavity C. It is constructed so that a melted resin passes through the resin supply part B and flows into the cavity C. - By the transfer molding construction method using such a
molding mold 70, the melted resin is allowed to flow into the side of the cavity C through the resin supply part B. After the whole cavity C is filled with the resin, theupper mold 74 and thelower mold 72 are detached from the stackedwiring member 2 and a gate resin part formed in the resin supply part B is broken off and thereby, the gate resin part is separated from the resin with which the inside of the cavity C is filled. - Consequently, a gap between the
first wiring substrate 10 and thesecond wiring substrate 50 is filled with amolding resin 76 and thesemiconductor chip 30 is sealed with the resin as shown inFIG. 5 . A mold release material (wax) is included in themolding resin 76 used by the transfer molding construction method in order to be easily detached from themolding mold 70. Therefore, when themolding resin 76 is directly formed on the mirror surface in the case of performing polishing processing of the upper surface of thesemiconductor chip 30, adhesion properties are low and peeling at its interface tends to occur. - As the mold release material (wax), there is a natural material or a chemical synthetic material. As the natural material, for example, there is carnauba wax obtained by using wax present on a surface of a leaf of a palm plant as a raw material.
- Also, 65 to 85% (for example, 75%) fillers with a diameter of about 30 μm are contained in the
molding resin 76 and adhesion properties to thesemiconductor chip 30 tend to be low from the standpoint of a small resin component. - However, in the embodiment, the
adhesive layer 40 is disposed on the upper surface of thesemiconductor chip 30, so that themolding resin 76 is formed on theadhesive layer 40 with sufficient adhesion properties. As a result of that, themolding resin 76 is formed with sufficient adhesion properties to thesemiconductor chip 30 by a function of theadhesive layer 40. - Thereafter,
external connection terminals 78 are disposed by, for example, installing solder balls in the connection parts of thewiring layer 20 of the lower surface side of thefirst wiring substrate 10. - By the above, a resin-sealed semiconductor apparatus1 of the first embodiment is obtained as shown in
FIG. 5 . - As shown in
FIG. 5 , theconnection electrode 32 of thesemiconductor chip 30 is mounted on thewiring layer 20 of the upper surface side of thefirst wiring substrate 10 described inFIG. 2A by flip chip bonding in the semiconductor apparatus1 of the first embodiment. A gap between the lower portion of thesemiconductor chip 30 and the upper surface of thefirst wiring substrate 10 is filled with theunder fill resin 18. Polishing processing of the upper surface of thesemiconductor chip 30 is performed and surface roughness (Ra) of its mirror surface becomes about 10 μm and the surface is smoothed. - The
adhesive layer 40 is formed on the upper surface (mirror surface) of thesemiconductor chip 30. As theadhesive layer 40, for example, a coupling material or a resin without including a mold release material is used. - The
second wiring substrate 50 described inFIG. 3B is stacked and arranged on thefirst wiring substrate 10 through thebump electrode 62. Thewiring layer 20 of thefirst wiring substrate 10 is electrically connected to thewiring layer 60 of thesecond wiring substrate 50 through thebump electrode 62. - A height of the
bump electrode 62 is set higher than a height of thesemiconductor chip 30, and thesemiconductor chip 30 is received between the first andsecond wiring substrates second wiring substrates molding resin 76 and thesemiconductor chip 30 is sealed with themolding resin 76. - Thus, the
adhesive layer 40 is formed on the upper surface (mirror surface) of thesemiconductor chip 30 and the top of theadhesive layer 40 is filled with themolding resin 76. That is, themolding resin 76 is interposed between an upper surface of theadhesive layer 40 on thesemiconductor chip 30 and a lower surface of thesecond wiring substrate 50. - Consequently, the
molding resin 76 is formed with sufficient adhesion properties to thesemiconductor chip 30 through theadhesive layer 40. - Therefore, even when the semiconductor apparatus1 absorbs moisture and the moisture gathered at an interface between different materials evaporates (vaporizes) by heating treatment and thereby volume expansion is caused, the
semiconductor chip 30, theadhesive layer 40 and themolding resin 76 adhere mutually by high adhesion force, so that peeling is prevented from occurring at their interfaces. - As a result of that, reliability in the case of actually using the semiconductor apparatus1 can be improved while a yield can be improved in moisture absorption and heating tests of the semiconductor apparatus1.
FIGS. 6 and 7 are sectional views showing a manufacturing method of a semiconductor apparatus of a second embodiment of the invention.- The second embodiment is characterized in that a semiconductor chip is made to adhere to a second wiring substrate directly by an adhesive layer without interposing a molding resin between an upper surface (mirror surface) of the semiconductor chip and a lower surface of the second wiring substrate.
- In the second embodiment, the detailed description is omitted by assigning the same numerals to the same elements and the same steps as those of the first embodiment.
- In the manufacturing method of the semiconductor apparatus of the second embodiment, the same structural body as that of
FIG. 2C of the first embodiment described above is prepared as shown inFIG. 6A . That is, after asemiconductor chip 30 is mounted in afirst wiring substrate 10 by flip chip bonding, a gap between a lower portion of thesemiconductor chip 30 and an upper surface of thefirst wiring substrate 10 is filled with an underfill resin 18. - Then, an
adhesive material 40ais applied to an upper surface (mirror surface) of thesemiconductor chip 30 as shown inFIG. 6B . As theadhesive material 40a, the resin without including the mold release material (wax) described in the first embodiment is suitably used. - Subsequently, as shown in
FIG. 6C , asecond wiring substrate 50 in which conductive balls62xare installed on the lower surface side is stacked and connected on thefirst wiring substrate 10 like the step ofFIG. 3B of the first embodiment. In the second embodiment, the application amount (volume) of theadhesive material 40aor a diameter of the conductive ball62xinstalled on thesecond wiring substrate 50 is adjusted so that a gap does not occur by making contact between theadhesive material 40aon thesemiconductor chip 30 and a lower surface of thesecond wiring substrate 50. - Or, the
adhesive material 40amay be formed using a coupling material as a main material. In this case, for example, an adhesive in which the coupling material is included is used and its application amount (volume) or a diameter of the conductive ball62xinstalled on thesecond wiring substrate 50 is adjusted. - Consequently, as shown in
FIGS. 6( c) and7(a), the uncuredadhesive material 40aon thesemiconductor chip 30 is pushed in a lateral direction by thesecond wiring substrate 50 and flows and a gap between the upper surface (mirror surface) of thesemiconductor chip 30 and the lower surface of thesecond wiring substrate 50 is filled with theadhesive material 40a. - Further, an
adhesive layer 40 is obtained by heat-treating and curing theadhesive material 40a. Also at the same time, awiring layer 20 of thefirst wiring substrate 10 is electrically connected to awiring layer 60 of thesecond wiring substrate 50 through abump electrode 62. - In the second embodiment, a gap is not disposed between the
second wiring substrate 50 and theadhesive layer 40 on thesemiconductor chip 30, and thesemiconductor chip 30 is received in a receiving part A between the first andsecond wiring substrates second wiring substrate 50 and an upper surface of thesemiconductor chip 30 with theadhesive layer 40. - Further, as shown in
FIG. 7B , the receiving part A (cavity) between the first andsecond wiring substrates molding resin 76 by a transfer molding construction method similar to that of the first embodiment. The receiving part is filled with themolding resin 76 so as to surround thesemiconductor chip 30 and theadhesive layer 40. - Consequently, a
semiconductor apparatus 1aof the second embodiment is obtained. The second embodiment has an effect similar to that of the first embodiment. - In the first embodiment described above, a gap between the
adhesive layer 40 on thesemiconductor chip 30 and the solder resist56 of the lower surface of thesecond wiring substrate 50 is filled with themolding resin 76. In the first embodiment, adhesion properties between thesemiconductor chip 30 and themolding resin 76 are improved by theadhesive layer 40, but the case where adhesion properties between themolding resin 76 and the solder resist56 of thesecond wiring substrate 50 are not always obtained sufficiently depending on their materials is assumed. - In the second embodiment, filling with the
adhesive layer 40 is performed without interposing themolding resin 76 between the upper surface (mirror surface) of thesemiconductor chip 30 and the lower surface side of thesecond wiring substrate 50. - Therefore, even when adhesion properties between the
molding resin 76 and the solder resist56 of thesecond wiring substrate 50 are not obtained sufficiently, the solder resist56 is arranged with sufficient adhesion properties to thesemiconductor chip 30 by theadhesive layer 40 and a strength of adhesion between first andsecond wiring substrates - While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (10)
1. A semiconductor apparatus comprising:
a first wiring substrate;
a second wiring substrate which is stacked and connected on the first wiring substrate through a bump electrode;
a semiconductor chip which is mounted on the first wiring substrate by flip chip bonding and received between the first wiring substrate and the second wiring substrate, an upper surface of the semiconductor chip being subject to a mirror treatment;
an adhesive layer which is formed on the upper surface of the semiconductor chip; and
a molding resin which is filled in a gap between the first wiring substrate and the second wiring substrate.
2. A semiconductor apparatus as claimed inclaim 1 , wherein the molding resin is interposed between an upper surface of the adhesive layer on the semiconductor chip and a lower surface of the second wiring substrate.
3. A semiconductor apparatus as claimed inclaim 1 , wherein the adhesive layer on the semiconductor chip is in contact with a lower surface of the second wiring substrate and the molding resin is formed so as to surround the semiconductor chip and the adhesive layer.
4. A semiconductor apparatus as claimed inclaim 1 , wherein the adhesive layer is formed of a coupling material or a resin without including a mold release material and the molding resin includes the mold release material.
5. A semiconductor apparatus as claimed inclaim 1 , further comprising:
an under fill resin which fills in a gap between a lower side of the semiconductor chip and an upper surface of the first wiring substrate,
wherein the adhesive layer is made of the same resin as the under fill resin.
6. A manufacturing method of a semiconductor apparatus, comprising steps of:
mounting a semiconductor chip, an upper surface of which is subject to a mirror treatment, on a first wiring substrate by flip chip bonding;
forming an adhesive layer on the upper surface of the semiconductor chip;
receiving the semiconductor chip between the first wiring substrate and a second wiring substrate by stacking the second wiring substrate on the first wiring substrate through a bump electrode; and
filling a gap between the first wiring substrate and the second wiring substrate with a molding resin by a transfer molding construction method.
7. A manufacturing method of a semiconductor apparatus as claimed inclaim 6 , wherein in the step of receiving the semiconductor chip, a gap is disposed between an upper surface of the adhesive layer on the semiconductor chip and a lower surface of the second wiring substrate, and
wherein in the step of filling with the molding resin, the gap disposed between the upper surface of the adhesive layer and the lower surface of the second wiring substrate is filled with the molding resin.
8. A manufacturing method of a semiconductor apparatus as claimed inclaim 6 , wherein in the step of receiving the semiconductor chip, the second wiring substrate is arranged in a state in which the adhesive layer on the semiconductor chip is in contact with a lower surface of the second wiring substrate, and
wherein in the step of filling with the molding resin, the molding resin is filled so as to surround the semiconductor chip and the adhesive layer.
9. A manufacturing method of a semiconductor apparatus as claimed inclaim 6 , wherein the adhesive layer is formed of a coupling material or a resin without including a mold release material and the molding resin includes the mold release material.
10. A manufacturing method of a semiconductor apparatus as claimed inclaim 6 , further comprising a step of:
filling a gap between a lower side of the semiconductor chip and an upper surface of the first wiring substrate with an under fill resin after the step of mounting the semiconductor chip,
wherein the adhesive layer is formed of the same resin as the under fill resin.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008321038AJP2010147153A (en) | 2008-12-17 | 2008-12-17 | Semiconductor apparatus and method of manufacturing the same |
| JP2008-321038 | 2008-12-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20100148332A1true US20100148332A1 (en) | 2010-06-17 |
| US8106495B2 US8106495B2 (en) | 2012-01-31 |
Family
ID=42239520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/639,421Active2030-03-23US8106495B2 (en) | 2008-12-17 | 2009-12-16 | Semiconductor apparatus and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8106495B2 (en) |
| JP (1) | JP2010147153A (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646668A (en)* | 2011-02-17 | 2012-08-22 | 三星电子株式会社 | Intermediate semiconductor package with through-substrate hole and manufacturing method thereof |
| CN103165555A (en)* | 2011-12-08 | 2013-06-19 | 欣兴电子股份有限公司 | Package structure of stacked package and manufacturing method thereof |
| CN103187405A (en)* | 2012-01-03 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Methods and apparatus for package on package devices with reduced strain |
| US20140048310A1 (en)* | 2012-08-16 | 2014-02-20 | Apple Inc. | Printed Circuit Solder Connections |
| WO2014120483A1 (en)* | 2013-01-29 | 2014-08-07 | Apple Inc. | ULTRA THIN PoP PACKAGE |
| WO2014126818A1 (en)* | 2013-02-13 | 2014-08-21 | Qualcomm Incorporated | Dual substrate, power distribution and thermal solution for direct stacked integrated devices |
| US20140335657A1 (en)* | 2011-05-02 | 2014-11-13 | Samsung Electronics Co., Ltd | Stack packages having fastening element and halogen-free inter-package connector |
| US20150035148A1 (en)* | 2013-07-30 | 2015-02-05 | Heeseok Lee | Semiconductor packages and methods of fabricating the same |
| US20150041972A1 (en)* | 2013-08-12 | 2015-02-12 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and fabrication method thereof |
| CN104851962A (en)* | 2014-02-13 | 2015-08-19 | 日亚化学工业株式会社 | Light emitting device |
| KR20160017381A (en)* | 2014-08-05 | 2016-02-16 | 삼성전자주식회사 | Semiconductor Package and methods for manufacturing the same |
| US20160056119A1 (en)* | 2014-08-20 | 2016-02-25 | Samsung Electro-Mechanics Co., Ltd. | Flip chip package and manufacturing method thereof |
| CN106601709A (en)* | 2015-10-15 | 2017-04-26 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| US9640505B2 (en)* | 2011-12-21 | 2017-05-02 | Mediatek Inc. | Semiconductor package with trace covered by solder resist |
| US9659893B2 (en)* | 2011-12-21 | 2017-05-23 | Mediatek Inc. | Semiconductor package |
| US9831105B2 (en)* | 2013-09-26 | 2017-11-28 | Besi Netherlands B.V. | Method for moulding and surface processing electronic components and electronic component produced with this method |
| US20190229060A1 (en)* | 2016-01-22 | 2019-07-25 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and manufacturing method of the same |
| CN111403368A (en)* | 2019-01-02 | 2020-07-10 | 台湾积体电路制造股份有限公司 | Semiconductor package |
| US20210384125A1 (en)* | 2019-01-02 | 2021-12-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming package structure |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5279631B2 (en)* | 2009-06-23 | 2013-09-04 | 新光電気工業株式会社 | Electronic component built-in wiring board and method of manufacturing electronic component built-in wiring board |
| US8466997B2 (en)* | 2009-12-31 | 2013-06-18 | Stmicroelectronics Pte Ltd. | Fan-out wafer level package for an optical sensor and method of manufacture thereof |
| US20110156240A1 (en)* | 2009-12-31 | 2011-06-30 | Stmicroelectronics Asia Pacific Pte. Ltd. | Reliable large die fan-out wafer level package and method of manufacture |
| US8502394B2 (en)* | 2009-12-31 | 2013-08-06 | Stmicroelectronics Pte Ltd. | Multi-stacked semiconductor dice scale package structure and method of manufacturing same |
| US8436255B2 (en)* | 2009-12-31 | 2013-05-07 | Stmicroelectronics Pte Ltd. | Fan-out wafer level package with polymeric layer for high reliability |
| US8884422B2 (en)* | 2009-12-31 | 2014-11-11 | Stmicroelectronics Pte Ltd. | Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture |
| US8742603B2 (en)* | 2010-05-20 | 2014-06-03 | Qualcomm Incorporated | Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) |
| US8378477B2 (en)* | 2010-09-14 | 2013-02-19 | Stats Chippac Ltd. | Integrated circuit packaging system with film encapsulation and method of manufacture thereof |
| US8461676B2 (en) | 2011-09-09 | 2013-06-11 | Qualcomm Incorporated | Soldering relief method and semiconductor device employing same |
| US9013037B2 (en) | 2011-09-14 | 2015-04-21 | Stmicroelectronics Pte Ltd. | Semiconductor package with improved pillar bump process and structure |
| US8916481B2 (en) | 2011-11-02 | 2014-12-23 | Stmicroelectronics Pte Ltd. | Embedded wafer level package for 3D and package-on-package applications, and method of manufacture |
| US8779601B2 (en) | 2011-11-02 | 2014-07-15 | Stmicroelectronics Pte Ltd | Embedded wafer level package for 3D and package-on-package applications, and method of manufacture |
| US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
| US9385006B2 (en)* | 2012-06-21 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SOP fan-out package |
| JP6230794B2 (en)* | 2013-01-31 | 2017-11-15 | 新光電気工業株式会社 | Electronic component built-in substrate and manufacturing method thereof |
| KR101486790B1 (en) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | Micro Lead Frame for semiconductor package |
| TWI533421B (en) | 2013-06-14 | 2016-05-11 | 日月光半導體製造股份有限公司 | Semiconductor package structure and semiconductor process |
| US9299650B1 (en) | 2013-09-25 | 2016-03-29 | Stats Chippac Ltd. | Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof |
| US9905491B1 (en) | 2013-09-27 | 2018-02-27 | STATS ChipPAC Pte. Ltd. | Interposer substrate designs for semiconductor packages |
| KR101563911B1 (en) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| US20150221570A1 (en)* | 2014-02-04 | 2015-08-06 | Amkor Technology, Inc. | Thin sandwich embedded package |
| US9693455B1 (en) | 2014-03-27 | 2017-06-27 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with plated copper posts and method of manufacture thereof |
| US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
| US9859200B2 (en)* | 2014-12-29 | 2018-01-02 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof |
| JP6444269B2 (en) | 2015-06-19 | 2018-12-26 | 新光電気工業株式会社 | Electronic component device and manufacturing method thereof |
| JP6570924B2 (en)* | 2015-08-31 | 2019-09-04 | 新光電気工業株式会社 | Electronic component device and manufacturing method thereof |
| KR20180095371A (en)* | 2017-02-17 | 2018-08-27 | 엘지전자 주식회사 | Mobile terminal and printed circuit board |
| JP6917295B2 (en)* | 2017-12-25 | 2021-08-11 | 新光電気工業株式会社 | Electronic component built-in board, sheet board |
| US11721657B2 (en) | 2019-06-14 | 2023-08-08 | Stmicroelectronics Pte Ltd | Wafer level chip scale package having varying thicknesses |
| KR20220093507A (en)* | 2020-12-28 | 2022-07-05 | 삼성전기주식회사 | Package embedded substrate |
| CN114975325B (en)* | 2021-02-25 | 2025-01-10 | 长鑫存储技术有限公司 | Semiconductor structure and method for preparing semiconductor structure |
| EP4181189B1 (en)* | 2021-02-25 | 2025-05-21 | Changxin Memory Technologies, Inc. | Semiconductor structure and preparation method therefor |
| KR20220169284A (en) | 2021-06-18 | 2022-12-27 | 삼성전자주식회사 | Semiconductor package and manufacturing method thereof |
| US12107037B2 (en)* | 2021-11-03 | 2024-10-01 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing electronic devices |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025648A (en)* | 1997-04-17 | 2000-02-15 | Nec Corporation | Shock resistant semiconductor device and method for producing same |
| US6344682B1 (en)* | 1999-02-01 | 2002-02-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device comprising a semiconductor element mounted on a substrate and covered by a wiring board |
| US20050003587A1 (en)* | 2003-05-02 | 2005-01-06 | Seiko Epson Corporation | Method of manufacturing semiconductor device and method of manufacturing electronics device |
| US7141873B2 (en)* | 2003-10-10 | 2006-11-28 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US20070096287A1 (en)* | 2005-10-27 | 2007-05-03 | Makoto Araki | Semiconductor device and a method of manufacturing the same |
| US20070096334A1 (en)* | 2005-10-27 | 2007-05-03 | Takeshi Kawabata | Stacked semiconductor module |
| US20080157329A1 (en)* | 2006-12-26 | 2008-07-03 | Akinobu Inoue | Electronic component contained substrate |
| US7982298B1 (en)* | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04254829A (en)* | 1991-02-07 | 1992-09-10 | Seiko Epson Corp | active device |
| JPH0577423A (en)* | 1991-09-24 | 1993-03-30 | Canon Inc | Ink-jet recording head |
| JP2765606B2 (en)* | 1992-07-02 | 1998-06-18 | シャープ株式会社 | Semiconductor package structure |
| JP3866880B2 (en)* | 1999-06-28 | 2007-01-10 | 株式会社日立製作所 | Resin-sealed electronic device |
| JP4630449B2 (en)* | 2000-11-16 | 2011-02-09 | Ｔｏｗａ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2003347722A (en) | 2002-05-23 | 2003-12-05 | Ibiden Co Ltd | Multilayer electronic parts mounting substrate and its fabricating method |
| JP4346333B2 (en)* | 2003-03-26 | 2009-10-21 | 新光電気工業株式会社 | Method for manufacturing multilayer circuit board incorporating semiconductor element |
| JP2007048860A (en)* | 2005-08-09 | 2007-02-22 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| JPWO2007069606A1 (en) | 2005-12-14 | 2009-05-21 | 新光電気工業株式会社 | Manufacturing method of chip embedded substrate |
| JP5128180B2 (en)* | 2007-05-28 | 2013-01-23 | 新光電気工業株式会社 | Chip built-in substrate |
- 2008
- 2008-12-17JPJP2008321038Apatent/JP2010147153A/enactivePending
- 2009
- 2009-12-16USUS12/639,421patent/US8106495B2/enactiveActive
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025648A (en)* | 1997-04-17 | 2000-02-15 | Nec Corporation | Shock resistant semiconductor device and method for producing same |
| US6344682B1 (en)* | 1999-02-01 | 2002-02-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device comprising a semiconductor element mounted on a substrate and covered by a wiring board |
| US20050003587A1 (en)* | 2003-05-02 | 2005-01-06 | Seiko Epson Corporation | Method of manufacturing semiconductor device and method of manufacturing electronics device |
| US7141873B2 (en)* | 2003-10-10 | 2006-11-28 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US20070096287A1 (en)* | 2005-10-27 | 2007-05-03 | Makoto Araki | Semiconductor device and a method of manufacturing the same |
| US20070096334A1 (en)* | 2005-10-27 | 2007-05-03 | Takeshi Kawabata | Stacked semiconductor module |
| US20080157329A1 (en)* | 2006-12-26 | 2008-07-03 | Akinobu Inoue | Electronic component contained substrate |
| US7982298B1 (en)* | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
Cited By (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646668A (en)* | 2011-02-17 | 2012-08-22 | 三星电子株式会社 | Intermediate semiconductor package with through-substrate hole and manufacturing method thereof |
| US20140335657A1 (en)* | 2011-05-02 | 2014-11-13 | Samsung Electronics Co., Ltd | Stack packages having fastening element and halogen-free inter-package connector |
| US9040351B2 (en)* | 2011-05-02 | 2015-05-26 | Samsung Electronics Co., Ltd. | Stack packages having fastening element and halogen-free inter-package connector |
| CN103165555A (en)* | 2011-12-08 | 2013-06-19 | 欣兴电子股份有限公司 | Package structure of stacked package and manufacturing method thereof |
| US9640505B2 (en)* | 2011-12-21 | 2017-05-02 | Mediatek Inc. | Semiconductor package with trace covered by solder resist |
| US9659893B2 (en)* | 2011-12-21 | 2017-05-23 | Mediatek Inc. | Semiconductor package |
| CN103187405A (en)* | 2012-01-03 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Methods and apparatus for package on package devices with reduced strain |
| US20140048310A1 (en)* | 2012-08-16 | 2014-02-20 | Apple Inc. | Printed Circuit Solder Connections |
| US8969730B2 (en)* | 2012-08-16 | 2015-03-03 | Apple Inc. | Printed circuit solder connections |
| WO2014120483A1 (en)* | 2013-01-29 | 2014-08-07 | Apple Inc. | ULTRA THIN PoP PACKAGE |
| CN104969347A (en)* | 2013-01-29 | 2015-10-07 | 苹果公司 | Ultra thin PoP package |
| WO2014126818A1 (en)* | 2013-02-13 | 2014-08-21 | Qualcomm Incorporated | Dual substrate, power distribution and thermal solution for direct stacked integrated devices |
| US20150035148A1 (en)* | 2013-07-30 | 2015-02-05 | Heeseok Lee | Semiconductor packages and methods of fabricating the same |
| US20150041972A1 (en)* | 2013-08-12 | 2015-02-12 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and fabrication method thereof |
| CN104377182A (en)* | 2013-08-12 | 2015-02-25 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| US9831105B2 (en)* | 2013-09-26 | 2017-11-28 | Besi Netherlands B.V. | Method for moulding and surface processing electronic components and electronic component produced with this method |
| CN104851962A (en)* | 2014-02-13 | 2015-08-19 | 日亚化学工业株式会社 | Light emitting device |
| US9378987B2 (en)* | 2014-08-05 | 2016-06-28 | Samsung Electronics Co., Ltd. | Semiconductor packages including gap in interconnection terminals and methods of manufacturing the same |
| KR102154830B1 (en)* | 2014-08-05 | 2020-09-11 | 삼성전자주식회사 | Semiconductor Package and methods for manufacturing the same |
| KR20160017381A (en)* | 2014-08-05 | 2016-02-16 | 삼성전자주식회사 | Semiconductor Package and methods for manufacturing the same |
| US9583368B2 (en) | 2014-08-20 | 2017-02-28 | Samsung Electro-Mechanics Co., Ltd. | Flip chip package and manufacturing method thereof |
| US20160056119A1 (en)* | 2014-08-20 | 2016-02-25 | Samsung Electro-Mechanics Co., Ltd. | Flip chip package and manufacturing method thereof |
| CN106601709A (en)* | 2015-10-15 | 2017-04-26 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| US20190229060A1 (en)* | 2016-01-22 | 2019-07-25 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and manufacturing method of the same |
| US10636743B2 (en)* | 2016-01-22 | 2020-04-28 | Samsung Electronics Co., Ltd. | Electronic component package and manufacturing method of the same |
| CN111403368A (en)* | 2019-01-02 | 2020-07-10 | 台湾积体电路制造股份有限公司 | Semiconductor package |
| US20210375755A1 (en)* | 2019-01-02 | 2021-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with improved interposer structure |
| US20210384125A1 (en)* | 2019-01-02 | 2021-12-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming package structure |
| US11848265B2 (en)* | 2019-01-02 | 2023-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with improved interposer structure |
| US12094819B2 (en)* | 2019-01-02 | 2024-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming package structure |
| TWI860313B (en)* | 2019-01-02 | 2024-11-01 | 台灣積體電路製造股份有限公司 | Semiconductor package |
| US12237262B2 (en) | 2019-01-02 | 2025-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with improved interposer structure |
| US12308313B2 (en) | 2019-01-02 | 2025-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with improved interposer structure |
Also Published As
| Publication number | Publication date |
|---|---|
| US8106495B2 (en) | 2012-01-31 |
| JP2010147153A (en) | 2010-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8106495B2 (en) | Semiconductor apparatus and manufacturing method thereof | |
| CN101017786B (en) | Manufacturing method of semiconductor package | |
| US6166434A (en) | Die clip assembly for semiconductor package | |
| US8334602B2 (en) | Die package including encapsulated die and method of manufacturing the same | |
| EP1670057B1 (en) | Manufacturing method of chip integrated substrate | |
| US7906857B1 (en) | Molded integrated circuit package and method of forming a molded integrated circuit package | |
| JP5064288B2 (en) | Manufacturing method of semiconductor device | |
| WO2005119776A1 (en) | Semiconductor device having three-dimensional stack structure and method for manufacturing the same | |
| CN101325188A (en) | Wafer level semiconductor package with double-sided build-up and method thereof | |
| US6002171A (en) | Integrated heat spreader/stiffener assembly and method of assembly for semiconductor package | |
| KR101003437B1 (en) | Electronic component mounting structure and manufacturing method | |
| US20110147905A1 (en) | Semiconductor device and method of manufacturing the same | |
| JPH0296343A (en) | Manufacture of hybrid integrated circuit device | |
| KR100804856B1 (en) | Manufacturing Method of Semiconductor Device | |
| US6943059B2 (en) | Flip chip mounting method of forming a solder bump on a chip pad that is exposed through an opening formed in a polyimide film that includes utilizing underfill to bond the chip to a substrate | |
| TWI420610B (en) | Semiconductor device and manufacturing method therefor | |
| US20080290514A1 (en) | Semiconductor device package and method of fabricating the same | |
| JP2001203297A (en) | Producing method for semiconductor device | |
| JP2000150716A (en) | Package structure and semiconductor device, manufacture of package and semiconductor device | |
| JP3990814B2 (en) | Electronic component manufacturing method and electronic component manufacturing apparatus | |
| TW594893B (en) | Wafer level packaging method with a stress absorbing film | |
| JP2957955B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4408015B2 (en) | Manufacturing method of semiconductor device | |
| JP2002319650A (en) | Flip chip mounting body and semiconductor chip mounting method | |
| JP5125309B2 (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment | Owner name:SHINKO ELECTRIC INDUSTRIES CO., LTD.,JAPAN Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KAJIKI, ATSUNORI;REEL/FRAME:023663/0542 Effective date:20091210 Owner name:SHINKO ELECTRIC INDUSTRIES CO., LTD., JAPAN Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KAJIKI, ATSUNORI;REEL/FRAME:023663/0542 Effective date:20091210 | |
| STCF | Information on status: patent grant | Free format text:PATENTED CASE | |
| FPAY | Fee payment | Year of fee payment:4 | |
| MAFP | Maintenance fee payment | Free format text:PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment:8 | |
| MAFP | Maintenance fee payment | Free format text:PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment:12 |