US20100102433A1 - Apparatus for use in semiconductor wafer processing for laterally displacing individual semiconductor devices away from one another - Google Patents

Abstract

A chip-scale or wafer-level package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed package, is provided. The package may be formed by disposing a first passivation layer on the passive or back side surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 11/409,350 filed Apr. 21, 2006, pending, which application is a divisional of U.S. patent application Ser. No. 10/767,952, filed Jan. 29, 2004, now U.S. Pat. No. 7,169,691, issued Jan. 30, 2007, the entire disclosure of each of which is hereby incorporated herein by this reference.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to wafer-level packaging for a semiconductor die. More particularly, the present invention relates to a semiconductor die having all of its sides sealed by a passivation layer and an improved method for forming the passivation layers on the semiconductor die.
• 2. State of the Art
• A solid-state electronic device in the form of a semiconductor die or chip is conventionally manufactured of materials such as silicon, germanium, or gallium arsenide. Circuitry is formed on an active surface of the semiconductor die and may include further levels of circuitry within the die itself. Bond pads are conventionally formed on the active surface to provide electrical contacts for the semiconductor die circuitry. Due to the materials used and the intricate nature of construction, semiconductor dice are highly susceptible to physical damage or contamination from environmental conditions including, for example, moisture.
• Conventionally, attempts to protect a semiconductor die from environmental conditions have included mounting the die within a plastic, metal or ceramic package that provides hermetic sealing and prevents environmental elements from physically contacting the die. Such a package also conventionally includes conductive leads or similar conductive elements for attaching the die bond pads to external electrical connections. Such a packaging approach, while providing some protection for the semiconductor die from external conditions, increases the cost of production by requiring additional materials and manufacturing steps. Additionally, such a packaging approach results in a relatively large device size which may unnecessarily consume valuable real estate when mounted to a carrier substrate. Moreover, the conductive lead structures used in such packaging approaches may negatively influence processing speed and, further, may present opportunities for moisture incursion at interfaces between the conductive leads and other packaging materials.
• There have been some efforts to reduce the size and cost of these electronic devices which have resulted in, more or less, doing away with the above-described packaging materials. Such efforts include, for example, fabrication processes commonly referred to as wafer-level packaging (WLP) or chip-scale packaging (CSP). Such packaging methods include disposing a relatively thin protective coating or passivation layer on one or more surfaces of the semiconductor die during fabrication. Connecting elements, such as conductive bumps, are formed over the die bond pads using a variety of known techniques such as screen printing or ball bumping. A redistribution layer may also be formed on the active surface of the semiconductor die to allow the formation of conductive bumps at locations other than directly above the bond pads. The conductive bumps may then be electrically connected to circuitry on a carrier substrate or other device through a process such as tape automated bonding (TAB), or by direct attachment including mounting the semiconductor die in a flip-chip fashion on the carrier substrate.
• Formation of the passivation layer on the surfaces of the semiconductor die may include sealing exposed die surfaces with a coating of, for example, silicon nitride (SiN), silicon dioxide (SiO₂), or other materials such as an epoxy or a polymer. In prior art processes, such coatings might be deposited on the active and passive surfaces of a wafer, which contains an array of solid-state electronic devices, with the wafer being subsequently singulated to provide individual semiconductor dice. The semiconductor dice which result from this fabrication process suffer from the fact that their side edges are left exposed after singulation of the dice from the wafer. The possibility remains, therefore, that moisture may enter the side edges of an individual die and damage nearby circuitry.
• It is further noted that, when processes such as wafer-level packaging and chip-scale packaging are utilized, difficulties may arise in the dicing of the wafer to effect singulation of the semiconductor dice therefrom. Such dicing is conventionally accomplished by cutting the wafer along street lines between the individual semiconductor dice with a wafer saw. However, when a passivation layer or coating on the wafer is formed of a polymer or similar material, the wafer saw tends to gum-up during singulation, thereby reducing cutting efficiency and requiring down time for cleaning and maintenance of the saw.
• In order to rectify some of these shortcomings, various attempts have been made to provide additional passivation layers on the side edges of a semiconductor die. For example, U.S. Pat. No. 5,451,550 to Wills et al., U.S. Pat. No. 5,742,094 to Ting and U.S. Pat. No. 5,933,713 to Farnworth teach methods of providing side edge passivation layers to semiconductor dice. While the methods disclosed by these patents provide such side edge passivation layers, they may require further processing of the semiconductor dice on an individual basis, which becomes time consuming, introduces additional expense, and may introduce additional complexities into the fabrication process.
• Other attempts to improve WLP and CSP processes include, for instance, U.S. Pat. No. 5,956,605 to Akram et al. and U.S. Pat. No. 6,303,977 to Schroen et al., which generally contemplate forming side edge passivation layers after wafer singulation. However, such methods may still result in die surfaces which are not completely coated and may require additional coating steps subsequent to attachment of the semiconductor die to a carrier substrate or other device.
• In view of the shortcomings in the art, it would be advantageous to provide an improved wafer-level packaging method for sealing the surfaces of a semiconductor die.
BRIEF SUMMARY OF THE INVENTION
• In accordance with one aspect of the present invention, a method of fabricating semiconductor packages is provided. The method includes providing a semiconductor wafer having a plurality of semiconductor devices formed thereon. The semiconductor wafer is adhered to a flexible membrane and diced to separate the plurality of semiconductor devices and define a plurality of side edges on each semiconductor device of the plurality of semiconductor devices. The flexible membrane is stretched to laterally displace the plurality of semiconductor devices relative to one another, thereby exposing the side edges of each semiconductor device. A passivation layer is then formed on the plurality of side edges of at least one of the plurality of semiconductor devices.
• In accordance with another aspect of the present invention, an apparatus is provided for use in fabricating semiconductor devices. The apparatus includes a frame and a membrane coupled to the frame. The membrane is configured to adhere to a surface of a semiconductor wafer. The frame is configured to stretch the membrane in at least one lateral direction while a semiconductor wafer is adhered thereto. The frame may include a plurality of frame members wherein at least two of the plurality of frame members are configured to be displaced laterally away from each other to stretch the membrane in the at least one lateral direction. The membrane may comprise an elastic film and may be formed of a material comprising polyethylene. In another embodiment, the membrane may comprise a flexible resin material.
• In accordance with yet another aspect of the present invention, a method of forming a memory device is provided. The method includes providing a semiconductor wafer having a plurality of semiconductor devices formed thereon. The semiconductor wafer is adhered to a flexible membrane and diced to separate the plurality of semiconductor devices and define a plurality of side edges on each semiconductor device of the plurality of semiconductor devices. The flexible membrane is stretched to laterally displace the plurality of semiconductor devices relative to one another, thereby exposing the side edges of each semiconductor device. A passivation layer is then formed on the plurality of side edges of at least one of the plurality of semiconductor devices. With the passivation layers formed on the active surface and side edges of the at least one semiconductor device, the at least one semiconductor device is electrically coupled to a carrier substrate.
• In accordance with a further aspect of the present invention, another method of fabricating a semiconductor device is provided. The method includes providing a semiconductor wafer having an active surface and an opposing passive surface and disposing a layer of polymer material on the passive surface. A plurality of cut lines is sawed substantially through the semiconductor wafer to define a plurality of semiconductor devices. Each cut line of the plurality exhibits a depth which does not substantially extend into the layer of polymer. A force is then applied to the semiconductor wafer to fracture the polymer layer along a plurality of lines which substantially corresponds with the plurality of cut lines.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
• The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
• FIG. 1 is a perspective view of a semiconductor wafer containing an array of electronic devices;
• FIG. 2A is a partial sectional view of the wafer shown inFIG. 1 having conductive bumps attached in a direct bump configuration;
• FIG. 2B is a partial sectional view of a wafer having a redistribution layer and associated conductive bumps;
• FIG. 3 is a partial sectional view of a wafer subsequent to a back-grinding operation in accordance with an aspect of the present invention;
• FIG. 4 is a partial sectional view of a wafer having a backside passivation layer formed on a passive surface thereof in accordance with an aspect of the present invention;
• FIG. 5 is a side view of a wafer attached to a frame membrane of a wafer frame;
• FIG. 6 is a partial sectional view of a wafer attached to a wafer frame and after an initial dicing operation;
• FIG. 7 is a partial sectional view of a wafer attached to a wafer frame and after a secondary dicing operation;
• FIGS. 8A and 8B show a partial sectional view and a top view, respectively, of a diced wafer on a stretched frame membrane;
• FIG. 9 is a partial sectional view of a diced wafer including active surface and side edge passivation layers formed on the individual devices thereof;
• FIG. 10 is a partial sectional view showing the semiconductor dice after removing a portion of the active surface passivation layer to expose the conductive bumps; and
• FIG. 11 is a side view showing a semiconductor die attached to a carrier substrate in a flip-chip orientation.
DETAILED DESCRIPTION OF THE INVENTION
• The following embodiments of the present invention are provided as examples to assist in a thorough understanding of the present invention. It should be apparent, however, that various additions, modifications and combinations of the embodiments are within the scope of the present invention. In the accompanying drawings, various aspects of the present invention are illustrated to more clearly show the wafer-level packaging structures and methods for their formation. Common elements of the illustrated embodiments are designated with like reference numerals. The drawings are not meant to be illustrative of actual views of any particular portion of a wafer-level packaging structure, but are merely idealized schematic representations that are employed to more clearly and fully depict the invention in connection with the following description.
• Referring toFIG. 1, asemiconductor wafer100 is shown, which contains an array ofsemiconductor devices102 formed thereon and defined by a plurality of streets or street lines104. The array ofsemiconductor devices102 may be conventionally fabricated as circuit layers (not shown) on and/or extending into one side ofwafer100, forming anactive surface106 of thewafer100 and, therefore,semiconductor devices102 formed thereon. The opposite side or backside may remain free of circuitry, leaving apassive surface108 comprised generally of the semiconductor material ofwafer100. In this manner,many semiconductor devices102 may be formed and processed substantially simultaneously for subsequent separation into individual or discrete semiconductor dice as will be described in further detail below.Bond pads112 are also formed on theactive surface106 of each individual ordiscrete semiconductor device102 for electrical interconnection between anindividual semiconductor device102 and, for example, a carrier substrate or other electronic device.
• Apassivation layer114 may be disposed on theactive surface106 during wafer fabrication. Thepassivation layer114 may be formed of, for example, silicon-based materials such as silicon oxides or silicon nitrides, which may be deposited by conventional sputtering or chemical vapor deposition (CVD) processes. Thebond pads112 may be exposed through thepassivation layer114, such as by an etching process.
• Referring toFIG. 2A, a partial sectional view of thewafer100 and, more particularly, asemiconductor device102 thereof is shown.Conductive bumps116 are formed onactive surface106 ofwafer100 in a direct bump configuration overbond pads112 of thesemiconductor device102. Asecond passivation layer118 may be deposited overpassivation layer114, and an under-bump metallization (UBM)120 may be formed onbond pads112 and overlap a portion of first and second passivation layers114,118.Conductive bumps116 are then attached toUBM120 directly overbond pads112, which may include one or more layers of solder-wettable material or other barrier layers of material thereon.Conductive bumps116 may be formed using known techniques such as screen printing or by ball bumping with wire bonding equipment. Exemplary materials forconductive bumps116 may include gold, eutectic tin/lead solder, and conductive or conductor-filled epoxies. Furthermore, while described in terms of bumps, it should be understood thatconductive bumps116 could be configured as balls, columns, pillars, or other desired geometrical configurations.
• Referring briefly toFIG. 2B, a partial sectional view of asemiconductor device102′ according to another embodiment of the present invention is shown. A redistribution layer (RDL) may be used to relocate connection points for thebond pads112 of theindividual semiconductor device102′. This may be required whenbond pads112 of asemiconductor device102′ are not configured in a suitable pattern for attachment or are too closely spaced to allow effective formation ofconductive bumps116. Thus, subsequent to depositingsecond passivation layer118,redistribution circuits122 may be formed thereon.Redistribution circuits122 may be deposited as a layer of metal, polysilicon or other conductive material onsecond passivation layer118 and etched to form a desired circuit pattern. Next, athird passivation layer124 may be deposited overredistribution circuits122 using similar materials and deposition techniques as with first and second passivation layers114,118. Thethird passivation layer124 may then be etched to expose newbump connection locations126 onredistribution circuits122. A layer ofUBM120′ may be formed to coverbump connection locations126 and overlap a portion ofthird passivation layer124, andconductive bumps116 are attached toUBM120′ directly overbump connection locations126.
• While the presently disclosed invention may be practiced in conjunction with either of the embodiments shown and described with respect toFIGS. 2A and 2B, subsequent discussion of the invention will assume reference to the embodiment shown and described with respect toFIG. 2A for purposes of simplicity and clarity.
• Referring to bothFIGS. 2A and 3,FIG. 3 shows a partial sectional view of thewafer100 at a further stage of fabrication as compared to that shown inFIG. 2A. Onceconductive bumps116 are added toactive surface106, thewafer100 may be subjected to a back-grinding process or a chemical-mechanical planarization process to remove a portion of material from the passive orbackside surface108 of thewafer100.
• In removing such material, thewafer100 may be secured in an appropriate frame member or other retaining apparatus (not shown) with theactive surface106 of thewafer100 being secured on a surface of a retaining apparatus so that passive orbackside surface108 of thewafer100 faces upwardly. Thewafer100 may be held in any suitable, known manner to the retaining surface such as, for example, by an adhesive bond, with clamping structures, by drawing a vacuum betweenactive surface106 and the retaining surface or any suitable combination thereof.
• A back-grinding process or chemical-mechanical planarization process may then be employed to remove excess semiconductor material from passive orbackside surface108 of thewafer100, thereby reducing the thickness ofwafer100 to a desired overall thickness and effectively exposing a new passive orbackside surface108′. The thinning of thewafer100 may be desirable in order to minimize the final package size. Additionally, such material removal may reduce the time and expense associated with sawing thewafer100 during subsequent dicing and singulation of theindividual semiconductor devices102. Moreover, thinning of thewafer100 using a suitable process helps to remove undesirable contaminants which may have been introduced into passive orbackside surface108 of thewafer100 during fabrication of thesemiconductor device102.
• As will be appreciated and understood by those of ordinary skill in the art, several types of processes are available to perform the thinning of thewafer100. For example, a mechanical grinding process, a mechanical planarization process, a chemical-mechanical planarization process (CMP) or a chemical planarization process could be used to remove material from passive orbackside surface108 of thewafer100. More specifically, a grinding wheel may be applied to passive orbackside surface108 of thewafer100 to abrade material therefrom. Alternatively, passive orbackside surface108 of thewafer100 could be chemically etched to remove material.
• Referring now toFIG. 4, after material has been removed from the passive or backside surface108 (FIG. 2A) of thewafer100 to a desired thickness, a coating is applied to the newly formed passive orbackside surface108′ to form abackside passivation layer130. In one embodiment, it may be desirable to form thebackside passivation layer130 as a layer of polymer or epoxy applied to passive orbackside surface108′ using conventional processes, such as spin coating. However, thebackside passivation layer130 could also comprise a suitable layer of glass applied by spin, dip or flow coating, or it could comprise a layer of silicon nitride or silicon oxide deposited by sputtering or CVD. Formation of thebackside passivation layer130 may be accomplished whilewafer100 remains attached to the retaining apparatus (not shown) which is used in conjunction with the removal of material from the passive orbackside surface108. Of course, the process of foaming thebackside passivation layer130 may be carried out at a location separate from that of the material removal operation if so desired.
• Referring now toFIG. 5, a side view of thewafer100 attached to awafer frame132 is shown. Thewafer100 may be held in place on thewafer frame132 by adhesively attaching backside passivation layer130 (FIG. 4) to aframe membrane134 such thatactive surface106 faces outward or upward.Frame membrane134 may include, for example, an elastic film or tape formed of a material, such as a polyethylene, a flexible resin or a sheet of similarly resilient material, and be coated with an adhesive. The adhesive may, for instance, include a pressure-sensitive or UV-releasable adhesive that adheres tobackside passivation layer130 without forming a permanent bond. Once attached towafer frame132, thewafer100 may be diced by cutting intoactive surface106 along street lines104 (shown as dashed lines inFIG. 5) running betweenadjacent semiconductor devices102. A conventional wafer saw may be used for this operation as will be appreciated by those of ordinary skill in the art.
• In dicing thewafer100, a wafer saw (not shown) may cut completely through thewafer100 without cutting theframe membrane134. However, the wafer saw need not cut entirely through thewafer100 in all cases. For example, as discussed above, while theactive surface106 andvarious passivation layers118,124 and UBM120 (FIG. 2A) may be formed of materials conducive to wafer sawing, the backside passivation layer130 (FIG. 4) may be formed of a polymer material which tends to gum-up and reduce the efficiency and accuracy of the wafer saw. Thus, if thebackside passivation layer130 is formed as a polymer layer, the cutting depth of the wafer saw may be reduced such thatbackside passivation layer130 is not cut, such as is shown inFIG. 6. A force may subsequently be applied to thewafer100 such as with rollers or other known mechanisms (not shown) so as to sever, fracture, crack or break thebackside passivation layer130 along the cuts corresponding with thestreet lines104 and separate theindividual semiconductor devices102, formingindividual sidewalls138 thereon as shown inFIG. 7. In this manner, the wafer saw does not have to cut any polymer material and may remain free from gumming.
• Referring now toFIGS. 8A and 8B, after dicing of thewafer100 to separate theindividual semiconductor devices102, themembrane134 may be stretched by thewafer frame132 to displace theindividual semiconductor devices102 from one another and further expose theirsidewalls138 for subsequent coating. Themembrane134 may be stretched by laterally displacingframe members132A-132D relative to each other such as is indicated bydirectional arrows139.
• As shown inFIG. 9, while still attached to theframe membrane134, a further protective coating may be applied to theindividual semiconductor devices102 and thereby form an activesurface passivation layer140 and side edge passivation layers142. In one embodiment of the present invention, thesemiconductor devices102 disposed on the stretchedframe membrane134 may be placed in a deposition chamber (not shown) and the active surface and side edge passivation layers140,142 may be formed by depositing a layer of polymer or other material onsemiconductor devices102 using CVD or atomic layer deposition (ALD) processes. As is well known in the art, in CVD processes, reactive species in a gaseous atmosphere of elevated temperature chemically react to deposit a film of material such as, for example, a polymer, onto the surfaces of theindividual semiconductor devices102. While very effective, the CVD process must be performed at relatively high temperatures and can introduce impurities from the gas atmosphere into the film of deposited material.
• An ALD process, which is a variant of the CVD process, is a relatively new process which allows the formation of high-quality, uniform films and can generally be carried out at lower temperatures than CVD processes. In general terms, an ALD process involves depositing multiple atomic layers on a surface to form a film. Each layer is formed by chemisorption from a precursor gas. A series of reactive precursors is injected into a deposition chamber with an inert gas purge between the introduction of each reactive precursor. A more detailed discussion of ALD processes is presented in U.S. Pat. No. 6,387,185 to Doering et al., the disclosure of which is incorporated herein in its entirety by reference. The deposition rate of ALD is slower than that of CVD, and the selected deposition technique will be selected accordingly based on process considerations as to which benefits are more desirable. It should be understood that CVD and ALD processes are exemplary deposition methods and that other known methods such as, for example, sputtering, may be used as well.
• Furthermore, in another embodiment of the present invention, active surface and side edge passivation layers140,142 may be formed by spraying a layer of epoxy onto theindividual semiconductor devices102 in an aerosolized form by a dispensing nozzle as will be appreciated by those of ordinary skill in the art.
• Referring now toFIG. 10, once active surface and side edge passivation layers140,142 are formed, a portion of activesurface passivation layer140 is removed from theindividual semiconductor devices102 to expose a portion of theconductive bumps116 formed thereon. This operation may also be completed while theindividual semiconductor devices102 remain attached toframe membrane134. The removal of the portion of activesurface passivation layer140 may be achieved through etching, for example, by a dry plasma etch process or by a wet etching process, such as by dipping the activesurface passivation layer140 into a wet etch solution. Alternatively, the removal may be achieved through a mechanical abrasion process, optionally assisted by a chemical agent, such as by the CMP process described above in relation to the back-grinding operation. The result is a plurality of wafer-level or chip-scale semiconductor packages150 havingpassivation layers130,140 and142 which hermetically seal its associatedsemiconductor device102 from environmental conditions. It is noted that the side edge passivation layers142 overlap the edge of thebackside passivation layer130 to form such a seal.
• At this point, the plurality ofindividual semiconductor packages150 may be removed from theframe membrane134 for subsequent attachment to circuitry on a carrier substrate or other device such as by TAB or flip-chip bonding. For example, as illustrated inFIG. 11, amemory device152 may be formed by electrically coupling theconductive bumps116 of anindividual semiconductor package150 with acarrier substrate154 by flip-chip bonding to thecontact pads156 formed on the surface of thecarrier substrate154. Such a memory device may be utilized in a computing system, including, for example, a central processing unit operably coupled with thememory device152, and also coupled with one or more appropriate input devices (e.g., mouse, keyboard, hard drive, etc.) and one or more output devices (e.g., monitor, printer, etc.).
• The above-illustrated embodiments of the present invention, and variations thereof, provide wafer-level or chip-scale packaging for semiconductor dice, including sealing of the dice from environmental elements, using a fewer number of fabrication steps and processing time therefor. Although the present invention has been depicted and described with respect to the illustrated embodiments, various additions, deletions and modifications are contemplated within its scope. The scope of the invention is, therefore, indicated by the appended claims rather than the foregoing description. Further, all changes which may fall within the meaning and range of equivalency of the claims and elements and features thereof are to be embraced within their scope.

Claims (20)

1. A semiconductor package, comprising:

a semiconductor device including an active surface, a back surface, and a side edge extending from the active surface to the back surface;

at least one bond pad on the active surface of the semiconductor device;

a first passivation material over the active surface of the semiconductor device, the at least one bond pad being exposed through the first passivation material;

a conductive bump secured on the at least one bond pad; and

a second passivation material over the first passivation material, the side edge of the semiconductor device, and at least substantially surrounding the conductive bump.

2. The semiconductor package ofclaim 1, wherein a portion of the conductive bump is exposed through the second passivation material.

3. The semiconductor package ofclaim 2, wherein the portion of the conductive bump exposed through the second passivation material is substantially flush with the second passivation material.

4. The semiconductor package ofclaim 1, wherein the first passivation material and the second passivation material comprise a silicon oxide material or a silicon nitride material.

5. The semiconductor package ofclaim 1, further comprising a third passivation material formed on the back surface of the semiconductor device.

6. The semiconductor package ofclaim 5, wherein the semiconductor device is substantially hermetically sealed by the first passivation material, the second passivation material, and the third passivation material.

7. The semiconductor package ofclaim 5, wherein the third passivation material comprises a polymer material, an epoxy material, a glass material, a silicon nitride material, or a silicon oxide material.

8. A packaged semiconductor device, comprising:

a semiconductor device having an active surface, a back side, and side edges extending from the active surface to the back side;

a plurality of bond pads on the active surface;

a first passivation material on the active surface exposing the plurality of bond pads;

a plurality of conductive bumps, one conductive bump of the plurality of conductive bumps over each bond pad of the plurality of bond pads;

a second passivation material over the first passivation material, the plurality of conductive bumps, and the side edges of the semiconductor device.

9. The packaged semiconductor device ofclaim 8, wherein a portion of at least one conductive bump of the plurality of conductive bumps is exposed through the second passivation material.

10. The packaged semiconductor device ofclaim 8, further comprising a third passivation material on the back side of the semiconductor device.

11. The packaged semiconductor device ofclaim 10, wherein the second passivation material on the side edges of the semiconductor device overlaps an edge of the third passivation material on the back side of the semiconductor device.

12. The packaged semiconductor device ofclaim 10, wherein a portion of the second passivation material on the side edges of the semiconductor device is adjacent to the third passivation material.

13. The semiconductor package ofclaim 8, further comprising a layer of under-bump metallization between each conductive bump of the plurality of conductive bumps and a corresponding bond pad of the plurality of bond pads on the semiconductor device.

14. A memory device, comprising:

a semiconductor device;

a first passivation material on a back side of the semiconductor device;

a second passivation material on an active surface of the semiconductor device;

a third passivation material on side edges of the semiconductor device extending from the first passivation material to the second passivation material; and

a carrier substrate electrically coupled to the semiconductor device.

15. The memory device ofclaim 14, further comprising an additional passivation material disposed between the active surface of the semiconductor device and the second passivation material.

16. The memory device ofclaim 14, further comprising a plurality of conductive bumps on the active surface of the semiconductor device.

17. The memory device ofclaim 16, wherein a portion of each of the conductive bumps of the plurality of conductive bumps is exposed through the second passivation material.

18. The memory device ofclaim 17, wherein the carrier substrate electrically coupled to the semiconductor device comprises a flip-chip arrangement wherein the plurality of conductive bumps are electrically coupled to the carrier substrate.

19. The memory device ofclaim 18, wherein the carrier substrate comprises a plurality of contact pads.

20. The memory device ofclaim 14, wherein the second passivation material and the third passivation material are congruent.

Images