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US20100082892A1 - Flash Memory Controller For Electronic Data Flash Card - Google Patents

Flash Memory Controller For Electronic Data Flash CardDownload PDF

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Publication number
US20100082892A1
US20100082892A1US12/631,748US63174809AUS2010082892A1US 20100082892 A1US20100082892 A1US 20100082892A1US 63174809 AUS63174809 AUS 63174809AUS 2010082892 A1US2010082892 A1US 2010082892A1
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United States
Prior art keywords
flash memory
memory device
data
memory controller
interface circuit
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Abandoned
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US12/631,748
Inventor
Abraham C. Ma
Charles C. Lee
I-Kang Yu
Edward W. Lee
Ming-Shiang Shen
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Super Talent Electronics Inc
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Super Talent Electronics Inc
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Publication date
Priority claimed from US09/478,720external-prioritypatent/US7257714B1/en
Priority claimed from US10/761,853external-prioritypatent/US20050160218A1/en
Priority claimed from US10/789,333external-prioritypatent/US7318117B2/en
Priority claimed from US11/458,987external-prioritypatent/US7690030B1/en
Application filed by Super Talent Electronics IncfiledCriticalSuper Talent Electronics Inc
Priority to US12/631,748priorityCriticalpatent/US20100082892A1/en
Publication of US20100082892A1publicationCriticalpatent/US20100082892A1/en
Abandonedlegal-statusCriticalCurrent

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Abstract

An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input— output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

Description

Claims (12)

1. A storage system comprising:
a host computer including an interface bus; and
an electronic data flash card adapted to communicate with the host computer through a communication link established by the host computer over the interface bus, the electronic data flash card comprising:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol; and
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,
wherein the flash memory controller comprises:
(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) means for operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device;
(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and
(e) one or more look-up-tables (LUTs)
implemented by at least one synchronous random-access memory (SRAM) for translation of a logical address received from the host computer into a corresponding flash physical address for use during operation in one of the data writing mode and the retrieving mode.
2. An electronic flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic flash card comprising:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol; and
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, wherein the flash memory controller comprises:
(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) means for operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device;
(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and
(e) one or more look-up-tables (LUTs)
implemented by at least one synchronous random-access memory (SRAM) for translation of a logical address received from the host computer into a corresponding flash physical address for use during operation in one of the data writing mode and the retrieving mode.
3. A electronic flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic flash card comprising:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USE) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol; and
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, wherein the flash memory controller comprises:
(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) means for operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device; and
(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller,
wherein the card body comprises a substrate on which the non-volatile memory device, the card reader interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology.
4. A flash memory controller for an electronic flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic flash card including:
a card body,
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device, and
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol,
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, and wherein the flash memory controller comprises:
(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) means for operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device; and
(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller.
5. A method for managing a flash memory device in an electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic flash card including:
a card body,
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device,
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol, and
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,
wherein the method comprises:
(a) determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) storing a plurality of logical addresses and a plurality of physical addresses in an index such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device; and
(d) storing boot code (BC) in a read-only memory (ROM) such that the BC provides initial executing sequences for the processor unit to initialize the flash memory controller.
6. A computer readable medium for managing a flash memory device in an electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the electronic flash card including:
a card body,
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device,
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol, and
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,
wherein the computer readable medium contain program instructions which, when executed by the flash memory controller, cause the electronic data flash card to execute a method comprising:
(a) determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) storing a plurality of logical addresses and a plurality of physical addresses in an index such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device; and
(d) storing boot code (BC) in a read-only memory (ROM) such that the BC provides initial executing sequences for the processor unit to initialize the flash memory controller.
7. A storage system comprising:
a host computer including an interface bus; and
a single chip electronic data flash card adapted to communicate with the host computer through a communication link established by the host computer over the interface bus, the single chip electronic data flash card comprising:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol; and
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, wherein the flash memory controller comprises:
(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) means for operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device;
(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and
(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations,
wherein the flash memory controller further comprises means for assigning each the physical address to its associated the logical address, and
wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package.
8. An single chip electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the single chip electronic data flash card comprising:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol; and
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, wherein the flash memory controller comprises:
(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) means for operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device;
(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller; and
(e) a SRAM for storing look-up-tables (LUT) for translation of a logical address from the host computer and a flash physical address for the data writing mode and the retrieving mode operations, wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package.
9. A single chip electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the single chip electronic data flash card comprising:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol; and
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit, wherein the flash memory controller comprises:
(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) means for operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device;
(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller,
wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package.
10. A flash memory controller for an single chip electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the single chip electronic data flash card including:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device;
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol;
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,
wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package, and
wherein the flash memory controller comprises:
(a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) an index for storing a plurality of logical addresses and a plurality of physical addresses such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) means for operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device; and
(d) a read-only memory (ROM) for storing boot code (BC) that provides initial executing sequences for the processor unit to initialize the flash memory controller.
11. A method for managing a flash memory device in an single chip electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the single chip electronic data flash card including:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device; and
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol;
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,
wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package, and
wherein the method comprises:
(a) determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) storing a plurality of logical addresses and a plurality of physical addresses in an index such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device; and
(d) storing boot code (BC) in a read-only memory (ROM) that provides initial executing sequences for the processor unit to initialize the flash memory controller.
12. A computer readable medium for managing a flash memory device in an single chip single chip electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, the single chip electronic data flash card including:
a card body;
a flash memory device mounted on the card body, the flash memory device including a plurality of non-volatile memory cells for storing a data file, the memory cells being arranged in at least one of a plurality of memory blocks, and a plurality of pages, and a plurality of sectors, wherein the flash memory device comprises one of a Multi-Level Cell flash memory device and a Single Level Cell flash memory device; and
an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol;
a flash memory controller mounted on the card body and electrically connected to the flash memory device and the input/output interface circuit,
wherein the card body comprises a substrate on which the non-volatile memory device, the input/output interface circuit, and the flash memory controller are mounted using integrated circuits packaging technology such that the non-volatile memory device, the card reader interface circuit and the flash memory controller are integrated into one integrated circuit package, and
wherein the computer readable medium contain program instructions which, when executed by the flash memory controller, cause the single chip electronic data flash card to execute a method comprising:
(a) determining whether the flash memory device is supported by a processing unit of the flash memory controller;
(b) storing a plurality of logical addresses and a plurality of physical addresses in an index such that each physical address is assigned to an associated logical address, where each physical address corresponds to an associated plurality of memory cells of the flash memory device, and wherein the index comprises at least one look-up-table (LUT) for storing the logical addresses and the associated physical addresses, each LUT including static random access memory(SRAM) cells;
(c) operating in one of:
a data writing mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a standard USB BOT write command issued from the host computer to the flash memory controller;
a data retrieving mode in which the flash memory controller receives a standard USB BOT read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer; and
a data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the standard USB BOT write command using arbitration logic and data that is stored on the flash memory device; and
(d) storing boot code (BC) in a read-only memory (ROM) that provides initial executing sequences for the processor unit to initialize the flash memory controller.
US12/631,7482000-01-062009-12-04Flash Memory Controller For Electronic Data Flash CardAbandonedUS20100082892A1 (en)

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US09/478,720US7257714B1 (en)1999-10-192000-01-06Electronic data storage medium with fingerprint verification capability
US10/761,853US20050160218A1 (en)2004-01-202004-01-20Highly integrated mass storage device with an intelligent flash controller
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US11/458,987US7690030B1 (en)2000-01-062006-07-20Electronic data flash card with fingerprint verification capability
US11/466,759US7702831B2 (en)2000-01-062006-08-23Flash memory controller for electronic data flash card
US12/631,748US20100082892A1 (en)2000-01-062009-12-04Flash Memory Controller For Electronic Data Flash Card

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US20100030961A9 (en)2010-02-04
US20080005471A1 (en)2008-01-03
US7702831B2 (en)2010-04-20
US20100082893A1 (en)2010-04-01

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