US20100038702A1 - Nonvolatile memory device and methods of forming the same - Google Patents

Abstract

Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.

Description

PRIORITY STATEMENT
• This non-provisional application is a divisional application of U.S. application Ser. No. 11/589,178, filed Oct. 30, 2006, which claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 2005-102470, filed on Oct. 28, 2005, in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference.
BACKGROUND
• 1. Field
• Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same.
• 2. Description of the Related Art
• Semiconductor memory devices may be classified as volatile memory devices or nonvolatile memory devices. The volatile memory devices (e.g., a dynamic random access memory (DRAM) and/or a static random access memory (SRAM)) may input and output data at a relatively high speed, but lose the stored data when power is interrupted. The nonvolatile memory devices may retain the stored data even though the power is interrupted.
• A flash memory device is a nonvolatile memory device and may be a highly integrated device having both an erasable programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM). The flash memory devices may be classified into a floating gate type flash memory device and a floating trap type flash memory device according to the type of data storage layer in a unit cell.
• The floating trap type flash memory device may store electrical charges in a trap formed in a nonconductive charge trap layer, whereas the floating gate type flash memory device may store electrical charges in a polysilicon layer. A memory cell of the floating trap type memory device may include a gate structure of a tunnel oxide layer, a silicon nitride layer serving as a charge trap layer, a blocking oxide layer and/or a conductive layer on a silicon substrate.
• FIG. 1 is a diagram illustrating a conventionalnonvolatile memory device10 of a silicon oxide nitride oxide semiconductor (SONOS) structure. Referring toFIG. 1, a memory cell of thememory device10 may include anONO layer15, including anoxide layer12, anitride layer13 and anoxide layer14, andpolysilicon16, which may be formed in achannel region18 defined between source/drain regions17 formed on asubstrate11. The memory cell may have a single bit structure indicating logic state “0” or “1” according to existence or nonexistence of electrical charges trapped in thenitride layer13 of theONO layer15. There may be a demand for a memory device that has an increased data storage capacity so that more than two logic states may be indicated, without increasing the size of the memory device. As nano technology has been developed, nonvolatile memory devices, using nano crystals, have been studied.
• FIGS. 2 and 3 are diagrams illustrating a conventional nonvolatile memory device using nano crystal. Referring toFIG. 2, achannel region28 may be disposed between source/drain regions27 formed on asubstrate21. A memory cell may include amemory layer25 and agate electrode26 formed on thechannel region28. Thememory layer25 may include atunnel oxide layer22, acharge trap layer23 and a blockingoxide layer24. Thecharge trap layer23 may include nano crystals23NC of cluster and/or dot shape of several to several tens nm. Electrical charges injected into the nano crystals23NC may not move easily between the nano crystals23NC. Compared with the general memory device of the SONOS structure, the memory device using nano crystals may restrain the lateral diffusion of electrical charges and may be suitable to achieve the memory device of a multi bit structure.
• In implementing the nonvolatile memory device using nano crystals as a multi-bit (e.g., about 2 bits per cell) nonvolatile memory device, there may be a limitation in scaling down the size of the memory device. Electrical charges may be locally injected into a charge trap layer close to the source/drain regions27 in order to use the memory device with nano crystals as the multi-bit memory device. With a short-channel memory device, overlapping may occur when injecting electrical charges and the injected electrical charges may be laterally diffused, causing disturbance. The memory device may not achieve the 1 cell-2 bits operation. A channel length of the memory device may be maintained at more than a given length, but this may be contrary to a relatively high integration of the memory device. Therefore, the memory layer may be divided into two layers.
• Referring toFIG. 3, source/drain regions37 may be formed in asubstrate31. Twomemory layers35L and35R, separated horizontally, may be disposed on achannel region38 defined between the source/drain regions37, with aninsulating layer35C being interposed therebetween. Thememory layers35L and35R may each includetunnel oxide layers32L and32R,charge trap layers33L and33R, and blockingoxide layers34L and34R. Agate electrode36 may be located on thememory devices35L and35R and the insulatinglayer35C. The structure may scale down the memory device to a degree. Depending on the number of the nano crystal33NC included in thecharge trap layers33L and33R during scaling down, a threshold voltage shift may become large and degrade the reliability of the device.
• FIG. 4A is a diagram illustrating a charge storage layer in the conventional nonvolatile memory device ofFIG. 3, andFIG. 4B is a diagram illustrating a dispersion of a threshold voltage shift according to a width W of the charge storage layer in the conventional nonvolatile memory device ofFIG. 4A.
• Referring toFIGS. 4A and 4B, as the width W of the channel decreases during scale down, the threshold voltage may increase due to the bottleneck effect. When the width of the channel decreases, electrical charges passing through the channel may be trapped by the nano crystals33NC, so that the threshold voltage may increase. The threshold voltage in each of the memory cells may increases to a different degree depending on the number of nano crystals33NC included in the charge trap layer. This may be a problem when the width W of the channel decreases.
• For example, when the width W of the channel is about 70 nm, the dispersion of the threshold voltage may be relatively small, but the dispersion of the threshold voltage in each of the memory cells may also be relatively small. When the width W of the channel is about 10 nm, the threshold voltage may increase, but the dispersion of the threshold voltage in each of the memory cells may be relatively large. Accordingly, errors may occur when the memory cell operates and there may be less reliability of the memory device. There may be a limitation in the relatively high integration of the memory device having divided memory layers, and thus, a more highly integrated memory device may be required.
SUMMARY
• Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. Example embodiments provide larger scale integrated (VLSI) nonvolatile memory devices having improved reliability and a method of fabricating the same. A method of forming nonvolatile memory devices according to example embodiments may include forming a memory cell of a multi bit structure.
• Example embodiments provide a method of forming nonvolatile memory devices including forming a device isolation layer in a substrate to define an active region in which a memory layer including a tunnel insulating layer, a charge storage layer, and a blocking insulating layer may be formed. A portion of the memory layer may be removed and a middle gate may be formed having an upper surface higher than an upper surface of the memory layer and a gate insulating layer adjacent to both sides and a bottom of the middle gate in the removed space. Side gates may be formed adjacent to the gate insulating layer on both sides of the middle gate and the memory layer may be patterned using the side gates as an etching mask to form first and second memory cells each including the patterned memory layer and the side gates. An ion implantation process may be performed to form a first impurity region on the substrate outside the first memory cell and to form a second impurity region on the substrate outside the second memory cell.
• In example embodiments, forming the middle gate and the gate insulating layer may include forming a hard mask pattern exposing a portion of the memory layer on the substrate including the device isolation layer. A portion of the memory layer may be etched using the hard mask pattern as an etching mask to expose the substrate. An insulating layer and a first conductive layer may be formed on the overall substrate and a planarization process may be performed for exposing the hard mask pattern, wherein forming the side gates may include forming the middle gate and the gate insulating layer and removing the hard mask pattern and forming a second conductive layer adjacent to the gate insulating layer on both sides of the middle gate.
• In example embodiments, forming the middle gate and the gate insulating layer may include forming a hard mask pattern exposing a portion of the memory layer on the substrate including the device isolation layer. Spacers may be formed on sides of the hard mask pattern and the memory layer may be etched using the hard mask pattern and the spacers as an etching mask to expose the substrate. An insulating layer and a first conductive layer may be formed on the overall substrate and a planarization process may be performed for exposing the hard mask pattern and the spacers, wherein the forming of the side gates may include forming the middle gate and the gate insulating layer, removing the spacers, forming a second conductive layer and performing a planarization process for exposing the hard mask pattern.
• Example embodiments provide a method of forming nonvolatile memory devices including forming a device isolation layer in a substrate to define an active region in which a memory layer including a tunnel insulating layer, a charge storage layer, and a blocking insulating layer may be formed. A hard mask pattern may be formed exposing a portion of the memory layer on the substrate and spacers may be formed on sides of the hard mask pattern. A portion of the memory layer may be etched using the hard mask pattern and the spacers as an etching mask to expose the substrate. An insulating layer and a conductive layer may be formed on the overall substrate and a planarization process may be performed for exposing the hard mask pattern and the spacers to form a middle gate and a gate insulating layer on the exposed substrate. The hard mask pattern may be removed and the memory layer may be patterned using the spacers as an etching mask. An ion implantation process may be performed to form impurity regions in the substrate outside the patterned memory layer.
• In example embodiments, the spacers may be formed of a conductive layer, and the spacers may serve as side gates. The memory layer may be patterned using the spacers as an etching mask, and then the spacers may be removed to form side gates in the removed space. The spacers may be formed of material having etch selectivity with respect to the hard mask pattern and the gate insulating layer. In example embodiments, the device isolation layer may be formed through the following methods.
• The first method may include forming the tunnel insulating layer, the charge storage layer, and the blocking insulating layer on the substrate and forming a linear sacrifice layer pattern on the blocking insulating layer. Spacers may be formed in sides of the sacrifice layer pattern and the sacrifice layer pattern may be removed. A trench may be formed using the spacers as an etching mask, the trench may be filled with oxide and a planarization process may be performed for exposing an upper surface of the blocking insulating layer. In this method, the sacrifice pattern and the spacer may be formed of material having etch selectivity with respect to each other.
• The second method may include forming the tunnel insulating layer, the charge storage layer, and the blocking insulating layer on the substrate and forming a linear hard mask pattern on the blocking insulating layer. A trench may be formed using the hard mask pattern as an etching mask and the trench may be filled with oxide. The oxide may be planarized up to an upper surface of the blocking insulating layer to form a first device isolation layer and a portion of both sides of the hard mask pattern may be removed to reduce its width and to expose a portion of the blocking insulating layer. A mask layer may be formed on the exposed blocking insulating layer and the first device isolation layer and the reduced hard mask pattern may be removed. A trench may be formed using the mask layer as an etching mask and the trench may be filled with oxide. The oxide may be planarized up to the upper surface of the blocking insulating layer to form a second device isolation layer. In this method, the hard mask pattern and the mask layer may be formed of a material having etch selectivity with respect to each other.
• According to example embodiments, larger scale integrated nonvolatile memory devices may be formed through a spacer forming process and/or a pull-back process. Nonvolatile memory devices, according to example embodiments, may include a nano-sized charge storage layer. Nano-sized means a size smaller than that of a pattern that may be formed by a photolithography process.
• Example embodiments provide nonvolatile memory devices including first and second impurity regions separately formed on a substrate to define a channel region therebetween, a middle gate formed on the channel region, a gate insulating layer adjacent to both sides and a bottom of the middle gate and first and second memory cells disposed on both sides of the middle gate, wherein the first and second memory cells each include a memory layer including a tunnel insulating layer, a nano-sized charge storage layer and a blocking insulating layer formed on the channel region and a side gate formed on the memory layer.
• In example embodiments, the charge storage layer may be formed of a single material, for example, amorphous silicon. Electrical charges may be more stably injected into the charge storage layer, thereby improving the reliability of the memory device.
• In example embodiments, the nonvolatile memory devices may further include a gate connection layer formed on the middle gate and the side gates to electrically connect the middle gate with the side gates. The nonvolatile memory devices may further include a first spacer layer covering outer sides of the first and second memory cells. The nonvolatile memory devices may further include a second spacer layer covering the first spacer layer, and each of the first and second impurity regions may include a low concentration impurity region formed under the second spacer layer.
BRIEF DESCRIPTION OF THE DRAWINGS
• Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.FIGS. 5-26C represent non-limiting, example embodiments as described herein.
• FIG. 1 is a diagram illustrating a conventional nonvolatile memory device with a SONOS structure andFIGS. 2 and 3 are diagrams illustrating a conventional nonvolatile memory device using nano crystals;
• FIG. 4A is a diagram illustrating a charge storage layer in the conventional nonvolatile memory device ofFIG. 3, andFIG. 4B is a diagram illustrating a dispersion of a threshold voltage shift according to a width of the charge storage layer in the conventional nonvolatile memory device ofFIG. 4A;
• FIG. 5 is a diagram illustrating a nonvolatile memory device according to example embodiments;
• FIGS. 6A to 13A are diagrams illustrating a portion of a substrate to show a method of forming a nonvolatile memory device according to example embodiments.FIGS. 6B and 13B are diagrams illustrating line A-A′ ofFIGS. 6A to 13A according to example embodiments andFIGS. 6C to 13C are diagrams illustrating line B-B′ ofFIGS. 6A to 13A according to example embodiments;
• FIGS. 14A and 21A are diagrams illustrating a portion of a substrate to show a method of forming a nonvolatile memory device according to example embodiments,FIGS. 14B to 21B are diagrams illustrating line A-A′ ofFIGS. 14A to 21A according to example embodiments andFIGS. 14C to 21C are diagrams illustrating line B-B′ ofFIGS. 14A to 21A according to example embodiments;
• FIGS. 22A and 23A are diagrams illustrating a portion of a substrate to show a method of forming a nonvolatile memory device according to example embodiments,FIGS. 22B and 23B are diagrams illustrating line A-A′ ofFIGS. 22A and 23A according to example embodiments andFIGS. 22C and 23C are diagrams illustrating line B-B′ ofFIGS. 22A and 23A according to example embodiments;
• FIGS. 24A to 26A are diagrams illustrating a portion of a substrate to show a method of forming a nonvolatile memory device according to example embodiments,FIGS. 24B to 26B are diagrams illustrating line A-A′ ofFIGS. 24A and 26A according to example embodiments andFIGS. 24C to 26C are diagrams illustrating line B-B′ ofFIGS. 24A and 26A according to example embodiments.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
• Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings. Example embodiments are not limited to example embodiments illustrated herein after, but rather example embodiments herein are introduced to provide easy and complete understanding of the scope and spirit of the claims.
• Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
• In example embodiments, the terms “first,” “second,” “third,” and the like in this specification, if any, are used for describing a memory cell, an impurity region, a side gate, or a spacer layer, etc., but such elements should not be construed as being limited by the terms so used. These terms are merely used for distinguishing desired memory cell, impurity region, side gate, or spacer layer, etc. from other memory cell, impurity region, side gate, or spacer layer, etc.
• In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it may be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
• Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same.
Structure of Nonvolatile Memory Device
• FIG. 5 is a diagram illustrating a nonvolatile memory device according to example embodiments. Referring toFIG. 5, achannel region108 may be defined betweenimpurity regions107L and107R formed on asubstrate100. Theimpurity regions107L and107R may include low-concentration impurity regions105L and105R and high-concentration impurity regions106L and106R.Memory cells120L and120R may be separately disposed on thechannel region108.
• Thememory cells120L and120R may each includememory layers114L and114R andside gates118L and118R thereon. The memory layers114L and114R may each includetunnel insulating layers111L and111R, charge storage layers112L and112R, and blocking insulatinglayers113L and113R. The charge storage layers112L and112R may be formed of a nano-sized material (e.g., amorphous silicon). Amiddle gate127 may be disposed on thechannel region108 between thememory cells120L and120R, and agate insulating layer121 may surround both sides and bottom of themiddle gate127. First and second spacer layers131 and133 may be disposed to cover outer sides of thememory cells120L and120R. Agate connection layer141 may be disposed on themiddle gate127 and theside gates118L and118R. Thegate connection layer141 may be formed of a conductive layer and may electrically connect themiddle gate127 to theside gates118L and118R. When a control voltage is applied to operate thememory cells120L and120R, the same voltage may be applied to themiddle gate127 and theside gates118L and118R.
• In a nonvolatile memory device according to example embodiments, the gate connection layer may not be formed on the middle gate and the side gates. In this case, the middle gate may be electrically isolated from the side gates by the gate insulating layer. Accordingly, different control voltages may be applied to the middle gate and the side gates, and the memory cells may independently perform a program operation, an erase operation, and a read operation. However, the same control voltages may be applied to each gate.
• The nonvolatile memory device, according to example embodiments, may have a multi bit structure where two memory cells are disposed in a channel region. Because the charge storage layer is nano-sized, the larger scale integration of the memory device may be achieved. When the charge storage layer is formed of single material, electrical charges may be stably injected into the charge storage layer, increasing the reliability of the memory device. When the number of electrons stored in the charge storage layer is controlled to form a multi-potential state of the charge storage layer, the memory cell may be implemented as a multi level cell (MLC).
Method of Forming Nonvolatile Memory Device
• Hereinafter, a method of forming a nonvolatile memory device according to example embodiments will be described in detail.FIGS. 6A to 13A are diagrams illustrating a portion of a substrate to illustrate a method of forming a nonvolatile memory device according to example embodiments.FIGS. 6B and 13B are diagrams illustrating line A-A′ ofFIGS. 6A to 13A, andFIGS. 6C to 13C are diagrams illustrating line B-B′ ofFIGS. 6A to 13A.
• Referring toFIGS. 6A,6B and6C, amemory layer114 may be formed on asubstrate100. Thememory layer114 may include atunnel insulating layer111, acharge storage layer112, and a blocking insulatinglayer113. Thetunnel insulating layer111 may be formed of silicon oxide using a thermal oxidation process or a well-known thin film deposition process. Thecharge storage layer112 may be formed of amorphous silicon using a well-known thin film deposition process. The blocking insulatinglayer113 may be formed of silicon oxide using a well-known thin film deposition process. In order to effectively retard or prevent electrons injected into thecharge storage layer112 from leaking out, the blocking insulatinglayer113 may be formed of an insulating material having a higher dielectric constant (e.g., Al₂O₃, HfO, HfAlO, HfSiO and/or any other suitable material) than silicon oxide. A linearsacrifice layer pattern116 may be formed on thememory layer114.Spacers116smay be formed on sides of thesacrifice layer pattern116. Thespacers116smay be formed of a material having an etch selectivity with respect to thesacrifice layer pattern116. For example, when thesacrifice layer pattern116 is formed of silicon oxide, thespacers116smay be formed of silicon nitride and/or polysilicon. Thespacers116smay be formed to a width less than about 30 nm using a well-known spacer forming process.
• Referring toFIGS. 7A,7B, and7C, thesacrifice layer pattern116 may be removed using a method (e.g., a wet etching process), and then thememory layer114 and thesubstrate100 may be etched using thespacers116sas an etching mask to form memory layers114aand a trench101t. Thespacers116s, used as an etching mask, may also be etched. The trench101tmay be filled withsilicon oxide101susing a well-known thin film deposition process. Referring toFIGS. 8A,8B and8C, a planarization process may be performed to remove thespacers116sand an upper portion of thesilicon oxide101sand to expose upper surfaces of the memory layers114a. The remaining silicon oxides may serve as device isolation layers101. Accordingly, an active region may be defined between the device isolation layers101 and the memory layers114amay be located on the active region.Hard mask patterns119 may be formed on thesubstrate100, and then the memory layers114amay be etched using thehard mask patterns119 as an etching mask to expose thesubstrate100. Patterned memory layers114bmay remain between the device isolation layers101 under thehard mask patterns119. Referring toFIGS. 9A,9B, and9C, an insulating layer and a conductive layer may be formed on thesubstrate100 through a well-known thin film deposition process. A planarization process for exposing upper surfaces of thehard mask patterns119 may be performed to form amiddle gate127 and agate insulating layer121. Thegate insulating layer121 may be formed of a material having an etch selectivity with respect to thehard mask patterns119. For example, when thehard mask patterns119 are formed of silicon nitride, thegate insulating layer121 may be formed of silicon oxide. Themiddle gate127 may be formed of doped polysilicon.
• Referring toFIGS. 10A,10B, and10C, thehard mask patterns119 may be removed through a method (e.g., a wet etching process), and then sidegates118L and118R may be formed adjacent to thegate insulating layer121 on both sides of themiddle gate127. Theside gates118L and118R may be formed to have a width below about 30 nm through a well-known spacer forming process. The memory layers114bmay be etched using theside gates118L and118R as an etching mask to expose thesubstrate100. Patterned memory layers114L and114R may remain under theside gates118L and118R.Memory cells120L and120R, each including the memory layers114L and114R and theside gates118L and118R, may be formed in both sides of themiddle gate127. The memory layers114L and114R each includingtunnel insulating layers111L and111R, charge storage layers112L and112R, and blocking insulatinglayers113L and113R may be formed to have a width and a length below about 30 nm.
• Referring toFIGS. 11A,11B, and11C, first spacer layers131 may be formed to cover the outer sides of thememory cells120L and120R. The first spacer layers131 may be formed of silicon oxide through a well-known spacer forming process. An ion implantation process may be performed to form lowconcentration impurity regions105L and105R on the exposedsubstrate100 outside the first spacer layers131. The first spacer layers131 may retard or prevent the lowconcentration impurity regions105L and105R from enlarging into achannel region108 under the memory layers114L and114R.
• Referring toFIGS. 12A,12B, and12C, second spacer layers133 may be formed to cover the outer sides of the first spacer layers131. The second spacer layers133 may be formed of silicon nitride through a well-known spacer forming process. An ion implantation process may be performed to form highconcentration impurity regions106L and106R on the exposedsubstrate100 outside the second spacer layers133.Impurity regions107L and107R, including the lowconcentration impurity regions105L and105R and the highconcentration impurity regions106L and106R, may be formed.
• Referring toFIGS. 13A,13B, and13C, agate connection layer141 may be formed on themiddle gate127 and theside gates118L and118R. Thegate connection layer141 may be formed of a conductive layer (e.g., a suicide layer). When thegate connection layer141 is formed, a conductive layer (not shown) of the same material as thegate connection layer141 may be formed on theimpurity regions107L and107R. For example, when a metal layer is deposited and heated on theoverall substrate100, and a non-reactive metal layer is removed, asilicide layer141 may be formed on themiddle gate127, theside gates118L and118R, and theimpurity regions107L and107R. Thesilicide layer141 may be formed by a reaction between metal and silicon. Because thegate insulating layer121 does not react with metal, thesuicide layer141 may not be formed on thegate insulating layer121. Thesilicide layer141, formed on themiddle gate127 and theside gates131, may be connected with thegate insulating layer121. Themiddle gate127 may be electrically connected with theside gates118L and118R by thegate insulating layer141. The same control voltage may be applied to themiddle gates127 and theside gates118L and118R in operation of the memory cell.
• FIGS. 14A and 21A are diagrams illustrating a portion of a substrate to illustrate a method of forming a nonvolatile memory device according to example embodiments.FIGS. 14B to 21B are diagrams illustrating line A-A′ ofFIGS. 14A to 21A, andFIGS. 14C to 21C are diagrams illustrating line B-B′ ofFIGS. 14A to 21A.
• Referring toFIGS. 14A,14B, and14C, amemory layer114 may be formed on asubstrate100. Thememory layer114 may include atunnel insulating layer111, acharge storage layer112, and a blocking insulatinglayer113. A linearhard mask pattern115 may be formed on thememory layer114. Referring toFIGS. 15A,15B, and15C, thememory layer114 and thesubstrate100 may be etched using thehard mask pattern115 as an etching mask to formtrenches102t. Thetrenches102tmay be filled with silicon oxide, and then the silicon oxide may be planarized as high as an upper surface of a patternedmemory layer114p(an upper surface of a blocking insulatinglayer113p) to form first device isolation layers102. The patternedmemory layer114pmay remain between the first device isolation layers102 under thehard mask pattern115.
• ReferringFIGS. 16A,16B, and16C, a portion of thehard mask pattern115 may be etched to decrease its width and expose a portion of the upper surface of thememory layer114p. An etching process may be a wet etching process using a phosphoric acid solution as a pull-back process. A removed portion of thehard mask pattern115 may be adjusted through the pull-back process. A width of the removed portion (a width of the exposedmemory layer114p) may be adjusted to be below about 30 nm. In order to perform the pull-back process using the phosphoric acid solution, thehard mask pattern115 may be formed of silicon nitride.
• Mask layers117 may be formed on both sides of the reducedhard mask pattern115a. The mask layers117 may be formed of a material having an etch selectivity with respect to thehard mask pattern115a. For example, when thehard mask pattern115ais formed of nitride, the mask layers117 may be formed of oxide.
• Referring toFIGS. 17A,17b, and17C, thehard mask pattern115amay be removed, and then thememory layer114aand thesubstrate100 may be etched using the mask layers117 as an etching mask to form atrench103t. Thetrench103tmay be filled with oxide, and then a planarization process may be performed up to an upper surface of thememory layer114a(an upper surface of a blocking insulatinglayer113a) to form a seconddevice isolation layer103. The seconddevice isolation layer103 may not be formed at the same depth as the first device isolation layers102. An active region may be defined between the first and second device isolation layers102 and103, and thememory layer114amay be located only on the active region.
• Referring toFIGS. 18A,18B, and18C,hard mask patterns119 may be formed on thesubstrate100.Spacers119smay be formed on the sides of thehard mask patterns119. Thespacers119smay be formed of a material having an etch selectivity with respect to thehard mask patterns119. For example, when thehard mask patterns119 are formed of silicon oxide, thespacers119smay be formed of silicon nitride. Thespacers119smay be formed to have a width below about 30 nm through a well-known spacer forming process. The memory layers114amay be etched using thehard mask patterns119 and thespacers119sas an etching mask to expose thesubstrate100. Patterned memory layers114bmay remain between the first and second device isolation layers102 and103 and under thehard mask patterns119 and thespacers119s.
• Referring toFIGS. 19A,19B, and19C, an insulating layer and a conductive layer may be formed on thesubstrate100 through a well-known thin film deposition process. A planarization process for exposing upper surfaces of thehard mask patterns119 may be performed to form amiddle gate127 and agate insulating layer121 on the exposedsubstrate100. Thegate insulating layer121 may be formed of a material having an etch selectivity with respect to thespacers119s. For example, when thespacers119sare formed of silicon nitride, thegate insulating layer121 may be formed of silicon oxide. Themiddle gate127 may be formed of doped polysilicon. Referring toFIGS. 20A,20B, and20C, thespacers119smay be selectively removed, and then a conductive layer may be formed in the removed space and planarized to expose thehard mask patterns119 andform side gates118L and118R. Thespacers119smay be removed through a wet etching process using a phosphoric acid solution or a dry etching process using plasma. Theside gates118L and118R may be formed of doped polysilicon.
• ReferringFIGS. 21A,21b, and21C, the memory layers114bmay be etched using theside gates118L and118R as an etching mask to expose thesubstrate100. Patterned memory layers114L and114R may remain between the first and second device isolation layers102 and103 under theside gates118L and118R.Memory cells120L and120R, each including the memory layers114L and114R and theside gates118L and118R, may be formed on both sides of themiddle gate127. The memory layers114L and114R, including charge storage layers112L and112R, may be formed to have a width and a length below about 30 nm through a pull-back process and a spacer forming process.
• FIGS. 22A and 23A are diagrams illustrating a portion of a substrate to illustrate a method of forming a nonvolatile memory device according to example embodiments.FIGS. 22B and 23B are diagrams illustrating line A-A′ ofFIGS. 22A and 23A, andFIGS. 22C and 23C are diagrams illustrating line B-B′ ofFIGS. 22A and 23A. Referring toFIGS. 22A,2B, and22C,hard mask patterns119 may be removed, and then memory layers114bmay be etched usingspacer119sas an etching mask. Patterned memory layers114L and114R may remain between first and second device isolation layers102 and103 and under thespacers119s. Referring toFIGS. 23A,23B, and23C, thespacers119smay be removed, and then sidegates118L and118R may be formed on the memory layers114L and114R. Theside gates118L and118R may be formed of a conductive layer, for example, doped polysilicon.
• FIGS. 24A to 26A are diagrams illustrating a portion of a substrate to illustrate a method of forming a nonvolatile memory device according to example embodiments.FIGS. 24B to 26B are diagrams illustrating line A-A′ ofFIGS. 24A and 26A andFIGS. 24C to 26C are diagrams illustrating line B-B′ ofFIGS. 24A and 26A. Example embodiments provide a method of formingside gates118L and118R.
• Referring toFIGS. 24A,24B, and24C,hard mask patterns119 may be formed on asubstrate100. Theside gates118L and118R may be formed in sides of thehard mask patterns119. Theside gates118L and118R may be formed of a conductive layer, for example doped polysilicon. Theside gates118L and118R may be formed to have a width below about 30 nm through a well-known spacer forming process. Memory layers may be etched using thehard mask patterns119 and theside gates118L and118R as an etching mask to expose thesubstrate100. Patterned memory layers114bmay remain between device isolation layers101 under thehard mask patterns119 and theside gates118L and118R.
• Referring toFIGS. 25A,25B, and25C, an insulating layer and a conductive layer may be formed on thesubstrate100 through a well-known thin film deposition process. A planarization process for exposing upper surfaces of thehard mask patterns119 may be performed to form amiddle gate127 and agate insulating layer121 on the exposedsubstrate100. Thegate insulating layer121 may be formed of silicon oxide, and themiddle gates127 may be formed of doped polysilicon.
• Referring toFIGS. 26A,26b, and26C, thehard mask patterns119 may be removed, and then the memory layers114bmay be etched using theside gates118L and118R as an etching mask to expose thesubstrate100. Patterned memory layers114L and114R may remain under theside gates118L and118R.Memory cells120L and120R, each including the memory layers114L and114R and theside gates118L and118R, may be formed on both sides of themiddle gate127. The memory layers114L and114R, each includingtunnel insulating layers111L and111R, charge storage layers112L and112R and blocking insulatinglayers113L and113R, may be formed to have a width and a length below about 30 nm. According to example embodiments, a nano-sized memory layer including a tunnel insulating layer, a charge storage layer, and a blocking insulating layer may be formed. The larger scale integration of the memory device may be achieved.
• According to example embodiments, a larger scale integrated nonvolatile memory device may be achieved with improved reliability. The memory cell may be implemented as a multi level cell (MLC) by controlling the number of electrons stored in the charge storage layer.
• It will be apparent to those skilled in the art that various modifications and variations may be made in example embodiments. For example, various example embodiments may be created by combining the methods of forming the device isolation layer with the methods of forming the side gates. Thus, it is intended that example embodiments cover all of the modifications and variations of example embodiments provided they come within the scope of the appended claims and their equivalents

Claims (16)

1. A nonvolatile memory device comprising:

device isolation layers formed in a substrate to define an active region between the device isolation layers;

first and second impurity regions separately formed in the active region to define a channel region therebetween;

a middle gate formed on the channel region;

a gate insulating layer adjacent to sidewalls and a bottom of the middle gate;

first and second memory cells adjacent to the sidewalls of the middle gate and spaced apart from each other, the first and second memory cells each including a memory layer on the channel region and a side gate formed on the memory layer;

a first spacer layer covering outer sides of the memory layer and the side gate; and

a second spacer layer covering the first spacer layer,

wherein each of the first and second impurity regions include a low concentration impurity region formed under the second spacer layer and a high concentration impurity region self-aligned to the second spacer layer.

2. The nonvolatile memory device ofclaim 1, wherein the memory layer includes a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer on the channel region.

3. The nonvolatile memory device ofclaim 2, wherein the charge storage layer is formed of a single material.

4. The nonvolatile memory device ofclaim 2, wherein the charge storage layer is formed of amorphous silicon.

5. The nonvolatile memory device ofclaim 1, further comprising:

a gate connection layer formed on the middle gate and the side gates to electrically connect the middle gate with the side gates.

6. The nonvolatile memory device ofclaim 1, wherein the first spacer layers is formed of silicon oxide and the second spacer layer is formed of silicon nitride.

7. The nonvolatile memory device ofclaim 1, wherein the middle gate and the side gate cross the device isolation layers and the memory layer is disposed between sidewalls of the device isolation layers.

8. The nonvolatile memory device ofclaim 1, wherein a top surface of the memory layer is coplanar with a top surface of the device isolation layers.

9. A nonvolatile memory device comprising:

device isolation layers formed in a substrate to define an active region between the device isolation layers;

a middle gate crossing the active region;

a gate insulating layer adjacent to sidewalls and a bottom of the middle gate;

first and second memory cells adjacent to the sidewalls of the middle gate and spaced apart from each other, the first and second memory cells each including a side gate crossing the active region and a memory layer between the side gate and the active region,

wherein the memory layer is disposed between sidewalls of the device isolation layers.

10. The nonvolatile memory device ofclaim 9, wherein a top surface of the memory layer is coplanar with a top surface of the device isolation layers.

11. The nonvolatile memory device ofclaim 9, wherein the memory layer includes a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer on the channel region.

12. The nonvolatile memory device ofclaim 11, wherein the charge storage layer is formed of a single material.

13. The nonvolatile memory device ofclaim 11, wherein the charge storage layer is formed of a single material.

14. The nonvolatile memory device ofclaim 9, further comprising:

a gate connection layer formed on the middle gate and the side gates to electrically connect the middle gate with the side gates.

15. The nonvolatile memory device ofclaim 9, further comprising:

a first spacer layer covering outer sides of the first and second memory cells.

16. The nonvolatile memory device ofclaim 15, further comprising:

a second spacer layer covering the first spacer layer, wherein each of the first and second impurity regions include a low concentration impurity region formed under the second spacer layer and a high concentration impurity region self-aligned to the second spacer layer.

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