US20100030930A1 - Bandwidth conserving protocol for command-response bus system - Google Patents
Bandwidth conserving protocol for command-response bus systemDownload PDFInfo
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- US20100030930A1 US20100030930A1US12/577,030US57703009AUS2010030930A1US 20100030930 A1US20100030930 A1US 20100030930A1US 57703009 AUS57703009 AUS 57703009AUS 2010030930 A1US2010030930 A1US 2010030930A1
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/26—Special purpose or proprietary protocols or architectures
Definitions
- Embodiments of the present inventionrelate to bus protocols for devices in computing systems.
- the embodimentsrelate to bus protocols that use a command-response protocol to manage transactions.
- Modern computer systemsinclude a plurality of integrated circuit devices interconnected with other devices via computer busses.
- Bus architecturesvary considerably among these systems and many systems, in fact, include multiples of busses having different bus architectures.
- the different bus architecturescan include different protocols used to manage the flow of data among agents connected to the bus.
- one bus protocolmay employ a command-response protocol in which a source agent on the bus transfers a packet of data to a destination agent according to a “command” transaction posted on the bus.
- the “command” transactiontypically includes the data and also includes an indication of what is to be done with the data.
- the destination agentmay generate a “response” transaction indicating either that the packet was received properly or that the commanded action has been completed.
- the command-response protocolhas been used on busses to which more than two agents are connected.
- the inventorhad identified a need in the art to conserve resources of busses that operate according to the command-response protocol.
- the inventorrecognized a need to limit the number of response transactions that are posted on the bus. These response transactions have limited utility—while they permit the source and destination agents to synchronize their operations, they do not transfer data packets themselves.
- FIG. 1illustrates a computer system according to an embodiment of the present invention.
- FIG. 2is a flow diagram of a method according to an embodiment of the present invention.
- FIG. 3illustrates a communication flow between source and destination agents according to an embodiment of the present invention.
- FIG. 4is a simplified block diagram of a transmitting agent according to an embodiment of the present invention.
- FIG. 5is a simplified block diagram of a device driver according to an embodiment of the present invention.
- Embodiments of the present inventionare directed to a command-response bus protocol that reduces the number of response transactions generated on the bus.
- an array of datais divided into a number of packets and transmitted over the bus in respective transactions.
- the transactionsinclude a writeback flag, which is enabled for the last packet but disabled otherwise.
- a receiver of the packetsobserves the enabled writeback flag, it generates a response transaction.
- the response transactionindicates either that all packets of the array were received properly or that the commanded operation has been completed for the entire array.
- FIG. 1illustrates a computer system 100 according to an embodiment of the present invention.
- the systemmay include one or more processors 110 and memory systems 120 provided in mutual communication.
- the systemfurther may include a plurality of peripheral devices 1 -N ( 130 , 140 , 150 ) coupled to a communication bus 160 .
- a bus bridge 170may provide an interface between the processors 110 and memory systems 120 and the communication bus 160 .
- the bus 160may include a shared bus architecture, a packet switched bus architecture or a circuit switched bus architecture, among others.
- Common peripheral devices 130 - 150include network interface cards, disk controllers, graphics controllers and the like. These devices typically read or write quantities of data to or from a memory 120 to another device outside the computer system 100 . In doing so, the peripheral devices may initiate bus transactions on the bus 160 to transfer a quantity of data. When multiple devices or even a single high-speed device is present on a communication bus 160 , the bus 160 can become highly loaded.
- Embodiments of the present inventionprovide a protocol for a communication bus in a computer system.
- the datamay be divided into a plurality of packets, each to be transmitted individually.
- a sourcetransmits the packets serially, in packet order, to a destination on the bus.
- the sourcesets a flag in the transmitted packet to signal the destination to return a response indicating that its processing of the final packet has been completed.
- the destinationso responds, it impliedly indicates that all earlier transmitted packets were received and processed properly.
- FIG. 2is a flow diagram of a method 1000 according to an embodiment of the present invention.
- the methodmay begin when a source stores a quantity of data (called an “array” herein) to be transmitted across a communication bus.
- the methoddivides the array into a plurality of packets for transmission (box 1010 ). For each packet, the method determines whether the packet is the last packet in the array (box 1020 ). If not, the method causes the packet to be transmitted without a “writeback flag” enabled (box 1030 ). Otherwise, if the packet is the last packet to be transmitted, the writeback flag is enabled and the packet is transmitted across the bus (box 1040 ).
- the methodmay operate continuously until the data array is transmitted in its entirety.
- FIG. 3illustrates a communication flow between a source 310 and a destination 320 using the communication protocol of the foregoing embodiments.
- the source 310transmits a data array to the destination as individual packets 1 -N.
- the sourceinitiates a series of transactions on the communication bus and transfers one of the packets across the bus pursuant to that transaction.
- transfer of packets 1 through N ⁇ 1may occur without having enabled a writeback flag within the packet.
- Transfer of the final packet N(box 370 ) may have the writeback flag enabled.
- the writeback flagonce detected by the destination 320 , may cause the destination to initiate a response to the source 310 in its own transaction, indicating that the data transfer was successfully performed.
- FIG. 3illustrates an example where successful communication is achieved between the source and destination agents. If successful transmission of an array occurs, a destination agent 320 will transmit only a single response to all packets in the array. If transmission errors occur with respect to a packet (say, packet 2 340 ), the destination agent 320 may generate a transaction on the bus indicating the occurrence of an error.
- FIG. 1illustrates a bridge interface 170 and a plurality of peripheral devices 130 - 150 coupled to bus 160 .
- the bridge interface 170may function as the source and device 2 may function as a destination in a manner consistent with the disclosure of FIG. 3 .
- another devicesay, device 1 130
- the bridge interface 170becomes the destination and the device 1 130 becomes the source.
- FIG. 3for the sake of clarity, omits interstitial communications that may occur on the bus 160 during operation.
- devicesare permitted to request and reserve bus bandwidth on round-robin or other pro rata bases.
- FIG. 3is representative of a data transfer between the bridge interface 170 and the first device 130 of FIG. 1
- the bus 160may carry not only those packets illustrated in FIG. 3 but additional packets of data pursuant to transactions initiated by other devices ( 140 - 150 ). These other transactions are extraneous to the present discussion and, therefore, have not been shown.
- agentstypically prioritize various transaction types against each other.
- Processor read requeststypically are deemed of higher priority than transfers of data from main memory to long term storage areas.
- an agentmay maintain separate queues for transmission of data to other agents.
- FIG. 4is a simplified block diagram of a transmitting agent 400 according to an embodiment of the present invention.
- the agent 400may include a plurality of queues 410 - 430 , a connection manager 440 and a bus interface 450 .
- the different queues 410 - 430represent transmissions having different levels of priority with respect to each other.
- the agent 400identifies a new data array to be transmitted on a bus, it assigns the array to one of the queues (say, queue 410 ) according to the array's priority level.
- the data arrayis queued, packetized and transmitted on the bus.
- the agent 400may implement multiple instances of the method of FIG. 2 simultaneously, one for each queue 410 - 430 maintained by the device. This embodiment is particularly useful in implementations where an agent 400 drains data from various queues according to some fairness scheme, perhaps a weighted round-robin selection scheme that reflects the relative priorities among the queues. Thus, at various points during operation, the agent 400 may have several partially transmitted arrays in its queues 410 - 430 . By managing each queue with independent instances of the method 1000 ( FIG. 2 ), however, the agent 400 may maintain synchronized communication with the various destination agents on the communication bus.
- queue 1 410may correspond to data destined for device 1 130
- queue 2 420may correspond to data destined for device 2 140
- the agent 400may manage data transmissions from the queues 410 - 430 by maintaining multiple independent instances of the method 1000 ( FIG. 2 ) for each queue.
- FIG. 5is a simplified block diagram of a device driver 500 according to an embodiment of the present invention.
- the device driver 500may include a processor 510 , a bus interface circuit 520 , a memory 530 and a medium interface circuit 540 .
- the processor 510may operate according to executable instructions stored in the memory 530 . In this embodiment, the executable instructions may cause the processor to operate as described above.
- the bus interface circuit 520provides an electrical connection between the processor 510 and a bus 550 .
- the bus interface circuit 520may generate electrical signals on the bus under command of the processor 510 .
- the medium interface circuit 540may provide electrical connection between the processor 510 and other components of the device 500 (not shown).
- the devicesmay vary considerably. They may include network interface cards, disk controllers and graphics controllers among others.
- the medium interface circuit 540may provide an interface between the processor 510 and the communication apparatus, disk drive or display apparatus as the case may be. Such components are not material to the present discussion and have been omitted for the sake of clarity.
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Abstract
Description
- Embodiments of the present invention relate to bus protocols for devices in computing systems. In particular, the embodiments relate to bus protocols that use a command-response protocol to manage transactions.
- Modern computer systems include a plurality of integrated circuit devices interconnected with other devices via computer busses. Bus architectures vary considerably among these systems and many systems, in fact, include multiples of busses having different bus architectures. The different bus architectures can include different protocols used to manage the flow of data among agents connected to the bus. For example, one bus protocol may employ a command-response protocol in which a source agent on the bus transfers a packet of data to a destination agent according to a “command” transaction posted on the bus. The “command” transaction typically includes the data and also includes an indication of what is to be done with the data. The destination agent may generate a “response” transaction indicating either that the packet was received properly or that the commanded action has been completed. The command-response protocol has been used on busses to which more than two agents are connected.
- These modern systems can be “bus-limited.” Conventionally, the rate at which agents can process data far exceeds the rate at which the busses between them can carry data. Thus, the speed of the bus can limit the performance of a computer system. These performance limits are particularly acute in systems where several agents are coupled to a common bus, each of them are faster than the bus and each of them compete against the other agents for bus resources.
- The inventor had identified a need in the art to conserve resources of busses that operate according to the command-response protocol. In particular, the inventor recognized a need to limit the number of response transactions that are posted on the bus. These response transactions have limited utility—while they permit the source and destination agents to synchronize their operations, they do not transfer data packets themselves.
FIG. 1 illustrates a computer system according to an embodiment of the present invention.FIG. 2 is a flow diagram of a method according to an embodiment of the present invention.FIG. 3 illustrates a communication flow between source and destination agents according to an embodiment of the present invention.FIG. 4 is a simplified block diagram of a transmitting agent according to an embodiment of the present invention.FIG. 5 is a simplified block diagram of a device driver according to an embodiment of the present invention.- Embodiments of the present invention are directed to a command-response bus protocol that reduces the number of response transactions generated on the bus. According to these embodiments, an array of data is divided into a number of packets and transmitted over the bus in respective transactions. The transactions include a writeback flag, which is enabled for the last packet but disabled otherwise. When a receiver of the packets observes the enabled writeback flag, it generates a response transaction. The response transaction indicates either that all packets of the array were received properly or that the commanded operation has been completed for the entire array.
FIG. 1 illustrates acomputer system 100 according to an embodiment of the present invention. The system may include one ormore processors 110 andmemory systems 120 provided in mutual communication. The system further may include a plurality of peripheral devices1-N (130,140,150) coupled to acommunication bus 160. Abus bridge 170 may provide an interface between theprocessors 110 andmemory systems 120 and thecommunication bus 160. Thebus 160 may include a shared bus architecture, a packet switched bus architecture or a circuit switched bus architecture, among others.- Common peripheral devices130-150 include network interface cards, disk controllers, graphics controllers and the like. These devices typically read or write quantities of data to or from a
memory 120 to another device outside thecomputer system 100. In doing so, the peripheral devices may initiate bus transactions on thebus 160 to transfer a quantity of data. When multiple devices or even a single high-speed device is present on acommunication bus 160, thebus 160 can become highly loaded. - Embodiments of the present invention provide a protocol for a communication bus in a computer system. When it is desired to transfer a quantity of data across the bus, the data may be divided into a plurality of packets, each to be transmitted individually. A source transmits the packets serially, in packet order, to a destination on the bus. When the last packet is to be transmitted, the source sets a flag in the transmitted packet to signal the destination to return a response indicating that its processing of the final packet has been completed. When the destination so responds, it impliedly indicates that all earlier transmitted packets were received and processed properly.
FIG. 2 is a flow diagram of amethod 1000 according to an embodiment of the present invention. The method may begin when a source stores a quantity of data (called an “array” herein) to be transmitted across a communication bus. The method divides the array into a plurality of packets for transmission (box1010). For each packet, the method determines whether the packet is the last packet in the array (box1020). If not, the method causes the packet to be transmitted without a “writeback flag” enabled (box1030). Otherwise, if the packet is the last packet to be transmitted, the writeback flag is enabled and the packet is transmitted across the bus (box1040). The method may operate continuously until the data array is transmitted in its entirety.FIG. 3 illustrates a communication flow between asource 310 and adestination 320 using the communication protocol of the foregoing embodiments. In this diagram, thesource 310 transmits a data array to the destination as individual packets1-N. The source initiates a series of transactions on the communication bus and transfers one of the packets across the bus pursuant to that transaction.- As noted, transfer of
packets 1 through N−1 (boxes330-360) may occur without having enabled a writeback flag within the packet. Transfer of the final packet N (box370) may have the writeback flag enabled. The writeback flag, once detected by thedestination 320, may cause the destination to initiate a response to thesource 310 in its own transaction, indicating that the data transfer was successfully performed. FIG. 3 illustrates an example where successful communication is achieved between the source and destination agents. If successful transmission of an array occurs, adestination agent 320 will transmit only a single response to all packets in the array. If transmission errors occur with respect to a packet (say,packet 2340), thedestination agent 320 may generate a transaction on the bus indicating the occurrence of an error.- The foregoing discussion has illustrated communication between a source and a destination. According to embodiments of the present invention, any of the devices directly coupled to a common communication bus may operate as a source or a destination.
FIG. 1 , for example, illustrates abridge interface 170 and a plurality of peripheral devices130-150 coupled tobus 160. When thebridge interface 170 has data to be transferred todevice 2140, for example, it may function as the source anddevice 2 may function as a destination in a manner consistent with the disclosure ofFIG. 3 . At some other point during operation, another device (say,device 1130) may store data to be transferred to thebridge interface 170; in this example, thebridge interface 170 becomes the destination and thedevice 1130 becomes the source. FIG. 3 , for the sake of clarity, omits interstitial communications that may occur on thebus 160 during operation. To provide a degree of fairness in the allocation of bus resources among devices, devices are permitted to request and reserve bus bandwidth on round-robin or other pro rata bases. Thus, ifFIG. 3 is representative of a data transfer between thebridge interface 170 and thefirst device 130 ofFIG. 1 , thebus 160 may carry not only those packets illustrated inFIG. 3 but additional packets of data pursuant to transactions initiated by other devices (140-150). These other transactions are extraneous to the present discussion and, therefore, have not been shown.- The principles of the present invention may be applied independently to various types of queued data transmissions that commonly are maintained by bus agents. For example, agents typically prioritize various transaction types against each other. Processor read requests typically are deemed of higher priority than transfers of data from main memory to long term storage areas. Alternatively, an agent may maintain separate queues for transmission of data to other agents.
FIG. 4 is a simplified block diagram of a transmittingagent 400 according to an embodiment of the present invention. Theagent 400 may include a plurality of queues410-430, aconnection manager 440 and abus interface 450. To simplify the present discussion, assume that the different queues410-430 represent transmissions having different levels of priority with respect to each other. When theagent 400 identifies a new data array to be transmitted on a bus, it assigns the array to one of the queues (say, queue410) according to the array's priority level. The data array is queued, packetized and transmitted on the bus.- According to an embodiment, the
agent 400 may implement multiple instances of the method ofFIG. 2 simultaneously, one for each queue410-430 maintained by the device. This embodiment is particularly useful in implementations where anagent 400 drains data from various queues according to some fairness scheme, perhaps a weighted round-robin selection scheme that reflects the relative priorities among the queues. Thus, at various points during operation, theagent 400 may have several partially transmitted arrays in its queues410-430. By managing each queue with independent instances of the method1000 (FIG. 2 ), however, theagent 400 may maintain synchronized communication with the various destination agents on the communication bus. - As noted, in other embodiments, separate queues may be maintained for separate agents on the external bus. Thus, if
FIG. 4 hypothetically represented apparatus within the bridge interface170 (FIG. 1 ),queue 1410 may correspond to data destined fordevice 1130,queue 2420 may correspond to data destined fordevice 2140, and so on. In this embodiment, theagent 400 may manage data transmissions from the queues410-430 by maintaining multiple independent instances of the method1000 (FIG. 2 ) for each queue. - The foregoing embodiments also find application in programmable device drivers.
FIG. 5 is a simplified block diagram of adevice driver 500 according to an embodiment of the present invention. Thedevice driver 500 may include aprocessor 510, abus interface circuit 520, amemory 530 and amedium interface circuit 540. Theprocessor 510 may operate according to executable instructions stored in thememory 530. In this embodiment, the executable instructions may cause the processor to operate as described above. Thebus interface circuit 520 provides an electrical connection between theprocessor 510 and abus 550. Thebus interface circuit 520 may generate electrical signals on the bus under command of theprocessor 510. Themedium interface circuit 540 may provide electrical connection between theprocessor 510 and other components of the device500 (not shown). As described above, the devices may vary considerably. They may include network interface cards, disk controllers and graphics controllers among others. Themedium interface circuit 540 may provide an interface between theprocessor 510 and the communication apparatus, disk drive or display apparatus as the case may be. Such components are not material to the present discussion and have been omitted for the sake of clarity. - Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.
Claims (25)
1. A communication method for a computer bus, comprising transferring a quantity of data across the bus in a series of bus transactions, each bus transaction including a portion of the data provided in a packet and a writeback flag, wherein the writeback flag is enabled for a final transaction in the series and disabled for all other transactions in the series.
2. The communication method ofclaim 1 , further comprising, responsive to the enabled writeback flag, generating a transaction by a destination agent on the bus indicating whether all packets in the series of transactions were received properly.
3. The communication method ofclaim 1 , wherein a destination agent on the bus generates no response to any of the transactions in the series having a disabled writeback flag, if the destination agent successfully received packets in those transactions.
4. A communication method, comprising:
queuing an array of data to be transmitted to an agent,
dividing the array into packets,
serially transmitting the packets to the agent via a communication bus wherein, for all packets except the last one, the packets are transmitted with a disabled writeback flag and the last packet is transmitted with an enabled writeback flag.
5. The communication method ofclaim 4 , further comprising, for each of a plurality of agents on the communication bus, maintaining a separate queue for data to be transmitted to each such agent.
6. The communication method ofclaim 4 , further comprising maintaining separate queues for data transmissions of different priorities.
7. The communication method ofclaim 4 , further comprising, by the agent and in response to the enabled writeback flag, generating a response to the transmitted array of data.
8. The communication method ofclaim 7 , wherein the response indicates that the agent successfully received all transmitted packets in the array.
9. The communication method ofclaim 7 , wherein the response indicates that the agent completed a commanded operation with respect to all transmitted packets in the array, the command transmitted to the second agent in association with the transmitted packets.
10. A computer system, comprising:
a plurality of agents coupled to a common communication bus, the agents to exchange data over the bus according to a common bus protocol, wherein:
a transmitting agent of an array of data is to transmit data to a receiving agent in a plurality of bus transactions, each transaction transferring a portion of the array to the receiving agent and including a writeback flag, the writeback flag of all transactions except the last one being disabled and the writeback flag of the last of the plurality of transactions being enabled,
the receiving agent of the array is to generate a response to the enabled writeback flag indicating successful reception of all packets in the array.
11. The computer system ofclaim 10 , wherein the transmitting agent comprises:
a plurality of queues to store arrays of data,
a connection manager to schedule transmissions of packets from the queues,
a bus interface circuit to electrically couple the connection manager to the communication bus.
12. The computer system ofclaim 10 , wherein the transmitting agent is to maintain separate queues to store arrays of data for transmission, one queue for each other agent on the communication bus.
13. The computer system ofclaim 10 , wherein the transmitting agent is to maintain separate queues to store arrays of data for transmission, one queue for grade of transmission priority supported by the agent.
14. The computer system ofclaim 10 , wherein the transmitting agent comprises:
a processor,
a memory to store executable instructions for the processor, and
an interface circuit to provide an electrical interface between the processor and the communication bus.
15. An agent, comprising:
a bus interface, coupled to a communication bus and to manage the agent's performance of transactions on the bus, wherein:
if the agent is a transmitter of an array of data on the bus, the agent it to generate a plurality of transactions on the bus, each including a portion of the array and a writeback flag, the writeback flags of all except the last in the plurality of transactions being disabled, the writeback flag of the last transaction being enabled,
if the agent is a receiver of an array of data on the bus, the agent captures data of a plurality of transactions on the bus, each transaction including a portion of the array and, in response to an enabled writeback flag in a transaction, to generate another transaction on the bus indicating whether the entire array was received properly.
16. The agent ofclaim 15 , further comprising:
a plurality of queues to store arrays of data,
a connection manager to schedule transmissions of packets from the queues,
a bus interface circuit to electrically couple the connection manager to the communication bus.
17. The agent ofclaim 15 , wherein the agent is to maintain separate queues to store arrays of data for transmission, one queue for each other agent on the communication bus.
18. The agent ofclaim 15 , wherein the agent is to maintain separate queues to store arrays of data for transmission, one queue for grade of transmission priority supported by the agent.
19. The agent ofclaim 15 , wherein the agent comprises:
a processor,
a memory to store executable instructions for the processor, and
an interface circuit to provide an electrical interface between the processor and the communication bus.
20. A computer readable medium, having executable instructions stored therein that, when executed, cause an executing device to:
queue an array of data to be transmitted,
divide the array into packets,
serially transmit the packets to another device via a common communication medium wherein, for all packets except the last one, the packets are transmitted with a disabled writeback flag and the last packet is transmitted with an enabled writeback flag.
21. The computer readable medium ofclaim 20 , the instructions further causing the executing device to maintain, for each of a plurality of other devices on the communication medium, a separate queue for data to be transmitted to each such other device.
22. The computer readable medium ofclaim 20 , the instructions further causing the executing device to maintain separate queues for data transmissions of different priorities.
23. The computer readable medium ofclaim 20 , the instructions further causing the executing device to receive a response from the other device to the enabled writeback flag.
24. The computer readable medium ofclaim 23 , wherein the response indicates that the other device successfully received all transmitted packets in the array.
25. The computer readable medium ofclaim 23 , wherein the response indicates that the other device completed a commanded operation with respect to all transmitted packets in the array, the command transmitted to the other device in association with the transmitted packets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| US12/577,030US20100030930A1 (en) | 2003-06-19 | 2009-10-09 | Bandwidth conserving protocol for command-response bus system |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/464,512US7603491B2 (en) | 2003-06-19 | 2003-06-19 | Bandwidth conserving protocol for command-response bus system |
| US12/577,030US20100030930A1 (en) | 2003-06-19 | 2009-10-09 | Bandwidth conserving protocol for command-response bus system |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| US10/464,512ContinuationUS7603491B2 (en) | 2003-06-19 | 2003-06-19 | Bandwidth conserving protocol for command-response bus system |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/464,512Expired - Fee RelatedUS7603491B2 (en) | 2003-06-19 | 2003-06-19 | Bandwidth conserving protocol for command-response bus system |
| US12/577,030AbandonedUS20100030930A1 (en) | 2003-06-19 | 2009-10-09 | Bandwidth conserving protocol for command-response bus system |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
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| US9819624B2 (en) | 2004-03-31 | 2017-11-14 | Google Inc. | Displaying conversations in a conversation-based email system |
| US7912904B2 (en) | 2004-03-31 | 2011-03-22 | Google Inc. | Email system with conversation-centric user interface |
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Also Published As
| Publication number | Publication date |
|---|---|
| US7603491B2 (en) | 2009-10-13 |
| US20040260856A1 (en) | 2004-12-23 |
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| STCB | Information on status: application discontinuation | Free format text:ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |