US20090314743A1

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Publication number: US20090314743A1
Application number: US12/142,799
Authority: US
Inventors: Hong Ma
Original assignee: Individual
Current assignee: United Microelectronics Corp
Priority date: 2008-06-20
Filing date: 2008-06-20
Publication date: 2009-12-24

Abstract

A method of etching a dielectric layer includes providing a substrate, which includes a dielectric layer and a metal layer, performing a first etching process on the metal layer, and performing a second etching process on the dielectric layer to form a opening in the dielectric layer. The first etching process and the second etching process are in-situ carried out in the same reaction chamber without a vent. Since the first and second etching processes are not performed in different reaction chambers respectively, the cycle time can therefore be improved in the present invention. Because the first and second etching processes are performed without a vent, the substrate is protected from the pollution existing in surrounding.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of etching a dielectric layer, and more particularly, to a method of etching a dielectric layer by utilizing a metal hard mask as an etching mask.

2. Description of the Prior Art

Devices in the semiconductor industry need to undergo several complicated processes such as a photolithograph process, a dry or wet etching process, an ion implantation, and a heat treatment, etc. to construct precise integrated circuits in layers. Among those complicated processes, the process control of dielectric layer etching has become a critical factor, particularly in some applications such as a damascene process or an interconnection technique. For example, in a damascene process, a dielectric layer is etched to form patterns comprising trenches or via. Next the trenches or via are filled with copper, and a planarization process is performed to complete formation of the damascene structure. Additionally, to satisfy requirements of low RC delay effects, a low-K material, an ultra low-k (ULK) material, or a porous low-k material is used to be the dielectric layer in the damascene structure.

Please refer toFIG. 1 throughFIG. 2, which are schematic diagrams of the traditional method of etching a dielectric layer. As shown inFIG. 1, asubstrate12 is first provided. Thesubstrate12 has adielectric layer18 thereon. Thereafter, a patternedphotoresist24 is formed on thedielectric layer18, and an opening26 of a conductive line pattern is defined in the patternedphotoresist24. As shown inFIG. 2, an etching process is afterward performed to etch thedielectric layer18 through the opening26 of the patternedphotoresist24 so that atrench28 is formed in thedielectric layer18. The etching process is performed until exposing thesubstrate12.

Since the process of etching thedielectric layer18 also causes a great loss of the patternedphotoresist24, thepatterned photoresist24 formed on thedielectric layer18 must be thick enough for masking thedielectric layer18. However, when the integrated density of semiconductor devices gets higher, the critical dimension (CD) of etch element becomes smaller, and the aspect ratio of theopening28 becomes higher. The trend to fabricate semiconductor devices with smaller features, has presented difficulties when attempting to form the opening28 with a high aspect ratio in thedielectric layer18. For example, the etching by-products are easily piled up in the opening28. As a result, the traditional method of etching the dielectric layer by utilizing thepatterned photoresist24 as the only etching mask is insufficient for the micro-miniaturization. Accordingly, it is still an important issue to provide an effective etching method without destroying the patterns of the dielectric layer.

SUMMARY OF THE INVENTION

It is therefore a primary objective of the present invention to provide a method of etching a dielectric layer to solve the above-mentioned problem.

From one aspect of the present invention, a method of etching a dielectric layer is disclosed. First, a substrate is provided. The substrate includes a base layer, a dielectric layer and a metal layer. The dielectric layer and the metal layer are disposed above the base layer. Subsequently, a first etching process is performed on the metal layer to turn the metal layer into a patterned metal layer. Next, a second etching process is performed on the dielectric layer to form at least one opening in the dielectric layer. The first etching process and the second etching process are performed in a same reaction chamber.

It is an advantage of the present invention that the cycle time can therefore be improved, and the substrate is protected from the pollution existing in the surrounding environment, since the first and second etching process are not performed in different reaction chambers respectively.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

FIG. 1 throughFIG. 2 are schematic diagrams of the traditional method of etching a dielectric layer;

FIGS. 3-6 are schematic diagrams illustrating a method of etching a dielectric layer in accordance with one preferred embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a reaction chamber provided in the present invention;

FIGS. 8-10 are schematic diagrams illustrating a method of forming an opening of a dual damascene structure in accordance with another preferred embodiment of the present invention; and

FIGS. 11-14 are schematic diagrams illustrating a method of etching a dielectric layer in accordance with another preferred embodiment of the present invention.

DETAILED DESCRIPTION

Please refer toFIG. 3 throughFIG. 7.FIGS. 3-6 are schematic diagrams illustrating a method of etching a dielectric layer in accordance with one preferred embodiment of the present invention, whereFIG. 7 is a schematic diagram illustrating a reaction chamber provided in the present invention. A trench structure is formed in this preferred embodiment. Like number numerals designate similar or the same parts, regions or elements. It is to be understood that the drawings are not drawn to scale and are used only for illustration purposes, and that some lithographic and etching processes relating to the present invention method are known in the art and thus not explicitly shown in the drawings.

As shown inFIG. 3, asemiconductor substrate100 is first provided. Thesemiconductor substrate100 includes abase layer102, aliner layer103 disposed on thebase layer102, adielectric layer104 disposed on theliner layer103, acap layer106 disposed on thedielectric layer104, and ametal layer108 disposed on thecap layer106. Subsequently, acap layer110, a bottom anti-reflection coating layer (BARC layer)112 and a patternedphotoresist114 are formed over themetal layer108 in turn.

The opening of the patternedphotoresist114 can include a predetermined pattern for the subsequent process, such as a trench pattern, and can expose parts of the BARClayer112. Thebase layer102 can include a dielectric layer and a plurality of conducting lines disposed in the dielectric layer. The detail structure of thebase layer102 can be adjusted according to the product design, so is not shown in the drawings. Themetal layer108 can serve as a hard mask during the follow-up etching processes, and is preferably a titanium nitride (TiN) layer or a tantalum nitride (TaN) layer. Thecap layer106 or thecap layer110 can include a silicon carbide (SiC), tetra-ethyl-ortho-silicate (TEOS), or silicon oxynitride (SiON). In addition, thedielectric layer104 can include a low-k material (k≦2.9), such as fluoride silicate glass (FSG), organosilicate (OSG), or ultra low-k (ULK) materials. Theliner layer103 can be applied to a copper (Cu) process to prevent copper from diffusing into the adjacent dielectric layers. In addition, theliner layer103 can also function as an etching stop layer. Theliner layer103 can include silicon nitride compounds, silicon oxide compounds, or silicon carbide compounds, such as SiC, SiN, SiON, SiCn, or NBLOK.

As shown inFIG. 4, an etching process is next performed to etch theBARC layer112 and thecap layer110 by utilizing the patternedphotoresist114 as an etching mask. In this embodiment, the process of etching theBARC layer112 can include a trifluoromethane (CHF₃) gas and a tetrafluoromethane (CF₄) gas. The flowing rate of the CHF₃gas can be about 70 standard cubic centimeters per minute (sccm), and the flowing rate of the CF₄gas can be about 110 sccm.

Furthermore, as shown inFIG. 5, another etching process is carried out to etch themetal layer108 by utilizing the patternedphotoresist114 as an etching mask. This etching process can turn themetal layer108 into a patternedmetal layer108a,and is performed until exposing thecap layer106. The process of etching themetal layer108 can be a plasma etching process, and usually includes an effective and potent corrosive as an etching gas, such as sulfur hexafluoride (SF₆) gas or chlorine (Cl₂) gas. For instance, the process of etching themetal layer108 can include an argon (Ar) gas and a chlorine gas. The flowing rate of the Ar gas can be about 200 sccm, and the flowing rate of the Cl₂gas can be about 75 sccm. Afterward, a flash process can be optionally performed (in other words, the flash process can be omitted in other embodiments). In the flash process, a flash gas, such as a nitrogen-containing gas, an oxygen-containing gas, an argon-containing gas, or a compound of the above chemical elements, can flow into the reaction chamber to remove the unwanted residuals on thesemiconductor substrate100. For example, a carbon monoxide (CO) gas can flow into the reaction chamber to remove polymers formed in the above etching processes.

As theFIG. 5 shows, thecap layer110, theBARC layer112 and the patternedphotoresist114 can still cover parts of the underlyingpatterned metal layer108aafter the process of etching themetal layer108. It deserves to be mentioned that thecap layer110, theBARC layer112 and/or the patternedphotoresist114 can be consumed during the etching process in other embodiment, so there can be nopatterned photoresist114 above the patternedmetal layer108a.

Next, as shown inFIG. 6, another etching process is carried out on thedielectric layer104 in the same reaction chamber. The patternedphotoresist114, the remainingBARC layer112, the remainingcap layer110, and the patternedmetal layer108aare utilized as an etching mask for etching thedielectric layer104, so as to form atrench116 in thedielectric layer104. The process of etching thedielectric layer104 can be a plasma etching process, and can include a hexafluorobutadiene (C₄F₆) gas, a nitrogen (N₂) gas, a CF₄gas and an Ar gas. The flowing rate of the C₄F₆gas can be about 10 sccm, the flowing rate of the N₂gas can be about 70 sccm, the flowing rate of the CF₄gas can be about 150 sccm, and the flowing rate of the Ar gas can be about 200 sccm. In practice, the process of etching thedielectric layer104 can include a plurality of etching steps. For instance, the process of etching thedielectric layer104 can include a first main etching procedure, an ashing procedure and a second main etching procedure.

In other embodiments, the method of etching a dielectric layer can be applied to processes of forming a dual damascene structure. Please refer toFIG. 8 andFIG. 10.FIGS. 8-10 are schematic diagrams illustrating a method of forming an opening of a dual damascene structure in accordance with another preferred embodiment of the present invention. As shown inFIG. 8, after the patternedmetal layer108ais formed by the processes shown inFIG.3 throughFIG. 5, theBARC layer112 and the patternedphotoresist114 disposed above the patternedmetal layer108acan be removed. Afterward, anotherBARC layer140 and another patternedphotoresist142 can be formed over thesemiconductor substrate100 in turn. The patternedphotoresist142 has an opening used to define a via pattern of a damascene structure.

As shown inFIG. 9, another etching process is performed on thedielectric layer104 by utilizing the patternedphotoresist142 as an etching mask, so parts of theBARC layer140, parts of thecap layer106, and parts of thedielectric layer104, which are not covered by the patternedphotoresist142, are etched through the opening, and a partial via feature is formed in an upper portion of thedielectric layer104. Thereafter, the remainingpatterned photoresist142, theBARC layer140 and thecap layer110 can be stripped off by an oxygen plasma etching process.

Next, as shown inFIG. 10, an etching process is performed to etch thedielectric layer104 and theliner layer103 by utilizing the patternedmetal layer108aas an etching hard mask, until thebase layer102 is exposed. Therefore, atrench116 and a viahole130 are formed in thedielectric layer104, and thetrench116 and the viahole130 form the opening of a dual damascene structure. It should be noted that the process of etching themetal layer108 and the process of etching thedielectric layer104 are performed in the same reaction chamber, such as thereaction chamber118 shown inFIG. 7. It should also be noted that theliner layer103 can be etched together with thedielectric layer104 in one etching process to expose parts of thebase layer102 in this embodiment. In other embodiments, theliner layer103 can function as an etching stop layer in the process of etching thedielectric layer104. In other words, thedielectric layer104 is etched by utilizing the patternedmetal layer108aas an etching hard mask, until theliner layer103 is exposed, and the exposed part of theliner layer103 is next removed to expose thebase layer102.

The method of etching the dielectric layer in the present invention can be applied to various processes of forming openings, such as processes of forming a via hole, processes of forming a contact hole, a via-first process of forming an opening of a dual damascene structure, a trench-first process of forming an opening of a dual damascene structure, a partial-via-first process of forming an opening of a dual damascene structure, or a self-aligned process of forming an opening of a dual damascene structure. Please refer toFIG. 11 throughFIG. 14.FIGS. 11-14 are schematic diagrams illustrating a method of etching a dielectric layer in accordance with another preferred embodiment of the present invention, where a contact hole is formed in this preferred embodiment. As shown inFIG. 11, asemiconductor substrate200 is first provided. Thesemiconductor substrate200 includes abase layer202, aliner layer203 disposed on thebase layer202, adielectric layer204 disposed on theliner layer203, and ametal layer208 disposed on thedielectric layer204. Subsequently, aBARC layer112 and apatterned photoresist214 are formed over themetal layer208 in turn.

The opening of the patternedphotoresist214 can include a predetermined pattern for the subsequent process, such as a contact hole pattern, and can expose parts of theBARC layer112. Thebase layer202 can include a silicon-based substrate and various devices disposed on the silicon-based substrate. The detail structure of thebase layer202 can be adjusted according to the product design, so is not shown in the drawings. Themetal layer208 is preferably a TiN layer or a TaN layer. Thedielectric layer204 can include an inter-level dielectric layer (ILD), and can be made from low-k materials or ULK materials. Theliner layer203 can include stressed SiN.

As shown inFIG. 12, an etching process is next performed to etch parts of theBARC layer112 by utilizing the patternedphotoresist214 as an etching mask. In this embodiment, the process of etching theBARC layer112 can include a CHF₃gas and a CF₄gas. The flowing rate of the CHF₃gas can be about 50 sccm, and the flowing rate of the CF₄gas can be about 150 sccm. Furthermore, as shown inFIG. 13, another etching process is carried out to etch themetal layer208 by utilizing the patternedphotoresist214 as an etching mask. This etching process can turn themetal layer208 into a patternedmetal layer208a.The process of etching themetal layer208 can be a plasma etching process, and usually includes an effective and potent corrosive as an etching gas, such as SF₆gas or Cl₂gas. For instance, the process of etching themetal layer208 can include an Ar gas and a Cl₂gas. The flowing rate of the Ar gas can be about 200 sccm, and the flowing rate of the Cl₂gas can be about 75 sccm.

As theFIG. 13 shows, theBARC layer112 and the patternedphotoresist214 can still cover parts of the underlyingpatterned metal layer208aafter the process of etching themetal layer208. It deserves to be mentioned that theBARC layer112 and/or the patternedphotoresist214 can be consumed during the etching process in other embodiment, so there can be nopatterned photoresist214 above the patternedmetal layer208a.

Next, as shown inFIG. 14, another etching process is carried out on thedielectric layer204 and theliner layer203 in the same reaction chamber, where theliner layer203 can function as a contact etch stop layer (CESL). Thedielectric layer204 is etched by utilizing the patternedphotoresist214, the remainingBARC layer112, and the patternedmetal layer208aas an etching hard mask, until theliner layer203 is exposed, and the exposed part of theliner layer203 is next removed to expose thebase layer202. Therefore, acontact hole216 is formed in thedielectric layer204. The process of etching thedielectric layer204 can be a plasma etching process, and can include a C₄F₆gas, a carbon monoxide (CO) gas, a CH₂F₂gas and an02 gas. The flowing rate of the C₄F₆gas can be about 20 sccm, the flowing rate of the CO gas can be about 300 sccm, the flowing rate of the CH₂F₂gas can be about 40 sccm, and the flowing rate of the O₂gas can be about 27 sccm. In practice, the process of etching thedielectric layer204 can include a plurality of etching steps. For instance, the process of etching thedielectric layer204 can include a main etching procedure, an ashing procedure and an over-etching procedure. It should be noted that the process of etching themetal layer208 and the process of etching thedielectric layer204 are performed in the same reaction chamber, such as thereaction chamber118 shown inFIG. 7. The different processes can be performed in the same reaction chamber by changing the process recipes, such as providing different process gases, providing different process frequencies, providing different process pressures. As a result, the cycle time can therefore be improved in the present invention, and the substrate is protected from the pollution existing in surrounding environments.

It should also be noted that theliner layer203 can function as the CESL in the process of etching thedielectric layer204, and is further removed to exposebase layer202 in this embodiment. In other embodiments, theliner layer203 can be etched together with thedielectric layer204 by utilizing the patternedphotoresist214, the remainingBARC layer112, and the patternedmetal layer208aas an etching hard mask, until thebase layer202 is exposed to form thecontact hole216 in thedielectric layer204.

Thereafter, the patternedmetal layer208a,theBARC layer112 and the patternedphotoresist214 can be removed from thedielectric layer204. Next, a conductive structure is formed in thecontact hole216 to complete the fabrication of a contact plug (not shown in the drawings).

In sum, the process of etching a dielectric layer and the process of etching a metal layer can be performed in the same reaction chamber without a vent in this invention to protect the semiconductor structure from external pollutions. Thus, the structures of the subsequently formed metal lines or conductive plugs can be improved. The metal layer is usually more anticorrosive than the photoresist in the process of etching dielectric layer. Thus, the patterned metal layer applied as an etching mask can be thinner than the patterned photoresist, and the aspect ratio of the formed opening can therefore be smaller. Since the metal-etching process and the dielectric-etching process are not performed in different reaction chambers respectively, the cycle time can therefore be improved in the present invention, and an efficient process is provided.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims

1. A method of etching a dielectric layer, comprising:

providing a substrate, the substrate comprising a base layer, a dielectric layer and a metal layer, the dielectric layer and the metal layer being disposed above the base layer;

performing a first etching process on the metal layer to turn the metal layer into a patterned metal layer; and

performing a second etching process on the dielectric layer to form at least one opening in the dielectric layer, wherein the first etching process and the second etching process are performed in a same reaction chamber.

2. The method ofclaim 1, wherein the metal layer comprises titanium nitride (TiN).

3. The method ofclaim 1, wherein the second etching process utilizes the patterned metal layer as an etching mask to etch the dielectric layer.

4. The method ofclaim 3, wherein the opening of the dielectric layer comprises a trench, a via hole or an opening of a dual damascene structure.

5. The method ofclaim 4, further comprising a step of forming a patterned photoresist on the metal layer, wherein the first etching process utilizes the patterned photoresist as an etching mask to etch the metal layer.

6. The method ofclaim 5, further comprising a step of forming a first cap layer on the metal layer before forming the patterned photoresist.

7. The method ofclaim 6, further comprising a step of forming a bottom anti-reflection coating layer (BARC layer) on the first cap layer before forming the patterned photoresist, wherein the patterned photoresist exposes parts of the BARC layer.

8. The method ofclaim 7, further comprising a step of etching the BARC layer and the first cap layer by utilizing the patterned photoresist as an etching mask after forming the patterned photoresist.

9. The method ofclaim 5, wherein the substrate further comprises a second cap layer disposed between the dielectric layer and the metal layer.

10. The method ofclaim 9, wherein the second etching process utilizes the patterned metal layer as an etching mask to etch the first cap layer and the dielectric layer.

11. The method ofclaim 1, wherein the opening of the dielectric layer comprises a contact hole.

12. The method ofclaim 11, further comprising a step of forming a patterned photoresist on the metal layer, wherein the first etching process utilizes the patterned photoresist as an etching mask to etch the metal layer.

13. The method ofclaim 12, further comprising a step of forming a bottom anti-reflection coating layer (BARC layer) on the metal layer before forming the patterned photoresist, wherein the patterned photoresist exposes parts of the BARC layer.

14. The method ofclaim 13, further comprising a step of etching the BARC layer by utilizing the patterned photoresist as an etching mask after forming the patterned photoresist.

15. The method ofclaim 11, wherein the dielectric layer comprises an inter-level dielectric layer.

16. The method ofclaim 1, wherein the first etching process and the second etching process comprises a plasma etching process.

17. The method ofclaim 1, wherein the first etching process comprises sulfur hexafluoride gas or chlorine gas.

18. The method ofclaim 1, wherein the reaction chamber comprises a protecting layer disposed on an inner surface of the reaction chamber.

19. The method ofclaim 18, wherein the protecting layer comprises silicon carbide or yttrium oxide compounds.

20. The method ofclaim 1, wherein the substrate is kept in the reaction chamber during a period between the first etching process and the second etching process.