US20090308439A1 - Solar cell fabrication using implantation - Google Patents

Abstract

A solar cell device and method of making are provided. The device includes a silicon substrate including a preexisting dopant. A homogeneous lightly doped region is formed on a surface of the silicon substrate to form a junction between the preexisting dopant and the lightly doped region. A heavily doped region is selectively implanted on the surface of the silicon substrate. A seed layer is formed over the heavily doped region. A metal contact is formed over the seed layer. The device can include an anti-reflective coating. In one embodiment, the heavily doped region forms a parabolic shape. The heavily doped regions can each be a width on the silicon substrate a distance in the range 50 to 200 microns. Also, the heavily doped regions can be laterally spaced on the silicon substrate a distance in the range 1 to 3 mm from each other. The seed layer can be a silicide. The silicon substrate can include fiducial markers configured for aligning the placement of the heavily doped regions during an ion implantation process.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application claims priority to co-pending U.S. Provisional Application Ser. No. 61/131,687, filed Jun. 11, 2008, entitled “SOLAR CELL FABRICATION USING IMPLANTATION,” co-pending U.S. Provisional Application Ser. No. 61/131,688, filed Jun. 11, 2008, entitled “APPLICATIONS SPECIFIC IMPLANT SYSTEM FOR USE IN SOLAR CELL FABRICATIONS,” co-pending U.S. Provisional Application Ser. No. 61/131,698, filed Jun. 11, 2008, entitled “FORMATION OF SOLAR CELL-SELECTIVE EMITTER USING IMPLANTATION AND ANNEAL METHODS,” co-pending U.S. Provisional Application Ser. No. 61/133,028, filed Jun. 24, 2008, entitled “SOLAR CELL FABRICATION WITH FACETING AND IMPLANTATION,” and co-pending U.S. Provisional Application Ser. No. 61/210,545, filed Mar. 20, 2009, entitled “ADVANCED HIGH EFFICIENCY CRYSTALLINE SOLAR CELL FABRICATION METHOD,” which are all hereby incorporated by reference as if set forth herein.
FIELD OF THE INVENTION
• The present invention relates to the field of solar cells. More particularly, the present invention relates to a solar cell device and method of making.
BACKGROUND
• The use of diffusion in forming dopants on the surface of a semiconductor substrate is plagued by several problems. One problem is excess accumulation of unactivated dopants near the surface as the dopants are driven into the bulk of the semiconductor material. This excess accumulation can vary the resistivity in different regions of the semiconductor substrate and thus lead to varying light absorption capability and varying electron-hole formation and recombination performance of a solar cell. In particular, one problem encountered is the lack of utilization of the blue light as the result of formation of a “dead layer.”
• Another drawback of conventional diffusion forming systems is the difficulty in laterally positioning of the dopants across the semiconductor substrate as the line widths and wafer thicknesses become smaller. The solar cell industry is expected to require dopant lateral placements, as emitter dimensions shrink from 200 microns down to less than 50 microns. Such miniaturization is difficult or even impossible for the present methodology of diffusion and screen printing in forming solar cells. Selectively altering the resistivity of regions underneath the metal grid lines with respect to the regions in between the grid lines provides charge collection and generation advantages and thus lead to gain in efficiencies.
• Diffusion processes typically use a dopant material that is applied as a paste or sprayed onto the surface of the semiconductor substrate. The semiconductor substrate is then heated to drive the dopant to a particular depth to form a junction. The semiconductor substrate is typically heated in a diffusion furnace or a similar heating means. An n-type or p-type of a dopant can be used to form the junction depending upon the background doping type. A subsequent screen printing step is used to form contact lines onto the surface of the wafer in completing the solar cell.
• The interface of the metal contact with the semiconductor affects the performance of the solar cell. Conventionally, the junction between the metal contact and the silicon is heated to form a silicide. This heating process improves the interface, but also includes drawbacks.
• Accordingly, it is desirable to provide an improved more economical method of forming a solar cell to overcome the drawbacks of conventional solar cell manufacturing methods, allow production of solar cells with smaller dimensions and having tighter control of the dose and dopant position.
SUMMARY OF THE INVENTION
• In accordance with a first aspect of the present invention, a solar cell device is provided. The device includes a silicon substrate including a preexisting dopant. A homogeneous lightly doped region is formed on a surface of the silicon substrate over the preexisting dopant. A junction is formed between the preexisting dopant and the lightly doped region. The junction is formed a predetermined distance from the surface of the silicon substrate. A heavily doped region is selectively implanted on the surface of the silicon substrate within the lightly doped region. A seed layer is formed over the heavily doped region. A metal contact is formed over the seed layer. The device can include an anti-reflective coating.
• In an exemplary embodiment, the device includes the homogeneous lightly doped region having a resistivity in a range of 80 to 160 Ohms/square and the heavily doped region having a resistivity in a range of 10 to 40 Ohms/square. In one embodiment, the homogeneous lightly doped region includes a resistivity of approximately 100 Ohms/square and the heavily doped region includes a resistivity of approximately 25 Ohms/square. The heavily doped regions can each be a width on the silicon substrate a distance in the range 50 to 200 microns. Also, the heavily doped regions can be laterally spaced on the silicon substrate a distance in the range 1 to 3 mm from each other.
• The seed layer can be a silicide. The seed layer can also be a layer of a material including any of the materials Ni, Ta, Ti, W or Cu. The silicon substrate can include fiducial markers configured for aligning the placement of the heavily doped regions during an ion implantation process.
• In accordance with a second aspect of the present invention, a method of forming a solar cell device is provided. The method includes providing a silicon substrate including a preexisting dopant. An ion implantation process is used to form a homogeneous lightly doped region on a surface of the silicon substrate over the preexisting dopant. A junction is formed between the preexisting dopant and the lightly doped region. The junction is formed a predetermined distance from the surface of the silicon substrate. A selective ion implantation process is used to form a heavily doped region implanted on the surface of the silicon substrate within the lightly doped region. The heavily doped region is implanted at predetermined locations on the silicon substrate surface. The selective ion implantation process is used to form a seed layer over the heavily doped region. A metal contact is formed over the seed layer. The method can include forming an anti-reflective coating.
• The heavily doped region is implanted at predetermined locations on the silicon substrate surface using a physical mask. The physical mask includes openings aligned with the predetermined locations. The physical mask is formed on the surface of the silicon substrate. The physical mask is positioned at a predetermined distance above the surface of the silicon substrate during the selective ion implantation process to form the heavily doped region. In an alternative embodiment, the selective ion implantation process uses a shaped ion beam that is aligned with the predetermined locations to form the heavily doped region. In a further embodiment, such selective implantation can be done through a mask on the surface of the substrate. A combination of all the above embodiments of forming the heavily doped regions can be used.
• In an exemplary embodiment, the homogeneous lightly doped region includes a resistivity in a range of 80 to 160 Ohms/square and the homogeneous lightly doped region includes a resistivity of approximately 100 Ohms/square. The heavily doped region can include a resistivity in a range of 10 to 40 Ohms/square. In one embodiment, the heavily doped region includes a resistivity of approximately 25 Ohms/square. The heavily doped regions each include a width on the silicon substrate a distance in the range 50 to 200 microns and the heavily doped regions are laterally spaced on the silicon substrate a distance in the range 1 to 3 mm from each other.
• The seed layer is preferably a silicide. The seed layer can be a layer of a material including any of the materials Ni, Ta, Ti, W or Cu. The silicon substrate can include fiducial markers configured for aligning the placement of the heavily doped regions during the selective ion implantation process. The method includes using an annealing process on the silicon substrate having the homogeneous lightly doped region. Alternatively, the annealing process is used on the silicon substrate after forming the metal contact. Using annealing after forming the metal contact allows for lower temperature annealing than conventional processes. Thus allowing for the use of substrates or thin substrates on carriers that otherwise may degrade at higher temperatures.
• Other features of the present invention will become apparent from consideration of the following description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• The novel features of the invention are set forth in the appended claims. However, for purposes of explanation, several embodiments of the invention are set forth in the following figures.
• FIG. 1 illustrates a method of making a selective emitter structure of a solar cell in accordance with an embodiment of the invention.
• FIG. 2 illustrates a method of making a selective emitter structure of a solar cell in accordance with an alternative embodiment of the invention.
• FIG. 3 illustrates a method of making a selective emitter structure of a solar cell in accordance with still another embodiment of the invention.
• FIG. 4 illustrates a method of forming a seed layer of a solar cell in accordance with an embodiment of the invention.
• FIG. 5 illustrates a method of forming a contact layer of a solar cell in accordance with an embodiment of the invention.
• FIG. 6 illustrates a side view of a solar cell device in accordance with an embodiment of the invention.
• FIG. 7 illustrates a side view of a solar cell device in accordance with an alternative embodiment of the invention.
• FIG. 7A illustrates a side view of a solar cell device in accordance with still another embodiment of the invention.
• FIG. 8 illustrates a process flow diagram of forming a solar cell device in accordance with an embodiment of the invention.
DETAILED DESCRIPTION
• In the following description, numerous details and alternatives are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail.
• The present invention uses implantation to form homogeneous and selective emitter regions. The present invention addresses the methods for the formation of solar cells and in particular formation of a selective emitter through a series of implantation processes. Presently, such ability to manipulate and place the dopant laterally is difficult with conventional diffusion or screen printing processes. The present invention selectively controls the resistance of gridlines, contacts, and selectively controls contact resistance of a metal/semiconductor interface. Moreover, the advantageous formation of a selective emitter with ion implantation allows improved performance for solar cell devices. The present invention can be applied to grown single or mono-crystalline, poly or multi-crystalline silicon as well as very thin silicon placed on a carrier (such as glass) or very thin film deposited silicon or other materials used for solar cell formation. The present invention can be extended to atomic species placement for any other material used in fabrication of junctions.
• FIG. 1, illustrates a method of making a selective emitter structure105 (step101D) using an implantation process according to an embodiment of the present invention. At thestep101A, asilicon substrate101 is provided that is pre-doped with adopant102. Thesilicon substrate101 comprises a wafer of mono or poly silicon material. In an exemplary embodiment, the silicon substrate comprises a 156×156 mm wafer. Other suitable substrates known to a person of ordinary skill can also be used for thesilicon substrate101. In an exemplary embodiment, thesilicon substrate101 includes apre-doped material102. Thepre-doped material102 is pre-doped with a p-type dopant, typically or alternatively an n-type dopant. Thepre-doped material102 can have a resistivity in the range of 0.5-1.5 Ohms/cm and atomic concentration of less than 5E16/cm-cube. An implantation system (not shown) with a high productivity is used for the formation of a homogeneous lightly doped region orhomogeneous layer104. Such an implantation system is the subject of a co-pending patent application Ser. No. ______ , entitled, “Application Specific Implant System for Use in Solar Cell Fabrications,” filed Jun. 11, 2009, which is hereby incorporated in the entirety. Thehomogeneous layer104 is a high resistivity region. Thehomogeneous layer104 allows the formation of electron-hole pairs as the result of an incidence of light. In operation, thehomogeneous layer104 preferably uses a relatively low level of a dopant (high resistivity) to facilitate the formation of charge carriers while avoiding recombination and thus avoiding the “dead layer” effect.
• An ion beam ‘A’ is used for the implantation of thehomogeneous layer104. The ion beam A implants thehomogeneous layer104 in a blanket fashion in thepre-doped material102. In implanting thehomogeneous layer104, either a spot beam or wide plasma beam is used to provide full coverage across thesilicon substrate101. The beam can be scanned across the wafer, the wafer can be moved under the beam or a combination thereof to achieve full coverage. A productivity of the implantation system comprises approximately 1000 or more wafers per hour.
• Ap-n junction103 is formed where thepre-doped material102 and thehomogeneous layer104 meet. Thejunction103 can be formed a predetermined distance from asurface107 of thesilicon substrate101. The distance of thejunction103 from thesurface107 is determined according to an amount of energy E1 used in the ion beam A. The amount of energy E1 can be in the range of 1 to 150 KeV depending on the desired specifications for the solar cell device. Thehomogeneous layer104 can have a resistivity in the range of 80 to 160 Ohms/square. In an exemplary embodiment, the resistivity of thehomogeneous layer104 comprises approximately 100 Ohms/square. An anneal step can be performed here and is described in further detail below at thestep101C. Alternatively, the anneal step here can be eliminated until a final anneal step below (FIG. 6).
• At thestep101B, acontact mask106 is formed on thesurface107 of thesilicon substrate101. Thecontact mask106 allows selective placement of dopant in thesilicon substrate101 at predetermined locations. Thecontact mask106 can be any suitable mask known to a person of ordinary skill. Examples of such masks can include photo-resist, a nitride layer, an oxide layer, a screen-printing or any other suitable film. Thecontact mask106 can be formed using processes known to a person of ordinary skill. In one embodiment, a lithography or contact printing process can be used to form thecontact mask106.Openings109 in thecontact mask106 can be a dimension as large as approximately 200 microns wide. Alternately, theopenings109 can be a dimension as small as 50 microns wide. Aselective emitter108 of the same size as theopenings109 can be formed by implanting dopant therethrough within thesilicon substrate101. A distance or pitch111 (Step101C) between each selective emitter108 (Step101C) can be in the range of approximately 1 mm to 3 mm.
• Thestep101C illustrates using an ion implantation beam ‘B’ for implanting a heavily doped region for theselective emitter108. The ion beam B implants theselective emitter108 in thehomogeneous layer104 that is not protected by thecontact mask106. The ion beam B can be applied in a blanketing fashion over thewhole silicon substrate101 wherein thecontact mask106 will prevent ions from entering the substrate. Alternatively, the ion beam B can be applied in a targeted fashion using a shaped beam that is appropriately directed. Using the shaped beam can help reduce dopant usage and increase the implantation process productivity. The ion beam B includes a dopant that is chosen depending on the manufacturer specifications. In an exemplary embodiment, the dopant for theselective emitter108 comprises an n-type dopant such as phosphorous or arsenic. Alternatively, the ion beam B can include a p-type dopant such as Boron in an embodiment that uses an n-type pre-doped material102 for thesilicon substrate101. Theselective emitter108 is implanted to a depth and distance from thesurface107 into thepre-doped material102. The distance of theselective emitter108 from thesurface107 is determined according to an amount of energy E2 used in the ion beam B. The distance also depends on a dopant concentration level chosen for the ion beam B. The amount of energy E2 can depend on the desired specifications for the solar cell device. In an alternative embodiment, thestep101C includes multiple implantations using varying energy levels and varying dopant concentration levels of the ion beam B. In one embodiment, the energy E2 can be a continuum of variability to provide a tailored atomic profile. Such profile tailoring is described in further detail in a co-pending patent application Ser. No. ______ , entitled, “Formation of Solar Cell Selective Emitter Using Implant and Anneal Method,” filed Jun. 11, 2009, which is hereby incorporated in the entirety.
• An annealing step heats thesilicon substrate101 to a temperature near but well below melting and restores any damage to the crystal structure of thesilicon substrate101 caused by the ion implantation. Also, such annealing will cause activation of dopant atoms. A temperature and time of such annealing and activation can be as low as 400-500 degrees Celsius, which is a sufficient temperature to eliminate any di-vacancies (missing atoms of a lattice structure of the silicon substrate101) and to provide enough activation of the dopant atoms. The annealing step can comprise furnace annealing. Alternatively, a laser annealing or flash lamp annealing can be used in place of the furnace annealing. The annealing step does not adversely affect subsequent process steps described below. In an alternative embodiment, this anneal step can be eliminated until the final anneal step below (FIG. 6).
• A surface texturing process can be included with thestep101C implantation of theselective emitter108. Surface texturing provides a good light capture and adherence to the surface contour and thus will improve a contact formation that is described below. Theselective emitter108 can have a resistivity in the range of 10 to 40 Ohms/square. In an exemplary embodiment, the resistivity of theselective emitter108 comprises approximately 25 Ohms/square.
• Thestep101D illustrates the completedselective emitter structure105.
• FIG. 2, illustrates a method of making a selective emitter structure205 (step201C) using an implantation process according to an alternative embodiment of the present invention. Similar to that described above inFIG. 1, at thestep201A, asilicon substrate201 is provided that is pre-doped with adopant202. Thesilicon substrate201 comprises a wafer of mono, poly or multi crystalline silicon material. In an exemplary embodiment, the silicon substrate comprises a 156×156 mm wafer. Other suitable substrates known to a person of ordinary skill can also be used for thesilicon substrate201. In an exemplary embodiment, thesilicon substrate201 includes apre-doped material202. Thepre-doped material202 is pre-doped with a p-type dopant. Thepre-doped material202 can have a resistivity in the range of 0.5-1.5 Ohms/cm and atomic concentration of less than 5E16/cm-cube. The implantation system as described above, includes a high productivity for the formation of a homogeneous lightly doped region orhomogeneous layer204. Thehomogeneous layer204 is a high resistivity region. The purpose of thehomogeneous layer204 is the formation of electron-hole pairs as the result of an incidence of light. In operation, thehomogeneous layer204 requires a relatively low level of dopant (high resistivity) to facilitate the formation of charge carriers. An ion beam A is used for the implantation of thehomogeneous layer204. The ion beam A implants thehomogeneous layer204 in a blanket fashion in thepre-doped material202. In implanting thehomogeneous layer204, either a spot beam or wide plasma beam is used to provide full coverage across thesilicon substrate201. A productivity of the implantation system comprises approximately 1000 or more wafers per hour.
• Ap-n junction203 is formed where thepre-doped material202 and thehomogeneous layer204 intersect. Thejunction203 can be formed a predetermined distance from asurface207 of thesilicon substrate201. The distance of thejunction203 from thesurface207 is determined according to an amount of energy E1 used in the ion beam A. The amount of energy E1 can be in the range of 1 to 150 KeV depending on the desired specifications for the solar cell device. Thehomogeneous layer204 can have a resistivity in the range of 80 to 160 Ohms/square. In an exemplary embodiment, the resistivity of thehomogeneous layer204 comprises approximately 100 Ohms/square. An anneal step can be performed here and is described in further detail below at thestep201B. Alternatively, the anneal step here can be eliminated until the final anneal step below (FIG. 6).
• At thestep201B ahard mask206 is used to facilitate implantation of aselective emitter208. The hard mask can be included in an implanter (not shown) of the implantation system (not shown). Thehard mask206 allows selective placement of dopant on thesilicon substrate201 at predetermined locations. Thehard mask206 can be any suitable material from which such mask are fabricated. The suitable material of thehard mask206 does not affect the implantation process or the solar cell device through sputtering. The suitable material of thehard mask206 is able to tolerate elevated temperatures experienced during the ion beam heating. In one embodiment, thehard mask206 can comprise Silicon or SiC. However, a person of ordinary skill will appreciate many suitable other materials. A suitable thickness of thehard mask206 allows control and management of thehard mask206 temperature during heating and cooling of thehard mask206. The placement and support of thehard mask206 depends on the material and thickness chosen for thehard mask206. Thehard mask206 can be placed on the wafer prior to the beginning of ion implantation. Thehard mask206 can be directly placed on thesilicon substrate surface207. Alternatively, a support or spacer (not shown) can be used to provide a gap between the hard mask and thesilicon substrate surface207. In another embodiment, thehard mask206 can be an array placed off from thesurface207.
• Openings209 in thehard mask206 can be a distance to produce theselective emitter208 as large as approximately 200 microns wide. Alternately, theopenings209 can be adjusted or can be a distance to produce theselective emitter208 as small as 50 microns wide. A distance or pitch211 between eachselective emitter208 can be in the range of approximately 1 mm to 3 mm. A registration mark or fiducial markers can be scribed onto thesilicon substrate201 using the implantation system. The registration mark can be used for alignment ofhard mask206 with thesilicon substrate201. The registration marks can be used for alignment during subsequent steps of the implantation process of theselective emitter208. In an alternative embodiment, a virtual center of the wafer is defined optically and thehard mask206 and the wafer are accordingly aligned to provide a consistent and repeatable pattern on many wafers.
• Still referring to thestep201B, an ion implantation beam ‘C’ for implanting a heavily doped region or theselective emitter208 is shown. The ion beam C implants theselective emitter208 in thehomogeneous layer204 that is not shadowed by thehard mask206. The ion beam C can be applied in a blanketing fashion over thewhole silicon substrate201 including thehard mask206. Alternatively, the ion beam C can be applied in a targeted fashion using a shaped beam. Using the shaped beam can help reduce dopant usage and increase the implantation process productivity. In an exemplary embodiment, the ion beam C can comprise a broad shaped ion beam. In another embodiment, the ion beam C can comprise a moving spot ion beam. The broad shaped ion beam and the moving spot beam can be used to facilitate forming theselective emitter208 approaching the width of 50 microns.
• The ion beam C includes a dopant that is chosen depending on the manufacturer specifications. In an exemplary embodiment, the dopant for theselective emitter208 comprises an n-type dopant such as phosphorous or arsenic. Alternatively, the ion beam C can include a p-type dopant in an embodiment that uses an n-type pre-doped material202 for thesilicon substrate201. Theselective emitter208 is implanted to a depth and distance from thesurface207 into thepre-doped material202. The distance of theselective emitter208 from thesurface207 is determined according to an amount of energy E2 used in the ion beam C. The distance also depends on a dopant concentration level chosen for the ion beam C. The amount of energy E2 can depend on the desired specifications for the solar cell device. In an alternative embodiment, thestep201B includes multiple implantations using varying energy levels and varying dopant concentration levels of the ion beam C. In one embodiment, the energy E2 can be a continuum of variability to provide a tailored atomic profile. Such profile tailoring is described in further detail in a co-pending patent application Ser. No. ______ , entitled, “Formation of Solar Cell Selective Emitter Using Implant and Anneal Method,” filed Jun. 11, 2009, which is hereby incorporated in the entirety.
• An annealing step heats thesilicon substrate201 to a temperature near but well below melting and restores any damage to the crystal structure of thesilicon substrate201 caused by the ion implantation. Also, such annealing will cause activation of dopant atoms. A temperature and time of such annealing and activation can be as low as 400-500 degrees Celsius, which is a sufficient temperature to eliminate any di-vacancies (missing atoms of a lattice structure of the silicon substrate201) and to provide enough activation of the dopant atoms. The annealing step can comprise furnace annealing. Alternatively, a laser annealing or flash lamp annealing can be used in place of the furnace annealing. The annealing step does not adversely affect subsequent process steps described below. In an alternative embodiment, the anneal step here can be eliminated until the final anneal step below (FIG. 6).
• A surface texturing process can be included with thestep201B implantation of theselective emitter208. Surface texturing provides a good light capture and adherence to the surface contour and thus will improve a contact formation that is described below. Theselective emitter208 can have a resistivity in the range of 10 to 40 Ohms/square. In an exemplary embodiment, the resistivity of theselective emitter208 comprises approximately 25 Ohms/square.
• Thestep201C illustrates the completedselective emitter structure205.
• FIG. 3, illustrates a method of making a selective emitter structure (step301C)305 using an implantation process according to yet another embodiment of the present invention. Theselective emitter structure305 is similar to theselective emitter structure205 described above inFIG. 2. At thestep301A, asilicon substrate301 is provided that is pre-doped with adopant302. Thesilicon substrate301 comprises a wafer of mono, poly or multi crystalline silicon material. In an exemplary embodiment, the silicon substrate comprises a 156×156 mm wafer. Other suitable substrates known to a person of ordinary skill can also be used for thesilicon substrate301. In an exemplary embodiment, thesilicon substrate301 includes apre-doped material302. Thepre-doped material302 is pre-doped with a p-type dopant. Thepre-doped material302 can have a resistivity in the range of 0.5-1.5 Ohms/cm and atomic concentration of less than 5E16/cm-cube. The implantation system as described above, includes a high productivity for the formation of a homogeneous lightly doped region orhomogeneous layer304. Thehomogeneous layer304 is a high resistivity region. The purpose of thehomogeneous layer304 is the formation of electron-hole pairs as the result of an incidence of light. In operation, thehomogeneous layer304 requires a relatively low level of dopant (high resistivity) to facilitate the formation of charge carriers. An ion beam A is used for the implantation of thehomogeneous layer304. The ion beam A implants thehomogeneous layer304 in a blanket fashion in thepre-doped material302. In implanting thehomogeneous layer304, either a spot beam or wide plasma beam is used to provide full coverage across thesilicon substrate301. A productivity of the implantation system comprises approximately 1000 or more wafers per hour.
• Ap-n junction303 is formed where thepre-doped material302 and thehomogeneous layer304 meet. Thejunction303 can be formed a predetermined distance from asurface307 of thesilicon substrate301. The distance of thejunction303 from thesurface307 is determined according to an amount of energy E1 used in the ion beam A. The amount of energy E1 can be in the range of 1 to 150 KeV depending on the desired specifications for the solar cell device. Thehomogeneous layer304 can have a resistivity in the range of 80 to 160 Ohms/square. In an exemplary embodiment, the resistivity of thehomogeneous layer304 comprises approximately 100 Ohms/square. An anneal step can be performed here. Alternatively, the anneal step here can be eliminated until the final anneal step below (FIG. 6).
• At thestep301B an ion implantation beam ‘D’ is used to facilitate implantation of theselective emitter308. A registration mark or fiducial markers can be scribed onto thesilicon substrate301 using the implantation system. The registration mark can be used for alignment during the implantation process of theselective emitter308 shown below in thestep301B.
• Still referring to thestep301B, the ion implantation beam D for implanting a heavily doped region or theselective emitter308 is shown. The ion beam D can be applied in a targeted fashion by shaping the ion beam D using a magnetic means, an electrostatic means or a combination of these means. The ion beam D can be shape to a prescribed size coinciding with awidth309 of theselective emitter308. The ion beam D can be narrowed in one or both directions coinciding with a length and a width of thesilicon substrate301. The ion beam D can be narrowed in one direction and scanned across the length of thesilicon substrate301. Alternatively, the ion beam D can be elongated or fast scanned along the width of thesilicon substrate301. In another embodiment, the ion beam D can be formed in a top hat shaped beam during the implantation of theselective emitter308. Using the shaped beam can help reduce dopant usage and increase the implantation process productivity. In an exemplary embodiment, the ion beam D can comprise a broad shaped ion beam. In an exemplary embodiment, the ion beam D can comprise a shaped beam or a scanning beam without any masking to generate regions of high and low dopant by manipulation of the beam, manipulation of the wafer position or by beam pulsing. Using the shaped or scanning beam without any masking provides an additive and over lapping spread of the ion beam D.
• The ion beam D implants theselective emitter308 in thehomogeneous layer304 at predetermined locations on thesurface307 of thesilicon substrate301. The ion beam D can be shaped to provide theselective emitter308 as large as approximately 200 microns wide. Alternately, the ion beam D can be shaped to provide theselective emitter308 as small as 50 microns wide. A distance or pitch311 between eachselective emitter308 can be in the range of approximately 1 mm to 3 mm.
• The ion beam D includes a dopant that is chosen depending on the manufacturer specifications. In an exemplary embodiment, the dopant for theselective emitter308 comprises an n-type dopant such as phosphorous or arsenic. Alternatively, the ion beam D can include a p-type dopant, such as Boron, in an embodiment that uses an n-type pre-doped material302 for thesilicon substrate301. Theselective emitter308 is implanted to a depth and distance from thesurface307 into thepre-doped material302. The distance of theselective emitter308 from thesurface307 is determined according to an amount of energy E2 used in the ion beam D. The distance also depends on a dopant concentration level chosen for the ion beam D. The amount of energy E2 can depend on the desired specifications for the solar cell device. In an alternative embodiment, thestep301B includes multiple implantations using varying energy levels and varying dopant concentration levels of the ion beam D. In one embodiment, the energy E2 can be a continuum of variability to provide a tailored atomic profile. Such profile tailoring is described in further detail in a co-pending patent application Ser. No. ______ , entitled, “Formation of Solar Cell Selective Emitter Using Implant and Anneal Method,” filed Jun. 11, 2009, which is hereby incorporated in the entirety.
• An annealing step heats thesilicon substrate301 to a temperature near but well below melting and restores any damage to the crystal structure of thesilicon substrate301 caused by the ion implantation. Also, such annealing will cause activation of dopant atoms. A temperature and time of such annealing and activation can be as low as 400-500 degrees Celsius, which is a sufficient temperature to eliminate any di-vacancies (missing atoms of a lattice structure of the silicon substrate301) and to provide enough activation of the dopant atoms. The annealing step can comprise furnace annealing. Alternatively, a laser annealing or flash lamp annealing can be used in place of the furnace annealing. The annealing step does not adversely affect subsequent process steps described below. In an alternative embodiment, the anneal step here can be eliminated until the final anneal step below (FIG. 6).
• A surface texturing process can be included with thestep301B implantation of theselective emitter308. Surface texturing provides a good light capture and adherence to the surface contour and thus will improve a contact formation that is described below. Theselective emitter308 can have a resistivity in the range of 10 to 40 Ohms/square. In an exemplary embodiment, the resistivity of theselective emitter308 comprises approximately 25 Ohms/square.
• Thestep301C illustrates the completedselective emitter structure305. Thestep301D illustrates an alternative embodiment of the completedselective emitter structure305A. Theselective emitter structure305A is similar to the completedselective emitter structure305 except theselective emitter structure305A includes a selective emitter308A.
• FIG. 4 illustrates the formation of a transition or aseed layer312 according to an embodiment of the present invention. Acontact mask310 is formed on theselective emitter structure305 similarly as described above inFIG. 1. Thecontact mask310 is formed on the surface of theselective emitter structure305. Thecontact mask310 can be any suitable mask as known to a person of ordinary skill. Examples of such masks can include anti-reflective coverings, a nitride layer, an oxide layer, a screen-printing or any other suitable film. Thecontact mask310 can be formed using processes known to a person of ordinary skill. In one embodiment, a lithography or contact printing process can be used to form thecontact mask310. A physical mask similar to the hard mask206 (FIG. 2) can also be employed.
• An ion beam ‘E’ is used to implant theseed layer312 over theselective emitter308. The ion beam E can comprise a relatively high dose of metal. The arrangement of the ion beam E can be similar to those described above. The ion beam E can comprise a shaped ion beam similarly as described above. Theseed layer312 can comprise a silicide layer. Theseed layer312 can comprise various metal implantations like, Ni, Ta, Ti, W or Cu. In an exemplary embodiment, theseed layer312 can comprise one or more layers each of a different material. Theseed layer312 alters a work function of a metal/semiconductor interface between the contact314 (FIG. 5) and theselective emitter308. In an exemplary embodiment, the work function of theseed layer312 is intermediate of a work function of theselective emitter308 and a work function of the contact314 (FIG. 5). Such work function or band gap engineering can improve the metal/semiconductor interface of the contact and improve the overall performance of the solar cell600 (FIG. 6). In an exemplary embodiment, theseed layer312 is implanted to comprise a width that is slightly smaller than the width of theselective emitter308. The slightly smaller width of theseed layer312 allows the lessening of contact leakage and allows the formation of a Schottky diode. Metal-to-semiconductor contacts are of great importance since they are present in every photovoltaic device. They can behave either as a Schottky barrier or as an ohmic contact dependent on the characteristics of the metal/semiconductor interface. The control and management of the metal/semiconductor interface is of great benefit in improving the performance of the solar cell600 (FIG. 6).
• FIG. 5 illustrates the formation of the contact layer or contact314 according to an embodiment of the present invention. Thecontact314 is formed using a suitable metal material. Thecontact314 can be formed using any well known metal deposition technique, screen printing technique or plating technique.
• An annealing step heats thesilicon substrate301 to a temperature near but well below melting and restores any damage to the crystal structure of thesilicon substrate301 caused by the ion implantation and contact formation. Also, such annealing will cause activation of dopant atoms. A temperature and time of such annealing and activation can be as low as 400-500 degrees Celsius, which is a sufficient temperature to eliminate any di-vacancies (missing atoms of a lattice structure of the silicon substrate301) and to provide enough activation of the dopant atoms. The annealing step can comprise furnace annealing. Alternatively, a laser annealing or flash lamp annealing can be used in place of the furnace annealing. The annealing step does not adversely affect subsequent process steps described below. In an alternative embodiment, the anneal step here can be eliminated until the final anneal step below (FIG. 6).
• FIG. 6 illustrates asolar cell600 according to an embodiment of the present invention. The contact mask310 (FIG. 5) is removed such as by chemical stripping or can by ashing. In an exemplary embodiment, a solution of NaOH (<3 wt %) or KOH (<3 wt %) is used for stripping thecontact mask310 with a spray of 2.4 bar of pressure at a dwell time of a few seconds at 55 degrees Celsius. A person of ordinary skill will appreciate other suitable solutions for stripping thecontact mask310. An anti-reflective coating (ARC) orARC film318 can be formed over the exposedsurface307 of thesilicon substrate301. TheARC film318 can also be used for passivation of thehomogeneous layer304. TheARC film318 also acts as an anti-reflective film to increase the trapping of the incident light within thesolar cell600. Thus, theARC film318 can improve the efficiency of thesolar cell600. A simple roller system using a dual layered organic film, such as Dupont MM500 or Shell SU8 and other alternatives can be laminated on thesurface307. The adhesion and continuity of theARC film318 is critical at this lamination stage. The lamination stage is conducted at a low temperature of approximately 50-100 degrees Celsius. In an exemplary embodiment, rollers of the roller system are preheated and operated at a speed of 1 to 2 mm/min to ensure thesilicon substrate301 preferably does not reach temperatures above approximately 50 degrees Celsius.
• In an alternative embodiment, theARC film318 can be formed using an ion implantation beam similar as described above. TheARC film318 can be formed on thesurface307 of thesilicon substrate301 above thehomogeneous layer304. In an alternative embodiment, theARC film318 can be formed prior to forming thehomogeneous layer304 of thestep301A ofFIG. 3. The quality of theARC film318 is not adversely affected by the lightly doping of thehomogeneous layer304. A final anneal step similar as such annealing described above can be performed. In an exemplary embodiment, only the final anneal step is performed instead of using multiple anneal steps after each implantation as describe above.
• Thesolar cell600 comprises a highly efficient light conversion efficiency in between the gridlines orcontacts314. Thesolar cell600 also provides a highly conductiveselective emitter308 underneath thecontacts314 and thus provide efficiency gains in the order of 1 to 2 absolute percentage points over solar cells absent of theselective emitter308 described herein.
• FIG. 7 illustrates asolar cell700 according to an alternative embodiment of the present invention. Thesolar cell700 includes apre-doped material702 and ahomogeneous layer704. Thesolar cell700 comprises aselective emitter structure705 similar to theselective emitter structure305A (FIG. 3) described above. Theselective emitter structure705 includes theselective emitter708. Acontact714 is formed using ion implantation using a suitable metal material. Thecontact714 can be formed using ion beam epitaxy or any well known metal deposition technique as described above. In an alternative embodiment, thesolar cell700 can include an anti-reflective coating (ARC) or ARC film (not shown) formed over the exposedsurface707 of thehomogeneous layer704. Thus, the charge carriers are advantageously coupled to thecontact714 of thesolar cell700.
• FIG. 7A illustrates asolar cell700A according to still another embodiment of the present invention. Aselective emitter708A can be significantly wider than thecontact714 as shown inFIG. 7A. Theselective emitter708A advantageously reduces the potential of electrical leakage from thecontact714 to other areas of thesolar cell700A. The width of theselective emitter708A can be increased by adjusting the dimensions of the ion beam D described above (FIG. 3). Further, the width of theselective emitter708A can be increased by adjusting the dimensions of thecontact mask106 or thehard mask201 described above inFIG. 1 andFIG. 2, respectively.
• Turning toFIG. 8, with reference toFIG. 1 toFIG. 7A, a process flow diagram800 is shown for a method of forming asolar cell device600 in accordance with an embodiment of the invention. The method begins at thestep810. Asilicon substrate101 is provided that is pre-doped with adopant102. In an exemplary embodiment, thedopant102 comprises a p-type dopant. At thestep820, an implantation system is used for the formation of ahomogeneous layer104. Thehomogeneous layer104 comprises a high resistivity region. An ion beam A is used for the implantation of thehomogeneous layer104. The ion beam A implants thehomogeneous layer104 in a blanket fashion in thepre-doped material102. In implanting thehomogeneous layer104, either a spot beam or wide plasma beam is used to provide full coverage across thesilicon substrate101. A productivity of the implantation system comprises approximately 1000 or more wafers per hour. Thehomogeneous layer104 can have a resistivity in the range of 80 to 160 Ohms/square. In an exemplary embodiment, the resistivity of thehomogeneous layer104 comprises approximately 100 Ohms/square. An anneal step can be performed. Alternatively, the anneal step can be eliminated.
• At thestep830, a heavily doped or selective emitter108 (FIG. 1) is implanted within the lightly dopedhomogeneous layer104. Theselective emitter108 is implanted in predetermined locations on thesilicon substrate101. In an exemplary embodiment, acontact mask106 is used to facilitate the implantation of theselective emitter108 using an ion implantation beam A in a blanketing fashion. In an alternative embodiment, the selective emitter208 (FIG. 2) is implanted using ahard mask206 and a shaped ion implantation beam C. In still another embodiment, the selective emitter308 (FIG. 3) is implanted using the shaped ion implantation beam D in a targeted fashion. A registration mark can be used for alignment of the shaped ion implantation beam D during the implantation process of theselective emitter308. The implantedselective emitter308 can be approximately 200 microns wide. Alternately, theselective emitter308 can be formed approximately 50 microns wide. A distance or pitch311 between eachselective emitter308 can be in the range of approximately 1 mm to 3 mm. Theselective emitter308 can have a resistivity in the range of 10 to 40 Ohms/square. In an exemplary embodiment, the resistivity of theselective emitter308 comprises approximately 25 Ohms/square. An anneal step can be performed. Alternatively, the anneal step can be eliminated.
• At thestep840, the seed layer312 (FIG. 4) is formed according to an embodiment of the present invention. Acontact mask310 is formed on the surface of theselective emitter structure305. In one embodiment, a lithography or contact printing process can be used to form thecontact mask310. An ion beam E is used to implant theseed layer312 over theselective emitter308. The ion beam E can comprise a relatively high dose of metal. The ion beam E can comprise a shaped ion beam similarly as those described above. Theseed layer312 can comprise a silicide layer. Theseed layer312 can comprise various metal implantations like, Ni, Ta, Ti, W or Cu. In an exemplary embodiment, theseed layer312 is implanted to comprise a width that is slightly smaller than the width of theselective emitter308. The slightly smaller width of theseed layer312 allows the lessening of contact leakage and allows the formation of a Schottky diode.
• At thestep850, a contact314 (FIG. 5) is formed according to an embodiment of the present invention. Thecontact314 is formed using ion implantation using a suitable metal material. Thecontact314 can be formed using ion beam implantation similarly as described above. A dopant concentration or dopant rate similar to plasma doping can be used in forming thecontact314. Alternatively, a beamline implantation system can be used in forming thecontact314. In still another embodiment, thecontact314 can be formed using high dose rate systems such as molecular beam epitaxy, molecular beam implantation or plasma ion implantation systems. Subsequent to implantation of thecontact314, an additional implantation step of a much higher implantation concentration of similar or matched work function of thecontact314 can be used to further form thecontact314. Alternatively, a subsequent deposition step can be used on thecontact314. In still another embodiment, a subsequent ink jet spray step can be used in further forming thecontact314.
• An annealing step heats thesilicon substrate301 to a temperature near but well below melting and restores any damage to the crystal structure of thesilicon substrate301 caused by the ion implantation and contact formation. Also, such annealing will cause activation of dopant atoms. A temperature and time of such annealing and activation can be as low as 400-500 degrees Celsius, which is a sufficient temperature to eliminate any di-vacancies (missing atoms of a lattice structure of the silicon substrate301) and to provide enough activation of the dopant atoms. The annealing step can comprise furnace annealing. Alternatively, a laser annealing or flash lamp annealing can be used in place of the furnace annealing. The annealing step does not adversely affect subsequent process steps described below. In an exemplary embodiment, only a final anneal step is performed instead of using multiple anneal steps after each implantation as describe above.
• A completed solar cell600 (FIG. 6) according to themethod800 is provided. Thesolar cell600 includes an anti-reflective coating (ARC) orARC film318 formed over the exposedsurface307 of thesilicon substrate301. TheARC film318 can be used for passivation of thehomogeneous layer304. TheARC film318 also acts as an anti-reflective film to increase the incidence of light trapped within thesolar cell600. Thus, theARC film318 can improve the efficiency of thesolar cell600. Thesolar cell600 comprises a highly efficient light conversion efficiency in between the gridlines orcontacts314. Thesolar cell600 also provides a highly conductiveselective emitter308 underneath the contacts and thus provide efficiency gains in the order of 1 to 2 absolute percentage points over solar cells absent of theselective emitter308 described herein. Themethod800 ends at thestep860.
• While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.

Claims (45)

1. A solar cell device comprising:

a silicon substrate including a preexisting dopant included therein;

a homogeneous lightly doped region formed on a surface of the silicon substrate over the preexisting dopant, thereby forming a junction between the preexisting dopant and the lightly doped region;

a heavily doped selectively implanted region on the surface of the silicon substrate within the lightly doped region;

a seed layer formed over the heavily doped region; and

a metal contact formed over the seed layer.

2. The device ofclaim 1, wherein the homogenous lightly doped region is uniformly implanted.

3. The device ofclaim 1, further comprising an anti-reflective coating on top of the lightly doped region.

4. The device ofclaim 1, wherein the homogeneous lightly doped region comprises a resistivity in a range of 80 to 160 Ohms/square.

5. The device ofclaim 4, wherein the homogeneous lightly doped region comprises a resistivity approximately 100 Ohms/square.

6. The device ofclaim 1, wherein the heavily doped region comprises a resistivity in a range of 10 to 40 Ohms/square.

7. The device ofclaim 6, wherein the heavily doped region comprises a resistivity approximately 25 Ohms/square.

8. The device ofclaim 1, wherein the junction is formed a predetermined distance from the surface of the silicon substrate.

9. The device ofclaim 1, wherein the seed layer comprises a silicide.

10. The device ofclaim 1, wherein the seed layer is formed by implanting a material from the group consisting of one or more of Ni, Ta, Ti, W or Cu.

11. The device ofclaim 1, wherein the heavily doped regions each comprise a width on the silicon substrate a distance in the range 50 to 200 microns.

12. The device ofclaim 1, wherein the heavily doped regions are laterally spaced on the silicon substrate a distance in the range 1 to 3 mm from each other.

13. The device ofclaim 1, wherein the silicon substrate includes fiducial markers configured for aligning the placement of the heavily doped regions during an ion implantation process.

14. A method of forming a solar cell device comprising the steps of:

providing a silicon substrate including a preexisting dopant included therein;

using an ion implantation process to form a homogeneous lightly doped region on a surface of the silicon substrate over the preexisting dopant, thereby forming a junction between the preexisting dopant and the lightly doped region;

using a selective ion implantation process to form a heavily doped region implanted on the surface of the silicon substrate within the lightly doped region, the heavily doped region being implanted at predetermined locations on the silicon substrate surface;

using the selective ion implantation process to form a seed layer over the heavily doped region; and

using the selective ion implantation process to form a metal contact over the seed layer.

15. The method ofclaim 14, further comprising using the selective ion implantation process to form an anti-reflective coating.

16. The method ofclaim 14, wherein the heavily doped region is implanted at predetermined locations on the silicon substrate surface using a physical mask, the physical mask having openings aligned with the predetermined locations.

17. The method ofclaim 16, wherein the physical mask is formed on the surface of the silicon substrate.

18. The method ofclaim 16, wherein the physical mask is positioned a predetermined distance above the surface of the silicon substrate during the selective ion implantation process to form the heavily doped region.

19. The method ofclaim 14, wherein the selective ion implantation process uses a shaped ion beam that is aligned with the predetermined locations to form the heavily doped region.

20. The method ofclaim 14, wherein the homogeneous lightly doped region comprises a resistivity in a range of 80 to 160 Ohms/square.

21. The method ofclaim 20, wherein the homogeneous lightly doped region comprises a resistivity approximately 100 Ohms/square.

22. The method ofclaim 14, wherein the heavily doped region comprises a resistivity in a range of 10 to 40 Ohms/square.

23. The method ofclaim 22, wherein the heavily doped region comprises a resistivity approximately 25 Ohms/square.

24. The method ofclaim 14, wherein the junction is formed a predetermined distance from the surface of the silicon substrate.

25. The method ofclaim 14, wherein the seed layer comprises a silicide.

26. The method ofclaim 14, wherein the seed layer comprises a layer of a material, wherein the material is Ni, Ta, Ti, W or Cu.

27. The method ofclaim 14, wherein the heavily doped regions each comprise a width on the silicon substrate a distance in the range 50 to 200 microns.

28. The method ofclaim 14, wherein the heavily doped regions are laterally spaced on the silicon substrate a distance in the range 1 to 3 mm from each other.

29. The method ofclaim 14, wherein the silicon substrate includes fiducial markers configured for aligning the placement of the heavily doped regions during the selective ion implantation process.

30. The method ofclaim 14, further comprising using an annealing process on the silicon substrate having the homogeneous lightly doped region.

31. The method ofclaim 14, further comprising using an annealing process on the silicon substrate after forming the metal contact.

32. A solar cell device comprising:

a silicon substrate including a preexisting dopant included therein;

a homogeneous lightly doped region formed on a surface of the silicon substrate over the preexisting dopant, thereby forming a junction between the preexisting dopant and the lightly doped region;

a heavily doped region selectively implanted on the surface of the silicon substrate within the lightly doped region, the heavily doped region being as a function of distance from the surface of the silicon substrate; and

a metal contact formed over the heavily doped region.

33. The device ofclaim 32, further comprising a seed layer formed over the heavily doped region and beneath the metal contact.

34. The device ofclaim 32, further comprising an anti-reflective coating.

35. The device ofclaim 32, wherein the homogeneous lightly doped region comprises a resistivity in a range of 80 to 160 Ohms/square.

36. The device ofclaim 35, wherein the homogeneous lightly doped region comprises a resistivity approximately 100 Ohms/square.

37. The device ofclaim 32, wherein the heavily doped region comprises a resistivity in a range of 10 to 40 Ohms/square.

38. The device ofclaim 37, wherein the heavily doped region comprises a resistivity approximately 25 Ohms/square.

39. The device ofclaim 32, wherein the junction is formed a predetermined distance from the surface of the silicon substrate.

40. The device ofclaim 32, wherein the lateral grade of the heavily doped region comprises a parabolic shape.

41. The device ofclaim 33, wherein the seed layer comprises a silicide.

42. The device ofclaim 33, wherein the seed layer comprises a layer of a material, wherein the material is Ni, Ta, Ti, W or Cu.

43. The device ofclaim 32, wherein the heavily doped regions each comprise a width on the silicon substrate a distance in the range 50 to 200 microns.

44. The device ofclaim 32, wherein the heavily doped regions are laterally spaced on the silicon substrate a distance in the range 1 to 3 mm from each other.

45. The device ofclaim 32, wherein the silicon substrate includes fiducial markers configured for aligning the placement of the heavily doped regions during an ion implantation process.

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