US20090296715A1 - Method and system for programmable data dependant network routing - Google Patents

Abstract

A method and system for routing fibre channel frames using a fibre channel switch element is provided. The switch element includes, a look up table that is indexed by domain, area, a virtual storage area number and/or AL_PA values of frames entering the fibre channel switch element; and logic for generating a column select signal that is used to select a column from the look up table for frame routing information The switch element also includes logic for validating a frame route by performing word depth match. A register is used to load look up table entries and column entries are selected based on the column select signal. The method includes, indexing a look up table with plural fibre channel frame header values; selecting a table value for routing a fibre channel frame based on a column select signal; and routing the frame if a route is valid.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application claims priority under 35 U.S.C.§ 119(e)(1) to the following provisional patent applications:
• Filed on Sep. 19, 2003, Ser. No. 60/503,812, entitled “Method and System for Fibre Channel Switches”;
• Filed on Jan. 21, 2004, Ser. No. 60/537,933 entitled “Method And System For Routing And Filtering Network Data Packets In Fibre Channel Systems”;
• Filed on Jul. 21, 2003, Ser. No. 60/488,757, entitled “Method and System for Selecting Virtual Lanes in Fibre Channel Switches”;
• Filed on Dec. 29, 2003, Ser. No. 60/532,965, entitled “Programmable Pseudo Virtual Lanes for Fibre Channel Systems”;
• Filed on Sep. 19, 2003, Ser. No. 60/504,038, entitled” Method and System for Reducing Latency and Congestion in Fibre Channel Switches;
• Filed on Aug. 14, 2003, Ser. No. 60/495,212, entitled “Method and System for Detecting Congestion and Over Subscription in a Fibre channel Network”;
• Filed on Aug. 14, 2003, Ser. No. 60/495,165, entitled “LUN Based Hard Zoning in Fibre Channel Switches”;
• Filed on Sep. 19, 2003, Ser. No. 60/503,809, entitled “Multi Speed Cut Through Operation in Fibre Channel Switches”;
• Filed on Sep. 23, 2003, Ser. No. 60/505,381, entitled “Method and System for Improving bandwidth and reducing Idles in Fibre Channel Switches”;
• Filed on Sep. 23, 2003, Ser. No. 60/505,195, entitled “Method and System for Keeping a Fibre Channel Arbitrated Loop Open During Frame Gaps”;
• Filed on Mar. 30, 2004, Ser. No. 60/557,613, entitled “Method and System for Congestion Control based on Optimum Bandwidth Allocation in a Fibre Channel Switch”;
• Filed on Sep. 23, 2003, Ser. No. 60/505,075, entitled “Method and System for Programmable Data Dependent Network Routing”;
• Filed on Sep. 19, 2003, Ser. No. 60/504,950, entitled “Method and System for Power Control of Fibre Channel Switches”;
• Filed on Dec. 29, 2003, Ser. No. 60/532,967, entitled “Method and System for Buffer to Buffer Credit recovery in Fibre Channel Systems Using Virtual and/or Pseudo Virtual Lane”;
• Filed on Dec. 29, 2003, Ser. No. 60/532,966, entitled “Method And System For Using Extended Fabric Features With Fibre Channel Switch Elements”;
• Filed on Mar. 4, 2004, Ser. No. 60/550,250, entitled “Method And System for Programmable Data Dependent Network Routing”;
• Filed on May 7, 2004, Ser. No. 60/569,436, entitled “Method And System For Congestion Control In A Fibre Channel Switch”;
• Filed on May 18, 2004, Ser. No. 60/572,197, entitled “Method and System for Configuring Fibre Channel Ports” and
• Filed on Dec. 29, 2003, Ser. No. 60/532,963 entitled “Method and System for Managing Traffic in Fibre Channel Switches”.
• The disclosure of the foregoing applications is incorporated herein by reference in their entirety.
BACKGROUND
• 1. Field of the Invention
• The present invention relates to network systems, and more particularly, to programmable routing.
• 2. Background of the Invention
• Fibre channel is a set of American National Standard Institute (ANSI) standards which provide a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre channel provides an input/output interface to meet the requirements of both channel and network users.
• Fibre channel supports three different topologies: point-to-point, arbitrated loop and fibre channel fabric. The point-to-point topology attaches two devices directly. The arbitrated loop topology attaches devices in a loop. The fibre channel fabric topology attaches host systems directly to a fabric, which are then connected to multiple devices. The fibre channel fabric topology allows several media types to be interconnected.
• Fibre channel is a closed system that relies on multiple ports to exchange information on attributes and characteristics to determine if the ports can operate together. If the ports can work together, they define the criteria under which they communicate.
• In fibre channel, a path is established between two nodes where the path's primary task is to transport data from one point to another at high speed with low latency, performing only simple error detection in hardware.
• Fibre channel fabric devices include a node port or “N_Port” that manages fabric connections. The N_port establishes a connection to a fabric element (e.g., a switch) having a fabric port or F_port. Fabric elements include the intelligence to handle routing, error detection, recovery, and similar management functions.
• A fibre channel switch is a multi-port device where each port manages a simple point-to-point connection between itself and its attached system. Each port can be attached to a server, peripheral, I/O subsystem, bridge, hub, router, or even another switch. A switch receives messages from one port and automatically routes it to another port. Multiple calls or data transfers happen concurrently through the multi-port fibre channel switch.
• Fibre channel switches use memory buffers to hold frames received and sent across a network. Associated with these buffers are credits, which are the number of frames that a buffer can hold per fabric port.
• Typically, fibre channel switches route frames to other switches based on frame destination address (D_ID), using the lower 8 bits of the D_ID. Usually for a receiving port and destination switch only one route IS used. This can result in inefficient routing in modern fabrics because sometimes load balancing is needed. In addition, a preferred route may be useful for certain ports sending high priority data. Conventional routing techniques do not provide load balancing and preferred routing using D_ID fields.
• Therefore, what is required is a system that is flexible and versatile that can perform intelligent routing based on a fabric needs.
SUMMARY OF THE PRESENT INVENTION
• A method for routing fibre channel frames using a fibre channel switch element is provided. The method includes, indexing a look up table with plural fibre channel frame header values; selecting a table value for routing a fibre channel frame based on a column select signal; and routing the frame if a route is valid. A fibre channel domain, area, a virtual storage area number and/or AL_PA values are used to index table rows. A valid route is determined by matching a correct word depth with a frame word depth. A frame's D_ID, S_ID, OX_ID, or any other bit is used to select a column for frame routing information.
• In yet another aspect of the present invention, a fibre channel switch element for routing fibre channel frames is provided. The switch element includes, a look up table that is indexed by domain, area, a virtual storage area number and/or AL_PA values of frames entering the fibre channel switch element; and
• logic for generating a column select signal that is used to select a column from the look up table to route fibre channel frames.
• The switch element also includes logic for validating a frame route by performing word depth match. A register is used to load look up table entries and column entries are selected based on the column select signal.
• This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:
• FIG. 1A shows an example of a Fibre Channel network system;
• FIG. 1B shows an example of a Fibre Channel switch element, according to one aspect of the present invention;
• FIG. 1C shows a block diagram of a 20-channel switch chassis, according to one aspect of the present invention;
• FIG. 1D shows a block diagram of a Fibre Channel switch element with sixteen GL_Ports and four 10G ports, according to one aspect of the present invention;
• FIGS.1E-1/1E-2 (jointly referred to asFIG. 1E) show another block diagram of a Fibre Channel switch element with sixteen GL_Ports and four 10G ports, according to one aspect of the present invention;
• FIG. 2 shows a block diagram of a look up table used for routing frames, according to one aspect of the present invention;
• FIGS.3A/3B (jointly referred to asFIG. 3) show a block diagram of a GL_Port, according to one aspect of the present invention;
• FIGS.4A/4B (jointly referred to asFIG. 3) show a block diagram of XG_Port (10G) port, according to one aspect of the present invention;
• FIG. 5 shows a system for routing frames, according to one aspect of the present invention;
• FIG. 6 shows a flow diagram of executable steps for routing frame, according to one aspect of the present invention; and
• FIGS. 7A and 7B show examples of applying the routing techniques, according to one aspect of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTSDefinitions
• The following definitions are provided as they are typically (but not exclusively) used in the fibre channel environment, implementing the various adaptive aspects of the present invention.
• “D_ID”: A 24-bit field in the Fibre Channel Frame header that contains the destination address for a frame.
• “Domain”: Bits16-23 of a Fibre Channel Address, that usually corresponds to a switch.
• “E-Port”: A fabric expansion port that attaches to another Interconnect port to create an Inter-Switch Link.
• “F_Port”: A port to which non-loop N_Ports are attached to a fabric and does not include FL_ports.
• “Fibre channel ANSI Standard”: The standard (incorporated herein by reference in its entirety) describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IP, ATM and others.
• “FC-1”: Fibre channel transmission protocol, which includes serial encoding, decoding and error control.
• “FC-2”: Fibre channel signaling protocol that includes frame structure and byte sequences.
• “FC-3”: Defines a set of fibre channel services that are common across plural ports of a node.
• “FC-4”: Provides mapping between lower levels of fibre channel, IPI and SCSI command sets, HIPPI data framing, IP and other upper level protocols.
• “Fabric”: The structure or organization of a group of switches, target and host devices (NL_Port, N_ports etc.).
• “Fabric Topology”: This is a topology where a device is directly attached to a fibre channel fabric that uses destination identifiers embedded in frame headers to route frames through a fibre channel fabric to a desired destination.
• Port: A general reference to N. Sub.—Port or F.Sub.—Port.
• “L_Port”: A port that contains Arbitrated Loop functions associated with the Arbitrated Loop topology.
• “N-Port”: A direct fabric attached port.
• “NL_Port”: A L_Port that can perform the function of a N_Port.
• “S_ID”: This is a 24-bit field in the Fibre Channel frame header that contains the source address for a frame.
• Fibre Channel System:
• To facilitate an understanding of the preferred embodiment, the general architecture and operation of a fibre channel system will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture of the fibre channel system.
• FIG. 1A is a block diagram of afibre channel system100 implementing the methods and systems in accordance with the adaptive aspects of the present invention.System100 includes plural devices that are interconnected. Each device includes one or more ports, classified as node ports (N_Ports), fabric ports (F_Ports), and expansion ports (E_Ports). Node ports may be located in a node device,e.g. server103,disk array105 andstorage device104. Fabric ports are located in fabric devices such asswitch101 and102. Arbitratedloop106 may be operationally coupled to switch101 using arbitrated loop ports (FL_Ports).
• The devices ofFIG. 1A are operationally coupled via “links” or “paths”. A path may be established between two N_ports, e.g. betweenserver103 andstorage104. A packet-switched path may be established using multiple links, e.g. an N-Port inserver103 may establish a path withdisk array105 throughswitch102.
• Fabric Switch Element
• FIG. 1B is a block diagram of a 20-port ASIC fabric element according to one aspect of the present invention.FIG. 1B provides the general architecture of a 20-channel switch chassis using the 20-port fabric element. Fabric element includesASIC20 with non-blocking fibre channel class2 (connectionless, acknowledged) and class3 (connectionless, unacknowledged) service between any ports. It is noteworthy thatASIC20 may also be designed for class1 (connection-oriented) service, within the scope and operation of the present invention as described herein.
• The fabric element of the present invention is presently implemented as a single CMOS ASIC, and for this reason the term “fabric element” and ASIC are used interchangeably to refer to the preferred embodiments in this specification. AlthoughFIG. 1B shows 20 ports, the present invention is not limited to any particular number of ports.
• ASIC20 has 20 ports numbered inFIG. 1B as GL0 through GL19. These ports are generic to common Fibre Channel port types, for example, F_Port, FL_Port and E-Port. In other words, depending upon what it is attached to, each GL port can function as any type of port. Also, the GL port may function as a special port useful in fabric element linking, as described below.
• For illustration purposes only, all GL ports are drawn on the same side ofASIC20 inFIG. 1B. However, the ports may be located on both sides ofASIC20 as shown in other figures. This does not imply any difference in port or ASIC design. Actual physical layout of the ports will depend on the physical layout of the ASIC.
• Each port GL0-GL19 has transmit and receive connections to switchcrossbar50. One connection is through receivebuffer52, which functions to receive and temporarily hold a frame during a routing operation. The other connection is through a transmitbuffer54.
• Switch crossbar50 includes a number of switch crossbars for handling specific types of data and data flow control information. For illustration purposes only,switch crossbar50 is shown as a single crossbar.Switch crossbar50 is a connectionless crossbar (packet switch) of known conventional design, sized to connect 21×21 paths. This is to accommodate 20 GL ports plus a port for connection to a fabric controller, which may be external toASIC20.
• In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/out processor (“IOP”).IOP66 is shown inFIG. 1C as a part of a switch chassis utilizing one or more ofASIC20. As seen inFIG. 1B, bi-directional connection toIOP66 is routed throughport67, which connects internally to a control bus60. Transmit buffer56, receivebuffer58, control register62 and Status register64 connect to bus60. Transmit buffer56 and receivebuffer58 connect the internalconnectionless switch crossbar50 toIOP66 so that it can source or sink frames.
• Control register62 receives and holds control information fromIOP66, so thatIOP66 can change characteristics or operating configuration ofASIC20 by placing certain control words inregister62.IOP66 can read status ofASIC20 by monitoring various codes that are placed instatus register64 by monitoring circuits (not shown).
• FIG. 1C shows a 20-channel switch chassisS2 using ASIC20 andIOP66. S2 will also include other elements, for example, a power supply (not shown). The 20 GL ports correspond to channel C0-C19. Each GL port has a serial/deserializer (SERDES) designated as S0-S19. Ideally, the SERDES functions are implemented onASIC20 for efficiency, but may alternatively be external to each GL port.
• Each GL port has an optical-electric converter, designated as OE0-OE19 connected with its SERDES through serial lines, for providing fibre optic input/output connections, as is well known in the high performance switch design. The converters connect to switch channels C0-C19. It is noteworthy that the ports can connect through copper paths or other means instead of optical-electric converters.
• FIG. 1D shows a block diagram ofASIC20 with sixteen GL ports and four 10G (Gigabyte) port control modules designated as XG0-XG3 for four 10G ports designated as XGP0-XGP3.ASIC20 include acontrol port62A that is coupled toIOP66 through aPCI connection66A.
• FIG.1E-1/1E-2 (jointly referred to asFIG. 1E) show yet another block diagram ofASIC20 with sixteen GL and four XG port control modules. Each GL port control module has a Receive port (RPORT)69 with a receive buffer (RBUF)69A and a transmitport70 with a transmit buffer (TBUF)70A, as described below in detail. GL and XG port control modules are coupled to physical media devices (“PMD”)76 and75 respectively.
• Control port module62A includescontrol buffers62B and62D for transmit & receive sides, respectively.Module62A also includes aPCI interface module62C that allows interface withIOP66 via aPCI bus66A.
• XG_Port (for example74B) includesRPORT72 withRBUF71 similar to RPORT69 andRBUF69A and a TBUF and TPORT similar toTBUF70A andTPORT70.Protocol module73 interfaces with SERDES to handle protocol based functionality.
• GL Port:
• FIGS. 3A-3B (referred to asFIG. 3) show a detailed block diagram of a GL port as used inASIC20.GL port300 is shown in three segments, namely, receive segment (RPORT)310, transmit segment (TPORT)312 andcommon segment311.
• Receive Segment of GL Port:
• Frames enter throughlink301 andSERDES302 converts data into 10-bit parallel data to fibre channel characters, which are then sent to receive pipe (“Rpipe” may also be referenced asRpipe1 orRpipe2,303A via a de-multiplexer (DEMUX)303.Rpipe303A includes,parity module305 anddecoder304.Decoder304 decodes10B data to8B andparity module305 adds a parity bit.Rpipe303A also performs various Fibre Channel standard functions such as detecting a start of frame (SOF), end-of frame (EOF), Idles, R_RDYs (fibre channel standard primitive) and the like, which are not described since they are standard functions.
• Rpipe303A connects to smoothing FIFO (SMF)module306 that performs smoothing functions to accommodate clock frequency variations between remote transmitting and local receiving devices.
• Frames received byRPORT310 are stored in receive buffer (RBUF)69A, (except for certain Fibre Channel Arbitrated Loop (AL) frames).Path309 shows the frame entry path, and allframes entering path309 are written toRBUF69A as opposed to theAL path308.
• Cyclic redundancy code (CRC)module313 further processes frames that enterGL port300 by checking CRC and processing errors according to FC_PH rules. The frames are subsequently passed toRBUF69A where they are steered to an appropriate output link.RBUF69A is a link receive buffer and can hold multiple frames.
• Reading from and writing toRBUF69A are controlled by RBUF read control logic (“RRD”)319 and RBUF write control logic (“RWT”)307, respectively.RWT307 specifies whichempty RBUF69A slot will be written into when a frame arrives through the data link via multiplexer (“Mux”)313B, CRC generatemodule313A and inEF module314. EF (external proprietary format)module314 encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel8B codes.Mux313B receives input fromRx Spoof module314A, which encodes frames to a proprietary format (if enabled)RWT307 controlsRBUF69A write addresses and provides the slot number to tag writer (“TWT”)317.
• RRD319 processes frame transfer requests fromRBUF69A. Frames may be read out in any order and multiple destinations may get copies of the frames.
• Steering state machine (SSM)316 receives frames and determines the destination for forwarding the frame.SSM316 produces a destination mask, where there is one bit for each destination. Any bit set to a certain value, for example,1, specifies a legal destination, and there can be multiple bits set, if there are multiple destinations for the same frame (multicast or broadcast).
• SSM316 makes this determination using information fromalias cache315, steering registers316A, control register326 values and frame contents.IOP66 writes all tables so that correct exit path is selected for the intended destination port addresses.
• The destination mask fromSSM316 is sent toTWT317 and a RBUF tag register (RTAG)318.TWT317 writes tags to all destinations specified in the destination mask fromSSM316. Each tag identifies its corresponding frame by containing anRBUF69A slot number where the frame resides, and an indication that the tag is valid.
• Each slot inRBUF69A has an associated set of tags, which are used to control the availability of the slot. The primary tags are a copy of the destination mask generated bySSM316. As each destination receives a copy of the frame, the destination mask inRTAG318 is cleared. When all the mask bits are cleared, it indicates that all destinations have received a copy of the frame and that the corresponding frame slot inRBUF69A is empty and available for a new frame.
• RTAG318 also has frame content information that is passed to a requesting destination to pre-condition the destination for the frame transfer. These tags are transferred to the destination via a read multiplexer (RMUX) (not shown).
• Transmit Segment of GL Port:
• Transmit segment (“TPORT”)312 performs various transmit functions. Transmit tag register (TTAG)330 provides a list of all frames that are to be transmitted.Tag Writer317 orcommon segment311write TTAG330 information. The frames are provided to arbitration module (“transmit arbiter” (“TARB”))331, which is then free to choose which source to process and which frame from that source to be processed next.
• TTAG330 includes a collection of buffers (for example, buffers based on a first-in first out (“FIFO”) scheme) for each frame source.TTAG330 writes a tag for a source andTARB331 then reads the tag. For any given source, there are as many entries inTTAG330 as there are credits inRBUF69A.
• TARB331 is activated anytime there are one or more valid frame tags inTTAG330.TARB331 preconditions its controls for a frame and then waits for the frame to be written intoTBUF70A. After the transfer is complete,TARB331 may request another frame from the same source or choose to service another source.
• TBUF70A is the path to the link transmitter. Typically, frames don't land inTBUF70A in their entirety. Mostly, frames simply pass throughTBUF70A to reach output pins, if there is a clear path.
• Switch Mux332 is also provided to receive output fromcrossbar50.Switch Mux332 receives input from plural RBUFs (shown as RBUF00 to RBUF19), and input fromCPORT62A shown asCBUF1 frame/status.TARB331 determines the frame source that is selected and the selected source provides the appropriate slot number. The output fromSwitch Mux332 is sent toALUT323 for S_ID spoofing and the result is fed intoTBUF Tags333.
• TMUX (also referred to as “Tx Mux”)339 chooses which data path to connect to the transmitter. The sources are: primitive sequences specified byIOP66 via control registers326 (shown as primitive339A), and signals as specified by Transmit state machine (“TSM”)346, frames following the loop path, or steered frames exiting the fabric viaTBUF70A.
• TSM346 chooses the data to be sent to the link transmitter, and enforces all fibre Channel rules for transmission.TSM346 receives requests to transmit fromloop state machine320,TBUF70A (shown asTARB request346A) and from variousother IOP66 functions via control registers326 (shown asIBUF Request345A).TSM346 also handles all credit management functions, so that Fibre Channel connectionless frames are transmitted only when there is link credit to do so.
• Loop state machine (“LPSM”)320 controls transmit and receive functions when GL_Port is in a loop mode.LPSM320 operates to support loop functions as specified by FC-AL-2.
• IOP buffer (“IBUF”)345 providesIOP66 the means for transmitting frames for special purposes.
• Frame multiplexer (“Frame Mux” or may be referenced as “Mux”)336 chooses the frame source, while logic (TX spoof334) converts D_ID and S_ID from public to private addresses.Frame Mux336 receives input fromTx Spoof module334, TBUF tags333, andMux335 to select a frame source for transmission.
• EF (external proprietary format)module338 encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel8B codes andCRC module337 generates CRC data for the outgoing frames.
• Modules340-343 put a selected transmission source into proper format for transmission on anoutput link344.Parity340 checks for parity errors, when frames are encoded from8B to10B byencoder341, marking frames “invalid”, according to Fibre Channel rules, if there was a parity error.Phase FIFO342A receives frames from encodemodule341 and the frame is selected byMux342 and passed toSERDES343.SERDES343 converts parallel transmission data to serial before passing the data to the link media.SERDES343 may be internal or external toASIC20.
• Common Segment of CL Port:
• As discussed above,ASIC20 includecommon segment311 comprising of various modules.LPSM320 has been described above and controls the general behavior ofTPORT312 andRPORT310.
• A loop look up table (“LLUT”)322 and an address look up table (“ALUT”)323 is used for private loop proxy addressing and hard zoning managed by firmware.
• Common segment311 also includes control register326 that controls bits associated with a GL_Port,status register324 that contains status bits that can be used to trigger interrupts, and interrupt mask register325 that contains masks to determine the status bits that will generate an interrupt toIOP66.Common segment311 also includes AL control andstatus register328 and statistics register327 that provide accounting information for FC management information base (“MIB”).
• Output fromstatus register324 may be used to generate a Fp Peek function. This allows astatus register324 bit to be viewed and sent to the CPORT.
• Output fromcontrol register326, statistics register327 and register328 (as well as328A for an X_Port, shown inFIG. 4) is sent toMux329 that generates an output signal (FP Port Reg Out).
• Output from Interruptregister325 andstatus register324 is sent tologic335 to generate a port interrupt signal (FP Port Interrupt).
• BIST module321 is used for conducting embedded memory testing.
• XG Port
• FIGS. 4A-4B (referred to asFIG. 4) show a block diagram of a 10G Fibre Channel port control module (XG FPORT)400 used inASIC20. Various components ofXG FPORT400 are similar to GLport control module300 that are described above. For example,RPORT310 and310A,Common Port311 and311A, andTPORT312 and312A have common modules as shown inFIGS. 3 and 4 with similar functionality.
• RPORT310A can receive frames from links (or lanes)301A-301D and transmit frames tolanes344A-344D. Each link has a SERDES (302A-302D), a de-skew module, a decode module (303B-303E) and parity module (304A-304D). Each lane also has a smoothing FIFO (SMF)module305A-305D that performs smoothing functions to accommodate clock frequency variations. Parity errors are checked bymodule403, while CRC errors are checked bymodule404.
• RPORT310A uses a virtual lane (“VL”)cache402 that stores plural vector values that are used for virtual lane assignment. In one aspect of the present invention,VL Cache402 may have32 entries and two vectors per entry.IOP66 is able to read or writeVL cache402 entries during frame traffic.State machine401 controls credit that is received. On the transmit side,credit state machine347 controls frame transmission based on credit availability.State machine347 interfaces with credit counters328A.
• Also on the transmit side, modules340-343 are used for eachlane344A-344D, i.e., each lane can have its own module340-343.Parity module340 checks for parity errors and encodemodule341 encodes 8-bit data to 10 bit data.Mux342B sends the 10-bit data to a SMF module (“Tx SMF”)342 that handles clock variation on the transmit side.SERDES343 then sends the data out to the link.
• Programmable Data Dependent Network Routing:
• In one aspect of the present invention, a versatile routing technique/system is provided that allows selection of plural routes to a destination. The routes can be selected based on fields in the fibre channel frame header. The choice of routes can be used for load balancing or for setting up preferred routes, as described below.
• In one aspect of the present invention, a “column” steering system is used for routing frames.FIG. 2 shows a block diagram ofsystem200 that is used to route frames, according to one aspect of the present invention.
• System200 includes a look up table (“LUT”)202 (similar to LUT322) that receives Domain bits (16-23 bits) or Area bits(8-21) bits of the D_ID) values201. Domain bits are used to steer frames to a different switch, while Area bits are used to steer within a local switch. It is noteworthy that values201 may also include virtual storage area network numbers (“VSAN #”), ALPA values, or any other parameter.
• When a frame is received, Domain/Area/VSAN and/or ALPA numbers are used to indexLUT202. These values are loaded intoregister203. This is performed by firmware. Steering register load signal204 (same as511 ofFIG. 5) commands a table look up based on the frames that are passing through.
• As shown inFIG. 2, columns A-D provide four different routing options. Column select signal (or value)205 (same as511 fromFIG. 5) is used to select one of the destination routes. The columnselect value205 determines which particular column (i.e. A-D) is selected for routing frames. Aroute206 is selected based on the column viamultiplexer208.Register207 also generates avalid signal207.
• FIG. 5 shows a block diagram of asystem500 that shows how the columnselect value511 is determined.D_ID bits501 andS_ID bits502 are sent to multiplexer (MUX)510, viaMux508 and506, respectively.Ox_ID502A is also sent toMux510 viaMux508A.Mux510, as shown inFIG. 5, has 8 bits used to output columnselect signal511. It is noteworthy that the present invention is not limited to any particular type or size ofMux510 or the type of logic. The following provides a description of the 8 bits used inMux510 to generate column select signal511:
• 0-Always use column A
• 1-Always use column B p02-Always use column C
• 3-Always use column D
• 4-Use bits from the Fibre Channel header OX_ID field (502A) to select the column. The bits from the OX_ID are selected by bit0_sel503 (viaMux505 and508) and bit1_sel504 (viaMux506 and507) values.
• 5-Use bits from the Fibre Channel header S_ID field to select the column. The bits from the S_ID are selected bybit0_sel503 andbit1_sel504 values.
• 6-Decode the Fibre Channel header Type field (509) to select the column. The values used are:
• 5-(Internet Protocol) use column A
• 8-(SCSI FCP) use column B
• 88-(hex 0×58, Virtual Interface) use column C All others—use column D
• 7-Use bits from the Fibre Channel header D_ID field to select the column. The bits from D_ID are selected bybit0_sel503 andbit1_sel504 values.
• Another bit value that may be used is for VSAN_ID (virtual storage area identifier) (shown asbit8 inFIG. 5) to route the frame.
• Bit0_sel503 andbit1_sel504 values are programmable by firmware and are used to select D_ID or S_ID bits if bit values 5 or 7 are used for the columnselect value511.
• Select column value (or signal/command)511A is received fromcontrol register326. This value is again programmable and is used to set the columnselect value511 based on which a particular column value is used to route frames.
• For domain steering, the domain part of the D_ID is not used for column select bits since that part of the address is already used to address the steering table202. For area steering, D_ID is not needed for column select values because the domain is always the local switch domain, and area is used to look up steering table202.
• Select column signal511A is also sent toMux512 that maps the 8 bits ofMux510 to actual frame depth. For example, if OX_ID (bit4, from Mux510) is used for routing, then the fourth word in the frame header must be read. If D-ID is used, then the 0^thword must be read.
• Based on the columnselect value511, the selected word depth and the frame depth are matched bylogic513. If the match is correct, avalid route514 is selected and sent toSSM316.
• Frame word depth515 for every frame is sent tologic513 andlogic516. When the 0^thword of a frame is read, steering register load signal517(same asFIG. 2, signal204) is generated that commands table look up, discussed above.
• FIG. 6 is a flow diagram of process steps, for routing frames, according to one aspect of the present invention.
• In step S600, table202 is indexed. Domain/Area/VSAN and/or ALPA numbers are used to indexLUT202.
• In step S601, the indexed table values are loaded intoregister203.
• In step S602, a particular column is selected for routing. The column selection is based onselect column signal511. One of the 8 bits shown inMUX510 can be used for routing frames.
• In step S603, based on the column, a route is selected.
• In step S604, the process determines if the route is valid. This can be performed bylogic513, which makes sure that the correct word depth matches the frame word depth.
• If the route is not valid, the process goes back to step S600.
• If the route is valid, then in step S605, a port is selected for transfer.
• The following provides examples of how the present invention can be used for load balancing and/or preferred routing:
EXAMPLE 1
• FIG. 7A shows thatlink1 between switch A and B is a high-speed 10 Gigabit link.Links2,3,4, and5 are 2 Gigabit links. If all the traffic from switch A to switch C is through one of the 2 Gigabit links (i.e. links2,3,4 or5) then the 10 Gigabit link would not be able to send data faster than 2 Gigabits and hence cause congestion.
• Using the column steering methodology described above, the receive port forlink1 on switch B will allow traffic destined for switch C to be routed through all 4 of the slower links to get better performance. S_ID, D_ID, OX_ID, VSAN# or any other parameter may be used for the selecting the appropriate column.
EXAMPLE 2
• As shown inFIG. 7B, switches D and F are coupled vialinks1 and2. If ports on switch D want to send higher priority data to switch B, the lower 2 bits of the OX_ID may be reserved for the higher priority traffic. The higher priority traffic could uselink2, while all other traffic from D to F uselink1.
• If the bits0-1 of the OX_ID for high priority traffic are set to binary ‘11’, the select column and steering tables for each port on switch D would be set as follows:
• Select column=4 (bits0-1 of OX_ID)
• Steering table for Domain of switch E=
• Column A=link1
• Column B=link1
• Column C=link1
• Column D=link2
• Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.

Claims (20)

1-16. (canceled)

17. A method for routing frames via a network element having a plurality of ports, comprising:

(a) receiving a frame at a port of the network element;

(b) indexing a look up table by using one or more of (i) a domain value for routing the frame to another network element, (ii) an area value for routing the frame to a port of the network element that received the frame, (iii) a Virtual Storage Area Network identifier (VSAN#) for routing the frame within a Virtual Storage Area Network, and (iv) an Arbitrated Loop Physical Address (AL_PA) value included in a header of the frame; wherein the look up table includes a plurality of columns for storing destination information indexed by one or more of the Domain value, the Area value, the Virtual Storage Network identifier and the Arbitrated Loop Physical Address;

(c) selecting a column value from the look up table based on a column select signal generated by a hardware logic of the network element; and

(d) based on the selected column value, routing the frame if a route is valid.

18. The method ofclaim 17, wherein a valid route is determined by matching a correct word depth with a frame word depth.

19. The method ofclaim 17, wherein a frame's destination identifier field is used to select a column for routing the frame.

20. The method ofclaim 17, wherein a frame's source identifier field value is used to select a column for routing the frame.

21. The method ofclaim 17, wherein a frame's originator identification field is used to select a column for routing the frame.

22. The method ofclaim 17, wherein a frame's type field is used to select a column for routing the frame.

23. The method ofclaim 17, wherein bits other than a type field of a frame are used to select a column for routing the frame.

24. The method ofclaim 17, wherein the column select signal is generated after a plurality of fields are input to the hardware logic and one of the input is selected to generate the column select signal.

25. The method ofclaim 24 wherein the hardware logic is a multiplexer and the plurality of inputs are a destination identifier field, a source identifier field, a virtual storage area network identifier, an originator exchange identification field, a type field, and a decode frame header type field.

26. A network element for routing frames, configured to select a route from amongst a plurality of routes, the network element comprising:

at least one port for receiving and transmitting a frame;

a look up table having a plurality of columns indexed by one or more of (i) a Domain value for routing the frame to another network element, (ii) an Area value for routing the frame within the network element that received the frame, (iii) a Virtual Storage Area Network identifier (VSAN#) for routing the frame within a Virtual Storage Area Network, and (iv) an Arbitrated Loop Physical Address (AL_PA) value; and

a hardware logic that receives a plurality of inputs and based on one of the inputs, a column select signal is generated to select a value from one of the plurality of columns to route the frame, if the route based on the selected column is valid.

27. The network element ofclaim 26, wherein a frame's destination identifier is used to select a column for routing the frame.

28. The network element ofclaim 26, wherein a frame's source identifier value is used to select a column for routing the frame.

29. The network element ofclaim 26 wherein a frame's originator exchange identification field is used to select a column for routing the frame.

30. The network element ofclaim 26, wherein a register is used to load look up table entries and column entries are selected based on the column select signal.

31. The network element ofclaim 26, wherein a frame's type field is used to select a column for routing the frame.

32. The network element ofclaim 26, wherein bits other than a type field of a frame are used to select a column for routing the frame.

33. A network system, comprising:

a computing system for sending and receiving information;

at least one network element operationally coupled to the computing system for routing frames and configured to select a route from amongst a plurality of routes, where the network element includes:

at least one port for receiving and transmitting a frame having a frame header;

a look up table with a plurality of columns that is indexed by one or more of (i) a domain value for routing the frame to another network element, (ii) an area value for routing the frame to a port of the network element that received the frame, (iii) a Virtual Storage Area Network identifier (VSAN#) for routing the frame within a Virtual Storage Area Network, and (iv) an Arbitrated Loop Physical Address (AL_PA) value; and

a hardware logic that receives a plurality of inputs and based on one of the inputs generates a column select signal, wherein the column select signal is used to select a column from the one of the plurality of columns of the look up table to route frames, if a route based on the selected column is valid.

34. The system ofclaim 33, wherein a register is used to load look up table entries and column entries are selected based on the column select signal.

35. The system ofclaim 33, wherein the hardware logic is a multiplexer and the plurality of inputs are a destination identifier field, a source identifier field, a virtual storage area network identifier, an originator exchange identification field, a type field, and a decode frame header type field.

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