US20090190386A1 - Hybrid content addressable memory - Google Patents

Abstract

A CAM device memory array having different types of memory cells is disclosed. A CAM device memory array is subdivided into at least two different portions, where each portion uses only one particular type of CAM cell, and each portion is dedicated to storing a particular type of data. In particular, at least one portion consists of binary CAM cells and the other portion consists of ternary CAM cells. The portions can be partitioned along the row, or matchline, direction or along the bitline direction. Since particular data formats only require predefined bit positions of a word of data to be ternary in value, the remaining binary bit positions can be stored in binary CAM cells. Therefore, the CAM device memory array will occupy an overall area that is less than memory arrays of the same density consisting exclusively of ternary CAM cells.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 10/809,421, filed Mar. 26, 2004, the contents of which are expressly incorporated herein by reference in their entirety.
FIELD OF THE INVENTION
• The present invention relates generally to content addressable memories. More particularly, the present invention relates to content addressable memory array architectures.
BACKGROUND OF THE INVENTION
• An associative memory system called Content Addressable Memory (CAM) has been developed to permit its memory cells to be referenced by their contents. Thus CAM has found use in lookup table implementations such as cache memory subsystems and is now rapidly finding use in networking system applications such as network address translation, pattern recognition, and data compression. CAM's most valuable feature is its ability to perform a search and compare of multiple locations as a single operation, in which search data is compared with data stored within the CAM. Typically search data is loaded onto search lines and compared with stored words in the CAM. During a search-and-compare operation, a match or mismatch signal associated with each stored word is generated on a matchline, indicating whether the search word matches a stored word or not.
• A CAM stores data in a matrix of cells, which are typically SRAM based cells. However, to provide ternary state CAMs, ie. where each CAM cell can store one of three values: a logic “0”, “1” or “don't care” result, ternary SRAM based cells require two binary SRAM cells.
• A typical CAM block diagram is shown inFIG. 1. TheCAM10 includes a matrix, orCAM memory array25, of CAM cells (not shown) arranged in rows and columns. A predetermined number of CAM cells in a row store a word of data. Anaddress decoder17 is used to select any row within theCAM array25 to allow data to be written into or read out of the selected row. Data access circuitry such as bitlines and column selection devices, are located within thearray25 to transfer data into and out of thearray25. Located withinCAM array25 for each row of CAM cells are matchline sense circuits, which are not shown, and are used during search-and-compare operations for outputting a result indicating a successful or unsuccessful match of a search word against the stored word in the row. The results for all rows are processed by thepriority encoder22 to output the address (Match Address) corresponding to the location of a matched word. The match address is stored inmatch address registers18 before being output by the matchaddress output block19. Data is written intoarray25 through the data I/O block11 and thevarious data registers15. Data is read out from thearray25 through thedata output register23 and the data I/O block11. Other components of the CAM include thecontrol circuit block12, theflag logic block13, the voltagesupply generation block14, various control andaddress registers16, and JTAGblock21.
• FIG. 2 depicts a hierarchical view of thetypical CAM array25.CAM array25 includes a matrix ofCAM cells30 and a matchlinesense circuit block26.CAM cells30 of theCAM array25 are arranged in rows and columns.CAM cells30 of a row are connected to a common matchline MLi, andCAM cells30 of a column are connected to a common pair of search lines SLjb/SLj and a common pair of bitlines BLj/BLjb, where i is an integer value between 0 and n, and j is an integer value between 0 and m. While not shown to simplify the schematic, each row ofCAM cells30 is connected to a wordline, and those of skill in the art will understand that wordlines are required to ensure operability of theCAM cells30. Located adjacent to theCAM array25 for each row is matchlinesense circuit block26. Matchlinesense circuit block26 includes onematchline sense circuit27 connected to a respective matchline MLi, and is used during search-and-compare operations for outputting match signals ML_OUT0-ML_OUTn which indicate a successful or unsuccessful match of a search word against the stored word. Although not shown in the simplified schematic ofFIG. 2, thematchline sense circuits27 also receive control signals to control their operation, and a person skilled in the art would understand that such control signals to be necessary for their proper operation of the circuit. While the bitlines are connected to well known bitline circuits, the searchlines in aCAM device10 are connected to searchline drivers (not shown), such as those disclosed in commonly owned U.S. Pat. No. 6,522,596.
• FIGS. 3 through 5 show circuit schematics of the types ofCAM cells30 that can be used in theCAM array25 ofFIG. 2.FIG. 3 shows a typical ternary data SRAM type CAM cell,FIG. 4 shows an alternate ternary SRAM type CAM cell, andFIG. 5 shows a binary SRAM type CAM cell.
• FIG. 3 shows a typical ternary SRAM type CAM cell, referred to as a ternary SCAM cell from this point forward.SCAM cell40 includes two well-known six-transistor SRAM cells42 and44, and a pair of search and compare stacks. Since bothSRAM cells42 and44 are identical to each other, the following description ofSRAM cell42 will apply toSRAM cell44.SRAM cell42 includes afirst access transistor46 and asecond access transistor48 for coupling bitlines BLP and BLPb respectively, to the complementary nodes of cross coupledinverters50 and52 in response to an active WL signal. The first search and compare stack associated withSCAM cell42 includes comparetransistor54 andsearch transistor56 serially connected between the matchline ML and the tail-line TL. The gate terminal ofcompare transistor54 is connected to a node ofSRAM cell42 while the gate terminal ofsearch transistor56 is connected to searchline SLb. Tail-line TL is typically coupled to a ground, or VSS power supply. The second search and compare stack associated withSRAM cell44 includes comparetransistor58 andsearch transistor60 serially connected between the matchline ML and the tail-line TL. The gate terminal ofcompare transistor58 is connected to a node ofSRAM cell44 while the gate terminal ofsearch transistor60 is connected to searchline SL.
• SCAM cell40 includes a total of 16 transistors and stores encoded ternary data. Together, the two SRAM cells ofSCAM cell40 can store a ternary value representing logic “1”, logic “0”, or “don't care”. Table 1 below shows an example of the ternary data encoding. Persons of skill in the art should understand thatSCAM cell40 can be implemented with n-channel transistors as shown inFIG. 3, and/or p-channel transistors.

• TABLE 1
  	SRAM	SRAM
  Ternary Value	Cell	42	Cell 44
  0	0	1
  1	1	0
  “Don't Care”	0	0

• FIG. 4 shows an alternate type of ternary SCAM cell similar to the one shown inFIG. 3. The presently shown ternary SCAM cell stores one bit of data and one mask bit of data to block the search and compare results from affecting the matchline ML.SCAM cell70 includes the previously describedSRAM cells42 and44, and the search and compare stacks consisting oftransistors54,56,58 and60. However, thisSCAM cell70 includes anadditional mask transistor72, and the gate terminal ofcompare transistor58 is now connected to a storage node ofSRAM cell42 that is complementary to the storage node connected to the gate ofcompare transistor54.Mask transistor72 is connected between the source terminals ofsearch transistors56 and60 and the tail line TL, and has its gate terminal connected to a storage node ofSRAM cell44. Accordingly,SCAM cell70 consists of 17 transistors, implemented in n-channel and/or p-channel technology.SCAM cell70 essentially functions as a searchable binary CAM cell with masking capability. More specifically, the comparison circuit is enabled if the mask bit stores a logic “0” and the comparison circuit is disabled if the mask bit stores a logic “1”.
• In applications where the mask bit is unnecessary, or where the data to be stored is only binary in nature, a typical binary SCAM cell can be used.
• FIG. 5 is a circuit schematic of a typical binary SCAM cell.Binary SCAM cell80 uses thesame SRAM cell42 and search and compare stacks as seen in the previous ternary SCAM cell schematics, and includes a total of 10 transistors which can be implemented in n-channel and/or p-channel technology. Clearly, the absence of thesecond SRAM cell44 andmask transistor72 makesbinary SCAM cell80 smaller than previously shownternary SCAM cells40 and70.
• As previously mentioned, binary based CAM, and in particular binary SCAM, has found wide use in networking applications where data packets are transferred through the network according to the data in the header portion of the data packet. More specifically, network data packet routing and switching operations involve matching the header portion of the data packet with predetermined comparand data. While binary CAM can be used to match header data, it is limited to searching for exact matches between the comparand data and the header data having the same bit length headers. Therefore, binary CAM is not practical for use in systems that receive data packets having variable bit length headers.
• However, the additional “don't care” state provided by ternary CAM permits partial match searches to be executed as the irrelevant bit positions can be set to the “don't care” state such that no comparison to the corresponding bit of comparand data occurs. This capability is useful in modern network longest prefix matching operations, where only leading bits of the header portion are relevant for routing and switching.
• Present ternary CAM chips are available in a 9M-bit density, meaning that the chip has approximately 9 million ternary CAM cells in its memory array arranged in rows and columns. A typical data packet can include a word of 144 bits stored by 144 ternary CAM cells in a row, or multiple 144-bit words stored in consecutive rows memory cells. With ternary data storage capability in each ternary CAM cell, the CAM chip can be used as a universal device for accommodating any data packet format because any number of ternary CAM cells can be reserved for header data.
• However, it can be observed from progressive standardization of communication protocols and data packet formats that a specific number of bits of each data packet will only ever store binary data. Use of ternary CAM cells for storing only binary data is an inefficient use of silicon area because the unused storage cell of the ternary CAM cell cannot be used to store an unrelated bit of data, and use of ternary search circuits for performing binary searches unnecessarily wastes power.
• Various schemes have been proposed in which ternary CAM cells can be dynamically configurable as binary CAM cells, such that the second data bit storage location of the ternary CAM cell can be used for storing another bit of data. Accordingly, the storage density of the CAM device memory array is effectively doubled. Unfortunately, such schemes require relatively complex CAM cell configurations which will further increase the size of the ternary CAM device memory array, and circuit overhead for controlling the operating mode of the configurable memory cells.
• It is, therefore, desirable to provide a hybrid binary/ternary CAM device memory array that occupies minimal silicon area and consumes less power, while maintaining or improving CAM search and compare performance.
SUMMARY OF THE INVENTION
• It is an object of the present invention to obviate or mitigate at least one disadvantage of previous CAM device memory array architectures. In particular, it is an object of the present invention to minimize the size of the CAM device memory array that can efficiently store both binary and ternary data.
• In a first aspect, the present invention provides a hybrid content addressable memory array. The hybrid content addressable memory array includes a first memory portion having a first type of content addressable memory cells arranged in rows and columns, and a second memory portion having a second type of content addressable memory cells arranged in rows and columns, where the second type of content addressable memory cells being electrically coupled to the first type of content addressable memory cells.
• In an embodiment of the first aspect, the first memory portion and the second memory portion include matchlines, where each matchline of the first memory portion is coupled to the first type of content addressable memory cells, and each matchline of the second memory portion is coupled to the second type of content addressable memory cells. According to an aspect of the present embodiment, the first type of content addressable memory cells include ternary content addressable memory cells and the second type of content addressable memory cells include binary content addressable memory cells, and the matchlines of the first memory portion and the matchlines of the second memory portion are interleaved with each other.
• According to further embodiments of the first aspect, the first type of content addressable memory cells can include binary content addressable memory cells, the second type of content addressable memory cells can include ternary content addressable memory cells, the first and the second type of content addressable memory cells include SRAM based binary content addressable memory cells and SRAM based ternary content addressable memory cells, and at least one of the first and the second type of content addressable memory cells include configurable ternary-binary content addressable memory cells.
• According to another embodiment of the first aspect, the first type of content addressable memory cells and the second type of content addressable memory cells of a row are coupled to a logical matchline, where the logical matchline can include a segmented matchline having a first matchline segment and a second matchline segment. The first type of content addressable memory cells can be coupled to the first matchline segment and the second type of content addressable memory cells can be coupled to the second matchline segment. Alternatively, the first type of content addressable memory cells and the second type of content addressable memory cells of a column can be coupled to common searchlines.
• In a second aspect, the present invention provides a hybrid content addressable memory array having a first type of content addressable memory cells coupled to a logical matchline, and a second type of content addressable memory cells coupled to the logical matchline. The first type of content addressable memory cells can include binary content addressable memory cells and the second type of content addressable memory cells can include ternary content addressable memory cells, where the content addressable memory cells can be SRAM based.
• According to an embodiment of the present aspect, the logical matchline includes a segmented matchline having at least two matchline segments, where the first type of content addressable memory cells are coupled to one of the at least two matchline segments and the second type of content addressable memory cells are coupled to the other of the at least two matchline segments.
• In a third aspect, the present invention provides a hybrid content addressable memory array having a first type of content addressable memory cells coupled to common searchlines, and a second type of content addressable memory cells coupled to the common searchlines. The first type of content addressable memory cells can include binary content addressable memory cells and the second type of content addressable memory cells can include ternary content addressable memory cells, where the content addressable memory cells can be SRAM based.
• Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
• Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
• FIG. 1 is a block diagram of a typical DRAM based CAM chip;
• FIG. 2 is a circuit schematic of the memory array ofFIG. 1;
• FIG. 3 is a circuit schematic of an SRAM based ternary CAM cell;
• FIG. 4 is a circuit schematic of an alternate SRAM based ternary CAM cell;
• FIG. 5 is a circuit schematic of an SRAM based binary CAM cell;
• FIG. 6 is a hybrid CAM device memory array architecture according to an embodiment of the present invention;
• FIG. 7 is a circuit schematic of the hybrid CAM device memory array ofFIG. 6;
• FIG. 8 is a hybrid CAM device memory array architecture according to another embodiment of the present invention; and,
• FIG. 9 is a circuit schematic of the hybrid CAM device memory array ofFIG. 8, and,
• FIG. 10 is a schematic of a DRAM based ternary CAM cell.
DETAILED DESCRIPTION
• Generally, the present invention provides a content addressable memory array architecture that optimizes storage of binary-only and ternary data without additional circuit overhead. Furthermore, the embodiments of the present invention benefit from reduced power consumption and improved performance as a result of the optimized storage scheme for binary-only and ternary data.
• As standardization of formats for network data packets develop, specific fields of the data packets can become constrained by rules of the standard. For example, header fields of data packets must not exceed a predetermined number of bits in length, where each bit position of the header field must be able to store one of three states. As previously mentioned, the three states in the CAM context include logic “1”, logic “0” and “don't care” states. Other fields of the data packets, such as the data portion, are simply restricted to binary values. As most CAM devices use only ternary CAM cells, an in particular ternary SCAM cells, significant silicon area can be saved if ternary CAM cells used only for binary storage can be replaced with smaller binary CAM cells.
• According to the embodiments of the present invention, a CAM device memory array is subdivided into at least two different portions, where each portion uses only one particular type of CAM cell, and each portion is dedicated to storing a particular type of data.
• FIG. 6 is a schematic illustrating a CAMdevice memory array100 according to a first embodiment of the present invention that stores each word of data in two different types of CAM cells. In the presently described embodiment, CAMdevice memory array100 is subdivided into a binaryCAM cell section102 and a ternaryCAM cell section104, where the CAM cells are disposed in rows and columns, where each row of CAM cells forms a word of data. Hence, each wordline and matchline is coupled to CAM cells in thebinary section102 and CAM cells in theternary section104. In this particular example,ternary section104 stores bit positions D0 to D71 of each word, andbinary section102 stores bit positions D72 to D143 of each word. However, the bit length of each section is not limited to the configuration shown inFIG. 6. Therefore, since half of the CAMdevice memory array100 consists of binary CAM cells, such as binary SCAM cells, the overall memory array size is significantly reduced over an equivalent density memory array consisting exclusively of ternary SCAM cells. Although CAMdevice memory array100 is 144 bits wide and 64K rows long, a memory array of any dimension can be partitioned into a binary section and ternary section according to the embodiment of the present invention.
• FIG. 7 is a schematic showing the details of the CAMdevice memory array100 illustrated inFIG. 6. Matchlines ML0 to MLn extend horizontally between thebinary section102 and theternary section104, and are each coupled to amatchline sense circuit106 for sensing a respective voltage level during a search and compare operation. As shown inFIG. 7, the content addressable memory cells ofbinary section102 andternary section104 are electrically coupled to each other via the common matchlines. Wordlines and tail lines are not shown to simplify the schematic, but those of skill in the art will understand that they are required for proper operation. Eachmatchline sense circuit106 provides a matchline output ML_OUT representing a match or mismatch condition of its corresponding matchline. Each matchline is coupled tobinary CAM cells90 inbinary section102 andternary CAM cells92 internary section104. It is noted thatbinary CAM cell90 can be implemented with the circuit configuration ofbinary SCAM cell80, andternary CAM cell92 can be implemented with the circuit configuration of eitherternary SCAM cells40 or70 shown inFIGS. 3 and 4 respectively. It should be apparent to those of skill in the art thatbinary CAM cells90 inbinary section102 minimizes silicon area consumption since eachbinary CAM cell90 uses fewer transistors than eachternary CAM cell92. Therefore, CAMdevice memory array100 maximizes silicon area efficiency because smaller sized binary CAM cells are used to store data that will only be binary in format. It is noted thatbinary CAM cells90 can have a layout optimized to minimize column pitch. Hence silicon area along the row direction can be further conserved.
• Advantages of the present embodiment are as follows. The reduced row length of each matchline translates into reduced capacitance thereof. Therefore, the performance of each matchline is enhanced while overall power consumption is reduced.
• While the embodiments of the present invention shown inFIGS. 6 and 7 partitions the CAM device memory array by columns, the memory array can be partitioned by rows according to an alternate embodiment of the present invention.
• FIG. 8 is a schematic illustrating a CAMdevice memory array110 according to a second embodiment of the present invention, with the memory array partitioned into different portions by rows. It is noted that for the purposes of illustrating the present embodiment, CAMdevice memory array110 has the same number of rows and columns as CAMdevice memory array100 shown inFIG. 6. In the presently described embodiment, CAMdevice memory array110 is subdivided into a ternaryCAM cell section112 and a binaryCAM cell section114, where the CAM cells are disposed in rows and columns, where each row of CAM cells forms a word of data. As shown inFIG. 8, ternaryCAM cell section112 occupies16K rows while binaryCAM cell section114 occupies48K rows. As will be shown inFIG. 9, each row includes the same type of CAM cell.
• FIG. 9 is a schematic showing the details of the CAMdevice memory array110 illustrated inFIG. 8. Matchlines ML0 and ML1 are part of theternary CAM section114, and are each coupled toternary CAM cells92 and a respectivematchline sense circuit116. Eachmatchline sense circuit116 is analogous to matchlinesense circuit106 ofFIG. 7, therefore further description of its operation is not necessary. Matchlines MLn-1 and MLn are part of thebinary CAM section112, and are each coupled tobinary CAM cells90 and a respectivematchline sense circuit116. As inFIG. 7, wordlines and tail lines are not shown to simplify the schematic, and the samebinary CAM cells90 andternary CAM cells92 can be used. It is noted that each pair of complementary searchlines and bitlines extend vertically between both thebinary CAM section112 and theternary CAM section114 such that theternary CAM cells92 andbinary CAM cells90 coupled to the same bitline and searchline form one column of CAM cells. Therefore, the content addressable memory cells ofbinary section112 andternary section114 are electrically coupled to each other via the common bitlines and searchlines. For example,ternary CAM cells92 andbinary CAM cells90 coupled to SL0band BL0 are part of the same column of CAM cells. In this particular embodiment,binary CAM cells90 have been optimized in layout to minimize its footprint along the bitline direction, hence the overall area occupied by CAMdevice memory array110 can be minimized along the bitline direction since the pitch of each row ofbinary CAM cells90 in thebinary CAM section112 can be made smaller than the pitch of each row ofternary CAM cells92 internary CAM section114. Therefore, an advantage resulting from the reduced bitline and searchline length is the reduced corresponding capacitance. Therefore, bitline and searchline drive circuit performance can be improved while reducing overall power consumption.
• While the embodiments of the present invention have shown the CAM device memory array partitioned into two memory portions, the memory array can be partitioned into any number of memory portions to suit the particular application.
• The operation of CAMdevice memory arrays100 and110 according to the embodiments of the present invention, will be analogous to the operation ofCAM array25. More specifically, once search data has been driven onto the searchlines, eachCAM cell90/92 compares its stored data against the searchline data to affect the matchline if a mismatch condition exists.
• In the embodiment of the invention shown inFIG. 9, the system may execute a search for binary data stored only inbinary section112, or for ternary data stored internary section114. Although the searchlines are coupled to both thebinary section112 andternary section114, the system will have knowledge of those physical rows in each section. More specifically, the results provided by thematchline sense circuits116 corresponding to results that are undesired can be masked out. For example, this can be done by disabling thematchline sense circuits116 that correspond to either thebinary section112 during a ternary data search, or theternary section114 during a binary data search.
• According to another embodiment of the present invention, the CAMdevice memory array100 can have segmented matchlines, where each matchline segment of the same row is coupled to different types of CAM cells. Accordingly, each matchline segment of the same row belong to the same logical matchline. Matchline segmentation is disclosed and taught in commonly owned U.S. Pat. No. 6,584,003, the contents of which are incorporated herein by reference, as a technique to reduce power consumption in a CAM device memory array. For example, a first matchline segment of a row of CAM cells can be coupled only tobinary CAM cells90, and a second matchline segment of the row of CAM cells can be coupled only toternary CAM cells92. Alternatively, each matchline segment can be coupled to groups ofbinary CAM cells90 andternary CAM cells92. Those of skill in the art will appreciate that each row can be configured to include any number of matchline segments.
• While the previous embodiments of the present invention shown inFIGS. 7 and 9 show the CAMdevice memory array100 as having two different CAM memory cell sections, additional CAM memory cell sections can be included. For example, CAMdevice memory array100 can include several CAM memory cell sections interleaved with each other, where each section can include any number of rows or columns of CAM memory cells. Hence, the CAMdevice memory array100 can be seen as including two logical CAM memory cell blocks having rows or columns, or small groups of rows or columns, interleaved with other.
• An alternate embodiment where one or more ternary rows of CAM memory cells is interleaved with one or more binary rows of CAM memory cells can be used in very wide word applications where a word spans more than one physical row of CAM memory cells. In one such an embodiment, each row of ternary CAM cells can be followed by three rows of binary CAM cells. Descriptions of wide word applications are available in commonly owned U.S. Pat. No. 6,708,250 and commonly owned U.S. patent application Ser. No. 10/357,270.
• In a further alternate embodiment of the invention shown inFIGS. 6 and 7, theternary section104 can include another section of cells, consisting of columns of configurable ternary-binary CAM cells adjacent to thebinary section102 so that the width ofternary section104 can be dynamically configurable. Alternatively, the entireternary section104 can consist of configurable ternary-binary CAM cells. Examples of configurable ternary-binary CAM cells are shown in U.S. Pat. Nos. 6,108,227 and 6,362,992. Persons of skill in the art will understand how to incorporate such cells into the embodiments of the present invention. Therefore, significant silicon area savings can be realized by employing the previously described embodiments of the present invention. Preferably, ternary CAM cell sections of the CAM device memory array include ternary SCAM cells while binary CAM cell sections include binary SCAM cells, to maximize silicon area savings.
• While binary and ternary SCAM cells are preferably used in the binary and ternary sections of the CAM device memory array, DRAM based binary and ternary CAM cells, referred to as a ternary or binary DCAM cells from this point forward, can be used instead.
• FIG. 10 shows a typicalternary DCAM cell200 as described in Canadian Patent Application No. 2,266,062, filed Mar. 31, 1999, the contents of which are incorporated herein by reference.DCAM cell200 has a comparison circuit that includes an n-channel search transistor202 connected in series with an n-channel comparetransistor204 between a matchline ML and a tail line TL. A search line SL is connected to the gate ofsearch transistor202. The storage circuit includes an n-channel access transistor206 having a gate connected to a wordline WL and connected in series withcapacitor208 between bitline BL and a cell plate voltage potential VCP. Charge storage node CELL1 is connected to the gate of comparetransistor204 to turn ontransistor204 if there is charge stored oncapacitor208 i.e. if CELL1 is logic “1”. The remaining transistors and capacitor replicatetransistors202,204,206 andcapacitor208 for the other half of the ternary data bit, and are connected to corresponding lines SLb and BLb and are provided to support ternary data storage. Further description of theternary DCAM cell200 is detailed in the aforementioned reference. It is noted that a binary DCAM version of theternary DCAM cell200 is identical toternary DCAM cell200, since complementary data states of a single bit of data are necessary for executing a binary search and compare operation. Therefore,ternary DCAM cell200 can store either binary or ternary data.
• Therefore, according to another embodiment of the present invention, CAMdevice memory arrays100 and110 can include ternary and binary DCAM cells in their binary and ternary sections respectively. More specifically,DCAM cells200 in the ternary section stores ternary data whileDCAM cells200 in the binary section stores binary data. Control logic therefore determines the particular columns ofDCAM cells200 that should have binary data or ternary data written to them. The control logic also determines the appropriate type of search, ie. binary or ternary search, to be applied to specific columns.
• The above-described embodiments of the present invention are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims (17)

1. A content addressable memory device comprising:

rows of first matchlines precharged to a voltage level corresponding to a miss condition;

ternary cells connected in parallel to each of the first matchlines;

rows of second matchlines precharged to a voltage level corresponding to a miss condition;

binary cells connected in parallel to each of the second matchlines, the binary cells being smaller in size than the ternary cells and operable simultaneously with the ternary cells; and

searchlines connected to the ternary cells of the rows of first matchlines and to the binary cells of the rows of second matchlines.

2. The content addressable memory device ofclaim 1, further including matchline sense amplifiers connected to the first matchlines and the second matchlines for detecting one of the miss condition and a match condition in response to search data on the searchlines, each matchline sense amplifier providing a match output if data stored in the ternary cells and the binary cells of each row matches the search data.

3. The content addressable memory device ofclaim 1, wherein the rows of first matchlines are interleaved with the rows of second matchlines.

4. The content addressable memory device ofclaim 1, wherein one row of the rows of first matchlines is adjacent to at least two consecutive rows of second matchlines.

5. The content addressable memory device ofclaim 1, wherein the ternary cells include static random access memory (SRAM) based ternary content addressable memory cells.

6. The content addressable memory device ofclaim 1, wherein the binary cells include static random access memory (SRAM) based binary content addressable memory cells.

7. The content addressable memory device ofclaim 1, wherein the ternary cells include dynamic random access memory (DRAM) based ternary content addressable memory cells.

8. The content addressable memory device ofclaim 1, wherein the binary cells include dynamic random access memory (DRAM) based binary content addressable memory cells.

9. A content addressable memory (CAM) device comprising:

a first matchline row prechargeable to a first voltage level corresponding to a first miss condition;

a second matchline row prechargeable to a second voltage level corresponding to a second miss condition;

a ternary CAM cell coupled to the first matchline;

a binary CAM cell coupled to the second matchline, the binary CAM cell being smaller than the ternary CAM cell and the binary CAM cell being simultaneously operable with the ternary CAM cell; and

the ternary CAM cell and the binary CAM cell being coupled to a common bitline and searchline.

10. The CAM device as claimed inclaim 9, wherein the ternary CAM cell comprises a static random access memory (SRAM) based ternary CAM cell.

11. The CAM device as claimed inclaim 9, wherein the binary CAM cell comprises a static random access memory (SRAM) based binary CAM cell.

12. The CAM device as claimed inclaim 9, wherein the ternary CAM cell comprises a dynamic random access memory (DRAM) based ternary CAM cell.

13. The CAM device as claimed inclaim 9, further comprising:

a first sense circuit coupled to the first matchline row for detecting one of the first miss condition or a first match condition on the first matchline row; and

a second sense circuit coupled to the second matchline row for detecting one of the second miss condition or a second match condition on the second matchline row.

14. The CAM device as claimed inclaim 13, wherein a result provided by the first sense circuit is maskable.

15. The CAM device as claimed inclaim 13, wherein a result provided by the second sense circuit is maskable.

16. The CAM device as claimed inclaim 9, wherein the first voltage level and the second voltage level are substantially the same.

17. The CAM device as claimed inclaim 13, wherein the first match condition and the second match condition correspond to substantially a same voltage of the first matchline and the second matchline.

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