US20090184394A1 - High performance system-on-chip inductor using post passivation process - Google Patents

Abstract

A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Description

• This is a continuation of application Ser. No. 10/445,559, filed on May 27, 2003, which is a Continuation-In-Part of application Ser. No. 10/303,451, filing date Nov. 25, 2002, now issued as U.S. Pat. No. 6,897,507, which is a continuation of application Ser. No. 10/156,590, filed on May 28, 2002, now issued as U.S. Pat. No. 6,489,647, which is a Divisional of application Ser. No. 09/970,005, filing date Oct. 3, 2001, now U.S. Pat. No. 6,455,885, which is a Divisional of application Ser. No. 09/721,722, filing date Nov. 27, 2000, now U.S. Pat. No. 6,303,423, which is a continuation-in-part of application Ser. No. 09/637,926, filing date Aug. 14, 2000, now abandoned.
RELATED PATENT APPLICATIONS
• This application is related to attorney docket number MEG02-016, Ser. No. ______, filed on ______, and assigned to a common assignee.
• This application is related to attorney docket number MEG02-018, Ser. No. ______, filed on ______, and assigned to a common assignee.
BACKGROUND OF THE INVENTION
• (1) Field of the Invention
• The invention relates to the manufacturing of high performance Integrated Circuit (IC's), and, more specifically, to methods of creating high performance electrical components (such as an inductor) on the surface of a semiconductor substrate by reducing the electromagnetic losses that are typically incurred in the surface of the substrate.
• (2) Description of the Related Art
• The continued emphasis in the semiconductor technology is to create improved performance semiconductor devices at competitive prices. This emphasis over the years has resulted in extreme miniaturization of semiconductor devices, made possible by continued advances of semiconductor processes and materials in combination with new and sophisticated device designs. Most of the semiconductor devices that are at this time being created are aimed at processing digital data. There are however also numerous semiconductor designs that are aimed at incorporating analog functions into devices that simultaneously process digital and analog data, or devices that can be used for the processing of only analog data. One of the major challenges in the creation of analog processing circuitry (using digital processing procedures and equipment) is that a number of the components that are used for analog circuitry are large in size and are therefore not readily integrated into devices that typically have feature sizes that approach the sub-micron range. The main components that offer a challenge in this respect are capacitors and inductors, since both these components are, for typical analog processing circuits, of considerable size.
• A typical application for inductors of the invention is in the field of modern mobile communication applications. One of the main applications of semiconductor devices in the field of mobile communication is the creation of Radio Frequency (RF) amplifiers. RF amplifiers contain a number of standard components, a major component of a typical RF amplifier is a tuned circuit that contains inductive and capacitive components. Tuned circuits form, dependent on and determined by the values of their inductive and capacitive components, an impedance that is frequency dependent, enabling the tuned circuit to either present a high or a low impedance for signals of a certain frequency. The tuned circuit can therefore either reject or pass and further amplify components of an analog signal, based on the frequency of that component. The tuned circuit can in this manner be used as a filter to filter out or remove signals of certain frequencies or to remove noise from a circuit configuration that is aimed at processing analog signals. The tuned circuit can also be used to form a high electrical impedance by using the LC resonance of the circuit and to thereby counteract the effects of parasitic capacitances that are part of a circuit. One of the problems that is encountered when creating an inductor on the surface of a semiconductor substrate is that the self-resonance that is caused by the parasitic capacitance between the (spiral) inductor and the underlying substrate will limit the use of the inductor at high frequencies. As part of the design of such an inductor it is therefore of importance to reduce the capacitive coupling between the created inductor and the underlying substrate.
• At high frequencies, the electromagnetic field that is generated by the inductor induces eddy currents in the underlying silicon substrate. Since the silicon substrate is a resistive conductor, the eddy currents will consume electromagnetic energy resulting in significant energy loss, resulting in a low Q inductor. This is one of the main reasons for a low Q value of a inductor, whereby the resonant frequency of 1/{square root} (LC) limits the upper boundary of the frequency. In addition, the eddy currents that are induced by the inductor will interfere with the performance of circuitry that is in close physical proximity to the inductor. Furthermore, the fine metal lines used to form the inductor also consume energy, due to the metal's resistance, and result in low Q inductors.
• It has already been pointed out that one of the key components used in creating high frequency analog semiconductor devices is the inductor that forms part of an LC resonance circuit. In view of the high device density that is typically encountered in semiconductor devices and the subsequent intense use of the substrate surface area, the creation of the inductor must incorporate the minimization of the surface area that is required for the inductor, while at the same time maintaining a high Q value for the inductor. Typically, inductors that are created on the surface of a substrate are of a spiral shape whereby the spiral is created in a plane that is parallel with the plane of the surface of the substrate. Conventional methods that are used to create the inductor on the surface of a substrate suffer several limitations. Most high Q inductors form part of a hybrid device configuration or of Monolithic Microwave Integrated Circuits (MMIC's) or are created as discrete components, the creation of which is not readily integratable into a typical process of Integrated Circuit manufacturing. It is clear that, by combining the creation on one semiconductor monolithic substrate of circuitry that is aimed at the functions of analog data manipulation and analog data storage with the functions of digital data manipulation and digital data storage, a number of significant advantages can be achieved. Such advantages include the reduction of manufacturing costs and the reduction of power consumption by the combined functions. The spiral form of the inductor that is created on the surface of a semiconductor substrate however results, due to the physical size of the inductor, in parasitic capacitances between the inductor wiring and the underlying substrate and causes electromagnetic energy losses in the underlying resistive silicon substrate. These parasitic capacitances have a serious negative effect on the functionality of the created LC circuit by sharply reducing the frequency of resonance of the tuned circuit of the application.
• More seriously, the inductor-generated electromagnetic field will induce eddy currents in the underlying resistive silicon substrate, causing a significant energy loss that results in low Q inductors.
• The performance parameter of an inductor is typically indicated is the Quality (Q) factor of the inductor. The quality factor Q of an inductor is defined as Q=Es/El, wherein Es is the energy that is stored in the reactive portion of the component while El is the energy that is lost in the reactive portion of the component. The higher the quality of the component, the closer the resistive value of the component approaches zero while the Q factor of the component approaches infinity. For inductors that are created overlying a silicon substrate, the electromagnetic energy that is created by the inductor will primarily be lost in the resistive silicon of the underlying substrate and in the metal lines that are created to form the inductor. For components, the quality factor serves as a measure of the purity of the reactance (or the susceptance) of the component, which can be degraded due to the resistive silicon substrate, the resistance of the metal lines and dielectric losses. In an actual configuration, there are always some physical resistors that will dissipate power, thereby decreasing the power that can be recovered. The quality factor Q is dimensionless. A Q value of greater than 100 is considered very high for discrete inductors that are mounted on the surface of Printed Circuit Boards. For inductors that form part of an integrated circuit, the Q value is typically in the range between about 3 and 10.
• In creating an inductor on a monolithic substrate on which additional semiconductor devices are created, the parasitic capacitances that occur as part of this creation limit the upper bound of the cut-off frequency that can be achieved for the inductor using conventional silicon processes. This limitation is, for many applications, not acceptable. Dependent on the frequency at which the LC circuit is designed to resonate, significantly larger values of quality factor, such as forinstance 50 or more, must be available. Prior Art has in this been limited to creating values of higher quality factors as separate units, and in integrating these separate units with the surrounding device functions. This negates the advantages that can be obtained when using the monolithic construction of creating both the inductor and the surrounding devices on one and the same semiconductor substrate. The non-monolithic approach also has the disadvantage that additional wiring is required to interconnect the sub-components of the assembly, thereby again introducing additional parasitic capacitances and resistive losses over the interconnecting wiring network. For many of the applications of a RF amplifier, such as portable battery powered applications, power consumption is at a premium and must therefore be as low as possible. By raising the power consumption, the effects of parasitic capacitances and resistive power loss can be partially compensated, but there are limitations to even this approach. These problems take on even greater urgency with the rapid expansion of wireless applications, such as portable telephones and the like. Wireless communication is a rapidly expanding market, where the integration of RF integrated circuits is one of the most important challenges. One of the approaches is to significantly increase the frequency of operation to for instance the range of 10 to 100 GHz. For such high frequencies, the value of the quality factor obtained from silicon-based inductors is significantly degraded. For applications in this frequency range, monolithic inductors have been researched using other than silicon as the base for the creation of the inductors. Such monolithic inductors have for instance been created using sapphire or GaAs as a base. These inductors have considerably lower substrate losses than their silicon counterparts (no eddy current, hence no loss of electromagnetic energy) and therefore provide much higher Q inductors. Furthermore, they have lower parasitic capacitance and therefore provide higher frequency operation capabilities. Where however more complex applications are required, the need still exists to create inductors using silicon as a substrate. For those applications, the approach of using a base material other than silicon has proven to be too cumbersome while for instance GaAs as a medium for the creation of semiconductor devices is as yet a technical challenge that needs to be addressed. It is known that GaAs is a semi-insulating material at high frequencies, reducing the electromagnetic losses that are incurred in the surface of the GaAs substrate, thereby increasing the Q value of the inductor created on the GaAs surface. GaAs RF chips however are expensive, a process that can avoid the use of GaAs RF chips therefore offers the benefit of cost advantage.
• A number of different approaches have been used to incorporate inductors into a semiconductor environment without sacrificing device performance due to substrate losses. One of these approaches has been to selectively remove (by etching) the silicon underneath the inductor (using methods of micro machining), thereby removing substrate resistive energy losses and parasitic effects. Another method has been to use multiple layers of metal (such as aluminum) interconnects or of copper damascene interconnects.
• Other approaches have used a high resistivity silicon substrate thereby reducing resistive losses in the silicon substrate. Resistive substrate losses in the surface of the underlying substrate form a dominant factor in determining the Q value of silicon inductors. Further, biased wells have been proposed underneath a spiral conductor, this again aimed at reducing inductive losses in the surface of the substrate. A more complex approach has been to create an active inductive component that simulates the electrical properties of an inductor as it is applied in active circuitry. This latter approach however results in high power consumption by the simulated inductor and in noise performance that is unacceptable for low power, high frequency applications. All of these approaches have as common objectives to enhance the quality (Q) value of the inductor and to reduce the surface area that is required for the creation of the inductor. The most important consideration in this respect is the electromagnetic energy losses due to the electromagnetic induced eddy currents in the silicon substrate.
• When the dimensions of Integrated Circuits are scaled down, the cost per die is decreased while some aspects of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
• Current techniques for building an inductor on the surface of a semiconductor substrate use fine-line techniques whereby the inductor is created under a layer of passivation. This however implies close physical proximity between the created inductor and the surface of the substrate over which the inductor has been created (typically less than 10 .mu.m), resulting in high electromagnetic losses in the silicon substrate which in turn results in reducing the Q value of the inductor.
• U.S. Pat. No. 5,212,403(Nakanishi) shows a method of forming wiring connections both inside and outside (in a wiring substrate over the chip) for a logic circuit depending on the length of the wire connections.
• U.S. Pat. No. 5,501,006(Gehman, Jr. et al.) shows a structure with an insulating layer between the integrated circuit (IC) and the wiring substrate. A distribution lead connects the bonding pads of the IC to the bonding pads of the substrate.
• U.S. Pat. No. 5,055,907(Jacobs) discloses an extended integration semiconductor structure that allows manufacturers to integrate circuitry beyond the chip boundaries by forming a thin film multi-layer wiring decal on the support substrate and over the chip. However, this reference differs from the invention.
• U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layer interconnect structure of alternating polyimide (dielectric) and metal layers over an IC in a TAB structure.
• U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method for reducing RC delay by a PBGA that separates multiple metal layers.
• U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate that reduces RC delay by separating the power and I/O traces.
• U.S. Pat. No. 6,008,102 (Alford et al.) shows a helix inductor using two metal layers connected by vias.
• U.S. Pat. No. 5,372,967 (Sundaram et al.) discloses a helix inductor.
• U.S. Pat. No. 5,576,680 (Ling) and U.S. Pat. No. 5,884,990 (Burghartz et al.) show other helix inductor designs.
SUMMARY OF THE INVENTION
• It is the primary objective of the invention to improve the RF performance of High Performance Integrated Circuits.
• Another objective of the invention is to provide a method for the creation of a high-Q inductor.
• Another objective of the invention is to replace the GaAs chip with a silicon chip as a base on which a high-Q inductor is created.
• Yet another objective of the invention is to extend the frequency range of the inductor that is created on the surface of a silicon substrate.
• It is yet another objective of the invention to create high quality passive electrical components overlying the surface of a silicon substrate.
• The above referenced U.S. Pat. No. 6,383,916 adds, in a post passivation processing sequence, a thick layer of dielectric over a layer of passivation and layers of wide and thick metal lines on top of the thick layer of dielectric. The present invention extends referenced U.S. Pat. No. 6,383,916 by in addition creating high quality electrical components, such as an inductor, a capacitor or a resistor, on a layer of passivation or on the surface of a thick layer of dielectric. In addition, the process of the invention provides a method for mounting discrete passive electrical components on the surface of Integrated Circuit chips.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a cross sectional representation of the interconnection scheme shown in U.S. Pat. No. 6,383,916.
• FIG. 2 is a cross sectional representation of an inductor of the invention, created on a thick layer of polyimide.
• FIG. 3 is a top view of an inductor created following the process of the invention.
• FIG. 4 is a cross sectional representation of a substrate and overlying layers, an inductor has been created on the surface of a thick layer of polyimide, a layer of conductive material has been added to further insulate the inductor from the underlying silicon substrate.
• FIG. 5ashows an inductor of the invention above a layer of passivation.
• FIGS. 5b-5care a cross-sectional representation, and top view, respectively, of inductors of the invention formed on an isolated section of polymer.
• FIG. 6ais a cross sectional representation of a transformer according to the invention, formed over a polymer layer, over a layer of passivation.
• FIG. 6bis a cross sectional representation of a transformer according to the invention, with the bottom coil formed on a layer of passivation.
• FIG. 6cis a three dimensional view of another embodiment of a solenoidal inductor of the invention, over a passivation layer.
• FIG. 6dis a three-dimensional view of a solenoidal inductor of the invention, formed over a polymer layer, over a passivation layer.
• FIG. 6eis a top view of the inductors ofFIGS. 6cand6d.
• FIG. 6fis a cross sectional representation of the structure ofFIG. 6e, taken along theline6f-6fofFIG. 6e.
• FIG. 6gis a three dimensional view of an inductor of the invention, in the shape of a toroid.
• FIG. 6his a top view of the toroidal inductor ofFIG. 6g.
• FIGS. 7a-7cis a cross sectional representation of a capacitor of the invention, formed over a polymer layer over passivation.
• FIG. 8 is a cross sectional representation of a resistor of the invention, formed over a passivation layer.
• FIGS. 9a-9bare cross sectional representations of a resistor of the invention, formed over a thick polymer layer, over a passivation layer.
• FIG. 10 is a cross sectional representation of, a silicon substrate over which a discrete electrical component has been mounted, on the top of a thick polymer layer, using surface mount technology.
• FIG. 11 is a cross sectional representation of a silicon substrate, having a passivation layer on the surface of which a discrete electrical component has been mounted, using surface mount technology.
• FIGS. 12-18 depict, in cross-sectional form, the creation of gold metal structures of the invention, through a layer of polymer.
• FIGS. 19-23 depict the creation of copper metal structures of the invention, through a layer of polymer.
• FIGS. 24a-24cshow alternate methods of connecting to the inductor of the invention.
• FIGS. 25 and 26 show extended methods of connecting a capacitor and a resistor under the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
• U.S. Pat. No. 6,383,916, assigned to a common assignee as the current invention, teaches an Integrated Circuit structure where re-distribution and interconnect metal layers are created in layers of dielectric over the passivation layer of a conventional Integrated Circuit (IC). A layer of passivation is deposited over the IC, a thick layer of polymer is alternately deposited over the surface of the layer of passivation, and thick, wide metal lines are formed over the passivation.
• U.S. Pat. No. 6,303,423, also assigned to a common assignee as the current invention, addresses, among other objectives, the creation of an inductor whereby the emphasis is on creating an inductor of high Q value above the passivation layer of a semiconductor substrate. The high quality of the inductor of the invention allows for the use of this inductor in high frequency applications while incurring minimum loss of power. The invention further addresses the creation of a capacitor and a resistor on the surface of a silicon substrate whereby the main objective (of the process of creating a capacitor and resistor) is to reduce parasitics that are typically incurred by these components in the underlying silicon substrate.
• Referring now more specifically toFIG. 1, there is shown a cross section of one implementation of U.S. Pat. No. 6,383,916. The surface ofsilicon substrate10 has been provided withtransistors11 and other devices (not shown inFIG. 1). The surface ofsubstrate10 is covered by a interlevel dielectric (ILD)layer12, formed over the devices.
• Layers14 represent metal and dielectric layers that are typically created overILD12.Layers14 contain one or more layers of dielectric, interspersed with one or moremetal interconnect lines13 that make up a network of electrical connections. At a top metal layer arepoints16 of electrical contact. Thesepoints16 of electrical contact can establish electrical interconnects to the transistors andother devices11 that have been provided in and on the surface of thesubstrate10. Apassivation layer18, formed of, for example, a composite layer of silicon oxide and silicon nitride, is deposited over the surface oflayers14, and function to prevent the penetration of mobile ions (such as sodium ions), moisture, transition metal (such as gold, copper, silver), and other contamination. The passivation layer is used to protect the underlying devices (such as transistors, polysilicon resistors, poly-to-poly capacitors, etc.) and the fine-line metal interconnection.
• The key steps of U.S. Pat. No. 6,383,916, begin with the deposition of athick layer20 of polyimide that is deposited over the surface ofpassivation layer18. Access must be provided to points ofelectrical contact16, for this reason a pattern ofopenings22,36 and38 is formed through thepolyimide layer20 and thepassivation layer18, the pattern ofopenings22,36 and38 aligns with the pattern of electrical contact points16. Contact points16 are, by means of theopenings22/36/38 that are created in thelayer20 of polyimide, electrically extended to the surface oflayer20.
• Layer20 is a polymer, and is preferably polyimide.Polymer 20 may optionally be photosensitive. Examples of other polymers that can be used include benzocyclobutene (BCB), parylene or epoxy-based material such as photoepoxy SU-8 (available from Sotec Microsystems, Renens, Switzerland).
• After formation ofopenings22/36/38, metallization is performed to create patternedwide metal layers26 and28, and to connect to contact points16.Lines26 and28 can be of any design in width and thickness to accommodate specific circuit design requirements, which can be used for power distribution, or as a ground or signal bus. Furthermore,metal26 may be connected off-chip through wire bonds or solder bumps.
• Contact points16 are located on top of a thin dielectric (layers14,FIG. 1), and the pad size must be kept small to minimize capacitance with underlying metal layers. In addition, a large pad size will interfere with the routing capability of the layer of metal.
• Layer20 is a thick polymer dielectric layer (for example, polyimide) having a thickness in excess of 2 .mu.m (after curing). The range of the polymer thickness can vary from 2 .mu.m to 150 .mu.m, dependent on electrical design requirements. For a thicker layer of polyimide, the polyimide film can be multiple coated and cured.
• U.S. Pat. No. 6,383,916 B1 allows for the interconnection of circuit elements at various distances, over the path30/32/34 shown inFIG. 1, using the thick, wide (as compared to the underlying “fine line” metallization in layers14) metal of 28. Thick,wide metal28 has smaller resistance and capacitance than thefine line metal14 and is also easier and more cost effective to manufacture.
• FIG. 2 shows how the interconnect aspect of U.S. Pat. No. 6,383,916, can be modified to form an inductor on the surface of thethick layer20 of polyimide. The inductor is created in a plane that is parallel with the surface of thesubstrate10 whereby this plane however is separated from the surface of thesubstrate10 by the combined heights oflayers12,14,18, and20.FIG. 2 shows across section40 of the inductor taken in a plane that is perpendicular to the surface ofsubstrate10. The wide and thick metal will also contribute to a reduction of the resistive energy losses. Furthermore, the low resistivity metal, such as gold, silver and copper, can be applied using electroplating, the thickness can be about 20 .mu.m.
• By increasing the distance between the inductor and the semiconductor surface, as compared to prior art approaches in which the inductor is formed under the passivation, the electromagnetic field in the silicon substrate will be reduced as the distance is increased, and the Q value of the inductor can be increased. The inductor overlies the layer of passivation and by, in addition, creating the inductor on the surface of a thick layer of dielectric (such as a polymer) formed over the passivation layer. In addition, by using wide and thick metal for the creation of the inductor, the parasitic resistance is reduced.
• In an important feature of the invention, theopenings19 inpassivation layer18 may be as small as 0.1 .mu.m wide. Thus,contact pads16 may also be nearly as small, which allows for greater routing capability in the top fine-line metallization layer, and lower capacitance.
• In another important feature of the invention, theopenings22/36/38 inpolymer20 are larger than thepassivation openings19. Thepolymer openings22/36/38 are aligned withpassivation openings19. The larger polymer openings allow for relaxed design rules, simpler opening formation, and the use of a thick metal layer for the post-passivation metallization of the invention.
• FIG. 2 illustratesinterconnect structure26 as well asinductor40, wherein the inductor includes twocontacts41 and43, throughpolymer layer20 to contactpads16.
• In another feature of the invention, theFIG. 2 structure may be covered by an additional layer of polymer (not shown).
• FIGS. 24aand24billustrate another feature of the invention, in which contacts to the inductor are formed in a different manner than the 2 downward contacts ofFIG. 2. Specifically, inFIG. 24a, alayer35 of dielectric, preferably polyimide or the like, is deposited overinterconnection26 andinductor40. Anopening36′ to one end of the inductor is then formed to expose one terminal of theinductor40.Inductor40 inFIG. 24athus can have one contact extending upward, and asecond contact40′ extending downward, in a “one-up, one-down” configuration.
• FIG. 24billustrates another alternative, in which 2upward contact openings36′ and38′ are formed frominductor40, in a “two-up” configuration.
• In bothFIGS. 24aand24b, the upward contacts may be used for connection to external devices or packaging, by way of wire bonding, solder bumps, or the like. For wire bonding, an upper surface ofinductor40 must be formed of a wire-bondable material such as Au or Al. For solder bump connection, under bump metallization (UBM) would be formed in the upward contact opening, followed by solder bump formation.
• In either of theFIG. 24aor24bconfigurations, interconnections to other contact pads on the same die (as opposed to connections to external devices, as described in the previous paragraph) may be made throughopenings36′ and/or38′, using similar metallization (but as an additional layer) as used forstructure26 andinductor40.
• Referring now toFIG. 24c, another feature of the invention is shown in whichextension89, connected toinductor40, is used to relocate aninductor contact opening36″ to another location on the die, such as at the die edge. This may be useful for ease of wire bonding, for example.Opening38″ is formed as earlier described.Extension89 is formed at the same time and of the same metallization asstructure26 andinductor40.
• Similarly,extension89 could be used to interconnectinductor40 to another contact point on the same die, by making a downward contact (not shown, but described earlier) instead ofupward contact36″.
• If a contact to a center point of the inductor, such as that shown under opening38″ inFIG. 24c, is desired, then such contact cannot of course be made by an extension such as40′, but instead must be either upward or downward.
• FIG. 3 shows atop view42 of the spiral structure of theinductor40 that has been created on the surface oflayer20 of dielectric. Theinductor40 cross section that is shown inFIG. 2 is taken along line2-2 ofFIG. 3.
• FIG. 4 shows a cross section ofinductor40 whereby the inductor has been further isolated from the surface of thesubstrate10 by the addition of aconductive plate44′, of conducting material, formed under substantially all of the inductor, and preferably formed of Cu (copper) or Au (gold). The surface area of theconductive plate44′ typically extends over the surface ofpassivation layer18 such that theinductor40 aligns with and overlays theconductive plate44′, the surface area ofconductive plate44′ can be extended slightly beyond these boundaries to further improve shielding the surface ofsubstrate10 from the electromagnetic field ofinductor40.
• Conductive plate44′ can be connected to one of the inductor terminals (as shown inFIG. 4, in which it is connected to the rightmost inductor terminal43), or may be left at a floating voltage level, or may be connected to another voltage level, deciding on the system's electrical design.
• Conductive plate44′ is formed using the methods and material of the invention, as later described with regard to the metal layer used to formmetal interconnect26 andinductor40.Conductive plate44′ is formed at the same time asconnectors44, which serve to connect the next level metal to contactpoints16, as shown inFIG. 4.
• Optionally, asecond polymer layer47 may be deposited overinductor40 andinterconnect structure26, to provide additional protection of the metal structures.
• Referring now toFIGS. 12-23, further details are provided for forming the post passivation inductor (and other passive devices) of the invention. InFIG. 12, asubstrate80 is shown, which could be an underlying dielectric layer, and ametal contact point81, preferably comprising aluminum. Alayer84 of passivation has been patterned creating anopening82 throughlayer84 that exposes thecontact pad81.Layer86 is a layer of polymer, preferably polyimide, as earlier described, deposited over thelayer84 of passivation, including the exposed surface of the contact pad.Polymer layer86, such as polyimide, is typically spun on. For some thick layers of polymer, the polymer can be screen printed. Alternately, a laminated dry film polymer may be used.
• FIG. 13 illustrates forming anopening87 inpolymer86, wherein thepolymer opening87 is larger thanpassivation opening82.Opening87 is depicted having sloped sides85.Polymer layer86 is exposed and developed to form opening87, which initially has vertical sidewalls. However, the subsequent curing process causes the sidewalls to have aslope85, and aopening87 to have a resultant partially conical shape. Thesidewall slope85 may have an angle of 45 degrees or more, and is typically between about 50 and 60 degrees. It may be possible to form the sidewalls with an angle as small as 20 degrees.
• By creating relatively large vias through the layer of polyimide or polymer, aligned with smaller vias created through the underlying layer of passivation, aligned with underlying sub-micron metal layer, it is clear that the sub-micron metal vias can effectively be enlarged when progressing from the sub-micron metal layer to the level of the wide metal.
• Continuing to refer toFIG. 13, one metallization system and process for forming the post passivation interconnect and inductor of the invention is depicted. First, a glue/barrier layer88, preferably comprising TiW, is deposited, preferably by sputtering to a thickness of between about 500 and 5,000 Angstroms. Agold seed layer90, is next sputter deposited over the glue/barrier88, to a thickness of between about 300 and 3,000 Angstroms.
• Referring now toFIG. 14, abulk layer92 of gold (Au) is next formed by electroplating, to a thickness of between about 1 and 20 .mu.m. Electroplating is preceded by deposition of a thick photoresist94 (to a thickness greater than the desired bulk metal thickness), and conventional lithography to expose thegold seed layer90 in those areas where electroplating thick metallization is desired.
• After electroplating,photoresist94 is removed, as shown inFIG. 15. Glue/barrier Layer88 andgold seed layer90 are now removed, as shown inFIG. 16, by etching, usingbulk Au layer92 as a mask. One coil ofinductor40 is shown, but it would be understood that the complete inductor would be formed at the same time.
• In another feature of the invention,polymer opening87 may be only partially filled, as shown inFIGS. 17-18, which provides tight design rules for fine-pitch inductors. The design rule ofpolymer opening87 is typically about 15 .mu.m, while the metal traces of inductor are as tight as a 4 .mu.m pitch. Therefore, patterning metal inside the polyimide opening is a very important feature of this technology.
• Glue/barrier layer88 andAu seed layer90 are sputtered as previously described, andphotoresist95 formed as shown inFIG. 17, followed by electroplatinggold bulk layer92.Photoresist95 is then stripped, and the seed layer and glue/barrier etched as previously described, and as shown inFIG. 18.
• In another embodiment of the invention, copper may be used as the bulk metal in the post-passivation metallization scheme. TheFIG. 13 structure is a starting point. Next, as shown inFIG. 19, a glue/barrier layer100 of Cr or Ti is sputter deposited to a thickness of between about 200 and 2000 Angstroms. Next, aCu seed layer102 is sputter deposited to a thickness of between about 2,000 and 10,000 Angstroms.Bulk layer104 of Cu is next electroplated to a thickness of between about 3 and 20 .mu.m, also using aphotoresist94′ and conventional lithography to define the areas to be electroplated. Finally, anoptional cap layer106 comprising Ni may also be formed, also by electroplating, to a thickness of between about 0.1 and 3 .mu.m.
• Referring toFIG. 20,photoresist94′ is stripped, exposingCu seed layer104. Glue/barrier layer100 andCu seed layer102 are now removed, as shown inFIG. 21, by etching. Thebulk Cu layer104 is used as a mask for this etch.
• If optionalNi cap layer106 is used, it acts as an etch stop during the etching of glue/barrier100 andseed layer102. With the Ni cap, a faster Cu etch recipe can be used for removing the seed layer since there is no loss of Cu bulk in this configuration.
• One coil ofinductor40 is shown, but it would be understood that the complete inductor would be formed at the same time.
• In another feature of the invention and as earlier described,polymer opening87 may be only partially filled, as shown inFIGS. 22-23. Glue/barrier layer100 andCu seed layer102 are sputtered as previously described, andphotoresist95′ formed as shown inFIG. 22, followed by electroplatingCu bulk layer104 andNi106.Photoresist95′ is then stripped, and the seed layer and glue/barrier etched as previously described, and as shown inFIG. 23.
• Referring now toFIG. 5a, layers similar to earlier descriptions are shown whereby in this case no layer of polyimide has been deposited over the layer of passivation. Aninductor19 has been created on the surface oflayer18 of passivation. The ohmic resistivity of the metal that is used forinductor19 must be as low as possible. For this reason, the use of a thick layer of, for instance, gold is preferred for the formation ofinductor19. It has been shown that a thick layer of gold increased the Q value ofinductor19 from about 5 to about 20 for 2.4 GHz applications.
• TheFIG. 5ainductor may be connected to other elements in various configurations, as earlier described. These include both terminals being connected to lower levels, as shown inFIG. 4, one up and one down as shown inFIG. 24a, or both up as inFIG. 24b.
• An additional layer of polymer (not shown) may optionally be formed overinductor19.
• In another feature of the invention, polymer islands may be formed only under the inductor coils, and not elsewhere over the passivation layer, in order to reduce the stress caused by a larger sheet of polymer. This is depicted inFIGS. 5b-5c, which are a cross-sectional representation, and top view, respectively, of inductors of the invention formed on polymer islands. Each island may contain one or more than one inductor, such as on the right-most island ofFIG. 5chaving afirst inductor40′ andsecond inductor40′″.
• Referring first toFIG. 5b, isolated islands ofpolymer20′ are formed, by depositing a polymer layer and then patterning the polymer layer to form the polymer islands. The polymer islands may also be formed by screen printing, or by dry film lamination. The islands ofpolymer20′ are formed only at the location ofinductors40′ and40″, which are formed subsequent to polymer island formation.
• Theinductors40′ and40″ ofFIG. 5bare formed as earlier described. For illustrative purposes,inductor40″ is shown withdownward contacts41′ and43′ connecting to metal contact points16.Inductors40′ are shown without contacts but could be connected upward for connection to external circuits, as described elsewhere.
• FIG. 5cis a top view of the inductors of the invention shown inFIG. 5b, in which theFIG. 5bcross-section is taken alongline5b-5binFIG. 5c. It can be seen inFIG. 5cthatpolymer islands20′ are isolated from one another, and polymer is only located under inductor locations—passivation layer18 is exposed in all other areas of the substrate.
• An additional protective layer of polymer (not shown) may optionally be formed overinductors40′ and40″.
• In a similar fashion to that shown inFIGS. 5b-5cfor inductors, polymer islands may be formed under other devices of the invention, including passive devices such as resistors and capacitors.
• FIGS. 6a-6bdepict a transformer made according to the invention. The transformer consists ofbottom coil60, andtop coil62, isolated by adielectric layer47. Polymer layers20,47 and64 are formed, and comprise materials, previously described.Openings66 are provided intop polymer layer64 for connections to thetop coil62.
• FIG. 6bis a cross-sectional representation of a transformer of the invention, in which thebottom coil60 is formed directly onpassivation layer18.
• FIG. 6cis a three-dimensional view of a solenoid structure of aninductor19 that has been created onpassivation layer18, according to the invention. Further highlighted inFIG. 6care:
• 23, vias that are created in the thick layer ofpolymer20, having substantially vertical metal segments
• 25, the bottom metal segments of the solenoid
• 27, the top metal segments of the solenoid.
• The top andbottom metal segments25,27 are connected, as shown, by the substantially vertical metal segments formed invias23, to form a continuous solenoid.
• FIG. 6dis a three dimensional view of a solenoid that has been created on afirst layer29 of polymer, havingvias23 created in a second layer of polymer.
• FIG. 6eis a top view of the solenoid ofFIGS. 6cand6d.Vias23 are shown, connectingtop metal segments27 tobottom metal segments25.
• FIG. 6fis a cross section of the structure ofFIGS. 6c-e, taken alongline6f-6fofFIG. 6e.
• Referring now toFIGS. 6g-6h, atoroidal inductor68 is shown, also formed according to the method and structure of the invention. InFIG. 6g, a three-dimensional view is shown, includingtop metal wires27′, withvias23′ connecting the top metal wires to thebottom metal wires25′.
• FIG. 6hshows, for further clarification, a top view of thetoroidal inductor68 ofFIG. 6g. The highlighted features of this figure have previously been explained and therefore do not need to be further discussed at this time.
• Besides inductors, it is very useful to form other passive devices, such as capacitors and resistors, using the method and structure of the invention.
• FIG. 7ais a cross section of a capacitor that has been created over asubstrate10. A layer (or layers)14 of conductive interconnect lines and contact points16 have been created oversubstrate10. Alayer18 of passivation has been deposited overlayer14, with openings created inlayer18 of passivation through whichcontact pads16 can be accessed.
• A capacitor contains, as is well known, a lower plate, an upper plate and a layer of dielectric that separates the upper plate from the lower plate.FIG. 7aincludeslower plate42,upper plate45, anddielectric layer46. The upper and lower plates are formed as earlier described, using electroplated Au or Cu for the bulk metals. An optional protective polymer, preferably polyimide, may be formed over the capacitor. Contacts to the capacitor may be made as described earlier for inductor terminals (both down, one up and one down, or both up).
• Lower plate42 is formed to a thickness of between about 0.5 and 20 .mu.m.Layer46 of dielectric is between about 500 and 50,000 Angstroms.Upper plate45 is between about 0.5 and 20 .mu.m thick.
• The post-passivation capacitor shown in cross section inFIG. 7ahas:
• reduced parasitic capacitance between the capacitor and the underlying silicon substrate
• allowed for the use of a thick layer of conductive material for the capacitor plates, reducing the resistance of the capacitor; this is particularly important for wireless applications
• can use high-dielectric-constant material such as TiO.sub.2 or Ta.sub.20.sub.5, in addition to polymer, Si.sub.3N.sub.4 or SiO.sub.2, for the dielectric between the upper and the lower plate of the capacitor, resulting in a higher capacitive value of the capacitor.
• The capacitor ofFIG. 7amay alternately be formed above a polymer layer (deposited over passivation18), similar to the inductor ofFIG. 4.
• Dielectric layer46 is formed of a high-K dielectric material such as Si.sub.3N.sub.4, TEOS, Ta.sub.2O.sub.5, TiO.sub.2, SrTiO.sub.3, or SiON, which are typically deposited by CVD (Chemical Vapor Deposition).
• Alternately, thedielectric layer46 can be a polymer film, including polyimide, benzocyclobutene (BCB), parylene or an epoxy-based material such as photoepoxy SU-8.
• FIGS. 7b-7cshow a cross section where, as inFIG. 7a, a capacitor is created. In the cross section that is shown inFIG. 7bathick layer20 of polymer has been deposited over the surface of thepassivation layer18 and has been patterned in order to make thecontact pads16 accessible though thethick layer20 of polymer.FIG. 7bshows the polymer vias having a smaller via diameter than the vias created through the layer of passivation. It is however preferred, as shown inFIG. 7c, that larger vias be used in conjunction with smaller passivation vias. Thethick layer20 of polymer moves most of the capacitor, that is thelower plate42, theupper plate45 and the dielectric46, further from the surface ofsubstrate10 by a distance equal to the thickness oflayer20. It has previously been stated that the range of polyimide thickness can vary from 2 .mu.m to 150 .mu.m, depending on electrical design requirements. This leads to a significant increase in distance between the capacitor and underlying structures, including metal lines and/or the silicon substrate, so that parasitic capacitance is significantly reduced.
• FIGS. 7a-7cdepict both capacitor terminals being connected down to a lower layer. The capacitor may also be contacted in one-up-one-down configuration—as shown in FIG.25—or a two-up technique, as previously described with reference toFIG. 24b.
• Specifically relating to the cross section ofFIGS. 7a-7c, theupper capacitor plate45 can be connected in an upward manner through a layer of dielectric that has been deposited over thesecond capacitor plate45 ofFIGS. 7a-7c. This is further highlighted in the cross section ofFIG. 25, wherein alayer35 of dielectric has been deposited over the capacitorupper plate45, with anopening37 created through thelayer35 of dielectric to expose the capacitorupper plate45, for further connection to external circuits.
• The capacitor ofFIGS. 7a-7cmay optionally be covered with a protective layer of polymer, as previously described.
• FIG. 8 shows a cross section of asubstrate10 over which has been deposited alayer18 of passivation, with aresistor48 formed overpassivation layer18. A resistor, as is well known, is created by connecting two points with a material that offers electrical resistance to the passage of current through the material. For the creation of layer48 a resistive material is used, such as TaN, NiCr, NiSn, tungsten (W), TiW, TiN, Cr, Ti, TaSi or Ni. Among these resistive materials, NiCr provides the best TCR (Temperature Coefficient of Resistance), which can be as small as 5 ppm/.degree. C. Resistor dimensions such as thickness, length and width of deposition of highresistive material48 are application dependent. The resistor that is shown in cross section inFIG. 8 is, as are the capacitors ofFIGS. 7a-7c, created in a post-passivation process on the surface oflayer18 of passivation.
• FIGS. 9a-9bshows the resistor of the invention formed over a thick layer ofpolymer20, connected to contactpads16. By increasing the distance between the body of the resistor and the substrate (by the thickness of thepolymer layer20 and other intervening layers) the parasitic capacitance between the body of the resistor and the substrate is reduced, resulting in an improved resistive component (reduced parasitic capacitive loss, improved high frequency performance).
• FIGS. 8,9aand9bshow a “two-down” system for contacting the terminals of theresistor48. The resistor may also be contacted in one-up-one-down configuration, as shown inFIG. 26, or a two-up technique, as previously described with reference to the inductor ofFIG. 24b.
• An additional layer of polymer, to protect the resistor, may optionally be formed over the resistor ofFIGS. 8,9aand9b.
• Further applications of the post-passivation processing of the invention are shown inFIGS. 10 and 11, which concentrate on making contact points betweencontact pads16 and an overlying electric component, such as a discrete inductor, capacitor, resistor or other passive device.Interconnect metal50 of the invention is formed in polymer openings, as previously described, which are aligned with smaller passivation openings, to connect topads16, and serves as an under-bump metal (UBM). Solder contact bumps are formed overUBM50 using conventional methods of selective solder deposition (plating, ball mounting, or screen printing on the surface of contacts50), the application of a flux on the deposited solder and flowing the solder. Adiscrete device54 is connected to solderballs52 and hassolder53 to facilitate the connection. This is similar to the surface mount technology used in the assembly of printed circuit boards. The discrete electrical component may be, but is not limited to, devices such as inductors, capacitors or resistors.
• FIG. 11 illustrates mounting ofdiscrete device54, using solder bumps56, andUBM50, directly overpassivation layer18.
• The discrete components ofFIGS. 10 and 11 have the advantages of performance and cost savings since the discrete component does not have to be mounted on a Printed Circuit Board as is the common practice in the art.
• UBM50 is formed using the metallization scheme of the invention (as shown and described with respect toFIGS. 12-23), except that when Au is used as the bulk layer, its thickness is in the range of between about 0.1 and 20 .mu.m, the thinner range being preferable to avoid a high gold concentration in the solder near the UBM/solder interface, after processing.
• The invention and its various features provide the advantages of:
• the discrete components provide optimized parameters and can be mounted close to the circuits, which offer true system-on-chip performance
• the discrete components mounting close to the circuits also minimizes parasitics
• the post-passivation process of the invention allows for the selection of discrete component design parameters that result in reduced resistance of the discrete capacitor and the discrete inductor, this is further clear from the following comparison between prior art processes and the processes of the invention.
• Prior approaches in the art uses thinner metal for inductors, requiring wider coils (to minimize resistance), resulting in increased surface area, increasing the parasitic capacitance of the inductor and causing eddy current losses in the surface of the substrate.
• The present invention by contrast, can use easily formed thick metal layers, the thickness reducing resistance. Use ofpolymer20 further separates the components formed from underlying structures, reducing capacitance. With the reduced capacitance, a higher frequency of operation results due to a higher resonant frequency.
• Although the preferred embodiment of the present invention has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.

Claims (20)

1. A system-on-chip structure comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first interconnect layer over said silicon substrate and a second interconnect layer over said first interconnect layer;

a first dielectric layer between said first and second interconnect layers;

a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises a nitride layer;

a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and

a capacitor on said polymer layer, wherein said capacitor comprises a lower plate on said polymer layer, an upper plate over said lower plate and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 angstroms, wherein said lower plate comprises a first metal layer and a first electroplated copper layer on said first metal layer, and wherein said upper plate comprises a second metal layer and a second electroplated copper layer on said second metal layer.

2. The system-on-chip structure ofclaim 1, wherein said second dielectric layer comprises a nitride.

3. The system-on-chip structure ofclaim 1, wherein said second dielectric layer comprises titanium oxide.

4. The system-on-chip structure ofclaim 1, wherein said second dielectric layer comprises tantalum oxide.

5. The system-on-chip structure ofclaim 1, wherein said second dielectric layer comprises an oxide.

6. The system-on-chip structure ofclaim 1, wherein said first metal layer comprises a titanium-containing layer under said first electroplated copper layer.

7. The system-on-chip structure ofclaim 1, wherein said first metal layer comprises a copper seed layer under said first electroplated copper layer.

8. A system-on-chip structure comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first interconnect layer over said silicon substrate and a second interconnect layer over said first interconnect layer;

a first dielectric layer between said first and second interconnect layers;

a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises a nitride layer; and

a capacitor on said passivation layer, wherein said capacitor comprises a lower plate on said passivation layer, an upper plate over said lower plate and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 angstroms, wherein said lower plate comprises a first metal layer and a first electroplated copper layer on said first metal layer, and wherein said upper plate comprises a second metal layer and a second electroplated copper layer on said second metal layer.

9. The system-on-chip structure ofclaim 8, wherein said second dielectric layer comprises a nitride.

10. The system-on-chip structure ofclaim 8, wherein said second dielectric layer comprises tantalum oxide.

11. The system-on-chip structure ofclaim 8, wherein said second dielectric layer comprises an oxide.

12. The system-on-chip structure ofclaim 8, wherein said first metal layer comprises a titanium-containing layer under said first electroplated copper layer.

13. The system-on-chip structure ofclaim 8, wherein said first metal layer comprises a copper seed layer under said first electroplated copper layer.

14. A system-on-chip structure comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first interconnect layer over said silicon substrate and a second interconnect layer over said first interconnect layer;

a first dielectric layer between said first and second interconnect layers;

a passivation layer over said metallization structure and over said first dielectric layer, wherein an opening in said passivation layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening in said passivation layer;

a first capacitor over said passivation layer, wherein said first capacitor comprises a first lower plate over said passivation layer, a first upper plate over said first lower plate and a second dielectric layer between said first upper plate and said first lower plate, wherein said first upper plate is connected to said contact point, and wherein said first upper plate comprises electroplated copper; and

a second capacitor over said passivation layer, wherein said second capacitor comprises a second lower plate over said passivation layer, a second upper plate over said second lower plate and a third dielectric layer between said second upper plate and said second lower plate, wherein said second upper plate is connected to said contact point and to said first upper plate, and wherein said second upper plate comprises electroplated copper.

15. The system-on-chip structure ofclaim 14 further comprising a polymer layer on said passivation layer, wherein said first and second capacitors are further on said polymer layer.

16. The system-on-chip structure ofclaim 14, wherein said passivation layer comprises a nitride layer.

17. The system-on-chip structure ofclaim 14, wherein said first lower plate comprises electroplated copper.

18. The system-on-chip structure ofclaim 14, wherein said first upper plate further comprises a titanium-containing layer under said electroplated copper of said first upper plate.

19. The system-on-chip structure ofclaim 14, wherein said second dielectric layer comprises an oxide.

20. The system-on-chip structure ofclaim 14, wherein said second dielectric layer comprises a nitride.

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