US20090168484A1 - Multiple-port sram device - Google Patents

Abstract

A multiple-port SRAM cell includes a latch having a first node and a second node for retaining a value and its complement, respectively. The cell has a write port separate from a read port for parallel operation. A number of transistors are used to connect the first and second nodes to a number of bit lines, such as a read port bit line, a read port complementary bit line, a read/write port bit line, and a read/write port complementary bit line. In a layout view of the multiple-port SRAM cell, the read port bit line, read port complementary bit line, read/write port bit line and read/write port complementary bit line are separated by at least one supply voltage line, one or more complementary supply voltage lines, and one or more word line landing pads.

Description

CROSS REFERENCE
• This application is a continuation application of U.S. patent application Ser. No. 11/605,757, which was filed on Nov. 29, 2006 entitled MULTIPLE-PORT SRAM DEVICE.
BACKGROUND
• The present invention relates generally to an integrated circuit (IC) design, and more particularly to a multiple-port static-random-access-memory (SRAM) cell structure with balanced read and write operation speeds and an improved noise margin.
• SRAM devices have become increasingly popular as data storage units for high-speed communication devices, image processing devices, and other system-on-chip (SOC) products. A SRAM device is typically comprised of a logic circuit portion and a memory cell portion, which includes a plurality of cells arranged in one or more arrays. The SRAM cells, based on their structures, can be categorized as single-port cells, two-port cells, dual-port cells, and multiple-port cells. SRAM devices made of two-port, dual-port or multiple-port cells have become increasingly popular, as they are particularly suitable for parallel operations.
• FIG. 1A schematically illustrates a conventional two-port SRAM cell100 that is implemented with eight transistors. The conventional two-port SRAM cell100 includes twoPMOS transistors102 and104 and sixNMOS transistors106,108,110,112,114, and116. ThePMOS transistors102 and104 function as pull-up devices, while theNMOS transistors106 and108 function as pull-down devices. TheNMOS transistors110 and112 function as pass-gate devices for read or write operations. The sources of thePMOS transistors102 and104 are both connected to a supply voltage Vcc, while the sources of theNMOS transistors106 and108 are both connected to a complementary supply voltage, such as ground or Vss. The gates of thePMOS transistor102 andNMOS transistor106 are coupled at anode118, while their drains are also tied together at a node120. ThePMOS transistor104 and theNMOS transistor108 also having gates coupled together at the node120, and drains at thenode118. Thenode118 is coupled to a complementary read/write port bit line BLB via theNMOS transistor112, which is controlled by a read/write word line WL. The node120 is coupled to a read/write port bit line BL via theNMOS transistor110, which is also controlled by the same read/write word line WL. In some special cases, this read/write port may serve only as a write port without the read function.
• The read port portion of the conventional two-port SRAM cell100 includes theNMOS transistor114, which acts as a pull-down device and theNMOS transistor116, which acts as a pass-gate device. A gate of theNMOS transistor114 is connected to the node120 (or 118), while its source is tied to the complementary supply voltage, such as ground or Vss. A high signal at the node120 (or 118) can turn theNMOS transistor114 on and ground the read port bit line BL when theNMOS transistor116 is turned on by a high signal on the read word line WL.
• FIG. 1B illustrates a layout diagram122 of the metal routing for the conventional two-port SRAM cell100 shown inFIG. 1A. The layout diagram122 shows the metal routing for most of the interconnections used within the conventional two-port SRAM cell100 ofFIG. 1A. These interconnections include several power lines such as a supplyvoltage Vcc line124, a complementary supplyvoltage Vss line128, alanding pad126 for another complementary supply voltage Vss line (not shown in this figure), and several bit lines and word lines. The bit lines shown are a read/write portbit line BL130, a complementary read/write portbit line BLB132, and a read portbit line BL134. A read/writeword line WL136 is shown lined up in parallel with a readword line WL138 on a metallization layer higher than that on which theVcc line124, theVss line128, thelanding pad126, the read/write portbit line BL130, the complementary read/write portbit line BLB132, and read portbit line BL134 are constructed. Threelanding pads140,142, and144 are also implemented in parallel with the bit lines on the same metallization layer. Thelanding pads140 and142 are used for making connections with the read/write word line WL136, while thelanding pad144 is used for making connections with the read word line WL138.
• One drawback of the conventional two-port SRAM cell110 is that its layout structure is asymmetric. The read/writeport bit line130 is interposed between thelanding pad140 and theVcc line124. However, the complementary read/write port bit line BLB132 is interposed between theVss line128 and theVcc line124. This asymmetric layout causes an imbalance of coupling capacitance between the read/write portbit line BL130 and the complementary read/write port bit line BLB132. As a result, theSRAM cell100 suffers from a mismatch between read and write operations, induced by unwanted coupling capacitance and noise.
• FIG. 2A schematically illustrates a conventional dual-port SRAM cell200 that is implemented with eight transistors. The conventional dual-port SRAM cell200 includes twoPMOS transistors202 and204 and sixNMOS transistors206,208,210,212,214, and216. The dual-port SRAM cell200 utilizes two sets of bit lines and complementary bit lines for A port (first read/write port) and B port (second read/write port), respectively. The sources of thePMOS transistors202 and204 are both connected to a supply voltage Vcc, while the sources of theNMOS transistors206 and208 are both connected to a complementary supply voltage, such as ground or Vss. The gates of thePMOS transistor202 andNMOS transistor206 are coupled at a node218, while their drains are also tied together at a node220. The gates of thePMOS transistor204 and the NMOS transistor208 are also coupled together at the node220, and their drains coupled at the node218. The node218 is coupled to an A port (first read/write port) complementary bit line BLB via theNMOS transistor212 as well as to a B port (second read/write port) complementary bit line BLB via theNMOS transistor216. TheNMOS transistor212 is controlled by an A port word line, while theNMOS transistor216 is controlled by a B port word line. The node220 is coupled to an A port bit line BL via theNMOS transistor210 as well as to a B port bit line BL via theNMOS transistor214. TheNMOS transistor210 is controlled by the A port word line while theNMOS transistor214 is controlled by the B port word line.
• FIG. 2B illustrates a layout diagram222 of the metal routing for the conventional dual-port SRAM cell200 shown inFIG. 2A. The layout diagram222 shows interconnections including several supply lines such as a supplyvoltage Vcc line224 and two complementary supplyvoltage Vss lines226 and228 as well as several bit lines and word lines. The bit lines shown are an A portbit line BL230, a complementary A portbit line BLB232, a B portbit line BL234, and a complementary B portbit line BLB236. An A portword line WL238 is shown lined up in parallel with a B portword line WL240. Twolanding pads242 and244 are also implemented in parallel with the bit lines and supply voltage lines. Thelanding pad242 is used for making connections with the A port word line WL238, while thelanding pad244 is used for making connections with the B port word line WL240.
• Although the conventional dual-port SRAM cell200 provides a symmetrical layout structure, there is still a balancing issue induced by the coupling capacitance on the bit lines. For example, the placements of the A portbit line BL230 between the complementary supplyvoltage Vss line226 and thelanding pad242, and the placement of the complementary write portbit line BLB232 between the complementary supplyvoltage Vss line226 and the supplyvoltage Vcc line224 can create an imbalance of coupling capacitance. The same coupling capacitance imbalance issue may occur for the B portbit line BL234 and the complementary B portbit line BLB236, since the B portbit line BL234 is placed between the complementary supplyvoltage Vss line228 and thelanding pad244 and the complementary B portbit line BLB236 is placed between the complementary supplyvoltage Vss line228 and the supplyvoltage Vcc line224. An imbalance between the coupling capacitance of the interconnection wires may result in an undesired level of noise margin, thereby hindering the operation speed of the cell.
• As such, desirable in the art of integrated circuit designs are new SRAM cell structures with balanced read and write operation speeds and an improved noise margin.
SUMMARY
• The present invention discloses a multiple-port SRAM cell structure. In one embodiment of the invention, the cell structure includes a latch having a first node and a second node for retaining a value and a complementary value, respectively; a first NMOS transistor coupled between the first node and a read/write port bit line, with its gate controlled by a read/write word line; a second NMOS transistor coupled between the second node and a read/write port complementary bit line, with its gate controlled by the read/write word line; a third NMOS transistor having a gate coupled to the second node, and a source coupled to a complementary supply voltage; a fourth NMOS transistor having a source coupled to a drain of the third NMOS transistor, a drain coupled to a read port bit line, and a gate coupled to a read word line; a fifth NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage; and a sixth NMOS transistor having a source coupled to a drain of the fifth NMOS transistor, a drain coupled to a read port complementary bit line, and a gate coupled to the read word line. In a layout view of the multiple-port SRAM cell, the read port bit line, read port complementary bit line, read/write port bit line and read/write port complementary bit line are separated by at least one supply voltage line, one or more complementary supply voltage lines, and one or more word line landing pads.
• The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1A schematically illustrates a conventional two-port SRAM cell implemented with eight transistors.
• FIG. 1B illustrates a layout diagram of the metal routing for the conventional two-port SRAM cell shown inFIG. 1A.
• FIG. 2A schematically illustrates a conventional dual-port SRAM cell implemented with eight transistors.
• FIG. 2B illustrates a layout diagram of the metal routing for the conventional dual-port SRAM cell shown inFIG. 2A.
• FIG. 3A schematically illustrates a two-port SRAM cell implemented with ten transistors in accordance with one embodiment of the present invention.
• FIGS. 3B and 3C illustrate two layout diagrams of the metal routing for the two-port SRAM cell shown inFIG. 3A in accordance with various embodiments of the present invention.
• FIG. 4A schematically illustrates a multiple-port SRAM cell implemented with fourteen transistors in accordance with another embodiment of the present invention.
• FIG. 4B illustrates a layout diagram of the metal routing for the multiple-port SRAM cell shown inFIG. 4A in accordance with yet another embodiment of the present invention.
DESCRIPTION
• This invention is related to a multiple-port SRAM cell with a symmetric layout structure in order to achieve balanced read and write operation speeds and an improved noise margin. The following merely illustrates various embodiments of the present invention for purposes of explaining the principles thereof. It is understood that those skilled in the art will be able to devise various equivalents that, although not explicitly described herein, embody the principles of this invention.
• FIG. 3A illustrates a circuit diagram of a two-port SRAM cell300 that is implemented with ten transistors in accordance with one embodiment of the present invention. The two-port SRAM device300 includes twoPMOS transistors302 and304 and eightNMOS transistors306,308,310,312,314,316,318, and320. In the read/write port portion of this two-port SRAM cell300, thePMOS transistors302 and304 are used as pull-up devices, theNMOS transistors306 and308 are used as pull-down devices, and theNMOS transistors310 and312 are used as pass-gate devices. The sources of thePMOS transistors302 and304 are both connected to a supply voltage Vcc, while the sources of theNMOS transistors306 and308 are both connected to a complementary supply voltage, such as ground or Vss. The gates of thePMOS transistor302 andNMOS transistor306 are coupled at anode322, while their drains are also tied together at anode324. ThePMOS transistor304 and theNMOS transistor308 are also coupled together at the gates at thenode324 and at the drains at thenode322. Thenode322 is coupled to the read/write port complementary bit line BLB via theNMOS transistor312, which is controlled by a read/write word line WL connected to its gate. Thenode324 is coupled to the read/write port bit line BL via theNMOS transistor310, which is also controlled by the same read/write word line WL via its gate. The combination of thetransistors302,304,306,308,310 and312 can be alternatively seen as a latch into which a value and its complement can be written.
• The read port portion of this two-port SRAM device300 includes theNMOS transistors314,316,318, and320. TheNMOS transistors314 and318 are utilized as pull-down devices, and theNMOS transistors316 and320 are used as pass-gate devices. Thetransistors314 and316 can be seen as one read pair to be coupled with the read port bit line BL, while thetransistors318 and320 can be seen as another read pair to be coupled with the read port complementary bit line BLB. A gate of theNMOS transistor314 is connected to thenode322, while its source is tied to the complementary supply voltage Vss. A high signal at thenode322 can turn on theNMOS transistor314, and ground the read port bit line BL when theNMOS transistor316 is turned on by a high signal on the read word line WL. A gate of theNMOS transistor318 is connected to thenode324, while its source is tied to the complementary supply voltage Vss. A high signal at thenode324 can turn theNMOS transistor318 on and ground the read port complementary bit line BLB when theNMOS transistor320 is turned on by a high signal on the read word line WL.
• Before write operation of read/write port, the read/write port bit lines BL is pre-charged (to high state) and the complementary read/write port bit line BLB is dis-changed (to low state). The logic states on the bit line BL and the complementary bit line BLB can be inversed depending on the value to be written into the cell. The read/write word line WL is then pulled high to turn on theNMOS transistors310 and312 to allow the data to be stored in the cell.
• This read/write port also can serve for data read purposes. In read operation, both read/write port bit lines BL and BLB are pre-charged. The read/write word line WL is then pulled high to turn on theNMOS transistors310 and312 to allow the data to be read by sensing circuits. The bit cells data can also be read by the read port. During read port sensing operation, the read word line WL is pulled high to turn on theNMOS transistors316 and320. If a high signal is at thenode322 and a low signal is at thenode324, theNMOS transistor318 will be turned on pulling the read port complementary bit line BLB low to ground, while theNMOS transistor314 remains at an off-state keeping the read port bit line BL high.
• FIG. 3B illustrates a layout diagram326 of the metal routing for the two-port SRAM device300 shown inFIG. 3A in accordance with one embodiment of the present invention. The layout diagram326 shows the metal routing for most of the interconnections used within the two-port SRAM device300 ofFIG. 3A. These interconnections include several supply lines such as a supplyvoltage Vcc line328, two complementary supplyvoltage Vss lines330 and332, wordline landing pads350,346,348 and352, as well as several bit lines and word lines. The bit lines shown include a read/write portbit line BL334, a read/write port complementarybit line BLB336, a read portbit line BL338, and a read port complementarybit line BLB340. A readword line WL342 is shown lined up in parallel with a read/writeword line WL344. Fourlanding pads346,348,350, and352 are also implemented in parallel with the bit lines and supply lines. Thelanding pads346 and348 are used for making connections with the read/writeword line WL344, while thelanding pads350 and352 are used for making connections with the readword line WL342. With this structure, the length ratio between the bit lines and the word lines can be made less than about ¼ for high speed SRAM devices.
• In order to prevent coupling capacitance imbalance from occurring, each bit line is designed to be separated by a landing pad or a supply line such as the supplyvoltage Vcc line328 or the complementary supplyvoltage Vss line330 or332. The placement of the metals within this layout structure is also fully symmetrical, thus allowing a balance performance for the cell current and RC delay between the bit lines and the complementary bit lines. In other words, a set of conductor lines including the read portbit line BL338, the read port complementarybit line BLB340, the read/write portbit line BL334, and the read/write port complementarybit line BLB336 are separated from one another by a set of separators including the complementary supplyvoltage Vss lines330 and332, the supplyvoltage Vcc line328, and thelanding pads346,348,350 and352.
• Note that the layout direction of the N-well and the P-well, which are not shown in this figure, are in parallel with the bit lines along the shorter side of the SRAM cell, and each SRAM cell has one N-well located between two P-wells. The word lines, such as the readword line WL342 and the read/writeword line WL344, are placed in a perpendicular direction to the bit lines.
• FIG. 3C illustrates an alternative layout diagram354 of the metal routing for the two-port SRAM cell300 shown inFIG. 3A in accordance with another embodiment of the present invention. This alternative layout diagram354 is similar to the layout diagram326 shown inFIG. 3B where the exact same interconnections used within the layout in diagram326 are also used within this alternative layout diagram354. One difference between the layout diagrams326 and354 is the placements of four metal routings. The placement of the complementary supplyvoltage Vss line330 is switched with the placement of thelanding pad346, and the placement of the complementary supplyvoltage Vss line332 is switched with the placement of thelanding pad348.
• Similar to the layout diagram326 shown inFIG. 3B, each bit line in this structure is designed to be separated by a landing pad or a supply line, and the placement of the metals within this layout structure is also fully symmetrical, thus allowing a balance performance for the cell current and RC delay between the bit lines and the complementary bit lines.
• FIG. 4A illustrates a circuit diagram of a multiple-port SRAM cell400 that is implemented with fourteen transistors in accordance with another embodiment of the present invention. By implementing multiple ports for a SRAM cell, more read ports can be created to increase the read/write operation speed. The multiple-port SRAM cell400 includes twoPMOS transistors402,404 and twelveNMOS transistors406,408,410,412,414,416,418,420,422,424,426, and428. In the read/write port portion of this multiple-port SRAM device400, thePMOS transistors402 and404 are used as pull-up devices while theNMOS transistors406 and408 are used as pull-down devices, and theNMOS transistors410 and412 are used as pass-gate devices. The sources of thePMOS transistors402 and404 are both connected to a supply voltage Vcc while the sources of theNMOS transistors406 and408 are both connected to a complementary supply voltage Vss. The gates of thePMOS transistor402 andNMOS transistor406 are coupled at anode430, while their drains are also tied together at a node432. ThePMOS transistor404 and theNMOS transistor408 are also coupled together at the gates at the node432 and at the drains at thenode430. Thenode430 is coupled to the read/write port complementary bit line BLB via the NMOS transistor412, which is controlled by a read/write word line WL connected to its gate. The node432 is coupled to the read/write port bit line BL via theNMOS transistor410, which is also controlled by the same read/write word line WL via its gate. The combination of thetransistors402,404,406,408,410 and412 can be alternatively seen as a latch to which a value and its complement can be written.
• Since there are multiple read ports for this multiple-port SRAM cell400, the number of transistors implemented within the read port portion will also be higher. The first read port portion of this multiple-port SRAM cell400 includes fourNMOS transistors414,416,418, and420, while the second read port portion of this multiple-port SRAM cell400 includes fourNMOS transistors422,424,426, and428. TheNMOS transistors414 and418 are utilized as pull-down devices for the first read port, and theNMOS transistors416 and420 are used as pass-gate devices for the first read port. TheNMOS transistors422 and426 are utilized as pull-down devices for the second read port, and theNMOS transistors424 and428 are used as pass-gate devices for the second read port. The gates of theNMOS transistors414 and422 are both connected to thenode430, while both sources of theNMOS transistors414 and422 are tied to the complementary supply voltage Vss. A high signal at thenode430 will turn bothNMOS transistors414 and422 on allowing both first read port bit line BL and second read port bit line BL to be pulled low to the ground when theNMOS transistors416 and424 are turned on by a high signal on the read word line WL. The gates of theNMOS transistors418 and426 are both connected to the node432 while both sources of theNMOS transistors418 and426 are tied to the supply ground Vss. A high signal at the node432 will turn bothNMOS transistors418 and426 on allowing both first read port complementary bit line BLB and second read port complementary bit line BLB to be pulled low to the ground when theNMOS transistors420 and428 are turned on by a high signal on the read word line WL.
• Before a write operation, the read/write port bit lines BL is pre-charged (to high state) and the complementary read/write port bit line BLB is dis-changed (to low state). The logic states on the bit line BL and the complementary bit line BLB can be inversed depending on a value to be written into the cell. The read/write word line WL is then pulled high to turn on theNMOS transistors410 and410 to allow the data to be stored in the cell.
• During sensing operation, the read word line WL for both the first and the second read ports are pulled high to turn on theNMOS transistors416,420,424, and428. If a high signal is at the node432 and a low signal is at thenode430, theNMOS transistors418 and426 will be turned on, thus pulling the first read complementary port bit line BLB and the second read complementary port bit line BLB low to the ground, while theNMOS transistors414 and422 remain at off-states, thus keeping both the first read port bit line BL and the second read port bit line BL high.
• It is understood by those skilled in the art that the number of read ports needs not be limited to the two illustrated inFIG. 4A, and may be increased without deviating from the spirit of this invention.
• FIG. 4B illustrates a layout diagram434 of the metal routing for the multiple-port SRAM cell400 shown inFIG. 4A in accordance with another embodiment of the present invention.
• The layout diagram434 shows the metal routing for most of the interconnections used within the multiple-port SRAM cell400 ofFIG. 4A. These interconnections include several supply lines such as a supplyvoltage Vcc line436 and two complementary supplyvoltage Vss lines438 and440 as well as several bit lines and word lines. The bit lines shown include a read/write portbit line BL442, a read/write port complementarybit line BLB444, a first read portbit line BL446, a first read port complementarybit line BLB448, a second read portbit line BL450, and a second read port complementarybit line BLB452. A readword line WL454 is shown lined up in parallel with a read/writeword line WL456. Sixlanding pads458,460,462,464,466, and468 are also implemented in parallel with the bit lines and supply lines. Thelanding pads458 and460 are used for making connections with the read/writeword line WL456 while thelanding pads462,464,466, and468 are used for making connections with the readword line WL454.
• Similar to the examples shown inFIGS. 3B and 3C, the placement of the metals within this layout diagram434 is also fully symmetrical, thus allowing a balance performance for read and write operations. With this structure, the length ratio between the bit lines and the word lines for this layout structure can be made less than about ⅕ for high speed SRAM devices.
• Note that the layout direction of the N-well and the P-well, which are not shown in this figure, are in parallel with the bit lines along the shorter side of the SRAM cell, and each SRAM cell has one N-well located between two P-wells. The word lines, such as the readword line WL454 and the writeword line WL456, are placed in perpendicular direction to the bit lines.
• By implementing a symmetrical layout structure for a SRAM cell, a stable and high speed two-port or multiple-port SRAM device can be created. The symmetrical nature of this invention provides a high speed and fully speed-balanced SRAM cell structure between both read cycles and write cycles. Proposed metal routings also provide fully noise shielding to prevent coupling capacitance imbalance between interconnections, thereby improving noise margins.
• The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.
• Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.

Claims (20)

1. A static random access memory (SRAM) cell having a dedicated read port separated from a write port, the SRAM cell comprising:

a first and a second bit-line placed in parallel forming a complimentary bit-line pair for the dedicated read port;

a first and second metal line adjacently flanking in both side of and in parallel to the first bit-line, the first and second metal line being formed in the same metal layer as the first bit-line and having a first and second predetermined distance to the first bit-line, respectively; and

a third and fourth metal line adjacently flanking in both side of and in parallel to the second bit-line, the third and fourth metal line being formed in the same metal layer as the second bit-line and having a third and fourth predetermined distance to the second bit-line, respectively,

wherein the first predetermined distance is equal to the third distance and the second predetermined distance is equal to the fourth distance for keeping the first and second bit-lines having balanced capacitance loading.

2. The SRAM cell ofclaim 1, wherein the first and second bit-lines are formed in the same metal layer and have substantially the same width for having balanced resistance and capacitance loading.

3. The SRAM cell ofclaim 1, wherein both the first and the third metal lines are high voltage power supply lines while both the second and the fourth metal lines are for word line landing pad.

4. The SRAM cell ofclaim 1, wherein both the first and the fourth metal lines are high voltage power supply lines while both the second and the third metal lines are for word line landing pad.

5. The SRAM cell ofclaim 1, wherein both the first and the third metal lines are high voltage power supply lines while both the second and the fourth metal lines are complimentary low voltage power supply lines.

6. The SRAM cell ofclaim 1, wherein both the first and the fourth metal lines are high voltage power supply lines while both the second and the third metal lines are complimentary low voltage power supply lines.

7. The SRAM cell ofclaim 1 further comprising:

a latch having a first and a second storage node, the first and the second storage node always storing complimentary values;

a first NMOS transistor having a source, a drain and a gate coupled to the complimentary low voltage supply, the first bit-line and the second node, respectively; and

a second NMOS transistor having a source, a drain and a gate coupled to the complimentary low voltage supply, the second bit-line and the first node, respectively.

8. The SRAM cell ofclaim 7 further comprising:

a third NMOS transistor having a source and a drain coupled between the drain of the first NMOS transistor and the first bit-line, the third NMOS transistor having a gate coupled to a read word-line; and

a fourth NMOS transistor having a source and a drain coupled between the drain of the second NMOS transistor and the second bit-line, the fourth NMOS transistor having a gate also coupled to the read word-line.

9. The SRAM cell ofclaim 1 further comprising:

a third and a fourth bit-line placed in parallel forming a complimentary bit-line pair for the write port;

a fifth NMOS transistor having a source and drain coupled between the third bit-line and the first storage node, the fifth NMOS transistor having a gate coupled to a write word-line; and

a sixth NMOS transistor having a source and drain coupled between the fourth bit-line and the second storage node, the sixth NMOS transistor having a gate coupled to the write word-line.

10. A multiple-port static random access memory (SRAM) device having a plurality of cells, each of which comprises:

a latch having a first node and a second node for retaining a value and a complementary value, respectively;

a first NMOS transistor coupled between the first node and a read/write port bit line, with its gate controlled by a read/write word line;

a second NMOS transistor coupled between the second node and a read/write port complementary bit line, with its gate controlled by the read/write word line;

a third NMOS transistor having a gate coupled to the second node, and a source coupled to a complementary supply voltage;

a fourth NMOS transistor having a source coupled to a drain of the third NMOS transistor, a drain coupled to a first read port bit line, and a gate coupled to a read word line;

a fifth NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage;

a sixth NMOS transistor having a source coupled to a drain of the fifth NMOS transistor, a drain coupled to a first read port complementary bit line, and a gate coupled to the read word line;

a seventh NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage;

an eighth NMOS transistor having a source coupled to a drain of the seventh NMOS transistor, a drain coupled to a second read port bit line, and a gate coupled to the read word line;

a ninth NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage; and

a tenth NMOS transistor having a source coupled to a drain of the ninth NMOS transistor, a drain coupled to a second read port complementary bit line, and a gate coupled to the read word line,

wherein, in a layout view of the cell, the first read port bit line, first read port complementary bit line, second read port bit line, second read port complementary bit line, read/write port bit line and read/write port complementary bit line are separated by at least one supply voltage line, one or more complementary supply voltage lines, and one or more word line landing pads.

11. The multiple-port SRAM device ofclaim 10, wherein the first read port bit line, the first read port complementary bit line, the second read port bit line, the second complementary read port bit line, the read/write port bit line, the read/write port complementary bit line, the supply voltage line, the complementary supply voltage lines, and the word line landing pads are constructed on the same metallization layer.

12. The multiple-port SRAM device ofclaim 11, wherein the read word line and the read/write word line are constructed on a metallization layer above the metallization layer on which the first read port bit line, the first read port complementary bit line, the second read port bit line, the second read port complementary bit line, the read/write port bit line, the read/write port complementary bit line, the supply voltage line, the complementary supply voltage lines, and the word line landing pads are constructed.

13. The multiple-port SRAM device ofclaim 12, wherein the first read port bit line, the first read port complementary bit line, the second read port bit line, the second read port complementary bit line, the read/write port bit line, the read/write port complementary bit line, the supply voltage line, the complementary supply voltage lines, and the word line landing pads are arranged in substantial parallel with one another.

14. The multiple-port SRAM device ofclaim 13, wherein the second read port bit line and the first read port bit line are separated by the word line landing pad.

15. The multiple-port SRAM device ofclaim 14, wherein the first read port bit line and the read/write port bit line are separated by the word line landing pad and the complementary supply voltage line.

16. The multiple-port SRAM device ofclaim 15, wherein the read/write port bit line and the read/write port complementary bit line are separated by the supply voltage line.

17. The multiple-port SRAM device ofclaim 16, wherein the write port complementary bit line and the first read port complementary bit line are separated by the complementary supply voltage line and the word line landing pad.

18. The multiple-port SRAM device ofclaim 17, wherein the first read port complementary bit line and the second read port complementary bit line are separated by the word line landing pad.

19. The multiple-port SRAM device ofclaim 18 has at least six word line landing pads for connecting the read word line and the read/write word line to the gates of the first, second, fourth, sixth, eighth and tenth NMOS transistors.

20. The multiple-port SRAM device ofclaim 10, wherein a length ratio between the bit line and the word line is less than about ⅕.

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