US20090148970A1 - Method for manufacturing semiconductor device - Google Patents

Abstract

To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate TFT structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, a step of lifting off using a halftone mask or a gray-tone mask and a step of reflowing a photoresist are used.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to a method for manufacturing semiconductor devices, in particular, a method for manufacturing active matrix display devices.
• 2. Description of the Related Art
• Heretofore, liquid crystal display devices utilizing, as switching elements, TFTs each formed using amorphous silicon have been often used as display devices which have been widely used, such as liquid crystal televisions, displays of personal computers, and cellular phones. A technique by which a TFT is formed using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The TFT has been widely applied to electronic devices such as ICs and electro-optical devices and particularly developed as a switching element of an image display device.
• For a TFT using amorphous silicon, a layered structure has been conventionally formed through a photolithography process using five or more photomasks. Reduction in photolithography process using photomasks has been desired. Heretofore, each of Patent Document 1 (Japanese Published Patent Application No. 2000-131719) and Patent Document 2 (Japanese Published Patent Application No. 2003-45893) has been known as a technique achieving reduction in number of steps in a photolithography process using photomasks.
• FIGS. 10A to 10E are structural views illustrating a conventional TFT using amorphous silicon.
• The manufacturing process thereof is described, Agate electrode501 is formed over aglass substrate500 by a photolithography step using a first photomask (FIG. 10A).
• A gateinsulating film502, an i-typeamorphous silicon layer503, and an n⁺-typeamorphous silicon layer504 are formed. The i-typeamorphous silicon layer503 and the n⁺-typeamorphous silicon layer504 form an island region by a photolithography step using a second photomask (FIG. 10B).
• A source electrode508 and adrain electrode509 are formed by a photolithography step using a third photomask. At that time, a photoresist formed by the third photomask is successively utilized to etch the n⁺-type amorphous silicon layer so that achannel region505, asource region506, and adrain region507 are formed.
• Aprotective film510 is formed, and a contact hole through which a contact with apixel electrode511 is made is formed by a photolithography step using a fourth photomask (FIG. 1C).
• Indium tin oxide (ITO) is formed, and thepixel electrode511 is formed by a photolithography step using a fifth photomask (FIGS. 10D and 10E).
• Photolithography steps using a photomask includes application of a photoresist, pre-baking, a step of light exposure using a metal photomask, a step of development, post-baking, a step of etching, a step of resist separation, and the like. In addition, many steps such as a step of cleaning and a step of inspection are included in the photolithography steps. Thus, performing the conventional process using five photomasks means that the steps are repeated five times, which is a significant factor in the decrease in throughput in the manufacturing process or the increase in manufacturing cost.
SUMMARY OF THE INVENTION
• Therefore, reduction in number of photomasks means reduction in manufacturing time and manufacturing cost and thus has been anticipated. In view of mass production, reduction in number of photomasks has been a major object. Further, reduction in number of steps is another object.
• In order to achieve the above objects, the present invention adopts a channel-etched bottom gate TFT structure in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, in which a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, the present invention includes a step of lifting off using a halftone mask or a gray-tone mask and a step of performing a reflow process on a photoresist. The step of lifting off is a method in which a pattern other than a target pattern is formed of a photoresist or the like over a substrate, a target thin film is formed, and then an unnecessary portion which overlaps with the photoresist and the photoresist are removed together so that the target pattern is left. The reflow process is a step of processing a photoresist over a substrate by heat treatment or chemical treatment. By repeating combination of the step of lifting off and mask alignment, a thin film of which thickness partially varies or a thin film in which substances partially vary can be patterned.
• According to an aspect of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; etching the first conductive film using a first photoresist to form a gate electrode; forming a gate insulating film over the gate electrode; forming a first semiconductor layer (e.g. an i-type semiconductor layer) over the gate insulating film; forming a second semiconductor layer including the impurity element imparting one conductivity type (e.g. an n⁺-type semiconductor layer) over the first semiconductor layer; performing rear surface exposure to form a second photoresist; etching the first semiconductor layer and the second semiconductor layer to form a first semiconductor island and a second semiconductor island using the second photoresist; forming a second conductive film over the second semiconductor island; forming a third photoresist using a multi-tone mask; etching the second conductive film, the second semiconductor island, and the first semiconductor island using the third photoresist; ashing the third photoresist; etching the second conductive film using the third photoresist having been ashed to form a source electrode and a drain electrode; etching the second semiconductor island and the first semiconductor island using the third photoresist having been ashed to form a channel region, a source region, and a drain region; forming an insulating film over the source electrode and the drain electrode; forming a contact hole in the insulating film using a fourth photoresist; forming a conductive film over the insulating film; and etching the conductive film using a fifth photoresist to form a pixel electrode.
• According to another aspect of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; etching the first conductive film using a first photoresist to form a gate electrode; forming a gate insulating film over the gate electrode; forming a first semiconductor layer (e.g. an i-type semiconductor layer) over the gate insulating film; forming a second semiconductor layer including the impurity element imparting one conductivity type (e.g. an n⁺-type semiconductor layer) over the first semiconductor layer; performing rear surface exposure to form a second photoresist; etching the first semiconductor layer and the second semiconductor layer to form a first semiconductor island and a second semiconductor island using the second photoresist; forming a second conductive film over the second semiconductor layer; forming a third photoresist using a first multi-tone mask; etching the second conductive film, the second semiconductor layer, and the first semiconductor layer using the third photoresist; ashing the third photoresist; etching the second conductive film using the third photoresist having been ashed to form a source electrode and a drain electrode; etching the second semiconductor layer and the first semiconductor layer using the third photoresist having been ashed to form a channel region, a source region, and a drain region; forming a fourth photoresist using a second multi-tone mask; forming a contact hole in the gate insulating film using the fourth photoresist; ashing the fourth photoresist; forming a conductive film over the fourth photoresist having been ashed; removing the fourth photoresist having been ashed and the conductive film formed over the fourth photoresist together to form a pixel electrode; forming an insulating film over the pixel electrode; performing rear surface exposure to form a fifth photoresist over the insulating film; performing a reflow process on the fifth photoresist; and etching the insulating film using the fifth photoresist having been subjected to the reflow process.
• Owing to the advantageous effect of the present invention, whereas a conventional amorphous silicon TFT is manufactured using five photomasks, a TFT can be manufactured using four or three photomasks and thus manufacturing time and cost can be reduced. Further, since rear surface exposure is performed, a self-aligning step is performed and thus a step of aligning the photomask is not required. In the self-aligning step, it doesn't occur that the photomask is out of position; therefore, a margin for misalignment is not required and a more refined pattern can be formed. Further, a channel region is protected from light from external by a gate electrode, so that an increase of a leakage current when the TFT is off can be suppressed.
• Further, by adopting a reflow process, the TFT is entirely covered with an insulating film and thus reliability of elements can be improved. That is, an end portion of a source electrode can be surely covered so that a TFT can be prevented from being contaminated. An i-type amorphous silicon layer, an n⁺-type amorphous silicon layer, a source metal, and a drain metal are etched all at once by the conventional halftone technique. Therefore, the i-type amorphous silicon layer is connected between the elements. Meanwhile, in the present invention, before formation of a source metal and a drain metal, only an i-type amorphous silicon layer and an n⁺-type amorphous silicon layer are formed into an island region by using a photoresist patterned desirably by rear surface exposure; therefore, the i-type amorphous silicon layer is cut and thus the elements can be more surely separated from each other.
BRIEF DESCRIPTION OF THE DRAWINGS
• In the accompanying drawings:
• FIGS. 1A to 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention;
• FIGS. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention;
• FIGS. 3A to 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention;
• FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention;
• FIGS. 5A and 5B are a top plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention, respectively;
• FIGS. 6A to 6E are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention;
• FIGS. 7A to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention;
• FIGS. 8A to 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention;
• FIGS. 9A to 9D are cross-sectional views each illustrating a periphery of a pixel portion of a semiconductor device of the present invention;
• FIGS. 10A to 10E are cross-sectional views illustrating a method for manufacturing a conventional semiconductor device;
• FIGS. 11A to 11C are diagrams each illustrating a semiconductor device of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
• Embodiment modes of the present invention will be described below.
• The present invention relates to a semiconductor device manufactured using four or three photomasks to reduce the number of steps in the conventional process using five photomasks and a manufacturing method thereof.
• FIGS. 1A to 1E,FIGS. 2A to 2D,FIGS. 3A to 3C,FIG. 4,FIGS. 5A and 5B,FIGS. 6A to 6E,FIGS. 7A to 7D,FIGS. 8A to 8C, andFIGS. 9A to 9D are views each illustrating a manufacturing method of the present invention.
• In this embodiment mode, a photoresist is selectively exposed to light by rear surface exposure using a gate wiring material as a photomask to obtain a desired pattern so that an island region is formed. Further, a channel region, a source region, a drain region, a source wiring, and a drain wiring are formed by a halftone exposure technique. Although a halftone exposure technique is used in this embodiment mode, a gray tone exposure technique may be used. The combination of the features enables the process using four photomasks which is fewer than five photomasks used for the conventional process. Further, by using a halftone exposure technique, the process using three photomasks becomes possible.
Embodiment Mode 1
• The process using four photomasks of the present invention will be described with reference toFIGS. 1A to 1E,FIGS. 2A to 2D, andFIGS. 3A to 3C.
• InFIG. 1A, a metal film is stacked over aglass substrate100 by a sputtering method. The glass substrate is allowable as long as it has a light transmitting property. Barium borosilicate glass or aluminoborosilicate glass, which is typified by the No. 7059 or No. 1737 glass manufactured by Corning Inc., may be used. Alternatively, a light-transmitting substrate such as a quartz substrate or a plastic substrate may be used. A first photomask is used to form a desired photoresist and then the metal film is etched, so that agate electrode101 and a gate wiring are formed. Thegate electrode101 and the gate wiring are desirably formed of a low resistant conductive material such as aluminum (Al) or copper (Cu); however, since aluminum alone has disadvantages such as low heat resistance and a tendency to be corroded, it is used in combination with a material having both heat resistance and conductivity to form thegate electrode101 and the gate wiring. An AgPdCu alloy may be used as a low resistant conductive material. As a material having both heat resistance and conductivity, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and neodymium (Nd), an alloy containing any of the above elements as its component, an alloy film combining any of the above elements, or nitride containing any of the above elements as its component. The gate electrode and the gate wiring comprise a conductive film containing any of the above elements or a layered structure of the abovementioned conductive films. For example, a stack of titanium and copper or a stack of tantalum nitride and copper can be used. In the case where a low resistant conductive material is used in combination with a material having both heat resistance and conductivity such as titanium, silicon, chromium, or neodymium, flatness is improved, which is preferable. Alternatively, only such materials having both heat resistance and conductivity, for example, molybdenum and tungsten, may be used in combination.
• InFIG. 1B, an insulatingfilm102, an i-typeamorphous silicon layer103, and an n⁺-typeamorphous silicon layer104 are sequentially formed over thegate electrode101. The insulatingfilm102 is to form thegate insulating film102 later and formed to have, for example, a single-layer structure of a silicon nitride film, a silicon oxide film, or a silicon oxynitride film or a layered structure of any of the above films. It is needless to say that the material of the gate insulating film is not limited to the above materials and may have a single-layer or layered structure using any other insulating film such as a tantalum oxide film. The i-typeamorphous silicon layer103 and the n⁺-typeamorphous silicon layer104 are to form a channel region, a source region, and a drain region later. The i-typeamorphous silicon layer103 is a non-doped layer which does not contain an impurity imparting conductivity. The i-typeamorphous silicon layer103 may contain a very small amount of impurities. Also, the n⁺-typeamorphous silicon layer104 is a semiconductor film containing an impurity element imparting one conductivity type, in particular, an n-type semiconductor layer containing phosphorus at high concentration. The insulatingfilm102, the i-typeamorphous silicon layer103, and the n⁺-typeamorphous silicon layer104 are formed by a CVD method. A multi-chamber CVD apparatus enables even successive film formation. They are thus formed by not being exposed to the air, so that an impurity is prevented from being mixed. Although a CVD method is used in this embodiment mode, a sputtering method or the like may alternatively be used.
• InFIG. 1C, aphotoresist121 formed over the n⁺-typeamorphous silicon layer104 is selectively exposed to light by rear surface exposure with the metal film of thegate electrode101 and the gate wiring as a photomask, so that a desirable photoresist pattern is formed. By rear surface exposure, light transmits a thin film and thephotoresist121 is exposed to light; therefore, the layers other than thegate wiring101, that is, the i-typeamorphous silicon layer103 and the n⁺-typeamorphous silicon layer104 are necessarily thin enough to be exposed to light. That is to say, light transmits the i-typeamorphous silicon layer103 and the n⁺-typeamorphous silicon layer104 to expose thephotoresist121. By using the photoresist pattern formed by rear surface exposure, the i-typeamorphous silicon layer103 and the n⁺-typeamorphous silicon layer104 are etched to form an i-typeamorphous silicon island123 and an n⁺-typeamorphous silicon island124 as shown inFIG. 1D. In the case of performing rear surface exposure, a self-aligning step is performed and thus a step of aligning the photomask is not required, so that etching can be performed in a self-aligned manner while the photoresist pattern after exposure is not misaligned.
• InFIG. 1E, ametal film105 is formed over an entire surface of the substrate. Themetal film105 is to form a source electrode, a drain electrode, and a source wiring later. The material of themetal film105 is allowable as long as it is a metal material which can provide ohmic contact with the n⁺-typeamorphous silicon island124, and an element selected from aluminum, chromium, tantalum, and titanium, an alloy containing any of the above elements as its component, an alloy film combining any of the above elements, and the like are given.
• InFIG. 2A, aphotoresist1 is formed using a second photomask. For thephotoresist1, a halftone exposure technique is used. That is, a photoresist of which thickness varies is formed. Parts which are to form a source electrode, a drain electrode, and a source wiring are formed thick and a part which is to form a channel is formed thin.
• InFIG. 2B, etching is performed using thephotoresist1. Thus, awiring106 is formed.
• InFIG. 2C, thephotoresist1 is subjected to ashing treatment to be processed such that the shape of thephotoresist1 is like that of a photoresist2 ofFIG. 2C. That is, the part of the photoresist, which has been formed thin, is exposed.
• InFIG. 2D, the photoresist2 which has been processed by ashing is used to etch themetal film105 so that thesource electrode110 and thedrain electrode111 are formed. Similarly, the photoresist2 is used to etch the n⁺-typeamorphous silicon island124 and the i-typeamorphous silicon island123 so that achannel region107, asource region108, and adrain region109 are formed. The i-type amorphous silicon layer which overlaps with thegate electrode101 with thegate insulating film102 interposed therebetween forms achannel formation region107. After that, the photoresist2 is removed by separation.
• InFIG. 3A, an insulating film is formed over an entire surface of the substrate to serve as aprotective film112. The insulating film serving as the protective film may be a silicon nitride film, a silicon oxide film, or a stack of the films. The silicon nitride film is particularly preferred because of high passivation performance thereof.
• InFIG. 3B, an opening of a contact portion, which exposes thedrain electrode111, is formed by a photoresist3 formed using a third photomask.
• InFIG. 3C, ITO is formed over an entire surface of the substrate, a desired photoresist is formed using a fourth photomask, and apixel electrode113 is formed using the photoresist. Although ITO is used as a pixel electrode material in this embodiment mode, tin oxide, indium oxide, nickel oxide, zinc oxide, or a compound of any of the above may be used as a transparent conductive material, for example.
• Although the i-type amorphous silicon layer is used as achannel region107 in this embodiment mode, it is also possible that a microcrystal semiconductor film (also referred to as a semi-amorphous semiconductor film) be formed, a buffer layer be formed over the microcrystal semiconductor film, and an n⁺-type amorphous silicon layer be formed over the buffer layer. The buffer layer may be an amorphous silicon layer and preferably contains one or more of nitrogen, hydrogen, and halogen. The amorphous silicon layer contains any one or more of nitrogen, hydrogen, and halogen, so that a crystal grain contained in the microcrystal semiconductor film can be prevented from being oxidized. The buffer layer is formed between the source region and the drain region; therefore, a TFT has higher mobility, a smaller amount of leakage current, and a higher withstand voltage.
• FIG. 4 illustrates a TFT in which amicrocrystalline semiconductor film201 and abuffer layer202 are formed in this order as a channel region instead of the i-type amorphous silicon layer. By using themicrocrystalline semiconductor film201 and thebuffer layer202 instead of the i-type amorphous silicon layer, the TFT can be formed to have higher mobility, a smaller amount of leakage current, and a higher withstand voltage.
• FIG. 5A illustrates a top plan view of the TFT of this embodiment mode. Note that the same reference numerals are used for the parts corresponding to those inFIGS. 1A to 1E,FIGS. 2A to 2D, andFIGS. 3A to 3C.FIG. 5B corresponds to a cross sectional view taken along line A-A′ inFIG. 5A.
• Thus, inverted-staggered n-channel TFTs can be completed through the photolithography process using four photomasks. Then, they are arranged in matrix corresponding to pixels so that a pixel portion is formed, which can be a substrate for fabricating an active matrix electrooptic device.
Embodiment Mode 2
• Next, the process using three photomasks of the present invention will be described with reference toFIGS. 6A to 6E,FIGS. 7A to 7D, andFIGS. 8A to 8C. Description will be made including that of a terminal portion from a step using the second photomask, which requires a halftone exposure technique inFIG. 1E. That is, the step inFIG. 6A follows the step inFIG. 1E.
• InFIG. 6A, a photoresist4 is formed, using the second photomask, over aglass substrate100, agate electrode101, awiring311, an insulatingfilm102, an i-typeamorphous silicon layer123, a semiconductor layer including an impurity element imparting one conductivity type, which is particularly an n⁺amorphous silicon layer124, and ametal layer105. For the photoresist4, a halftone exposure technique is used. That is, a photoresist of which thickness varies is formed. Parts which are to form a drain electrode and a source wiring are formed thick and a part which is to form a channel is formed thin.
• InFIG. 6B, parts of the i-typeamorphous silicon layer303, the n⁺-typeamorphous silicon layer304, and themetal film105, which are not covered with the photoresist4, are etched.
• InFIG. 6C, the photoresist4 is processed by ashing to form a photoresist5.
• InFIG. 6D, asource electrode309 and adrain electrode310 are formed using the photoresist5 processed by ashing. Similarly, achannel region306, asource region307, and adrain region308 are formed using the photoresist5. After that, the photoresist5 is removed. The i-typeamorphous silicon layer123 which overlaps with the gate electrode with the gate insulating film interposed therebetween forms thechannel region306.
• InFIG. 6E, aphotoresist6 is formed using a third photomask. A halftone exposure technique is also used here. Part of the insulatingfilm102, which is not covered with thephotoresist6, is etched to form acontact hole321 so that awiring311 is exposed. Thewiring311 may comprise a single layer or a layered structure using aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and neodymium (Nd). This exposed part forms a connection portion with a transparent conductive film on the terminal portion.
• InFIG. 7A, thephotoresist6 is processed by ashing to form aphotoresist7.
• InFIG. 7B, a transparentconductive film312 is formed over thephotoresist7.
• InFIG. 7C, thephotoresist7 and portions of the transparentconductive film312 formed on thephotoresist7 are removed together by a step of lifting off, so that apixel electrode313 and awiring320 are formed. After that, aprotective film314 is formed over an entire surface of the substrate by a CVD method. An insulating film which serves as the protective film may be a silicon nitride film, a silicon oxide film, or a stack of them. A silicon nitride film is particularly preferred because of high passivation performance thereof.
• InFIG. 7D, a photoresist is applied to theprotective film314 and selectively exposed to light by rear surface exposure, so that a desirably patternedphotoresist8 is formed. Here, thephotoresist8 is not formed over only transparent films, that is, part including only the transparentconductive film312 and the insulating film302 because light is transmitted. Since rear surface exposure is performed, it is preferable that the gate electrode301, thesource electrode309, and thedrain electrode310 sufficiently overlap with each other in the channel region.
• InFIG. 8A, thephotoresist8 formed by the rear surface exposure is subjected to heat treatment as a reflow process. And when seen in section, thephotoresist8 forms a photoresist9 such that an end portion of thephotoresist8 is extended slightly outward. Further, thephotoresist8 is reduced in thickness to form the photoresist9 by the reflow process. Although not illustrated, a range of thephotoresist8, which covers the substrate, is slightly increased when seen from the top surface, so that the photoresist9 is formed. That is, the distance between the edge of the photoresist and the edge of the source electrode and the distance between the edge of the photoresist and the edge of the drain electrode are increased. As the reflow process, chemical treatment may be performed instead of heat treatment.
• InFIG. 8B, theprotective film314 is etched using the photoresist9 formed by slightly extending an end portion of thephotoresist8 outward and thus reducing thephotoresist8 in thickness, so that thepixel electrode313 is partly exposed. The exposed region forms a pixel region. By the reflow process, the end portion of thephotoresist8 is extended slightly outward. Therefore, theprotective film324 after etching is extended so that outer sides of the end portions of the source electrode and the drain electrode can be protected. Thus, a TFT or an electrode in a lower layer can be more surely protected. Further, in a peripheral portion, thecontact hole321 can be surely protected by theprotective film325.
• FIG. 8C is a view in the case where an LCD panel is manufactured using a TFT substrate inFIG. 8B. Acounter substrate319 is provided to face theglass substrate100 over which TFTs are formed. Thecounter substrate319 is provided with acolor filter318. Aliquid crystal315 and aspacer316 are provided between theglass substrate100 and thecounter substrate319 and are sealed with asealant317.
• Thus, inverted-staggered n-channel TFTs can be completed through the photolithography process using three photomasks. Then, they are arranged in matrix corresponding to pixels so that a pixel portion is formed, which can be a substrate for fabricating an active matrix electrooptic device.
Embodiment Mode 3
• Next, the structure of a connection terminal portion connected to a peripheral circuit provided on the periphery of a pixel portion will be described takingFIGS. 9A to 9D as an example.
• FIGS. 9A and 9B each illustrate a structure in the case where a source wiring is lead to an end portion of a substrate.FIG. 9A illustrates the case ofEmbodiment Mode 1 andFIG. 9B illustrates the case of Embodiment Mode 2. Note that the same reference numerals are used for the parts corresponding to those inFIGS. 1A to 1E,FIGS. 2A to 2D,FIGS. 3A to 3C,FIG. 4,FIGS. 5A and 5B,FIGS. 6A to 6E,FIGS. 7A to 7D, andFIGS. 8A to 8C. In the case ofFIG. 9A, theprotective film112 is etched using the photoresist3 inFIG. 3B to expose thewiring106 so that thewiring106 is in contact with the transparentconductive film114. In the case ofFIG. 9B, themetal film105 and the transparentconductive film312 are made to be in contact with each other using thephotoresist7 inFIG. 7B. Then, theprotective film314 is etched using the photoresist9 to expose the transparentconductive film312. The transparentconductive films114 and312 form connection terminals and are each connected to an FPC (flexible printed circuit) with a conductive adhesive such as an anisotropic conductive film interposed therebetween.
• FIGS. 9C and 9D each illustrate a structure in the case where a gate wiring is lead to an end portion of a substrate.FIG. 9C illustrates the case ofEmbodiment Mode 1 andFIG. 9D illustrates the case of Embodiment Mode 2. Note that the same reference numerals are used for the parts corresponding to those inFIGS. 1A to 1E,FIGS. 2A to 2D,FIGS. 3A to 3C,FIG. 4,FIGS. 5A and 5B,FIGS. 6A to 6E,FIGS. 7A to 7D, andFIGS. 8A to 8C. In the case ofFIG. 9C, thegate insulating film102 is exposed using thephotoresist1 inFIG. 2B, and thegate insulating film102 and theprotective film112 are etched using the photoresist3 inFIG. 3B so that the gate wiring is in contact with the transparentconductive film114. In the case ofFIG. 9D, the gate electrode301 is exposed using thephotoresist6 inFIG. 6E, and the gate electrode301 and the transparentconductive film312 are made to be in contact with each other using thephotoresist7 inFIG. 7B. Then, theprotective film314 is etched using the photoresist9 to expose the transparentconductive film312.
• Thus, a semiconductor device can be manufactured by the process using four or three photomasks, in which the number of photomasks is reduced and the number of steps is also reduced, as compared to the conventional process using five photomasks.
• FIGS. 11A to 11C illustrate a television set, a portable information terminal (such as a mobile computer, a cellular phone, a mobile game console, or an electronic book), and a laptop computer, respectively, as examples of a semiconductor device and an electronic appliance of the present invention.
• FIG. 11A illustrates a display device including ahousing1001, adisplay portion1002, speakers1003, avideo input terminal1004, a supportingbase1005, and the like. The display device is manufactured using TFTs formed by the manufacturing method described in any of the aforementioned embodiment modes for thedisplay portion1002 and a driver circuit thereof. Note that as the display device, a liquid crystal display device, a light emitting device, and the like are given. Specifically, the display device includes all display devices for information display, such as those for computers, television broadcasting reception, and advertisement display. According to the present invention, an inexpensive and highly reliable display device can be realized.
• A cellular phone illustrated inFIG. 11B includescontrol switches2001, adisplay portion2002, and the like. According to the present invention, an inexpensive and highly reliable cellular phone can be realized.
• FIG. 11C illustrates a laptop personal computer including amain body3001, adisplay portion3002, and the like. According to the present invention, an inexpensive and highly reliable laptop personal computer can be realized.
• This application is based on Japanese Patent Application serial no. 2007-275781 filed with Japan Patent Office on Oct. 23, 2007, the entire contents of which are hereby incorporated by reference.

Claims (23)

1. A method for manufacturing a semiconductor device, comprising:

forming a first conductive film over a substrate;

etching the first conductive film using a first photoresist to form a gate electrode;

forming a gate insulating film over the gate electrode;

forming a first semiconductor layer over the gate insulating film;

forming a second semiconductor layer including an impurity element imparting one conductivity type over the first semiconductor layer;

performing rear surface exposure to form a second photoresist;

etching the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type using the second photoresist, thereby forming a first semiconductor island and a second semiconductor island including the impurity element imparting one conductivity type;

forming a second conductive film over the substrate;

forming a third photoresist using a multi-tone mask over the second conductive film;

etching the second conductive film using the third photoresist;

ashing the third photoresist;

etching the second conductive film using the ashed third photoresist to form a source electrode and a drain electrode; and

etching the first semiconductor island and the second semiconductor island including the impurity element imparting one conductivity type using the ashed third photoresist to form a channel region, a source region, and a drain region.

2. The method for manufacturing a semiconductor device, according toclaim 1, wherein the multi-tone mask is a halftone mask or a gray-tone mask.

3. The method for manufacturing a semiconductor device, according toclaim 1, wherein the rear surface exposure is performed through the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type.

4. The method for manufacturing a semiconductor device, according toclaim 1, wherein the first semiconductor layer is an amorphous semiconductor layer.

5. The method for manufacturing a semiconductor device, according toclaim 1, wherein the first semiconductor layer is an i-type amorphous silicon layer.

6. A method for manufacturing a semiconductor device, comprising:

forming a first conductive film over a substrate;

etching the first conductive film using a first photoresist to form a gate electrode;

forming a gate insulating film over the gate electrode;

forming a first semiconductor layer over the gate insulating film;

forming a second semiconductor layer including an impurity element imparting one conductivity type over the first semiconductor layer;

performing rear surface exposure to form a second photoresist;

etching, using the second photoresist, the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type, thereby forming a first semiconductor island and a second semiconductor island including the impurity element imparting one conductivity type;

forming a second conductive film over the substrate;

forming a third photoresist using a multi-tone mask over the second conductive film;

etching, using the third photoresist, the second conductive film, the second semiconductor island including the impurity element imparting one conductivity type, and the first semiconductor island to form a wiring;

ashing the third photoresist;

etching the second conductive film using the ashed third photoresist to form a source electrode and a drain electrode;

etching the second semiconductor island including the impurity element imparting one conductivity type and the first semiconductor island using the ashed third photoresist to form a channel region, a source region, and a drain region;

forming a protective film over the substrate;

forming a contact hole in the protective film using a fourth photoresist;

forming a third conductive film over the protective film; and

etching the third conductive film using a fifth photoresist to form a pixel electrode.

7. The method for manufacturing a semiconductor device, according toclaim 6, wherein the multi-tone mask is a halftone mask or a gray-tone mask.

8. The method for manufacturing a semiconductor device, according toclaim 6, wherein the rear surface exposure is performed through the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type.

9. The method for manufacturing a semiconductor device, according toclaim 6, wherein the first semiconductor layer is an amorphous semiconductor layer.

10. The method for manufacturing a semiconductor device, according toclaim 6, wherein the first semiconductor layer is an i-type amorphous silicon layer.

11. The method for manufacturing a semiconductor device, according toclaim 6, wherein the pixel electrode is a transparent conductive film.

12. A method for manufacturing a semiconductor device, comprising:

forming a first conductive film over a substrate;

etching the first conductive film using a first photoresist to form a gate electrode;

forming a gate insulating film over the gate electrode;

forming a first semiconductor layer over the gate insulating film;

forming a second semiconductor layer including an impurity element imparting one conductivity type over the first semiconductor layer;

performing first rear surface exposure to form a second photoresist;

etching, using the second photoresist, the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type, thereby forming a first semiconductor island and a second semiconductor island including the impurity element imparting one conductivity type;

forming a second conductive film over the substrate;

forming a third photoresist using a first multi-tone mask over the second conductive film;

etching, using the third photoresist, the second conductive film, the second semiconductor island including the impurity element imparting one conductivity type, and the first semiconductor island;

ashing the third photoresist;

etching the second conductive film using the ashed third photoresist to form a source electrode and a drain electrode;

etching the second semiconductor island including the impurity element imparting one conductivity type and the first semiconductor island using the ashed third photoresist to form a channel region, a source region, and a drain region;

forming a fourth photoresist using a second multi-tone mask;

ashing the fourth photoresist;

forming a third conductive film over the second conductive film and the fourth photoresist;

removing the fourth photoresist and part of the third conductive film formed thereon to form a pixel electrode;

forming a protective film over the substrate;

performing second rear surface exposure to form a fifth photoresist over the protective film;

performing a reflow process on the fifth photoresist; and

etching the protective film using the fifth photoresist subjected to the reflow process.

13. The method for manufacturing a semiconductor device, according toclaim 12, wherein each of the first and second multi-tone masks is a halftone mask or a gray-tone mask.

14. The method for manufacturing a semiconductor device, according toclaim 12, wherein the first rear surface exposure is performed through the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type.

15. The method for manufacturing a semiconductor device, according toclaim 12, wherein the first semiconductor layer is an amorphous semiconductor layer.

16. The method for manufacturing a semiconductor device, according toclaim 12, wherein the first semiconductor layer is an i-type amorphous silicon layer.

17. The method for manufacturing a semiconductor device, according toclaim 12, wherein the pixel electrode is a transparent conductive film.

18. A method for manufacturing a semiconductor device, comprising:

forming a first conductive film over a substrate;

etching the first conductive film using a first photoresist to form a gate electrode and a wiring;

forming a gate insulating film over the gate electrode and a first wiring;

forming a first semiconductor layer over the gate insulating film;

forming a second semiconductor layer including an impurity element imparting one conductivity type over the first semiconductor layer;

performing first rear surface exposure to form a second photoresist;

etching, using the second photoresist, the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type, thereby forming a first semiconductor island and a second semiconductor island including the impurity element imparting one conductivity type over the gate electrode and forming a third semiconductor island and a fourth semiconductor island including the impurity element imparting one conductivity type over the first wiring;

forming a second conductive film over the substrate;

forming a third photoresist using a first multi-tone mask over the second conductive film;

etching, using the third photoresist, a part of the second conductive film and the fourth semiconductor island including the impurity element imparting one conductivity type and the third semiconductor island over the first wiring;

ashing the third photoresist;

etching the second conductive film using the ashed third photoresist to form a source electrode and a drain electrode;

etching the second semiconductor island including the impurity element imparting one conductivity type and the first semiconductor island using the ashed third photoresist to form a channel region, a source region, and a drain region;

forming a fourth photoresist using a second multi-tone mask over the substrate;

etching part of the gate insulating film, which is not covered with the fourth photoresist, using the fourth photoresist to form a contact hole over the first wiring;

ashing the fourth photoresist;

forming a third conductive film over the second conductive film and the fourth photoresist;

removing the fourth photoresist and parts of the third conductive film formed on the fourth photoresist to form a pixel electrode and a second wiring;

forming a protective film over the substrate;

performing second rear surface exposure to form a fifth photoresist over the protective film;

performing a reflow process on the fifth photoresist; and

etching the protective film using the fifth photoresist subjected to the reflow process.

19. The method for manufacturing a semiconductor device, according toclaim 18, wherein each of the first and second multi-tone masks is a halftone mask or a gray-tone mask.

20. The method for manufacturing a semiconductor device, according toclaim 18, wherein the first rear surface exposure is performed through the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type.

21. The method for manufacturing a semiconductor device, according toclaim 18, wherein the first semiconductor layer is an amorphous semiconductor layer.

22. The method for manufacturing a semiconductor device, according toclaim 18, wherein the first semiconductor layer is an i-type amorphous silicon layer.

23. The method for manufacturing a semiconductor device, according toclaim 18, wherein the pixel electrode is a transparent conductive film.

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