US20090144501A2 - Data storage system with complex memory and method of operating the same - Google Patents

Abstract

A data storage system and a data storing method for the data storage system are provided. The data storage system includes a host unit, a storage unit, and a first input/output bus functioning as an interface between the host unit and the storage unit. The storage unit includes a non-volatile memory buffer unit and a flash memory unit. The non-volatile memory buffer unit includes a plurality of buffers arranged in parallel. The flash memory unit includes a plurality of data storage devices arranged in parallel to input and output data using a parallel method. In the method, a writing request is first classified into one of a plurality of grades according to a writing request frequency when there is a writing request and the writing requested data is stored in one of the non-volatile memory buffer unit and the flash memory unit according to the writing request frequency.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION
• This application claims the benefit of Korean Patent Application No. 10-2005-0063301, filed on Jul. 13, 2005, and Korean Patent Application No. 10-2005-0076368, filed on Aug. 19, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to a data storage system and method of operating the same, and more particularly, to a data storage system with a complex memory comprising a flash memory and a method of operating the data storage system.
• 2. Description of the Related Art
• Data storage systems using a flash memory device have been widely used in an embedded system and a mobile system. The data storage system using a flash memory device is one of electrically erasable programmable read-only memories (EEPROMs) on and from which the data can be written, read, and erased. While reading speed of the data storage system using a flash memory device is fast, writing and erasing speeds thereof are slow.
• In the data storage system using a flash memory device, the data input/output unit is a page of 2-Bytes or 4-Bytes for a NOR-type flash memory device and 512-Bytes or 2-Kbytes for a NAND-type flash memory device. In addition, the erasing operation unit is a block of 128-Kbytes for the NOR-type flash memory device and 16-Kbytes or 64-Kbytes for the NAN D-type flash memory device.
• That is, for the NOR-type flash memory device, it takes about 400 μs to write 2-Bytes. For the NAND-type flash memory device, it takes about 220 μs to write 512-Bytes and takes about 2 ms-2 s to erase 512-Bytes. That is, for the NAND-type memory device, the erasing operation is relatively slow.
• In contrast, for a random access memory (RAM) device, it takes several tens of nano seconds to store a word. That is, the writing speed of data storage systems using the flash memory device is far slower than that of the RAM device.
• Accordingly, a flash memory device is generally used as a code memory device that does not frequently undergo writing operations or an auxiliary memory device of which writing performance is not important. In addition, a data storage system using a flash memory device cannot perform real-time data storing operation. Thus, there are limitations in using the data storage systems using a flash memory device in a digital product such as a digital camera or a digital camcorder.
• Therefore, a technology for logically and effectively hiding the erasing operation using a flash translation layer (FTL) employed using hardware or software has been developed (refer to U.S. Pat. No. 6,311,290 to J. Kim, et al. and “A space-Efficient Flash Translation Layer for Compact Flash systems” IEEE Trans. Consumer Elec., Vol. 48, No. 2 pp, 366-375, 2002).
• However, even when the erasing operation is hidden using the FTL, the writing speed of flash memory devices are still slow compared to RAM devices. Thus, in the case of storing mass data, the writing speed of a data storage system using a flash memory is less than that of a RAM device. Due to this, a flash memory device is generally used as a code memory device that does not frequently undergo writing operations or as an auxiliary memory device of which writing performance is not important. Particularly, flash memory devices are very limited in being used in a device such as the digital camera, camcorder and mobile phone that process and store data in real-time.
• An input/output buffer (or cash) is used to improve the input/output performance of the flash memory device. Korean Patent Application No. 2003-32552 discloses a data storage system that uses an SRAM or DRAM as the input/output buffer (or cash). US Patent Application No. 2004/0193782 A1 discloses a data storage system that improves writing performance by using a magnetic RAM as a writing buffer.
• In the data storage system disclosed in Korean Patent Application No. 2003-32552, input performance can be improved by maintaining data that is frequently accessed in the cash, which has a fast input/output speed, using a temporal-spatial locality appearing in an input/output pattern of the flash memory device. However, when the writing operation is done only in the cash, the data may be erased if power is turned off before the data is stored in the flash memory device. That is, the data maintenance that is a basic condition of the data storage system cannot be ensured. Therefore, although the reading performance is improved, the an ideal writing performance is not yet satisfied.
• In the data storage system disclosed in US Patent Application No. 2004/0193782 A1, when a writing operation larger than the capacity of a MRAM used in the system is continuously requested, an overflow is generated in the MRAM and thus the following writing request is directly done in the flash memory device. This leads to a deterioration of the writing performance.
SUMMARY OF THE INVENTION
• The present invention provides a data storage system with a complex memory that has an increased writing speed realized by managing only data which will be frequently updated in a writing buffer taking advantage of spatial locality and can reduce the number of writing and erasing operations for the flash memory that is an advantage obtained by using the buffer while reducing the size of the buffer.
• The present invention also provides a method of operating the data storage system.
• According to an aspect of the present invention, there is provided a data storage system including: a host unit; a storage unit; and a first input/output bus functioning as an interface between the host unit and the storage unit, wherein the storage unit includes a non-volatile memory buffer unit and a flash memory unit, the non-volatile memory unit including a plurality of buffers arranged in parallel, and the flash memory unit including a plurality of data storage devices arranged in parallel to input and output data using a parallel method.
• The number of buffers included in the non-volatile memory buffer unit may be greater than the number of data storage devices included in the flash memory unit.
• Each buffer may be a bank having a predetermined data storage capacity.
• Each buffer may be a non-volatile memory chip.
• Each data storage device may be a bank, and each bank may include a plurality of pages each having a predetermined data storage capacity.
• Each data storage device may be a flash memory chip.
• A data storage capacity of each buffer may be equal to, or N (N=1, 2, 3) times, that of each page.
• A data storage capacity of each buffer may be equal to, or N (N=1, 2, 3) times, a block size that is a deleting unit of the flash memory.
• According to another aspect of the present invention, there is provided a method of writing data in a data storage system including a host unit, a storage unit and a first input/output bus functioning as an interface between the host unit and the storage unit, wherein the storage unit includes a non-volatile memory buffer unit and a flash memory unit, the non-volatile memory unit includes a plurality of buffers arranged in parallel and the flash memory unit including a plurality of data storage devices arranged in parallel, the method including: writing data in a first buffer of the plurality of buffers; writing data in a second buffer of the plurality of buffers; writing data in a third buffer of the plurality of the buffers; writing the data written in the first buffer in a first page of a first data storage device of the plurality of data storage devices; and writing the data written in the second buffer in a first page of a second data storage device of the plurality of the data storage devices, wherein the writing of the data in the second buffer and the writing of the data written in the first buffer in the first page are simultaneously performed and the writing of the data in the third buffer and the writing of the data written in the second buffer in the first page are simultaneously performed.
• The method may further comprise writing the data written in the third buffer in a second page of the first data storage device of the plurality of data storage devices, wherein new data are written in the first buffer during the writing of the data written in the third buffer in a second page of the first data storage device of the plurality of data storage devices. The method may further comprise deleting the data written in the first buffer before the new data is written in the first buffer.
• The number of buffers included in the non-volatile memory unit may be greater than the number of data storage devices included in the flash memory unit. Each buffer may be a bank having a predetermined storage capacity.
• According to still another aspect of the present invention, there is provided a method of writing data in a data storage system including a host unit, a storage unit and a first input/output bus functioning as an interface between the host unit and the storage unit, wherein the storage unit includes a non-volatile memory buffer unit and a flash memory unit, the non-volatile memory unit including a plurality of buffers arranged in parallel, and the flash memory unit including a plurality of data storage devices arranged in parallel, the method including: writing data written in a first page of a first data storage device of the plurality of data storage devices in a first buffer of the plurality of buffers; writing data written in a first page of a second data storage device of the plurality of data storage devices in a second buffer of the plurality of buffers; writing data written in a second page of the first data storage device of the plurality of data storage devices in a third buffer of the plurality of buffers; wherein the writing of the data written in the first page of the second data storage device starts after the writing of the data written in the first page of the first data storage starts and ends after the writing of the data written in the first page of the first data storage device ends and the writing of the data written in the second page of the first storage device starts after the writing of the data written in the first page of the first data storage device ends; and while the writing of the data written in the first page of the second data storage device in the second buffer is performed, the data written in the first buffer is read and while the writing of the data written in the second page of the first data storage device in the third buffer is performed, the data written in the second buffer is read.
• The method may further include writing data written in a second page of a second data storage device in the first buffer after the data written in the first buffer is read and before the writing of the data written in the second page of the first data storage device in the third buffer ends.
• According to still yet another aspect of the present invention, there is provided a method of storing data in a data storage system having a flash memory unit and a writing buffer unit, the method including: classifying a writing request into one of a plurality of grades according to a writing request frequency when a writing request is made; and storing the writing requested data in one of the memory unit and the writing buffer unit according to the writing request frequency.
• In the method, the storing of the writing requested data may comprise storing a page having a relatively high writing request frequency in the writing buffer unit, and, when the writing buffer unit is full, storing one of the pages stored in the writing buffer unit in the flash memory unit.
• When the writing request is classified into one of two grades, the data having a relatively high writing request frequency may be stored in the writing buffer unit and the data having a relatively low writing request frequency are stored in the flash memory unit.
• Alternatively, when the writing request is classified into one of two grades, the storing of the writing requested data may include: temporarily storing data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers; temporarily storing data having a relatively low writing request frequency in a second writing buffer of the plurality of writing buffers or the flash memory unit.
• Alternatively, when the writing request is classified into one of three grades, the storing of the writing requested data may include: temporarily storing data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers; temporarily storing data having a middle writing request frequency in a second writing buffer of the plurality of writing buffers; and storing data having a relatively low writing request frequency in the flash memory unit.
• Alternatively, when the writing request is classified into one of three grades, the storing of the writing requested data includes: temporarily storing data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers; temporarily storing data having a middle writing request frequency in a second writing buffer of the plurality of writing buffers; and temporarily storing data having a relatively low writing request frequency in a third writing buffer of the plurality of writing buffers.
• When there is a page for the writing request available in the writing buffer unit, the page of the writing buffer unit may be updated to the available page in the writing buffer unit regardless of the classification of the writing request.
• The classifying of the writing request may include classifying the writing request as a hot or cold pages using one or more LRU (Least Recently Used) Q.
• Alternatively, the classifying of the writing request may include adding a count value to the writing request and classifying the writing request according to whether the count value is reduced to a predetermined value after a predetermined time has lapsed.
• When the data having the relatively high writing request frequency is to be written in the writing buffer unit and the writing buffer unit is full, data stored in the writing buffer unit and having a relatively low using frequency may be stored in the flash memory, after which the data having the relatively high writing request frequency is stored in the writing buffer unit.
• After the data having the relatively high writing request frequency is stored in the writing buffer unit, metadata may be updated.
• According to still yet another aspect of the present invention, there is provided a data storage system including: a memory unit having a flash memory unit and a writing buffer unit; and a memory control unit including a page classification unit for classifying a writing request into one of a plurality of grades according to a writing request frequency when a writing request is made, wherein the memory control unit stores the writing requested data in one of the memory unit and the writing buffer unit according to the writing request frequency.
• When the writing request is classified into one of two grades, the memory control unit may store data having a relatively high writing request frequency in the writing buffer unit and store data having a relatively low writing request frequency in the flash memory unit.
• The writing buffer unit may include a plurality of writing buffers arranged in parallel.
• Alternatively, when the writing request is classified into one of two grades, the memory control unit may temporarily store data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers, temporarily store data having a relatively low writing request frequency in a second writing buffer of the plurality of writing buffers or in the flash memory unit.
• Alternatively, when the writing request is classified into one of three grades, the memory control unit may temporarily store data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers, temporarily store data having a middle writing request frequency in a second writing buffer of the plurality of writing buffers, and store data having a relatively low writing request frequency in the flash memory unit.
• Alternatively, when the writing request is classified into one of three grades, the memory control unit may temporarily store data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers, temporarily store data having a middle writing request frequency in a second writing buffer of the plurality of writing buffers, and temporarily store data having a relatively low writing request frequency in a third writing buffer of the plurality of writing buffers.
• In the above-described systems and methods, the buffer may be one of a bank and a non-volatile memory chip having a predetermined data storage capacity. The first and second data storage devices may be first and second banks, respectively, and each of the first and second banks may include a plurality of pages each having a predetermined data storage capacity. The first and second data storage devices may be first and second flash memory chips, respectively.
• The data storage capacity of the buffer may be equal to, or N (N=1, 2, 3) times, that of the page. The data storage capacity of the buffer may be equal to, or N (N=1, 2, 3) times, a block size that is a deleting unit of the flash memory.
• The non-volatile memory unit and the flash memory unit may be formed in a single chip.
• The storage unit may further include a flash translation layer and a second input/output bus functioning as an interface between the non-volatile memory buffer unit and the flash memory unit.
• The storage unit may be provided in the form of a card that can be detachably installed on the host unit.
• The host unit may further include a first file system, a second file system, a flash translation layer interfacing with the first file system, and a device driver interfacing with the second file system.
• The non-volatile memory chip may be selected from the group consisting of an MRAM, a PRAM, an FRAM, a non-volatile polymer memory chip, and a combination thereof.
• The writing buffer unit may be a battery attached type non-volatile memory.
• The writing buffer unit may be a volatile memory.
• The flash memory unit may include a NAND-type Single Level Cell (SLC) flash memory and a NAND-type Multi Level Cell (MLC) flash memory.
BRIEF DESCRIPTION OF THE DRAWINGS
• The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
• FIG. 1 is a block diagram of a data storage system having a complex memory according to an embodiment of the present invention;
• FIG. 2 is a block diagram of a storage unit ofFIG. 1 according to an embodiment of the present invention;
• FIG. 3 is a block diagram of a data storage system with a complex memory according to another embodiment of the present invention;
• FIG. 4 is a block diagram of a storage unit ofFIG. 3 according to an embodiment of the present invention;
• FIG. 5 is a block diagram illustrating a writing process in the data storage system ofFIG. 1 or3 in reference to an applied clock cycle according to an embodiment of the present invention;
• FIG. 6 is a block diagram illustrating a reading process in the data storage system ofFIG. 1 or3 in reference to an applied clock cycle according to an embodiment of the present invention;
• FIG. 7 is a block diagram illustrating a data storage system with a complex memory according to another embodiment of the present invention; and
• FIG. 8 is a flowchart illustrating a data storage method of the data storage system ofFIG. 7.
DETAILED DESCRIPTION OF THE INVENTION
• The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.
• FIG. 1 is a block diagram of a data storage system (hereinafter, referred as “first system”) having a complex memory according to an embodiment of the present invention.
• Referring toFIG. 1, the first system includes ahost unit40, astorage unit44 and a first I/O (input/output) bus42. The first I/O bus42 functions as an interface between thehost unit40 and thestorage unit44. Thehost unit40 is a computer main body in which afile system40ais equipped. Thestorage unit44 includes aflash translation layer44a, anon-volatile buffer unit44b, a second I/O bus44c, and aflash memory unit44d. Theflash translation layer44ais provided in the form of hardware, which can identify data and a location where the data is recorded in theflash memory44d, perform the erasing operation, and identify data and a location where the data is recorded in the non-volatilememory buffer unit44b. Accordingly, the data recorded in the flashmemory buffer unit44bcan be read using theflash translation layer44a. The second I/O bus44cfunctions as an interface between the non-volatilememory buffer unit44band theflash memory unit44d. Thestorage unit44 is portable and can be detachably attached on thehost unit40. For example, thestorage unit44 may be any one of a compact flash card, a smart media card, a multimedia card, a secure digital card, a memory stick card, and a Universal Serial Bus (USB) storage device.
• FIG. 2 is a block diagram of a storage unit ofFIG. 1 according to an embodiment of the present invention. Referring toFIG. 2, the non-volatilememory buffer unit44bincludes first through nth non-volatile memory buffers (hereinafter, referred as “buffers”)44b1,44b2 . . .44b(n−1),44b(n). The first throughnth buffers44b1,44b2 . . .44b(n−1), and44b(n) are connected in parallel. The first throughnth buffers44b1,44b2 . . .44b(n−1), and44b(n) may be banks or chips each having a predetermined capacity. The banks or chips are MRAMs, FRAMs, PRAMs or non-volatile polymer memories. Theflash memory unit44dmay include first throughmth banks44d1,44d2 . . .44d(m−1), and44d(m). Each of the first throughmth banks44d1,44d2 . . .44d(m−1), and44b(m) includes a plurality of pages p1. Each page p1 has a predetermined capacity, which is preferably the same as that of each of the first throughnth buffers44b1,44b2 . . .44b(n−1),44b(n) of the non-volatilememory buffer unit44b. That is, a capacity of one of the buffers forming the non-volatilememory buffer unit44bis identical to that of one of the pages p1 forming each of the first to mthbanks44d1,44d2 . . .44d(m−1), and44d(m). For example, when the capacity of each buffer of the non-volatilememory buffer unit44bis 512 bytes, the capacity of one page p1 which forms each of the first throughmth banks44d1,44d2 . . .44d(m−1), and44d(m) is also 512 bytes. Each of the first to mthbanks44d1,44d2 . . .44d(m−1), and44d(m) may be formed using individual flash memory chips. Theflash memory unit44dmay include a NAND-type Single Level Cell (SLC) flash memory and a NAND-type Multi Level Cell (MLC) flash memory. At this point, each of the flash memories includes a plurality of banks that are connected in parallel.
• Although it is preferable that the capacity of each buffer of the non-volatilememory buffer unit44bis same as that of each page p1 of the banks of theflash memory unit44d, the capacity of the buffer may be n (where n=1, 2, 3) times larger or smaller than the capacity of the page. Alternatively, the capacity of the buffer may be identical to or n times (n=1, 2, 3) the size of the block that is an erasing unit of the flash memory.
• Meanwhile, in thenth buffer44b(n), the number “n” of the buffers (or banks) contained in the non-volatilememory buffer unit44bmay be 2p+1 where the p represents a degree of the parallelism of the flash memory devices of theflash memory unit44d. The degree of the parallelism is a natural number that is identical to or less than a value obtained by dividing the writing speed of a flash memory device by the writing speed of a non-volatile memory device. For example, when the first throughnth buffers44b1,44b2 . . .44b(n−1),44b(n) are FRAM devices and the first throughmth banks44d1,44d2 . . .44d(m−1), and44d(m) of theflash memory unit44dare NAND-type flash memory devices, the writing speed of the FRAM devices is 100 ns/word and the writing speed of the NAND-type flash memory devices is 500 ns/word. Therefore, the degree “p” of the parallelism of the flash memory devices of theflash memory unit44din relation to the FRAM devices is 5. In this case, the non-volatilememory buffer unit44bincludes 11(2×5+1) buffers (or banks) and theflash memory unit44dincludes 5 logical I/O banks.
• FIG. 3 is a block diagram of a data storage system (hereinafter, referred to as “second system”) having a parallel I/O complex memory according to another embodiment of the present invention.
• Referring toFIG. 3, the second system D includes ahost unit50, astorage unit54 and an I/O bus52. Thehost unit50, I/O bus52 andstorage unit54 are equipped in a single main body. That is, while thestorage unit44 of the first system is a portable device such as a diskette that can be detachably attached to thehost unit40, thestorage unit54 and thehost unit50 of the second system may be chips that are mounted on a single board. Thehost unit50 includes afile system50aand anadditional file system50b. Thehost unit50 further includes aflash translation layer50cassociated with the operation of thefile system50aand adevice driver50dassociated with the operation of theadditional file system50b. Thedevice driver50dis provided in the form of software. In the second system D, the I/O bus52 functions as an interface between thehost unit50 and thestorage unit54. Thestorage unit54 includes anon-volatile memory unit54aand aflash memory unit54b. Theflash memory unit54bmay include a NAND-type SLC flash memory and a NAND-type MLC flash memory.
• FIG. 4 is a diagram showing thestorage unit54 of the second system D ofFIG. 3 in more detail according to an embodiment of the present invention.
• Referring toFIG. 4, the non-volatilememory buffer unit54aincludes first through nth non-volatile memory buffers (hereinafter, referred as “buffers”)54a1,54a2 . . .54a(n−1),54a(n). Theflash memory unit54bmay include first throughmth banks54b1,54b2 . . .54b(m−1), and54b(m). Thebuffers54a1,54a2 . . .54a(n−1),54a(n) are arranged in parallel and thebanks54b1,54b2 . . .54b(m−1), and54b(m) are also arranged in parallel. The parallel arrangements of the buffers and banks means that their structures are parallel and the operations thereof are performed in parallel. In this way, data can be recorded in the buffers and banks in parallel. Thebuffers54a1,54a2 . . .54a(n−1),54a(n) may be identical to those of the first system. Each of thebanks54b1,54b2 . . .54b(m−1), and54b(m) includes a plurality of pages p2. Therefore, thebanks54b1,54b2 . . .54b(m−1), and54b(m) may be identical to those of the first system. Thebanks54b1,54b2 . . .54b(m−1), and54b(m) may be formed using a single chip. Alternatively, each of thebanks54b1,54b2 . . .54b(m−1), and54b(m) may be formed using individual flash memory chips.
• Meanwhile, each of theflash memory units44dand54dof the first and second systems includes a NAND-type flash memory or a NOR-type flash memory. When the NOR-type flash memory is applied, data is input or output in units of bytes or words. In this case, it is difficult to manage the data.
• Therefore, in the present invention, even when the flash memory is the NOR-type, the pages of the banks of each of theflash memory units44dand54dmay be logical pages conceptually identical to the case when the flash memory is the NAND-type. In addition, when the NOR-type flash memory is applied to theflash memory units44dand54b, the size of each page of the banks may be identical to or different from that of the page of the banks when the NAND-type flash memory is applied.
• When the NOR-type flash memory is applied and the pages of the banks are identical to that of the banks when the NAND-type flash memory is applied, the operation of theflash memory units44dand54bis identical to that when the NAND-type flash memory is applied, as will be described later.
• Writing processes of the first and second systems will now be described with reference toFIG. 5.
• InFIG. 5, the arrow indicates a dataflow direction from the non-volatile memory buffer unit to the flash memory unit. That is, the data written in the non-volatile memory buffer unit is moved to the flash memory unit.
• InFIGS. 5 and 6, it is assumed that one clock signal and two clock signals are utilized for the reading and writing operations, respectively, of the non-volatile memory and two clocks and four clocks are utilized for the reading and writing operations, respectively, of the flash memory. The reading/writing speeds depend on the types of the non-volatile memory and the flash memory. The relative ratio between the reading/writing performance of the non-volatile memory and the reading/writing performance of the flash memory becomes a design factor in determining the number of buffers of the non-volatile memory and the number of banks of the flash memory to be utilized.
• InFIG. 5, an example is given for convenience showing that the non-volatile memory buffer unit includes first tothird buffers70,74 and76 that are arranged in parallel and the flash memory unit includes first andsecond banks80 and90. At this point, thefirst bank80 includes first throughfifth pages80a,80b,80c,80d, and80e. Thesecond bank90 includes first throughfifth pages90a,90b,90c,90d, and90e. The first throughthird buffers70,74 and76 may be some of the buffers contained in the non-volatilememory buffer units44band54aas shown inFIGS. 2 and 4, respectively. The first andsecond banks80 and90 may be some of the banks contained in theflash memory units44dand54bas shown inFIGS. 2 and 4, respectively.
• Referring toFIG. 5, data is recorded in thefirst buffer70 of the non-volatile buffer unit at afirst clock pulse1. The recording of the data in thefirst buffer70 is continued until asecond clock pulse2. After the recording of the data in thefirst buffer70 is finished, the data recorded in thefirst buffer70 starts being recorded in thefirst page80aof thefirst bank80 at athird clock pulse3. The process for recording the data recorded in thefirst buffer70 in thefirst page80aof thefirst bank80 is continued until a sixth clock pulse. The time spent in recording the data recorded in thefirst buffer70 in thefirst page80aof thefirst bank80 is two times that spent in recording the data in one of the buffers of the non-volatile memory buffer unit. Therefore, while the data recorded in thefirst buffer70 is recorded in thefirst page80aof thefirst bank80, further data cannot be recorded in thefirst buffer70. Therefore, while the data recorded in thefirst buffer70 is recorded in thefirst page80aof thefirst bank80, further data input to the non-volatile memory buffer unit is consecutively recorded in the second andthird buffers74 and76. The point of time when data is recorded in the second andthird buffers74 and76 depends on whether the data input to the non-volatile buffer unit is continuous or discontinuous. For example, if there is no data input to the non-volatile memory buffer unit until the data recorded in thefirst buffer70 moves completely to thefirst page80aof thefirst bank80, the following data input to the non-volatile memory buffer unit can be recorded again in thefirst buffer70. On the other hand, if data is continuously input, further input data is recorded in thesecond buffer74 after initial data is first input to thefirst buffer70. That is, the recording of data to thesecond buffer74 starts at thethird clock pulse3 and ends at afourth clock pulse4. The recording of the data recorded in thefirst buffer70 to thefirst page80aof thefirst bank80 is continued at thefourth clock pulse4 where the recording of the data to thesecond buffer74 is completed. After recording of the data to thesecond buffer74 is completed, the data recorded in thesecond buffer74 starts being recorded in thefirst page90aof thesecond bank90. A process for recording the data recorded in thesecond buffer74 in thefirst page90aof thesecond bank90 starts at thefifth clock pulse5 and continues until aneighth clock pulse8. A process for recording the data recorded in thefirst buffer70 in thefirst page80aof thefirst bank80 starts at thethird clock pulse3 and continues until thesixth clock pulse6. Therefore, during the fifth andsixth clock pulses5 and6, recording of the data to the first andsecond buffers70 and74 cannot be done. Recording of the data to thesecond buffer74 cannot be done until theeighth clock pulse8. Therefore, after the data is recorded in thesecond buffer74, data input to the non-volatile memory buffer is recorded in thethird buffer76 at thefifth clock pulse5. Recording of the data in thethird buffer76 continues until thesixth clock pulse6. At thesixth clock pulse6, the recording of the data to thethird buffer76 is completed and the data recorded in thefirst buffer70 is recorded in thefirst page80aof thefirst bank80. However, the data recorded to thesecond buffer74 is continuously recorded in thefirst page90aof thesecond bank90. As described above, at thesixth clock pulse6 the recording of data to thethird buffer76 is completed and thefirst buffer70 of the non-volatile memory buffer unit is empty. Therefore, further data being input to the non-volatile memory buffer unit at theseventh clock pulse7 can be recorded to thefirst buffer70.
• The reading operation of the first or second system will now be described.
• The reading operation of the first or second system is similar to a conventional data cashing method. That is, an address region that is frequently used is maintained in a part of the non-volatile RAM using the hardware cash or the LRU (Least Recently Used) software. When there is a reading request for the data remained in the non-volatile RAM, the data is quickly read from the non-volatile RAM without using the flash memory and transmitted. According to a feature of the present invention, a prefetching method is additionally utilized for the reading operation. In this case, the stored data is quickly read from the selected bank of the flash memory using the parallel structure and the prefetching of the data is done from the selected buffer of the non-volatile memory buffer unit.
• In the above-described reading method, as in the writing operation, using the degree of the parallelism corresponding to the relative ratio of the reading performance between of the non-volatile RAM and the flash memory utilized, data that is expected to be read is first loaded on the selected buffer of the non-volatile memory buffer unit and data that is already read is pushed out.
• When the estimation of data that is expected to be read is accurate, the reading speed may be identical to a case where data is read from the non-volatile RAM even when a buffer having a relatively small capacity is used.
• FIG. 6 shows the reading process of the first or second system in reference to an applied clock cycle. InFIG. 6, the arrow indicates a dataflow direction.
• Referring toFIG. 6, data recorded in thefirst page80aof thefirst bank80 of the flash memory unit is read and recorded in thefirst buffer70 of the non-volatile memory buffer unit (hereinafter, “first recording”). At this point, thebank80 may be one of the banks contained in the SLC flash memory of the flash memory unit or one of the banks contained in the MLC flash memory of the flash memory unit. Since reading speed of the flash memory unit is faster than writing speed of the flash memory unit, the first recording starts at thefirst clock pulse1 and continues until thesecond clock pulse2. While the first recording is being performed, the data recorded in thefirst page90aof thesecond bank90 are read and recorded in thesecond buffer74 of the second non-volatile memory buffer unit (hereinafter, “second recording”). The second recording starts one clock pulse after the first recording starts. That is, the second recording starts at thesecond clock pulse2 and continues until thethird clock pulse3. While the second recording is being performed, data recorded in thesecond page80bof thefirst bank80 is read and recorded in the third buffer76 (hereinafter, “third recording”). The third recording starts at thethird clock pulse3 and continues until thefourth clock pulse4.
• The recording of data in the first andthird buffers70,74 and76 of the non-volatile buffer unit from the flash memory unit through the first through third recording processes can be successively read. That is, the data recorded in thefirst buffer70 is read right after the data recorded in thefirst page80aof thefirst bank80 is written in thefirst buffer70. That is, the data transferred from thefirst page80aof thefirst bank80 to thefirst buffer70 during the first recording is read until thethird clock pulse3. When thethird clock pulse3 appears, the second recording where the data recorded in thefirst page90aof thesecond bank90 is recorded in thesecond buffer74 is completed. Therefore, right after the data recorded in thefirst buffer70 is read until thethird clock pulse3, the data recorded in thesecond buffer74 can be read at thefourth clock pulse4. Likewise, the data recorded in thesecond buffer74 is read at thefourth clock pulse4, the data recorded in thethird buffer76 can be read at thefifth clock pulse5.
• FIG. 7 shows a block diagram of a data storage system (hereinafter, “third system”) with a complex memory according to another embodiment of the present invention.
• Referring toFIG. 7, the third system includes adata storage unit100 and ahost110. Thedata storage unit100 includes an I/O interface unit120, aflash translation layer130, and a memory unit M1. The memory unit M1 includes a writingbuffer unit140 and aflash memory150. Thedata storage unit100 is portable and can be detachably attached on thehost110. For example, thedata storage unit100 may be any one of a compact flash card, a smart media card, a multimedia card, a secure digital card, a memory stick card, and a USB storage device. Thehost110 controls theflash memory unit150 through amemory control unit131 of theflash translation layer130. Thehost110 transfers a logical address designating a location in which data of the flash memory will be recorded to the memoryflash translation layer130. Thehost100 may be a personal computer, a digital camera, or other portable electronic devices such as an MP3 player.
• The I/O interface unit120 functions as an interface between thehost110 and thedata storage unit100 for data exchange between each functional part of thedata storage unit100 and thehost110. The I/O interface unit120 transfers the logical address designating a read target page to theflash translation layer130 by decoding a flash memory reading order transferred from thehost110. In addition, the I/O interface unit120 transfers read target data, which is transferred from theflash memory unit150 by thememory control unit131, to thehost110 through an external bus. The I/O interface unit120 transfers the logical address designating a write target page to theflash translation layer130 by decoding a flash memory writing order transferred from thehost110.
• Theflash translation layer130 functions to allow theflash memory unit150 to be used as a block device such as a hard disk. Theflash translation layer130 functions to translate the logical address into the physical address using mapping information when there is a writing/reading operation request for at the logical address while maintaining the mapping information between the logical address on the imaginary block device and the physical address on the flash memory. Particularly, when there is a writing operation request for translating data of a logical address, theflash translation layer130 functions to electrically delete and rerecord the physical address corresponding to the logical address or to remap the logical address into another physical address. Theflash translation layer130 may include amemory control unit131 and aRAM132. Thememory control unit131 may include apage classification unit133 for classifying a writing request into one of a plurality of grades. Thememory control unit131 stores a logical address for the writing request received through the I/O interface unit110. When the writing request is received through the I/O interface unit110, thepage classification unit133 classifies the writing request into one of the plurality of grades according to a writing request frequency. Thepage classification unit133 may classify the writing request into two or three grades, as will be described in more detail.
• Thememory control unit131 stores data requested to be written in thewriting buffer unit140 or theflash memory unit150 according to a grades classified by thepage classification unit133. If the writing request can be classified into one of two grades, thememory control unit131 temporarily stores the data having a grade of a high writing request frequency in thewriting buffer unit140 and stores the data having a grade of a low writing request frequency in theflash memory150.
• The data received through the I/O interface unit120 is temporarily stored in thewriting buffer unit140 in a unit of a page by the control of thememory control unit131. The writingbuffer unit140 may be a non-volatile memory selected from the group consisting of an MRAM, an FRAM, a PRAM, a polymer memory, and a combination thereof. In addition, the writingbuffer unit140 may be a battery attached type non-volatile memory. Alternatively, the writingbuffer unit140 may be a volatile memory. The writingbuffer unit140 may be formed of a plurality of banks or chips that are arranged in parallel.
• Theflash memory unit150 is divided into a plurality of physical blocks each having a predetermined size. The physical blocks have their own physical block number (0, 1, 2 . . . n−1). Therefore, they can be individually designated and used as a deleting unit. In addition, each of the physical blocks is divided into a plurality of physical pages each having a predetermined size. Each of the physical pages can be accessed as an offset of a corresponding physical block and used as a reading/writing unit. The physical block and the physical page may be set to have various sizes according to the size of the NAND-type flash memory. For example, when an overall capacity, block size and page size of theflash memory unit150 are 128 Mbytes, 16 Kbytes, and 512 Bytes, respectively, each physical block of the flash memory comprises 32 physical pages. Theflash memory unit150 may include a NAND-typeSLC flash memory150aand a NAND-typeMLC flash memory150b. At this point, each of theflash memories150aand150bhas a plurality of physical blocks.
• A process for storing data in the third system will now be described.
• The present invention is based on a fact that the number of writing operations and the buffer size can be reduced by using a temporal locality appearing in the writing operation.
• There is a temporal-spatial locality in a memory accessing pattern of a computer system. Likewise, there is also the temporal-spatial locality in the I/O pattern of the storage system. At this point, the temporal locality means that data that has been more recently accessed is more likely to be accessed again. The spatial locality means that a block, file, or directory that is adjacent to a block, file or directory that has been recently accessed is more likely to be accessed in the future.
• That is, similar to a theory of 20:80, a part of the address space is frequently requested for the writing operation and the rest of the address space is rarely requested for the writing operation once the writing request is done. The part of the address space that is frequently requested for the writing operation is called a hot page and the rest of the address space that is rarely requested for the writing operation are each called a cold page. The classification of the address spaces as hot or cold pages and the storing of the classified data will now be described in more detail with reference toFIG. 8.
• FIG. 8 is a flowchart illustrating a data storage method of the data storage system ofFIG. 7.
• Referring toFIGS. 7 and 8, thememory control unit131 receives a data writing request from thehost110 through the I/O interface unit120 (Step200). At this point, data is transferred in a unit of a page and thememory control unit131 receives a logical address designating a write target page. Thememory control unit131 stores the logical address in theRAM132. Thememory control unit131 determines if there is a write target page having an address identical to that of the write target page for the writing request in thewriting buffer unit140 of the memory unit M1 (Step210). When it is determined there is a write target page having an address identical to that of the write target page for the writing request in thewriting buffer unit140 of the memory unit M1, thememory control unit131 updates the address of the writingbuffer unit140 regardless of the page classification (Step220).
• When it is determined there is no write target page having an address identical to that of the write target page for the writing request in thewriting buffer unit140 of the memory unit M1, thepage specification unit133 classifies the writing request as a hot or cold page according to the frequency of the writing request (Step230). That is, thepage classification unit133 estimates the probability of an amendment using the temporal locality appearing in the writing operation and classifies the writing request as a hot or cold page with reference to the estimation. The page classification is done according to the following method.
• First, the writing request may be classified by a method using the LRU software. This method is based on the temporal locality that a page that is not accessed for a long time is less likely to be accessed in the future. That is, one LRU Queue (hereinafter “LRU Q”) is managed and it is determined if an address region corresponding to a new writing request is registered in the LRU Q when the new writing request is input. When it is determined that an address region corresponding to a new writing request is registered in the LRU Q, it is regarded that there was a writing request for the address region during the former writing operation. Therefore, the writing request is classified as a hot page. When it is determined that the address region corresponding to a new writing request is not registered in the LRU Q, the writing request is classified as a cold page. The classified writing request is added to the LRU Q.
• Second, the writing request may be classified by a method adding a count value to the address receiving the writing request. At a time when the writing request is generated, a specific count value is set and the specific count value gradually reduces as time elapses. When a predetermined time (e.g., 10 minutes) has lapsed, the count value is set as “0”. At this point, the writing request generated in the region where the count value is not “0” is classified as a hot page and the writing request generated in the region where the count value is “0” is classified as a cold page.
• The writing request can be classified by the locality extracted by a variety of other methods such as a method using a hardware cash structure.
• Although the writing request is classified into two grades such as hot and cold pages according to the frequency in the foregoing description, the present invention is not limited to this case. That is, the writing request may be classified into three grades such as high, middle and low grades according to the frequency.
• Referring again toFIG. 8, it is determined if the writing request is classified as a hot page (Step240). When it is determined that the writing request is classified as a cold page, thememory control unit131 directly stores the writing requested data classified as a cold page in theflash memory unit150 without temporarily storing the data in the writing buffer unit140 (Step250). At this point, the writing requested data may be stored in theMLC flash memory150bof theflash memory unit150. Alternatively, the writing requested data may be stored in theflash memory unit150 via thewriting buffer unit140 when the writingbuffer unit140 is used to improve the performance. As a result, the number of deleting operations performed on theflash memory unit150 can be reduced.
• InStep240, when it is determined that the writing request is classified as a hot page, thememory control unit131 determines if the writingbuffer unit140 is full (Step260). When it is determined that the writingbuffer unit140 is full, one of the pages of the writingbuffer unit140, which has the lowest locality (i.e, the lowest using frequency), is stored in the flash memory unit150 (Step270). At this point, the page having the lowest locality may be stored in theSLC flash memory150aof theflash memory unit150.
• That is, one of the pages stored the writingbuffer unit140, which was accessed the longest time ago, is selected and the selected page is stored in theSLC flash memory150aof theflash memory unit150. Then, the writing request is stored in a range, in which the accessed page was stored, of the writingbuffer unit140.
• Then, when the writingbuffer unit140 is not full or an additional space is generated in thewriting buffer unit140 inStep270, the writing requested data are stored in the writing buffer unit140 (Step280). For example, when it is assumed that the writing request is generated in order of pages A1, B, A2, C, D, E, F, G, H, and A3 for the address spaces A through Z and the address space A is classified as the hot page and the pages B through H are classified as the cold pages, the writing request for the pages A1, A2 and A3 can be processed in the writing buffer even if the writing buffer has a size that can store only one flash page. Therefore, an advantage that only the page A3 is stored in the flash memory unit can be actually realized.
• Alternatively, when the writingbuffer unit140 includes a plurality of writing buffers, the data classified as a hot page can be stored in a first writing buffer and the data classified as a cold page can be stored in a second writing buffer. Then, the data classified as the cold page and stored in the second writing buffer can be stored in theSLC flash memory150aof theflash memory unit150.
• Alternatively, when thepage classification unit133 classifies the writing requested data into three grades, thememory control unit131 stores the data having high, middle and low using frequencies in first and second writing buffers and theMLC flash memory150bof theflash memory unit150, respectively.
• Alternatively, thememory control unit131 temporarily stores the data having high, middle and low using frequencies in first, second and third writing buffers, respectively. Then, the data stored in the third writing buffer moves to and is stored in one of the SLC orMLC flash memories150aand150bof theflash memory unit150.
• As described above, after the writing requested data is stored in thewriting buffer unit140 and the metadata is updated (Step290).
• In the data storage system according to the present invention, the data is written or read using a parallel input/output method by arranging an appropriate number of non-volatile memory buffers and flash memory banks in parallel considering a relative operation speed between a non-volatile memory device and a flash memory device. Therefore, a large capacity of data can be continuously processed, thereby preventing overflow and increasing writing/reading speed.
• In addition, data deletion caused by unexpected accidents such as power being turned off when some data has not been stored in the flash memory device can be prevented, thereby stably maintaining the data.
• Furthermore, the non-volatile memory buffer unit can be used as the cash for the reading operation and thus the XIP (execution in Place) support can be added to the NAND-type flash memory by supporting the data input/output in a unit of a byte.
• In addition, the data classified as a hot page (having a high writing request frequency) is recorded in the writing buffer (e.g., a non-volatile RAM) and the data classified as a cold page (having a low writing request frequency) is recorded in the flash memory unit. Therefore, writing speed increases. Furthermore, since the writing buffer is formed of a non-volatile RAM such as an MRAM, a PRAM, an FRAM and the like, data can be permanently stored and be read and write having a capacity (e.g., 8-byte) less than the page unit of the flash memory. In addition, since the flash memory includes the SLC and MLC flash memories, memory efficiency and function can be enhanced. Since only data classified as a cold page is recorded in the flash memory unit, the number of writing operations for the flash memory can be reduced and thus the number of deleting operations can also be reduced. The reduction in the number of the deleting operations increases the service life of the flash memories.
• While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
• For example, additional components may be further added between the host unit and the storage unit. In addition, other types of the non-volatile memory chips can be used to form the writing buffer unit. The writing buffer units may include different types of non-volatile memory devices. In addition, the flash memory unit may include only one of the SLC and MLC flash memories.

Claims (76)

1. A data storage system comprising:

a host unit;

a storage unit; and

a first input/output bus functioning as an interface between the host unit and the storage unit,

wherein the storage unit includes a non-volatile memory buffer unit and a flash memory unit, the non-volatile memory buffer unit including a plurality of buffers arranged in parallel and the flash memory unit including a plurality of data storage devices arranged in parallel to input and output data using a parallel method.

2. The data storage system ofclaim 1, wherein the number of buffers included in the non-volatile memory buffer unit is greater than the number of data storage devices included in the flash memory unit.

3. The data storage system ofclaim 1, wherein each buffer is a bank having a predetermined data storage capacity.

4. The data storage system ofclaim 1, wherein each buffer is a non-volatile memory chip.

5. The data storage system ofclaim 1, wherein each data storage device is a bank and each bank includes a plurality of pages each having a predetermined data storage capacity.

6. The data storage system ofclaim 1, wherein each data storage device is a flash memory chip.

7. The data storage system ofclaim 5, wherein a data storage capacity of each buffer is equal to, or N (N=1, 2, 3) times, that of each page.

8. The data storage system ofclaim 1, wherein the data storage capacity of each buffer is equal to, or N (N=1, 2, 3) times, a block size that is a deleting unit of the flash memory.

9. The data storage system ofclaim 4, wherein the non-volatile memory chip is selected from the group consisting of an MRAM, a PRAM, an FRAM, and a non-volatile polymer memory chip.

10. The data storage system ofclaim 1, wherein the first input/output bus is selected from the group consisting of an USB, a PCMCIA, an ISA, and a PCI.

11. The data storage system ofclaim 1, wherein the non-volatile memory unit and the flash memory unit are formed in a single chip.

12. The data storage system ofclaim 1, wherein the storage unit further includes a flash translation layer and a second input/output bus functioning as an interface between the non-volatile memory buffer unit and the flash memory unit.

13. The data storage system ofclaim 1 or12, wherein the storage unit is provided in the form of a card that can be detachably installed on the host unit.

14. The data storage system ofclaim 1, wherein the host unit further includes a first file system, a second file system, a flash translation layer interfacing with the first file system, and a device driver interfacing with the second file system.

15. The data storage system ofclaim 1, wherein the flash memory unit includes a NAND-type SLC flash memory and a NAND-type MLC flash memory.

16. A method of writing data in a data storage system comprising a host unit, a storage unit and a first input/output bus functioning as an interface between the host unit and the storage unit, wherein the storage unit includes a non-volatile memory buffer unit and a flash memory unit, the non-volatile memory unit including a plurality of buffers arranged in parallel and the flash memory unit including a plurality of data storage devices arranged in parallel, the method comprising:

writing data in a first buffer of the plurality of buffers;

writing data in a second buffer of the plurality of buffers;

writing data in a third buffer of the plurality of buffers;

writing the data written in the first buffer in a first page of a first data storage device of the plurality of data storage devices; and

writing the data written in the second buffer in a first page of a second data storage device of the plurality of data storage devices,

wherein the writing of the data in the second buffer and the writing of the data written in the first buffer in the first page are simultaneously performed and the writing of the data in the third buffer and the writing of the data written in the second buffer in the first page are simultaneously performed.

17. The method ofclaim 16, further comprising writing the data written in the third buffer in a second page of the first data storage device of the plurality of data storage devices,

wherein new data is written in the first buffer during the writing of the data written in the third buffer in a second page of the first data storage device of the plurality of data storage devices.

18. The method ofclaim 17, further comprising deleting the data written in the first buffer before the new data is written in the first buffer.

19. The method ofclaim 16, wherein the number of buffers included in the non-volatile memory unit is greater than the number of data storage devices included in the flash memory unit.

20. The method of clam16, wherein each buffer is a bank having a predetermined storage capacity.

21. The method ofclaim 16, wherein each buffer is one selected from the group consisting of an MRAM, a PRAM, an FRAM, and a non-volatile polymer memory chip.

22. The method ofclaim 16, wherein the first and second data storage devices are first and second banks, respectively, and each of the first and second banks includes a plurality of pages each having a predetermined data storage capacity.

23. The method ofclaim 16, wherein the first and second data storage devices are first and second flash memory chips, respectively.

24. The method ofclaim 22, wherein the data storage capacity of each buffer is equal to, or N (N=1, 2, 3) times, that of the page.

25. The method ofclaim 16, wherein the data storage capacity of each buffer is equal to, or N (N=1, 2, 3) times, a block size that is a deleting unit of the flash memory.

26. The method ofclaim 16, wherein the non-volatile memory unit and the flash memory unit are formed in a single chip.

27. The method ofclaim 16, wherein the storage unit further includes a flash translation layer and a second input/output bus functioning as an interface between the non-volatile memory buffer unit and the flash memory unit.

28. The method ofclaim 16, wherein the storage unit is provided in the form of a card that can be detachably installed on the host unit.

29. The method ofclaim 16, wherein the host unit further includes a first file system, a second file system, a flash translation layer interfacing with the first file system, and a device driver interfacing with the second file system.

30. The method ofclaim 16, wherein the flash memory unit includes a NAND-type SLC flash memory and a NAND-type MLC flash memory.

31. A method of writing data in a data storage system comprising a host unit, a storage unit and a first input/output bus functioning as an interface between the host unit and the storage unit, wherein the storage unit includes a non-volatile memory buffer unit and a flash memory unit, the non-volatile memory unit including a plurality of buffers arranged in parallel and the flash memory unit including a plurality of data storage devices arranged in parallel, the method comprising:

writing data written in a first page of a first data storage device of the plurality of data storage devices in a first buffer of the plurality of buffers;

writing data written in a first page of a second data storage device of the plurality of data storage devices in a second buffer of the plurality of buffers;

writing data written in a second page of the first data storage device of the plurality of data storage devices in a third buffer of the plurality of buffers;

wherein the writing of the data written in the first page of the second data storage device starts after the writing of the data written in the first page of the first data storage starts and ends after the writing of the data written in the first page of the first data storage device ends and the writing of the data written in the second page of the first storage device starts after the writing of the data written in the first page of the first data storage device ends; and

while the writing of the data written in the first page of the second data storage device in the second buffer is performed, the data written in the first buffer is read and while the writing of the data written in the second page of the first data storage device in the third buffer is performed, the data written in the second buffer is read.

32. The method ofclaim 31, further comprising writing data written in a second page of a second data storage device in the first buffer after the data written in the first buffer is read and before the writing of the data written in the second page of the first data storage device in the third buffer ends.

33. The method ofclaim 31, wherein the buffer is one of a bank and a non-volatile memory chip having a predetermined data storage capacity.

34. The method ofclaim 31, wherein the first and second data storage devices are first and second banks, respectively, and each of the first and second banks includes a plurality of pages each having a predetermined data storage capacity.

35. The method ofclaim 31, wherein the first and second data storage devices are first and second flash memory chips, respectively.

36. The method ofclaim 31, wherein the data storage capacity of the first buffer is equal to, or N (N=1, 2, 3) times, that of the first page.

37. The method ofclaim 31, wherein the data storage capacity of the first buffer is equal to, or N (N=1, 2, 3) times, a block size that is a deleting unit of the flash memory.

38. The method ofclaim 31, wherein the non-volatile memory unit and the flash memory unit are formed in a single chip.

39. The method ofclaim 31, wherein the storage unit further includes a flash translation layer and a second input/output bus functioning as an interface between the non-volatile memory buffer unit and the flash memory unit.

40. The method ofclaim 31, wherein the storage unit is provided in the form of a card that can be detachably installed on the host unit.

41. The method ofclaim 31, wherein the host unit further includes a first file system, a second file system, a flash translation layer interfacing with the first file system, and a device driver interfacing with the second file system.

42. The method ofclaim 31, wherein the flash memory unit includes a NAND-type SLC flash memory and a NAND-type MLC flash memory.

43. A method of storing data in a data storage system having a flash memory unit and a writing buffer unit, the method comprising:

classifying a writing request into one of a plurality of grades according to a writing request frequency when a writing request is made; and

storing the writing requested data in one of the memory unit and the writing buffer unit according to the writing request frequency.

44. The method ofclaim 43, wherein, when the writing request is classified into one of two grades, the data having a relatively high writing request frequency is stored in the writing buffer unit and the data having a relatively low writing request frequency is stored in the flash memory unit.

45. The method ofclaim 43, wherein the writing buffer unit includes a plurality of writing buffers arranged in parallel.

46. The method ofclaim 45, wherein, when the writing request is classified into one of two grades, the storing of the writing requested data comprises:

temporarily storing data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers; and

temporarily storing data having a relatively low writing request frequency in a second writing buffer of the plurality of writing buffers or in the flash memory unit.

47. The method ofclaim 45, wherein, when the writing request is classified into one of three grades, the storing of the writing requested data comprises:

temporarily storing data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers;

temporarily storing data having a middle writing request frequency in a second writing buffer of the plurality of writing buffers; and

storing data having a relatively low writing request frequency in the flash memory unit.

48. The method ofclaim 45, wherein, when the writing request is classified into one of three grades, the storing of the writing requested data comprises:

temporarily storing data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers;

temporarily storing data having a middle writing request frequency in a second writing buffer of the plurality of writing buffers; and

temporarily storing data having a relatively low writing request frequency in a third writing buffer of the plurality of writing buffers.

49. The method ofclaim 43, wherein, when there is a page for the writing request available in the writing buffer unit, the page of the writing buffer unit is updated to the available page in the writing buffer unit regardless of the classification of the writing request.

50. The method ofclaim 43, wherein the classifying of the writing request comprises classifying the writing request as a hot or cold page using one or more LRU (Least Recently Used) Q.

51. The method ofclaim 43, wherein the classifying of the writing request comprises adding a count value to the writing request and classifying the writing request according to whether the count value is reduced to a predetermined value after a predetermined time has lapsed.

52. The method ofclaim 43, wherein the storing of the writing requested data comprises storing a page having a relatively high writing request frequency in the writing buffer unit, and, when the writing buffer unit is full, storing one of the pages stored in the writing buffer unit in the flash memory unit.

53. The method ofclaim 43, wherein the writing buffer is one selected from the group consisting of an MRAM, a PRAM, an FRAM, and a non-volatile polymer memory chip, or a combination thereof.

54. The method ofclaim 43, wherein the writing buffer unit is a battery attached type non-volatile memory.

55. The method ofclaim 43, wherein the flash memory unit includes a NAND-type SLC flash memory and a NAND-type MLC flash memory.

56. The method ofclaim 44, wherein the flash memory unit is one of a NAND-type SLC flash memory and a NAND-type MLC flash memory.

57. The method ofclaim 44, wherein, when the data having the relatively high writing request frequency is to be written in the writing buffer unit and the writing buffer unit is full, data stored in the writing buffer unit and having a relatively low using frequency is stored in the flash memory, after which the data having the relatively high writing request frequency is stored in the writing buffer unit.

58. The method ofclaim 44, wherein, after the data having the relatively high writing request frequency is stored in the writing buffer unit, metadata is updated.

59. The method ofclaim 46, wherein the flash memory unit is one of a NAND-type SLC flash memory and a NAND-type MLC flash memory.

60. The method ofclaim 47, wherein the flash memory unit is one of a NAND-type SLC flash memory and a NAND-type MLC flash memory.

61. The method ofclaim 48, wherein the flash memory unit is one of a NAND-type SLC flash memory and a NAND-type MLC flash memory.

62. The method ofclaim 52, wherein, after the data having the relatively high writing request frequency is stored in the writing buffer unit, metadata is updated

63. The method ofclaim 57, wherein, after the data having the relatively high writing request frequency is stored in the writing buffer unit, metadata is updated

64. A data storage system comprising:

a memory unit having a flash memory unit and a writing buffer unit; and

a memory control unit including a page classification unit for classifying a writing request into one of a plurality of grades according to a writing request frequency when a writing request is made, wherein the memory control unit stores the writing requested data in one of the memory unit and the writing buffer unit according to the writing request frequency.

65. The data storage system ofclaim 64, wherein, when the writing request is classified into one of two grades, the memory control unit stores data having a relatively high writing request frequency in the writing buffer unit and stores data having a relatively low writing request frequency in the flash memory unit.

66. The data storage system ofclaim 64, wherein the writing buffer unit includes a plurality of writing buffers arranged in parallel.

67. The data storage system ofclaim 66, wherein, when the writing request is classified into one of two grades, the memory control unit temporarily stores data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers, and temporarily stores data having a relatively low writing request frequency in a second writing buffer of the plurality of writing buffers or in the flash memory unit.

68. The data storage system ofclaim 66, wherein, when the writing request is classified into one of three grades, the memory control unit temporarily stores data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers, temporarily stores data having a middle writing request frequency in a second writing buffer of the plurality of writing buffers, and stores data having a relatively low writing request frequency in the flash memory unit.

69. The data storage system ofclaim 66, wherein, when the writing request is classified into one of three grades, the memory control unit temporarily stores data having a relatively high writing request frequency in a first writing buffer of the plurality of writing buffers, temporarily stores data having a middle writing request frequency in a second writing buffer of the plurality of writing buffers, and temporarily stores data having a relatively low writing request frequency in a third writing buffer of the plurality of writing buffers.

70. The data storage unit ofclaim 64, wherein the writing buffer is one selected from the group consisting of an MRAM, a PRAM, an FRAM, and a non-volatile polymer memory chip, or a combination thereof.

71. The data storage unit ofclaim 64, wherein the writing buffer unit is a battery attached type non-volatile memory.

72. The data storage unit ofclaim 64, wherein the writing buffer unit is a volatile memory.

73. The data storage unit ofclaim 64, wherein the flash memory unit is one of a SLC flash memory and a MLC flash memory.

74. The data storage unit ofclaim 65, wherein the flash memory unit is one of a SLC flash memory and a MLC flash memory.

75. The data storage unit ofclaim 67, wherein the flash memory unit is one of a SLC flash memory and a MLC flash memory.

76. The data storage unit ofclaim 69, wherein the flash memory unit is one of a SLC flash memory and a MLC flash memory.

Images