US20090078999A1 - Semiconductor device structures with floating body charge storage and methods for forming such semiconductor device structures. - Google Patents

Abstract

Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths. When electrically biased, the floating charge-neutral region at least partially resides in the wider section of the semiconductor body.

Description

FIELD OF THE INVENTION
• The invention relates to semiconductor device structures and methods and, in particular, to semiconductor device structures having floating body charge storage permitting operation as a memory cell and methods of forming such semiconductor device structures.
BACKGROUND OF THE INVENTION
• Dynamic random access memory (DRAM) devices are the most commonly used type of semiconductor memory and, thus, are found in many integrated circuit designs. A generic DRAM device includes a plurality of substantially identical memory cell arrays, a plurality of bit lines, and a plurality of word lines that intersect the bit lines. Each individual memory cell array includes a plurality of memory cells arranged in rows and columns. Each individual memory cell includes a storage capacitor for storing data in the form of charges and an access device, such as a planar or vertical field effect transistor (FET), for allowing the transfer of data charges to, and from, the storage capacitor during read and write operations. Each memory cell in the array is located at the intersection of one of the word lines and one of the bit lines. Either the source or drain of the access device is connected to one of the bit lines and the gate of the access device is connected to one of the word lines.
• A different type of dynamic memory, referred to as zero capacitor DRAM or ZRAM, has been developed in which the charge is stored in a charge-neutral floating body of a transistor. Conventionally, the transistor used in a ZRAM device is built using a silicon-on-insulator substrate, which provides a high degree of isolation for the floating body to the substrate.
• Fin-type field effect transistors (FinFETs) are low-power, high-speed non-planar devices that can be more densely packed in an integrated circuit than traditional planar transistors. In comparison with traditional planar transistors, the three-dimensional FinFETs offer superior short channel scalability, a reduced threshold voltage swing, higher mobility, and the ability to operate at lower supply voltages.
• An integrated circuit that includes FinFETs may be fabricated a silicon-on-insulator (SOI) wafer that includes an active SOI layer of a single crystal semiconductor, such as silicon, a semiconductor substrate, and a buried insulating layer that separates and electrically isolates the semiconductor substrate from the SOI layer. Each FinFET includes a narrow vertical semiconductor body fashioned from the SOI layer. The sidewalls of each FinFET intersect the buried insulating layer. A conductive gate electrode, which intersects a channel of the semiconductor body, is isolated electrically from the semiconductor body by a thin gate dielectric layer. The opposite ends of the semiconductor body, which project outwardly from beneath the gate electrode, are heavily doped to define source and drains that flank the channel. When a voltage exceeding a characteristic threshold voltage is applied to the gate electrode, a depletion/inversion layer is formed in the channel that permits carrier flow between the source and drain (i.e., the device output current).
• A FinFET may be operated in two distinct modes contingent upon the characteristics of the depletion layer. A FinFET is considered to operate in a partially-depleted mode when the depletion layer fails to extend completely across the width of the fin body. The undepleted portion of the fin body in the channel, which is electrically conductive, slowly charges as the FinFET is switched to various voltages depending upon its most recent history of use. A FinFET is considered to operate in a fully-depleted mode when the depletion layer extends across the full width of the fin body and there is no charge-neutral region of the body
• Generally, a fully-depleted FinFET exhibits performance gains in comparison with a FinFET operating in a partially-depleted mode. Specifically, fully-depleted FinFETs exhibit significant reductions in leakage current and dissipate less power into the substrate, which reduces the probability of device overheating. Parasitic capacitances are also greatly reduced in fully-depleted FinFETs, which significantly improves the device switching speed.
• What is needed, nevertheless, is a FinFET device construction that operates as a memory cell in which a floating charge-neutral region of the partially-depleted semiconductor body of the FinFET is advantageously used for charge storage.
SUMMARY OF THE INVENTION
• An embodiment of the invention is directed to a semiconductor device structure carried on a dielectric layer. The semiconductor device structure comprises a semiconductor body having first and second sidewalls extending to the dielectric layer. The semiconductor body, which is doped with an impurity of a conductivity type, includes a first section at least partially intersected by a gate electrode and a second section. The first section is wider than the second section. The width of the first section and a concentration of the impurity in the first section are selected such that the first section is partially depleted to define a floating charge-neutral region therein when biased by a bias potential applied by the gate electrode.
• Another embodiment of the invention is directed to a method of forming a semiconductor structure using a semiconductor-on-insulator substrate having a semiconductor layer, a bulk region of a first conductivity type underlying the semiconductor layer, and a dielectric layer between the semiconductor layer and the bulk region. The method comprises patterning the semiconductor layer to define a semiconductor body with sidewalls extending to the dielectric layer. The semiconductor body has a first section with a first width between the opposite sidewalls and a second section with second width between the opposite sidewalls that is narrower than the first width. The method further comprises introducing an impurity into the first section of the semiconductor body with a first concentration selected in conjunction with the first width such that, when the first section is biased by a bias potential, the first section is partially depleted to define a floating charge-neutral region therein. In an alternative embodiment, the first impurity may also be introduced into the second section of the semiconductor body with a second concentration selected in conjunction with the second width such that, when the second section is biased by the bias potential, the second section is fully depleted.
• The semiconductor device structures of the embodiments of the invention may operate with stored-charge retention times, which may lower operation power. Embodiments of the invention rely on a FinFET operating in a partially-depleted mode in which a portion of the semiconductor body of the partially-depleted FinFET is used for charge storage. The state of memory cell is determined by the concentration of charge within an electrically-floating body region resulting from operation in a partially-depleted mode.
BRIEF DESCRIPTION OF THE DRAWINGS
• The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.
• FIG. 1A is diagrammatic top view of a portion of a substrate at an initial fabrication stage of a processing method in accordance with an embodiment of the invention.
• FIG. 1B is a diagrammatic cross-sectional view taken generally alongline1B-1B ofFIG. 1A.
• FIG. 2A is diagrammatic top view of the substrate portion at a fabrication stage subsequent toFIG. 1A.
• FIG. 2B is a diagrammatic cross-sectional view taken generally alongline2B-2B ofFIG. 2A.
• FIG. 3A is diagrammatic top view of the substrate portion at a fabrication stage subsequent toFIG. 2A.
• FIG. 3B is a diagrammatic cross-sectional view taken generally alongline3B-3B ofFIG. 3A.
• FIG. 4A is diagrammatic top view of the substrate portion at a fabrication stage subsequent toFIG. 3A.
• FIG. 4B is a diagrammatic cross-sectional view taken generally alongline4B-4B ofFIG. 4A.
• FIG. 5A is diagrammatic top view of the substrate portion at a fabrication stage subsequent toFIG. 4A.
• FIG. 5B is a diagrammatic cross-sectional view taken generally alongline5B-5B ofFIG. 5A.
• FIG. 5C is a diagrammatic cross-sectional view taken generally alongline5C-5C ofFIG. 5A.
• FIG. 6A is diagrammatic top view of the substrate portion at a fabrication stage subsequent toFIG. 5A.
• FIG. 6B is a diagrammatic cross-sectional view taken generally alongline6B-6B ofFIG. 6A.
• FIG. 6C is a diagrammatic cross-sectional view taken generally alongline6C-6C ofFIG. 6A.
• FIG. 7 is diagrammatic top view showing an array of the semiconductor device structures ofFIG. 6A distributed across a larger-area portion of the substrate.
• FIG. 8A is diagrammatic top view of the substrate portion similar toFIG. 6A, but in accordance with an alternative embodiment of the invention.
• FIG. 8B is a diagrammatic cross-sectional view taken generally alongline8B-8B ofFIG. 8A.
• FIG. 8C is a diagrammatic cross-sectional view taken generally alongline8C-8C ofFIG. 8A.
• FIG. 9A is diagrammatic top view of the substrate portion similar toFIG. 6A, but in accordance with an alternative embodiment of the invention.
• FIG. 9B is a diagrammatic cross-sectional view taken generally alongline9B-9B ofFIG. 9A.
• FIG. 9C is a diagrammatic cross-sectional view taken generally alongline9C-9C ofFIG. 9A.
• FIG. 10 is a diagrammatic cross-sectional view taken in a source of the semiconductor fin in accordance with an alternative embodiment of the invention.
DETAILED DESCRIPTION
• With reference toFIGS. 1A and 1B, a semiconductor-on-insulator (SOI)substrate10 includes asemiconductor layer12 with atop surface13, a buried insulatinglayer14, and a handle orbulk region16 separated from thesemiconductor layer12 by the buried insulatinglayer14. Thesemiconductor layer12 and buried insulatinglayer14 are coextensive along a boundary orinterface18. Similarly, thebulk region16 and buried insulatinglayer14 are coextensive along a boundary orinterface20.
• TheSOI substrate10 may be fabricated by any suitable conventional technique, such as a wafer bonding and splitting technique. In the representative embodiment, thesemiconductor layer12 is made from a single crystal or monocrystalline silicon-containing material, such as silicon, and thebulk region16 may likewise be formed from a single crystal or monocrystalline silicon-containing material, such as silicon. Thesemiconductor layer12 may be as thin as about 10 nanometers or less and, typically, is in the range of about 5 nanometers to about 150 nanometers, but is not so limited. The thickness of thebulk region16, which is considerable thicker than thesemiconductor layer12, is not shown to scale inFIG. 1. The buried insulatinglayer14 comprises a conventional dielectric material, such as silicon dioxide (SiO₂), and may have a thickness in the range of about 50 nanometers to about 150 nanometers, although not so limited.
• Thetop surface13 ofsemiconductor layer12 is covered by a pad stack consisting of first and second pad layers22,24. The thinnerfirst pad layer22 separates the thickersecond pad layer24 from thesemiconductor layer12. The constituent material(s) of pad layers22,24 are chosen to etch selectively to the semiconductor material constitutingsemiconductor layer12 and to be readily removed at a subsequent stage of the fabrication process. Thefirst pad layer22 may be SiO₂with a thickness on the order of about 5 nanometers to about 10 nanometers and may be grown by exposing thesemiconductor layer12 to either a dry oxygen ambient or steam in a heated environment or deposited by a conventional deposition process, such as thermal chemical vapor deposition (CVD). Thesecond pad layer24 may be a conformal layer of silicon nitride (Si₃N₄) with a thickness on the order of about 20 nanometers to about 200 nanometers and deposited by a thermal CVD chemical vapor deposition process like low-pressure chemical vapor deposition (LPCVD) or a plasma-assisted CVD process. Thefirst pad layer22 may operate as a buffer layer to prevent any stresses in the material constituting thesecond pad layer24 from initiating the formation of dislocations in the semiconductor material ofsemiconductor layer12.
• A resistlayer26 is applied on a top surface ofpad layer24 and patterned by a conventional lithography process. The resistlayer26 may be patterned by exposure to radiation, which creates a latent pattern in the constituent resist, and then developing the latent pattern in the exposed resist. The residual portions of the resistlayer26 define a mask that is used to pattern the pad layers22,24 and, subsequently, thesemiconductor layer12.
• The patterned resistlayer26 includes an array of substantially identical linear features, of whichlinear feature28 is representative.Linear feature28 includes constituent sub-features characterized by graduated or modulated widths. Specifically,linear feature28 includes relativelynarrow sections30, taperedsections32, and relativelywide sections34 joined in continuity with thenarrow sections30 and taperedsections32. Thenarrow sections30 andwide sections34 are arranged such that each of the relativelywide sections34 is disposed between a pair of adjacentnarrow sections30. Eachnarrow section30 is characterized by a constant width, W₁, and each of thewide sections34 is characterized by a constant width, W₂. Each of the taperedsections32 provides a dimensional transition between the width, W₁, of each of thenarrow sections30 and the width, W₂, of the adjacent one of thewide sections34. The widths of thesections30,32,34 are measured in a transverse direction relative to the sidewalls of thelinear feature28.
• In an alternative embodiment, the pad stack including pad layers22,24 can be omitted such that the patterned resistlayer26 is supported directly on thetop surface13 of thesemiconductor layer12.
• With reference toFIGS. 2A and 2B in which like reference numerals refer to like features inFIGS. 1A and 1B, respectively, and at a subsequent fabrication stage, thesemiconductor layer12 is patterned to define a plurality of substantially identical semiconductor fins, of whichsemiconductor fin36 is representative, that are distributed across theSOI substrate10 to reflect the patterned resist layer26 (FIGS. 1A and 1B). Thesemiconductor layer12 may be patterned using a conventional etching process that relies on the patterned resistlayer26 as a mask. In one embodiment, an anisotropic dry etching process, such as reactive-ion etching (RIE) or plasma etching, may be employed to transfer the pattern from the patterned resistlayer26 into the pad layers22,24 and, thereby, define a hardmask. The etching process, which may be conducted in a single etching step or multiple etching steps with different etch chemistries, removes portions of the pad layers22,24 visible through the pattern in the patterned resist and stops vertically on thetop surface13 ofsemiconductor layer12. After etching is concluded, resistlayer26 is stripped from the pad layers22,24 by, for example, plasma ashing or a chemical stripper.
• The pattern is then transferred from the patterned pad layers22,24 of the hardmask into theunderlying semiconductor layer12. The transfer may be accomplished using an anisotropic dry etching process such as, for example, a RIE or a plasma etching process. In one embodiment, an etch chemistry (e.g., a standard silicon RIE process) is employed to extend the pattern through thesemiconductor layer12 that removes the constituent semiconductor material selective to (i.e., with a significantly greater etch rate than) the materials constituting the pad layers22,24 and that stops on the buried insulatinglayer14. As a result, thesemiconductor layer12 is patterned to the depth of the buried insulatinglayer14.
• Thesemiconductor fin36 has a geometrical shape of constituent sub-features characterized by graduated or modulated widths that matches the respective overlyinglinear feature28 in the patterned resistlayer26. Specifically,semiconductor fin36 includes a series of spaced-apart relatively narrow sections, such as the representativenarrow sections37,38. Thenarrow sections37,38 are spatially correlated with and underlie thenarrow sections30 of thelinear feature28 of resist layer26 (FIG. 1).Semiconductor fin36 also includes a series of tapered sections, such as the representativetapered sections39,40,41, that are spatially correlated with and underlie thetapered sections32 of thelinear feature28 of resistlayer26.Semiconductor fin36 also includes a series of relatively wide sections, such as the representative relativelywide sections42,43, joined in continuity with thenarrow sections38 and taperedsections40. Thewide sections42 are spatially correlated with and underlie thewide sections34 of thelinear feature28 of resistlayer26.
• The sections38-43 are distributed along the length of thesemiconductor fin36. Thenarrow sections37,38 andwide sections42,43 of thesemiconductor fin36 are arranged such thatwide section42 is disposed between the adjacentnarrow sections37,38 andwide section43 is disposed betweennarrow section38 and an adjacent narrow section (not shown). Eachnarrow section37,38 is characterized by a constant width, W₃, measured between the sidewalls44,46 and each of thewide sections42,43 is characterized by a constant width, W₄, likewise measured between the sidewalls44,46. The width W₄of thewide sections42,43 is greater than the width W₃of thenarrow sections37,38. Thetapered sections39,40,41 provide dimensional transitions between the width, W₃, of thenarrow sections37,38 and the width, W₄, of thewide sections42,43. By definition, thetapered sections39,40,41 have a width that is narrower than the width W₄of thewide sections42,43.
• Thesemiconductor fin36 includesopposite sidewalls44,46 that extend from thetop surface13 to the buried insulatinglayer14. Theopposite sidewalls44,46 are substantially parallel to each other and perpendicular to thetop surface13 because of the directionality of the anisotropic etching process. Theopposite sidewalls44,46 are oriented substantially perpendicular to thetop surface13 ofsemiconductor fin36 and to the buried insulatinglayer14. The initial thickness of thesemiconductor layer12 determines the height, h, of thesemiconductor fins36. The distance between theopposite sidewalls44,46 varies between the widths W₃and W₄along the length ofsemiconductor fin36 because of the width modulation. The widths of the sections38-43 are measured in a transverse direction relative to thesidewalls44,46 of thesemiconductor fin36.
• Semiconductor fin36 is doped with animpurity48 that, when activated, is effective to increase the electrical conductivity of the constituent semiconductor material. If thesemiconductor fin36 is used for forming n-type field effect transistors,semiconductor fin36 may be doped with a p-type impurity48, such as boron (B), indium (In), or gallium (Ga). Alternatively, thesemiconductor fin36 may be doped with an n-type impurity48, such as arsenic (As), phosphorus (P), or antimony (Sb), for use in forming p-type field effect transistors. Theimpurity48 may introduced intosemiconductor fin36 by an angled ion implantation process, or by another technique for doping semiconductor material with an impurity, as understood by a person having ordinary skill in the art.
• In one embodiment, theimpurity48 is introduced into thesidewalls44,46 ofsemiconductor fin36 by an angled ion implantation process. An ensuing high-temperature anneal activates and distributes theimpurity48 throughout the semiconductor material of thesemiconductor fin36 and may also alleviate any crystal damage introduced by the ion implantation process.
• The concentration ofimpurity48 is selected in conjunction with widths W₃and W₄such that, when biased during device operation, the semiconductor material of at least a portion of each taperedsection39,40,41 ofsemiconductor fin36 is fully depleted, and at least a portion of eachwide section42,43 ofsemiconductor fin36 is partially depleted. The doping in thenarrow sections37,38 ofsemiconductor fin36 affects the threshold voltage of the subsequently formed field effect transistor. A typical concentration forimpurity48 in the semiconductor material may be approximately 1×10¹⁹cm⁻³.
• With reference toFIGS. 3A and 3B in which like reference numerals refer to like features inFIGS. 2A and 2B, respectively, and at a subsequent fabrication stage, agate dielectric layer50 is formed on thesidewalls44,46 ofsemiconductor fin36 and adjacent semiconductor fins (not shown). Thegate dielectric layer50 may comprise any suitable dielectric or insulating material like silicon dioxide, silicon oxynitride, a high-k dielectric material such as hafnon (HfSiO₄), or combinations of these materials. The dielectric material constitutinggate dielectric layer50 may have a thickness between about 1 nm and about 10 nm. Thegate dielectric layer50 may be formed by a CVD process, a physical vapor deposition (PVD) process, thermal reaction of the semiconductor material ofsemiconductor fin36 with a reactant, an atomic layer deposition process (ALD) or a combination of these techniques.
• Gate electrodes, such as therepresentative gate electrodes52,54,56, are formed across theSOI substrate10 from a layer of a gate conductor material that is deposited on the buried insulatinglayer14 such thatsemiconductor fin36 is covered. The gate conductor material may be, for example, doped polysilicon, a silicided gate conductor comprising polysilicon capped with a silicide containing a metal like nickel (Ni) or cobalt (Co), a metal such as tungsten (W), molybdenum (Mo), or tantalum (Ta), or any other refractory metal, or any other appropriate material deposited by a CVD process, a PVD process, etc. The layer of gate conductor material is covered by a hardmask, which is patterned using photolithography. An anisotropic etching process relies on the hardmask to remove portions of the layer of gate conductor material to definegate electrodes52,54,56. The etching process also removes thegate insulator layer50 from sections ofsemiconductor fin36 not covered by thegate electrodes52,54,56. Residual portions of thegate dielectric layer50 separate thesidewalls44,46 ofsemiconductor fin36 from thegate electrodes52,54,56. The pad layers22,24 and thegate dielectric layer50 are disposed between thetop surface13 of thesemiconductor fin36 and thegate electrodes52,54,56. The etching process, which stops on the buried insulatinglayer14, selectively removes portions of the layer of gate conductor material andgate dielectric layer50 without removing the semiconductor material contained insemiconductor fin36.
• Gate electrode52 includes atop surface58 and sidewalls59,60 that extend from thetop surface58 to intersect the buried insulatinglayer14. Similarly,gate electrode54 includes atop surface62 and sidewalls63,64 that extend from thetop surface62 to intersect the buried insulatinglayer14.Gate electrode56 likewise includes atop surface66 and sidewalls67,68 that extend from thetop surface66 to intersect the buried insulatinglayer14. The top surfaces58,62,66 are illustrated as overlapping thetop surface13 ofsemiconductor fin36.
• Gate electrode52 intersects thesemiconductor fin36 along achannel70 and, in the representative embodiment, partially overlapsnarrow section37,wide section42, and taperedsection39.Gate electrode54 intersects thesemiconductor fin36 along achannel71 and, in the representative embodiment, partially overlapsnarrow section38,wide section42, and taperedsection40.Gate electrode54 intersects thesemiconductor fin36 along achannel72 and, in the representative embodiment, partially overlapsnarrow section38,wide section43, and taperedsection41.
• In an alternative embodiment, the thickness of thegate electrodes52,54,56 may be reduced to be less than the height of thesemiconductor fin36. As a result, each of thegate electrodes52,54,56 is divided into two distinct electrically disconnected gates separated by the width of the semiconductor fin36 (i.e., the distance between the sidewalls44,46). Because of the thickness reduction, thegate electrodes52,54,56 will not overlap thesemiconductor fin36. For example,gate electrode54 may be reduced in thickness, as indicated by the dashed line inFIG. 3B, such thatgate electrode54 has twoportions54a,54bthat are not electrically coupled.Portion54amay be employed as a back gate for transferring charge to and from the floating charge-neutral region112 (FIG. 7) andportion54bmay be utilized as a wordline in the device construction.
• With reference toFIGS. 4A and 4B in which like reference numerals refer to like features inFIGS. 3A and 3B, respectively, and at a subsequent fabrication stage,dielectric spacers75,76 are formed on thesidewalls59,60 of thegate electrode52 and extend from a top surface ofgate electrode52 to the buried insulatinglayer14. Similarly,dielectric spacers77,78 are formed on thesidewalls63,64 of thegate electrode54 anddielectric spacers79,80 are formed on thesidewalls63,64 of thegate electrode56. Dielectric spacers77-80 each extend from a top surface of therespective gate electrode54,56 to the buried insulatinglayer14. The dielectric spacers75-80 may originate from a conformal layer (not shown) of an electrically insulating material, such as about 10 nanometers to about 50 nanometers of Si₃N₄deposited by CVD, that is shaped by a directional anisotropic etching process that preferentially removes the conformal layer from horizontal surfaces.
• Portions of thesemiconductor fin36, which are exposed by thegate electrodes52,54,56, are doped with a concentration of animpurity82 that has a conductivity type opposite to the impurity48 (FIG. 2). Theimpurity82 may comprise As, P, or Sb for n-type device structures or, for p-type device structures, B, In, or Ga. The concentration ofimpurity82 in the exposed portion of eachnarrow section37,38 is effective to impart a conductivity characteristic ofdrains83,84 of a field effect transistor. The concentration ofimpurity82 in the exposed portion of eachwide section42,43 is effective to impart a conductivity characteristic ofsources86,87 of a field effect transistor.Source86 includes a first portion86acontaining theimpurity82 that is located proximate tosidewall44 and a second portion86bcontaining theimpurity82 that is located proximate tosidewall46. Similarly,source87 includes a first portion87acontaining theimpurity82 that is located proximate tosidewall44 and asecond portion87bcontaining theimpurity82 that is located proximate tosidewall46.
• Theimpurity82 is introduced into thesidewalls44,46 with a limited range so that thesources86,87 do not extend completely across the width of thewide sections42,43. As a result, a width of thesemiconductor fin36 between the portions86a,86bofsource86 is not doped withimpurity82. Similarly, a width of thesemiconductor fin36 between theportions87a,87bofsource87 is not doped withimpurity82. Instead, these widths of thesemiconductor fin36 have a conductivity characteristic of impurity48 (FIGS. 2A,2B), which is opposite in conductivity type toimpurity82.
• Theimpurity82 may be introduced into thesemiconductor fin36 by angled ion implantation, followed by a high-temperature anneal to activate the impurity and to alleviate any damage introduced by the implantation process. For example, an appropriate dose for the implantedimpurity82 may be about 5×10¹⁵cm⁻². Because of the high impurity concentration, the source and drains83,84,86,87 have a degenerate level of doping such that the constituent semiconductor material has conductive character or, in other words, a character that is more similar to a conductor than a semiconductor. Therefore, regardless of operating or bias conditions, the source and drains83,84,86,87 are electrically conducting. Collectively, the pad layers22,24 have a thickness adequate to operate as an implant mask for thetop surface13 of thesemiconductor fin36, which helps to preserve the integrity of the floating bodies as described below. Optionally, extension and halo implants may be performed into the channels70-72.
• With reference toFIGS. 5A-5C in which like reference numerals refer to like features inFIGS. 4A and 4B, respectively, and at a subsequent fabrication stage, linear features, such as the representative linear feature inwide section42 generally indicated byreference numeral90, are defined in thewide sections42,43 of thesemiconductor fin36. Linear feature90 forms a discontinuity in thewide section42 ofsemiconductor fin36 that physically separates thewide section42 to definedistinct semiconductor bodies42a,42b. A similar linear feature (not shown) is formed inwide section43.Source86, which is divided by thelinear feature90, is still shared by thesemiconductor bodies42a,42b. As explained below, both portions of the dividedsource86 are coupled with a shared electrical contact and, therefore, are coupled electrically in the final device structure. Another semiconductor body42cshares drain84 withsemiconductor body42b. In addition, another semiconductor body (not shown) of an adjacent wide section (not shown) shares drain83 withsemiconductor body42a.
• In one embodiment, thelinear feature90 may be formed by a standard lithography and etching process familiar to a person having ordinary skill in the art that removes a strip of the constituent semiconductor material in eachwide section42 extending from one of thesidewalls44 to theopposite sidewall46. The etching process stops on the buried insulatinglayer14 so that thelinear feature90 extends vertically from thetop surface13 to the buried insulatinglayer14, as best shown inFIG. 5C. Asidewall92 ofsemiconductor body42aconfronts asidewall94 ofsemiconductor body42b.
• The pad layers22,24 are removed from thesemiconductor bodies42a,42b,42cby a separate wet chemical etch process selective to the material constituting thesemiconductor fin36. For example, the wet chemical etch process may entail sequentially exposing the pad layers22,24 to a heated etchant solution of phosphoric acid effective to remove nitride and an etchant solution of hydrofluoric acid effective to remove oxide.
• Asilicide layer96 is formed on thetop surface13 and sidewalls44,46 of thesemiconductor fin36 not covered by thegate electrodes52,54,56 and dielectric spacers75-80 by a silicidation process familiar to a person having ordinary skill in the art. Thesilicide layer96 provides a low resistance contact to the semiconductor material constituting thesemiconductor fin36.
• In one representative silicidation process, the silicidation process formingsilicide layer96 includes depositing a layer of suitable metal, such as nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), etc., across theSOI substrate10 and then subjecting the metal-coatedSOI substrate10 to a high temperature anneal by, for example, a rapid thermal annealing process. During the high temperature anneal, the metal reacts with the silicon-containing semiconductor material (e.g., silicon) of thesemiconductor fin36 to form thesilicide layer96. The annealing phase of the silicidation process may be conducted in an inert gas atmosphere or in a nitrogen-rich gas atmosphere, and at a temperature of about 350° C. to about 800° C. contingent upon the type of metal silicide being considered. Following the high temperature anneal, unreacted metal remains on the buried insulatinglayer14, the dielectric spacers75-80, and thegate electrodes52,54,56 (i.e., where the deposited metal is not in contact with a silicon-containing material). Unreacted metal is selectively removed using, for example, an isotropic wet chemical etch process.
• With reference toFIGS. 6A-C in which like reference numerals refer to like features inFIGS. 5A-C, respectively, and at a subsequent fabrication stage, ablanket layer98 of an insulating material is applied across theSOI substrate10 and planarized by a conventional planarization process like chemical mechanical planarization (CMP). The insulating material of theblanket layer98, which supplies an interlayer dielectric, may be composed of a spin-on glass (SOG) material applied by coating theSOI substrate10 with SOG material in liquid state, spinning theSOI substrate10 at high speeds to uniformly distribute the liquid on the surface by centrifugal forces, and baking at a low temperature to solidify the SOG material. Alternatively, the insulating material of theblanket layer98 may include multiple coatings of different dielectric materials as understood by a person having ordinary skill in the art.
• A portion of the dielectric material ofblanket layer98 fills thelinear feature90 to define anisolation region100 between the confrontingsidewalls92,94 ofsemiconductor bodies42a,42b. Theisolation region100 is characterized by a “mesa-type” appearance familiar to a person having ordinary skill in the art. Theisolation region100 electrically isolatesadjacent semiconductor bodies42a,42bfrom each other. Additional isolation regions (not shown), each substantially identical toisolation region100, electrically isolate other semiconductor bodies (not shown) of thesemiconductor fin36 from reach other.
• Electrical contacts to thedrains83,84, such as the representative electrical contact defined byplug102 to drain84, are defined in theblanket layer98. Electrical contacts to thesources86,87, such as the representative electrical contact defined byplug104 tosource86, are concurrently defined in theblanket layer98.Plug102 is electrically coupled with a sense line in one of the metallization levels (not shown).Plug104 is electrically coupled with a bit line in one of the metallization levels (not shown). In one embodiment, theplugs102,104 are formed by lithographically patterning theblanket layer98 in a conventional manner to form vias to thedrains83,84 and to thesources86,87.Plugs102,104 are formed into the vias using a conventional deposition technique, such as CVD or plating, that deposits conductive material in the vias and a chemical mechanical polishing (CMP) process that removes excess conductive material. Suitable conductive materials include, but are not limited to, doped polysilicon, a silicide (e.g., WSi), or metals such as tungsten (W), copper (Cu), aluminum (Al), gold (Au), and alloys thereof deposited by evaporation, sputtering, or other known deposition techniques.
• With reference toFIG. 7 in which like reference numerals refer to like features inFIGS. 6A-6C, thesemiconductor fin36 contains a one-dimensional, linear array of semiconductor bodies, such as therepresentative semiconductor bodies42a,42b,42c, that are functional as semiconductor device structures, which are indicated generally byreference numerals106,108,110. Each of thesemiconductor bodies42a,42b,42cincludes, when biased during operation, a respective floating charge-neutral region112,114,116. The floating charge-neutral regions112,114,116, when thesemiconductor bodies42a,42b,42care biased during device operation, represent charge neutral volumes of semiconductor material or floating bodies that exist insemiconductor fin36 as a consequence of partial depletion of carriers. The charge neutral volumes of the floating charge-neutral regions112,114,116 are located between the sidewalls44,46 and between thetop surface13 of thesemiconductor fin36 and thedielectric layer14.
• Floating charge-neutral region112 is located insemiconductor body42abetween thesource86 and drain83 insemiconductor fin36 and at least partially underliesgate electrode52 insections39 and42. Located between the floating charge-neutral region112 and thedrain83 is aregion113 that is fully depleted when thesemiconductor body42ais biased. Floating charge-neutral region114 is located insemiconductor body42abetweensource86 and drain83 insemiconductor fin36 and at least partially underliesgate electrode54 insections40 and42. Located between the floating charge-neutral region114 and thedrain84 is aregion115 that is fully depleted when thesemiconductor body42bis biased. Floating charge-neutral region116 is located in semiconductor body42cbetweensource87 and drain84 and at least partially underliesgate electrode56 insections41 and43. Located between the floating charge-neutral region116 and thedrain84 is aregion117 that is fully depleted when the semiconductor body42cis biased.
• The fully-depletedregions113,115,117 represent volumes of semiconductor material doped with impurity48 (FIGS. 2A,2B) at a concentration and with a width selected to provide full depletion when biased and define channel regions for carrier flow between the corresponding source and drain. The floating charge-neutral regions112,114,116 represent volumes of semiconductor material doped with impurity48 (FIGS. 2A,2B) at a concentration and with a width selected to provide only partial depletion when biased. As the taperedsection39 ofsemiconductor body42anarrows from the width W₄to width W₃, the floating charge-neutral region112 tapers to a tip at an intermediate width between W₄and W₃so as to transition to the fully-depletedregion113, which extends in the taperedsection39 at least between the intermediate width and width W₃. As the taperedsection40 ofsemiconductor body42bnarrows from the width W₄to width W₃, the floating charge-neutral region114 tapers to a tip at an intermediate width between W₄and W₃so as to transition to the fully-depletedregion115, which extends in the taperedsection40 between the intermediate width and width W₃. As the taperedsection41 of semiconductor body42cnarrows from the width W₄to width W₃, the floating charge-neutral region116 tapers to a tip at an intermediate width between W₄and W₃so as to transition to the fully-depletedregion117, which extends in the taperedsection41 between the intermediate width and width W₃.
• Each of the floating charge-neutral regions112,114 may be at least partially located in thewide section42 of thesemiconductor fin36 generally between the two portions86a,86bof thesource86, as shown inFIGS. 6A and 7. Similarly, the floating charge-neutral region116 may be at least partially located in thewide section43 of thesemiconductor fin36 generally between the twoportions87a,87bof thesource87, as also shown inFIGS. 6A and 7. The widths of these portions of the floating charge-neutral regions112,114,116 in thewide sections42,43 of thesemiconductor fin36 may be constant over their length, as depicted inFIGS. 6A and 7.
• Chevron-shaped portions of the floating charge-neutral regions112,114,116 are present in the respectivetapered sections39,40,41. The chevron shape arises from the narrowing of thesidewalls44,46 in taperedsections39,40,41 to a width that results in full depletion. Accordingly, fully-depletedregion113 intervenes between the tip of the chevron-shaped portion of the floating charge-neutral region112 and thenarrow section37, which includes thedrain83. Fully-depletedregion115 intervenes between the tip of the chevron-shaped portion of floating charge-neutral region114 and thenarrow section38, which includes thedrain84. Fully-depletedregion117 intervenes between the tip of the chevron-shaped portion of floating charge-neutral region116 and thenarrow section38, which includes thedrain84.
• The floating charge-neutral regions112,114,116 develop during device operation because thesemiconductor fin36 is only partially depleted in at least a portion of thewide sections42,43 and an adjacent portion of an adjoining one of the taperedsections39,40,41 because of the combination of the width and doping concentration. Consequently, thesemiconductor device structures106,108,110 include fin-type field effect transistors (FinFETs) and floating charge-neutral regions112,114,116 used for charge storage so that thesemiconductor device structures106,108,110 can operate as individual memory cells.
• As apparent fromFIG. 7, thesemiconductor device structures106,108,110 are replicated across theSOI substrate10 during the fabrication process. An adjacent set ofsemiconductor device structures106a,108a,110a, which are similar tosemiconductor device structures106,108,110, are formed using an adjacent semiconductor fin36a, which is similar tosemiconductor fin36. An adjacent set ofsemiconductor device structures106b,108b,110b, which are similar tosemiconductor device structures106,108,110, is formed using anadjacent semiconductor fin36b, which is similar tosemiconductor fin36. An adjacent set of semiconductor device structures106c,108c,110c, which are similar tosemiconductor device structures106,108,110, is formed using an adjacent semiconductor fin36cwhich is similar tosemiconductor fin36. Additional semiconductor device structures (not shown) are formed along the length of each thesemiconductor fins36,36a-cand additional semiconductor fins (not shown), each including additional semiconductor device structures (not shown), may be located in a flanking relationship withsemiconductor fins36,36a-cso as to define a memory cell array.
• Standard processing follows, which includes metallization for the M1 level interconnect wiring, and interlayer dielectric layers, conductive vias, and metallization for upper level (M2-level, M3-level, etc.) interconnect wiring. Metallization in one of the upper levels of interconnect wiring establishes electrical contacts with thegate electrodes52,54,56.
• Theisolation region100 between thesemiconductor bodies42a,42bof thesemiconductor fin36 may be established by alternative types of structures, as described below.
• With reference toFIGS. 8A-C in which like reference numerals refer to like features inFIGS. 6A-C and in accordance with an alternative embodiment, anisolation region130 is defined as a region of thesemiconductor fin36 doped to have the same conductivity type as thesource86. In this embodiment, the pad layers22,24 are removed from thetop surface13 of thesemiconductor fin36 before theimpurity82 is introduced into thesemiconductor fin36. A mask is applied to restrict the introduction ofimpurity82 so thatisolation region130 is defined as a doped portion of thesemiconductor fin36 in thewide section42 without also encroaching on the floating charge-neutral regions112,114, which are free of a significant concentration ofimpurity82. Theisolation region130 bridges the two portions96a,bof thesource86 formed along thesidewalls44,46. Theisolation region130 is therefore defined in thewide section42 ofsemiconductor fin36 as a junction-type isolation. Processing continues as described in connection withFIGS. 6A-C.
• With reference toFIGS. 9A-C in which like reference numerals refer to like features inFIGS. 6A-C and in accordance with an alternative embodiment, anisolation region140 is defined as a trench-type isolation in thewide section42 ofsemiconductor fin36. Theisolation region140 is formed by a standard lithography and etching process familiar to a person having ordinary skill in the art that defines an opening or via in the constituent semiconductor material inwide section42. The etching process stops on the buried insulatinglayer14 so that the gap extends from thetop surface13 to the buried insulatinglayer14. However, portions of the doped semiconductor material ofsource86 are preserved intact along eachsidewall44,46 when the via is defined. In contrast to isolation region100 (FIGS. 6A-C),isolation region140 does not extend across the entire width of thesemiconductor fin36. Instead, the perimeter of theisolation region140 is spaced inwardly from thesidewalls44,46. The via is filled by dielectric material originating from theblanket layer98 that is applied to define theisolation region140 between theadjacent semiconductor bodies42a,42b. Processing continues as described in connection withFIGS. 6A-C.
• With reference toFIG. 10 in which like reference numerals refer to like features inFIG. 6B and in accordance an alternative embodiment of the invention, the dielectric material of pad layers22,24 may be retained on thetop surface13 of thesemiconductor fin36 in the regions that define thesources86,87 and thedrains83,84. An electrical contact in the form of aplug104a, which is similar to plug104 (FIG. 9A), includesportions150,152 that extend downwardly along thesidewalls44,46 so as to have a greater degree of overlap with thesidewalls44,46 thanplug104. Theportions150,152 ofplug104aestablish electrical contact with thesilicide96 on thesidewalls44,46 of thesemiconductor fin36 so that theelectrical contact104ais electrically coupled with both portions86a,86bof thesource86. Similar electrical contacts (not shown) are fabricated that are used to establish an electrical connection withsource87 and thedrains83,84.
• References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor wafer or substrate, regardless of its actual three-dimensional spatial orientation. The term “vertical” refers to a direction perpendicular to the horizontal, as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, “beneath” and “under”, are defined with respect to the horizontal plane. It is understood that various other frames of reference may be employed for describing the invention without departing from the spirit and scope of the invention. The term “on” used in the context of two layers means at least some contact between the layers. The term “over” means two layers that are in close proximity, but possibly with one or more additional intervening layers such that contact is possible but not required. As used herein, neither “on” nor “over” implies any directionality.
• The fabrication of the semiconductor structure herein has been described by a specific order of fabrication stages and steps. However, it is understood that the order may differ from that described. For example, the order of two or more fabrication steps may be switched relative to the order shown. Moreover, two or more fabrication steps may be conducted either concurrently or with partial concurrence. In addition, various fabrication steps may be omitted and other fabrication steps may be added. It is understood that all such variations are within the scope of the invention. It is also understood that features of the invention are not necessarily shown to scale in the drawings.
• While the invention has been illustrated by a description of various embodiments and while these embodiments have been described in considerable detail, it is not the intention of the applicants to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. Thus, the invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative example shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicants' general inventive concept.

Claims (17)

1. A semiconductor device structure carried on a dielectric layer, the semiconductor device structure comprising:

a gate electrode; and

a semiconductor body having first and second sidewalls extending to the dielectric layer, the semiconductor body doped with a first impurity of a first conductivity type, the semiconductor body including a first section and a second section, the first section at least partially intersected by the gate electrode, the first section having a first width between the first and second sidewalls, and the second section having a second width between the first and second sidewalls,

wherein the first width of the first section is wider than the second width of the second section, and the first width and a concentration of the first impurity in the first section are selected such that the first section is partially depleted to define a floating charge-neutral region therein when biased by a bias potential applied by the gate electrode.

2. The semiconductor device structure ofclaim 1 wherein the second width and a concentration of the first impurity in the second section of the semiconductor body are selected such that the second section of the semiconductor body is fully depleted when biased by the bias potential.

3. The semiconductor device structure ofclaim 1 further comprising:

a source in the first section of the semiconductor body, the source doped with a second impurity having an opposite conductivity type to the first impurity.

4. The semiconductor device structure ofclaim 3 wherein the source includes a first portion proximate to the first sidewall and a second portion proximate to the second sidewall, and the floating charge-neutral region is at least partially disposed in the first section of the semiconductor body between the first and second portions of the source.

5. The semiconductor device structure ofclaim 4 wherein the semiconductor body includes a third section separated from the first section by the second section, the third section having a third width less than the second width, and further comprising:

a drain in the third section of the semiconductor body, the drain doped with the second impurity.

6. The semiconductor device structure ofclaim 4 further comprising:

an impurity-doped bridge extending across the semiconductor body to connect the first and second portions of the source, the bridge doped with a concentration of the second impurity.

7. The semiconductor device structure ofclaim 3 wherein the semiconductor body has a top surface, and further comprising:

a dielectric pad layer on the top surface of the semiconductor body; and

a conductive plug electrically connected to the source, the conductive plug extending toward the dielectric pad layer and overlapping at least a portion of the first and second sidewalls.

8. The semiconductor device structure ofclaim 1 wherein the second section is juxtaposed with the first section and tapers from the first width to the second width.

9. The semiconductor device structure ofclaim 1 wherein the gate electrode comprises:

a first gate adjacent to the first sidewall of the semiconductor body, the first gate configured to bias the first section to define the floating charge-neutral region; and

a second gate adjacent to the second sidewall of the semiconductor body and separated from the first gate by the semiconductor body, the second gate configured to operate as a wordline.

10. The semiconductor device structure ofclaim 1 further comprising:

an isolation region positioned in the first section of the semiconductor body, the isolation region electrically isolating the first section of the semiconductor body from an adjacent semiconductor body.

11. The semiconductor device structure ofclaim 10 wherein the isolation section further comprises:

a dielectric region defined in the semiconductor body.

12. The semiconductor device structure ofclaim 11 wherein the dielectric region extends completely across the semiconductor body from the first sidewall to the second sidewall.

13. A method of fabricating a semiconductor device structure using a semiconductor-on-insulator substrate having a semiconductor layer, a bulk semiconductor region underlying the semiconductor layer, and a dielectric layer between the semiconductor layer and the bulk semiconductor region, the method comprising, the method comprising:

patterning the semiconductor layer to define a semiconductor body with opposite sidewalls extending to the dielectric layer, the semiconductor body having a first section with a first width between the opposite sidewalls and a second section with second width between the opposite sidewalls that is narrower than the first width; and

introducing a first impurity into the first section of the semiconductor body with a first concentration selected in conjunction with the first width such that, when the first section is biased by a bias potential, the first section is partially depleted to define a floating charge-neutral region therein.

14. The method inclaim 13 further comprising:

introducing the first impurity into the second section of the semiconductor body with a second concentration selected in conjunction with the second width such that, when the second section is biased by the bias potential, the second section is fully depleted.

15. The method inclaim 13 further comprising:

introducing a second impurity of an opposite conductivity type to the first impurity into the first section of the semiconductor body with a concentration effective to define a source that includes a first portion proximate to one of the opposite sidewalls and a second portion proximate to the other of the opposite sidewalls so that the floating charge-neutral region is at least partially disposed between the first and second portions of the source.

16. The method inclaim 13 further comprising:

forming an isolation region in the first section of the semiconductor body that extends from a top surface of the semiconductor body to the dielectric layer and between the opposite sidewalls.

17. The method ofclaim 16 wherein forming the isolation region further comprises:

defining a dielectric-filled region in the semiconductor body or an impurity-doped bridge in the semiconductor body that is doped with a second impurity of opposite conductivity type to the first impurity.

Images