US20090026592A1 - Semiconductor dies with recesses, associated leadframes, and associated systems and methods - Google Patents

Abstract

Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application claims foreign priority benefits of Singapore Application No. 200705420-8 filed Jul. 24, 2007, which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
• The present disclosure is directed generally to semiconductor dies with recesses, associated leadframes, and associated systems and methods.
BACKGROUND
• Semiconductor processing and packaging techniques are continually evolving to meet industry demands for devices with improved performance and reduced size and cost. Electronic products require packaged semiconductor assemblies with a high density of devices in a relatively small space. For example, the space available for memory devices, processors, displays and other semiconductor devices is continually decreasing in cell phones, personal digital assistants, laptop computers and many other products. Accordingly, a need exists to increase the density of semiconductor devices and components within the confined footprint of a semiconductor assembly. One technique for increasing the density of semiconductor devices within a given footprint is to stack semiconductor dies. A challenge with this technique, however, is providing adequate electrical interconnects within and between the stacked dies.
• One approach to addressing the challenges associated with stacked semiconductor dies is to use a leadframe having a support paddle that supports the lowest die, and leadfingers that provide electrical connections between the stack of dies and devices external to the finished package. While this arrangement has proven to be suitable for many purposes, the continual pressure to reduce not only the footprint of the package but also the overall volume of the package has created the need for still smaller and more efficiently packaged dies.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a partially schematic, cross-sectional side elevation view of a portion of a package configured in accordance with an embodiment of the disclosure.
• FIG. 2 is a partially schematic, exploded plan view illustration of package components, including a semiconductor die and a leadframe having leadfingers and a support paddle configured in accordance with an embodiment of the disclosure.
• FIG. 3 is a partially schematic, exploded plan view illustration of a semiconductor die and a leadframe having a support paddle configured in accordance with an embodiment of the disclosure.
• FIG. 4 is a partially schematic, exploded plan view illustration of a semiconductor die and a leadframe having a support paddle configured in accordance with an embodiment of the disclosure.
• FIG. 5 is a flow diagram illustrating methods for packaging semiconductor dies in accordance with several embodiments of the disclosure.
• FIG. 6 is a partially schematic, block diagram illustrating a system in which packages may be incorporated in accordance with still further embodiments of the disclosure.
DETAILED DESCRIPTION
• Several embodiments of the present disclosure are described below with reference to packaged semiconductor devices and assemblies, and methods for forming packaged semiconductor devices and assemblies. Many details of certain embodiments are described below with reference to semiconductor dies. The term “semiconductor die” is used throughout to include a variety of articles of manufacture, including for example, individual integrated circuit dies and/or dies having other semiconductor features. Many specific details of certain embodiments are set forth inFIGS. 1-6 and the following text to provide a thorough understanding of these embodiments. Several other embodiments can have different configurations, components and/or processes than those described in this section. A person skilled in the relevant art, therefore, will appreciate that additional embodiments may be practiced without several details of the embodiments shown inFIGS. 1-6.
• FIG. 1 is a partially schematic, cross-sectional view of asystem100 that includes a package101 (a portion of which is shown) configured in accordance with a particular embodiment. Thepackage101 can include aleadframe130 having asupport paddle131 carrying one or more semiconductor dies110. For purposes of illustration, theleadframe130 is shown carrying four stacked semiconductor dies110, shown as first, second, third and fourth semiconductor dies110a,110b,110c, and110d, respectively. In other embodiments, theleadframe130 can carry more orfewer dies110, for example, asingle die110 or two stackeddies110. In any of these embodiments, the die(s)110 can include one ormore recesses114 that receive thesupport paddle131, as described in further detail below.
• In an embodiment shown inFIG. 1, each of thedies110 has a first (e.g., downwardly facing)die surface111, and a second (e.g., upwardly facing)second die surface112. The illustrated first diesurface111 includes tworecesses114, one along each of two opposing edges of thefirst die surface111, and one of which is visible inFIG. 1. Therecesses114 can locally reduce a thickness T of the die110. Suitable techniques for cutting therecesses114 in thedies110 are included in U.S. Pat. No. 7,218,001, assigned to the assignee of the present application and incorporated herein by reference. In the arrangement shown inFIG. 1, at least part of thesupport paddle131 is received in therecess114 of thefirst die110a. In a particular embodiment, therecess114 is deep enough so that a first paddle surface133 (e.g., an outwardly facing surface) is flush with or recessed from thefirst die surface111. Accordingly, the addition of thesupport paddle131 beneath thefirst die110adoes not add to the overall thickness T of thefirst die110aalone. Thesupport paddle131 can further include asecond paddle surface134 that faces into therecess114 and away from thefirst paddle surface133. Apaddle adhesive135 can adhesively bond thesupport paddle131 tosurfaces115 of therecess114.
• In a particular embodiment, the overall thickness of thefirst die110acan be about 120 microns, and therecess114 can have a depth of about 60 microns. The combined thickness of thesupport paddle131 and thepaddle adhesive135 can be about 60 microns or less, so that thefirst paddle surface133 is flush with or recessed from the adjacentfirst die surface111. In other embodiments, the foregoing features can have different dimensions, while thesupport paddle131 still does not add to the overall thickness T of thedie110aand thesupport paddle131 combined. In still further embodiments, thesupport paddle131 can be only partially received in therecess114, so that it protrudes, in part, from therecess114. In such instances, thesupport paddle131 does add to the overall thickness of thedie110aand thesupport paddle131 combined, but not as much as if therecess114 were not present.
• When thepackage101 includesmultiple dies110, the additional dies can be stacked on thefirst die110aand attached with corresponding layers of dieadhesive116. The layers of dieadhesive116 can be relatively thin to reduce the overall package thickness and/or the likelihood for thermal conductivity mismatches resulting from differing coefficients of thermal expansion. Each of thedies110 can include abond site113 located proximate to and accessible from thesecond die surface112. Thebond sites113 and therecesses114 of thestacked dies110 can be arranged so that therecesses114 of an upper die (e.g., thesecond die110b) lie directly overcorresponding bond sites113 of the next lower die (e.g., thefirst die110a) in the stack. Accordingly, therecesses114 of the upper dies can house, accommodate and/or receive electrical connections between theleadframe130 and thebond sites113 of the lower die.
• To support electrical connections to the semiconductor dies110, theleadframe130 includesleadfingers132 that extend inwardly toward thedies110.Individual leadfingers132 can be connected tocorresponding bond sites113 of thedies110 withwire bonds103. When thepackage101 includesmultiple dies110, anindividual leadfinger132 may be connected tocorresponding bond sites113 of each of thedies110. Therecesses114 can reduce or eliminate the likelihood for thewire bonds103 to contact thesemiconductor die110 in which therecesses114 are formed.
• Multiple leadfingers132 may be arranged side by side in a direction extending transverse to the plane ofFIG. 1, and may accordingly form a leadfinger plane L, an edge of which is visible inFIG. 1. The support paddle orpaddles131 may extend in a direction generally transverse to the plane ofFIG. 1 and may accordingly form a paddle plane P. In a particular embodiment, the leadfinger plane L is offset from the paddle plane. P in a direction generally aligned with the thickness dimension T of thedies110. This arrangement can reduce the length of thewire bond103 required to connect theleadfinger132 to the furthest die (e.g., thefourth die110d). In other embodiments, the leadfinger plane L and the paddle plane P can have arrangements other than that shown inFIG. 1. For example, when thepackage101 includes only thefirst die110a, the leadfinger plane L may be coplanar with the paddle plane P. In any of these arrangements, once the electrical connections between theleadframe130 and the die(s)110 are formed, the die(s)110, thewire bonds103, thesupport paddle131, and theleadfingers132 can be at least partially encapsulated with anencapsulant102. Portions of theleadfingers132 that project outwardly from theencapsulant102 can then be trimmed, shaped, and/or otherwise formed to provide connections to external components.
• FIG. 2 is a partially exploded, schematic plan view illustration of components of an embodiment of thepackage101, including theleadframe130 and thefirst die110ashown inFIG. 1. Theleadframe130 can be formed from a unitary thin sheet of conductive material (e.g., gold), using a stamping process or another suitable process. Theleadframe130 includes aframe member136, which temporarily carries the inwardly extendingleadfingers132 and thesupport paddle131. Thesupport paddle131 is positioned inwardly from theleadfingers132 and is supported relative to theframe member136 byremovable ties137. In this particular embodiment, thesupport paddle131 includes apaddle surface138 that is divided over afirst portion139aandsecond portion139b. Accordingly, thepaddle surface138 is discontinuous in this embodiment. When the first semiconductor die110ais inverted and positioned face down on top of the frame member136 (as indicated by arrow A), each of therecesses114 is aligned with and receives a corresponding one of the first andsecond portions139a,139b. The bond sites113 (FIG. 1) on thesecond die surface112 are then electrically connected to theleadfingers132 at correspondingleadfinger bond sites141 e.g., using standard wire bonds, or other suitable conductive couplers. If further dies are to be stacked on thefirst die110a, each one is stacked and connected to theleadfingers132 before the next die is stacked and electrically connected to theleadframe130. After all the dies have been stacked and electrically connected to theleadframe130, the assembly is placed in a mold and encapsulated, after which theframe member136, theties137 and (optionally) portions of theleadfingers132 are removed.
• In a particular embodiment of the arrangement shown inFIG. 2, theleadframe130 includes anopening140 between the first andsecond portions139a,139b. The first andsecond portions139a,139bcan be elongated so as to fit into the correspondingelongated recesses114 of the first semiconductor die110a. Because thefirst die110ais rectangular and therecesses114 are aligned with opposing edges of the first semiconductor die110a, the first andsecond portions139a,139bof thesupport paddle131 can also be aligned generally parallel to each other. In other embodiments, theleadframe130 can have other arrangements that also support one or more semiconductor dies110. Representative arrangements are described below with reference toFIGS. 3 and 4.
• Beginning withFIG. 3, aleadframe330 in accordance with another embodiment includes aframe member136 andleadfingers132 arranged generally similarly to the corresponding components described above with reference toFIG. 2. Theleadframe330 further includes asupport paddle331 having four spaced apart portions339 (shown as first, second, third andfourth portions339a,339b,339c, and339d, respectively) positioned around acentral opening340. Each of theportions339acan be connected to theframe member136 with acorresponding tie337. The first semiconductor die110acan include elongated recesses114 (shown in dashed lines) generally similar to those shown inFIG. 2 so as to accommodate and receive the portions339a-339dof thesupport paddle331. In another embodiment, the first semiconductor die110acan instead include four separate recesses314a-314d, each positioned at a corner of thefirst die110ato receive a corresponding one of the support paddle portions339a-339d. The support paddle portions339a-339dcan be arranged symmetrically, e.g., so that a diagonal line connecting the first andthird portions339a,339cbisects a diagonal line connecting the second andfourth portions339b,339d. In other embodiments, the paddle portions339 can have other symmetric or asymmetric arrangements.
• FIG. 4 illustrates aleadframe430 that carries a corresponding semiconductor die410 in accordance with another embodiment. Theleadframe430 can include aframe member436 that carries inwardly extendingleadfingers432 and aunitary support paddle431. Thesupport paddle431 can have acentral opening440, and can be temporarily supported relative to theframe member436 withties437. Accordingly, thesupport paddle431 can have a shape generally similar to a picture frame, and in a particular embodiment, can have four portions439a-439dthat are integrally connected to form a unitary structure. The corresponding semiconductor die410 includes acorresponding recess414 positioned around its periphery to mirror the arrangement of thesupport paddle431. Accordingly, when the semiconductor die410 is inverted and placed on theleadframe430, the generally frame-shapedsupport paddle431 is received in the generally framed-shapedrecess414 of the semiconductor die410, and the central portion of the semiconductor die410 is received in thecentral opening440 of theleadframe430.
• FIG. 5 is a flow diagram of aprocess500 for forming packaged semiconductor devices in accordance with several embodiments. For purposes of illustration, features of several embodiments are shown together inFIG. 5. It will be understood by one of ordinary skill in the relevant art that further particular embodiments may be practiced with fewer than all the steps identified inFIG. 5, and that in other embodiments, additional steps may be performed in addition to those identified inFIG. 5.
• Process portion501 includes positioning a semiconductor die and a leadframe proximate to each other. Inprocess portion502, a support paddle is received in a recess of the semiconductor die. For example, a support paddle or support paddle portion having any of the configurations described above with reference toFIGS. 1-4 be can be received in one or more corresponding recesses of a semiconductor die.
• Process portion503 includes positioning a support paddle (having a paddle surface with an opening extending through it) relative to the semiconductor die.Process portion503 can be performed in addition to or in lieu ofprocess portion502. For example, in the context of the arrangements describe above with reference toFIGS. 1-4, the opening in the support paddle can allow the support paddle to be positioned so that the paddle surface is received or partially received in one or more recesses of the die. However, in other embodiments, a paddle having an opening extending through it can support a semiconductor die without necessarily having the support surfaces received in a recess of the die.
• In any of the foregoing embodiments, the support paddle can be attached to the die (process portion504), and the die can be electrically connected to leadfingers (process portion505). Inprocess portion506, the die, the leadfingers, and/or the support paddle can be encapsulated to protect these components. Inprocess portion507, a frame member, which may temporarily support the leadfingers and the support paddle relative to the die, can be removed, typically after the encapsulation process has been completed.
• One feature of semiconductor packages configured and/or manufactured in accordance with at least some of the foregoing embodiments described above with reference toFIGS. 1-5 is that they include support paddles received in one or more recesses of a corresponding semiconductor die. This arrangement can reduce the overall thickness of the semiconductor package because the thickness of the support paddle is not cumulative to the thickness of the semiconductor die. Instead, the support paddle can be fully or partially recessed into the adjacent surface of the die. The presence of the recesses in the die can allow the overall thickness of the die to remain relatively high (e.g., above 100 microns) without adding to the overall thickness of the combined die/support paddle. Dies having a thickness in the foregoing range can have good refresh margins and/or read/write speeds, without compromising on the compact (e.g., thin) profile of the packaged dies. In further particular embodiments, the support paddles can form part of an overall leadframe that also includes leadfingers for electrical connections to the semiconductor die. Accordingly, the leadframe can provide both the low-profile support described above, and electrical connections with external devices.
• Another feature of at least some of the foregoing embodiments is that the support paddle can include multiple paddle surfaces separated by an opening. As a result, the amount of material required to form the support paddle can be reduced when compared to a conventional paddle that has a solid geometry generally mirroring the footprint of the die that it supports. Reducing the amount of material for the support paddle can reduce the cost of the paddle and therefore the cost of the completed package. Despite the reduction in the size of thesupport paddle131, the combination of thesupport paddle131, theties137 and theleadframe130 provide adequate support to the semiconductor die or dies they carry during the wire bond and encapsulation steps
• Any of the semiconductor packages described above with reference toFIGS. 1-5 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is asystem600 shown schematically inFIG. 6. Thesystem600 can include aprocessor602, a memory604 (e.g., SRAM, DRAM, flash memory and/or other memory device), input/output devices606 and/or other subsystems orcomponents608. Semiconductor packages having any one or a combination of the features described above with reference toFIGS. 1-5 may be included in any of the components shown inFIG. 6. The resultingsystem600 can perform any of a wide variety of computing, processing, storage, sensing, imaging and/or other functions. Accordingly, therepresentative system600 includes, without limitation, computers and/or other data processors, for example, desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), multi-processor systems, processor-based or programmable consumer electronics, network computers and mini computers. Otherrepresentative systems600 may be housed in a single unit or distributed over multiple interconnected units (e.g., through a communication network). The components of thesystem600 can accordingly include local and/or remote memory storage devices, and any of a wide variety of computer readable media.
• From the foregoing, it will be appreciated that specific embodiments have been described herein for purpose of illustration, but that the foregoing systems and methods may have other embodiments as well. For example, while the leadfingers and support paddles were described above in the context of a generally uniform and continuous leadframe, and accordingly have similar or identical material properties, in other embodiments, the leadfingers and the paddle supports can have different compositions, and/or non-unitary arrangements. The support paddles can have shapes and/or arrangements other than those specifically described above, for example, opposing “C” shaped support portions, more than four support portions, and/or others. The support paddle can be secured to the die with arrangements other than those shown in the Figures, e.g., a thin film that extends over both the support paddle and the adjacent (flush or semi-flush) die surface.
• Certain features described in the context of particular embodiments may be combined or eliminated in other embodiments. For example, several of the embodiments described above were described in the context of paddle supports received in recesses of corresponding semiconductor dies, but in other embodiments, the paddle supports can include multiple spaced apart portions, or openings between paddle support portions, without necessarily being received in recesses of corresponding semiconductor dies. In another example, the semiconductor die shown inFIG. 4 can be used with the support paddles shown inFIGS. 1-3. Further, while certain advantages may be associated with certain embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages. Accordingly, the disclosure can include other embodiments not shown or described above.

Claims (38)

1. A semiconductor system, comprising:

a semiconductor die having a first surface and a second surface facing opposite from the first surface, the first surface having a die recess; and

a support paddle carrying the semiconductor die, the support paddle being at least partially received in the die recess.

2. The system ofclaim 1 wherein:

the semiconductor die is a first semiconductor die, and the die recess is one of two elongated die recesses extending along opposing edges of the first surface;

the support paddle includes two spaced apart paddle portions, one received in each of the two die recesses, with each paddle portion being flush with or recessed from the first surface of the semiconductor die external to the die recesses;

the first semiconductor die has bond sites accessible from the second surface; and

the system further comprises:

a second semiconductor die stacked relative to the first semiconductor die, the second semiconductor die having a first surface facing toward the first semiconductor die, a second surface facing away from the first surface, and two elongated die recesses extending along opposing edges of the first surface of the second semiconductor die; and

wire bonds received in the recesses of the second semiconductor die and connected to the bond sites of the first semiconductor die.

3. The system ofclaim 1 wherein the support paddle has a first surface generally flush with or recessed from the first surface of the semiconductor die external to the recess, and wherein the support paddle has a second surface facing opposite the first surface of the support paddle and toward the semiconductor die.

4. The system ofclaim 1 wherein the semiconductor die includes multiple recesses, and wherein the support paddle includes multiple portions received in individual recesses.

5. The system ofclaim 4 wherein the semiconductor die includes a first elongated recess positioned along a first edge of the semiconductor die and a second elongated recess positioned along a second recess of the semiconductor die.

6. The system ofclaim 5 wherein the support paddle includes a first elongated portion received in the first recess and a second elongated portion received in the second recess.

7. The system ofclaim 5 wherein the support paddle includes first and second spaced apart portions received in the first recess, and third and fourth spaced-apart portions received in the second recess.

8. The system ofclaim 1 wherein the semiconductor die includes a contiguous recess adjacent a periphery of the semiconductor die, and wherein the support paddle includes a contiguous, generally frame-shaped support surface having a central opening and being received in the contiguous recess of the semiconductor die.

9. The system ofclaim 1, further comprising an encapsulant disposed around at least a portion of the semiconductor die and at least a portion of the support paddle.

10. The system ofclaim 1 wherein the semiconductor die includes multiple die bond sites, and wherein the system further comprises multiple leadfingers having leadfinger bond sites, with individual leadfinger bond sites connected to corresponding die bond sites via wire bonds, wherein the leadfingers and the support paddle have a generally identical composition.

11. The system ofclaim 1 wherein the semiconductor die is a first semiconductor die having first semiconductor die bond sites, wherein the die recess is a first die recess, and wherein the system further comprises:

a second semiconductor die stacked relative to the first semiconductor die, the second semiconductor die having a first surface and a second surface facing opposite from the first surface, the first surface of the second semiconductor die having a second die recess; and

a plurality of leadfingers having leadfinger bond sites, with individual leadfinger bond sites connected to corresponding die bond sites of the first semiconductor die via wirebonds that are received in the second die recesses of the second semiconductor die.

12. The system ofclaim 1, further comprising a computing device having at least one of a processor, a memory and an input/output device, and wherein the semiconductor die and the support paddle are included as a component of at least one of the processor, the memory, and the input/output device.

13. A semiconductor system, comprising:

a leadframe that includes:

a frame member;

a plurality of leadfingers connected to and extending inwardly from the frame member; and

a support paddle positioned inwardly from the leadfingers, the support paddle having:

a first paddle portion connected to and positioned inwardly from the frame member, the first paddle portion having a first support surface positioned to carry a semiconductor die; and

a second paddle portion connected to and positioned inwardly from the frame member, the second paddle portion being spaced apart from the first paddle portion and having a second paddle support surface spaced apart from and discontinuous with the first paddle support surface and positioned to carry the semiconductor die.

14. The semiconductor system ofclaim 13, further comprising:

a third paddle portion connected to and positioned inwardly from the frame member, the third paddle portion being spaced apart from the first and second paddle portions and having a third paddle support surface spaced apart from the first and second paddle support surfaces and positioned to carry the semiconductor die; and

a fourth paddle portion connected to and positioned inwardly from the frame member, the fourth paddle portion being spaced apart from the first, second and third paddle portions and having a fourth paddle support surface spaced apart from the first, second and third paddle support surfaces and positioned to carry the semiconductor die.

15. The system ofclaim 14 wherein the first, second, third and fourth paddle support surfaces are generally co-planar.

16. The system ofclaim 14 wherein a diagonal line between the first and third paddle support surfaces bisects a diagonal line between the second and fourth paddle support surfaces.

17. The system ofclaim 13 wherein the first and second paddle portions are elongated along generally parallel axes.

18. The system ofclaim 13 wherein the first and second paddle portions are elongated along generally parallel axes, spaced apart from each other by an opening.

19. A semiconductor leadframe, comprising:

a frame member;

a plurality of leadfingers connected to and extending inwardly from the frame member; and

a support paddle positioned inwardly from the leadfingers, the support paddle having a paddle surface positioned to carry a semiconductor die, the support paddle having an opening extending from the paddle surface through the support paddle.

20. The leadframe ofclaim 19 wherein the paddle surface includes a single, continuous surface that encloses the opening.

21. The leadframe ofclaim 19 wherein the paddle surface includes multiple spaced apart paddle surface portions positioned outwardly from the opening.

22. The leadframe ofclaim 21 wherein the wherein the paddle surface includes first and second spaced apart paddle surface portions positioned on opposite sides of the opening.

23. The leadframe ofclaim 21 wherein the paddle surface includes first, second, third and fourth spaced apart paddle surface portions positioned around and outwardly from the opening.

24. A semiconductor system, comprising:

a semiconductor die having multiple bond sites;

a support paddle having a paddle surface carrying the semiconductor die, the support paddle having an opening extending from the paddle surface through the support paddle;

a plurality of leadfingers positioned outwardly from the support paddle; and

conductive connectors coupled between the leadfingers and the bond sites.

25. The system ofclaim 24 wherein the paddle surface includes a first portion on one side of the opening carrying the semiconductor die toward a first edge of the semiconductor die, and a second portion on an opposite side of the opening carrying the semiconductor die toward a second edge of the semiconductor die opposite the first edge of the semiconductor die.

26. The system ofclaim 25 wherein the first and second portions of the paddle surface are spaced apart from each other and elongated along generally parallel axes.

27. The system ofclaim 26 wherein the paddle surface includes first, second, third and fourth spaced apart portions positioned around and outwardly from the opening, with each of the portions carrying the semiconductor die toward one of four corners of the semiconductor die.

28. The system ofclaim 24 wherein the paddle surface has a generally frame-type shape around the opening.

29. The system ofclaim 24, further comprising an encapsulant disposed at least partially around the semiconductor die, the support paddle, the leadfingers and the conductive connectors.

30. A method for manufacturing a semiconductor system, comprising:

receiving at least part of a support paddle in a recess of a semiconductor die, the semiconductor die having a first surface with the recess and a second surface facing opposite from the first surface; and

attaching the support paddle to the semiconductor die with the support paddle in the recess.

31. The method ofclaim 30 wherein the support paddle is a portion of a leadframe having a frame portion and a plurality of leadfingers extending from the frame portion, and wherein the method further comprises:

positioning the leadfingers proximate to the semiconductor die as the support paddle is received in the recess;

electrically connecting the leadfingers with bond sites of the semiconductor die using wirebonds;

disposing an encapsulant around the semiconductor die and the leadframe; and

removing the frame portion of the leadframe.

32. The method ofclaim 30 wherein receiving at least part of the support paddle in the recess of the semiconductor die includes receiving the support paddle with an outwardly facing surface of the support paddle flush with or recessed from the first surface of the semiconductor die adjacent to the recess.

33. The method ofclaim 30 wherein the recess is a first recess and wherein receiving at least part of the support paddle includes receiving a first portion of the support paddle in the first recess and wherein the method further comprises receiving a second portion of the support paddle in a second recess spaced apart from the first recess.

34. The method ofclaim 30 wherein the recess extends around a periphery of the semiconductor die, and wherein the support paddle has a support surface with a generally frame-type shape disposed around a central opening, and wherein the method further comprises positioning a central portion of the semiconductor die in the central opening of the support paddle.

35. The method ofclaim 30 wherein the recess includes at least one recess at four spaced apart corners of the semiconductor die, and wherein receiving at least part of the support paddle in the recess includes receiving four spaced apart paddle surfaces of support paddle in individual portions of the at least one recess at the four spaced apart corners of the semiconductor die.

36. A method for manufacturing a semiconductor system, comprising:

positioning a semiconductor die proximate to a leadframe, the leadframe having a frame member, a plurality of leadfingers connected to and extending inwardly from the frame member, and a support paddle positioned inwardly from the leadfingers, the support paddle having a paddle surface and an opening extending from the paddle surface through the support paddle;

attaching the support paddle to the semiconductor die with the opening facing directly toward the semiconductor die;

electrically connecting the semiconductor die to the leadfingers; and

separating the frame member from the leadfingers and the support paddle.

37. The method ofclaim 36 wherein the semiconductor die includes recesses facing toward the support paddle, and where the method further comprises positioning the support paddle in the recesses of the semiconductor die, and wherein attaching the support paddle includes attaching the support paddle to surfaces of the semiconductor die in the recesses.

38. The method ofclaim 36 wherein attaching the support paddle to the semiconductor die includes attaching multiple spaced apart paddle surfaces of the support paddle to corresponding portions of the semiconductor die.

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