US20090013207A1 - Predicting microprocessor lifetime reliability using architecture-level structure-aware techniques - Google Patents

Abstract

A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application is a continuation of U.S. patent application Ser. No. 11/735,533, filed Apr. 16, 2007, the disclosure of which is incorporated by reference herein in its entirety.
BACKGROUND
• The present invention relates generally to lifetime reliability analysis of semiconductor devices and, more particularly, to a method and system of predicting semiconductor device lifetime reliability using architecture-level structure-aware techniques.
• Lifetime reliability has become one of the major concerns in microprocessor architectures implemented with deep submicron technologies. In particular, extreme scaling resulting in atomic-range dimensions, inter and intra-device variability, and escalating power densities have all contributed to this concern. At the device and circuit levels, many reliability models have been proposed and empirically validated by academia and industry. As such, the basic mechanisms of failures at a low level have been fairly well understood, and thus the models at that level have gained widespread acceptance. For example, Black's equation of electromigration is a well-accepted model of failures applicable to on-chip wires.
• In recent work (e.g., U.S. Patent Application Publication Nos. 20050257078 and 20060080062, assigned to the assignee of the present application), lifetime reliability models for use with single-core architecture-level, cycle-accurate simulators have been disclosed. These disclosures focus on modeling certain major failure mechanisms, including electromigration (EM), negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB). The models discussed therein rely on several key assumptions that make it difficult to extend the models directly to cover the entire chip having many different (heterogeneous) components.
• For example, the baseline (target) total failure rate measured in Failures in Time (FITs) is assumed to be evenly distributed across all of the modeled failure mechanisms. FITs are the standard method of reporting constant failure rates for semiconductor components, which is the number of failures seen in 10⁹hours. The mean time to failure (MTTF) of a component, another lifetime reliability metric, is inversely related to this constant failure rate; i.e., MTTF=10⁹/FITs. However, this is somewhat of an arbitrary axiom since some failure mechanisms can be more severe than others, and since technology scaling affects the failure mechanisms in different ways and degrees.
• In addition, lifetime reliability models proposed to this point assume a uniform device density over the chip and an identical vulnerability of devices to failure mechanisms. As a result, the failure rates estimated by such models tend to be proportional to chip area, regardless of the exact component mix within that area. However, an examination of the floorplan or photomicrograph of any modern microprocessor chip reflects heterogeneity across the die area, and thus consequent limitations of such an assumption.
• Accordingly, for accurate lifetime reliability estimation, basic axioms such as those above adopted by prior architecture-level reliability models need to be improved based on a detailed understanding of the implementation of modern microprocessor architecture components and the characteristics of failure mechanisms.
SUMMARY
• In an exemplary embodiment, a computer program product includes a computer-readable medium having computer-executable program code stored thereon that, when executed, causes a computer to implement a method for predicting the lifetime reliability of an integrated circuit device with respect to one or more defined failure mechanisms. The method includes breaking down the integrated circuit device into microarchitecture structures; further breaking down each structure into one or more of elements and devices, with a device comprising a sub-component of an element; determining, for each vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into one of a fatal failure and a non-fatal failure, wherein a fatal failure of a given device is one in which the failure causes the element employing the given device to fail; determining, for those devices whose failures are classified as fatal, one or more of an effective stress degree and an effective stress time based on one or more architecture-level events and states; determining one or more of a failure rate and a probability of fatal failure for the devices, using the one or more of the associated effective stress degree and effective stress time; and aggregating the one or more of the failure rate of the devices and the probability of fatal failures of the devices, across the structures for the one or more defined failure mechanisms.
BRIEF DESCRIPTION OF THE DRAWINGS
• Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
• FIG. 1 is a flow diagram illustrating a structure-aware method of predicting the lifetime reliability of an integrated circuit device with respect to one or more defined failure mechanisms, in accordance with an embodiment of the invention;
• FIG. 2 is a flow diagram illustrating a more detailed subroutine to estimate the FIT rates of structures due to electromigration, in accordance with a further embodiment of the invention;
• FIG. 3 is a flow diagram illustrating a more detailed subroutine to estimate the FIT rates of structures due to NBTI, in accordance with a further embodiment of the invention;
• FIG. 4 is a flow diagram illustrating a more detailed subroutine to estimate the FIT rates of structures due to TDDB, in accordance with a further embodiment of the invention;
• FIG. 5 is a flow diagram illustrating a more detailed subroutine to aggregate the estimated FIT rates of multiple structures due to various failure mechanisms, in accordance with a further embodiment of the invention;
• FIG. 6 is an exemplary reference circuit for use in predicting the lifetime reliability of an integrated circuit device with respect to electromigration in a technology/environment independent manner;
• FIG. 7 is an exemplary reference circuit for use in predicting the lifetime reliability of an integrated circuit device with respect to NBTI in a technology/environment independent manner;
• FIG. 8 is an exemplary reference circuit for use in predicting the lifetime reliability of an integrated circuit device with respect to TDDB in a technology/environment independent manner; and
• FIG. 9 is a schematic diagram of an exemplary computing environment in which the lifetime reliability prediction method embodiments may be implemented.
DETAILED DESCRIPTION
• Disclosed herein is a robust structure-aware lifetime reliability modeling method and system that is implemented at the architecture-level, wherein the microarchitecture is first broken down into structures that in turn are further broken down into subcircuits including transistors, wires and vias (collectively referred to herein as “devices”). Each device is categorized as vulnerable or non-vulnerable with respect to the various failure mechanisms, and thus is “weeded out” from lifetime reliability analysis accordingly. Further, for those devices that are categorized as vulnerable, the embodiments further determine whether a failure of such a device is “fatal” or “non-fatal,” wherein a fatal failure is one in which the failure causes a circuit employing the given device to fail.
• Once a vulnerable, “fatal failure” device for a given failure mechanism (e.g., EM, NBTI, TDDB) is identified, the effective stress condition of the device is evaluated, instead of simply assuming a constant stress condition. For example, depending upon architecture-level events or states, the effective stress degree and/or time of one device may be greater or less than a similar device for a given failure mechanism. Such events or states may include, for example, the amount of current passed in a via, the frequency of access of a transistor, or the state of data in an array. Then, using relative stress condition information for those identified vulnerable/fatal devices, a more robust FIT for the device can be expressed.
• In addition, the inventive embodiments also separate architecture-level factors from technology and environment dependent parameters so as to allow a user to abstract the analysis of processor lifetime reliability from technology level effects. In particular, the disclosed methodology introduces a technology-independent unit of reliability, referred to herein as the FIT of a reference circuit or “FORC” for each failure type. FORC describes the failure rate, in FITs, of a specially defined reference circuit that is easy to model and understand while, at the same time, effective at representing the basic mechanism of a certain type of failures. As such, the failure rate of a given structure or unit on a chip, in the context of a given failure mechanism (e.g., electromigration), may be computed in relative FORC units, instead of in absolute FITs that are technology and environment dependent.
• Referring now toFIG. 1, there is shown a flow diagram illustrating a structure-aware method100 of predicting the lifetime reliability of an integrated circuit device with respect to one or more defined failure mechanisms. For a given microarchitecture analyzed in block102 (e.g., a microprocessor), the microarchitecture is broken down into basic structures (e.g., arrays, register files, latches, multiplexers, logic gates and repeated wires), as reflected inblock104. These structures are evaluated in terms of lifetime reliability or FIT rates due to various failure mechanisms as discussed above.Decision block106 is an exit condition for determining whether all of the failure mechanisms of interest (e.g., EM, NBTI, TDDB) have been processed, and if so, the individually determined FITs are aggregated as reflected inblock108. Further detail concerning the aggregations is provided hereinafter.
• Assuming one or more failure mechanisms are still under analysis,decision block110 is an exit condition for determining whether each of the structures identified inblock104 have been processed for that particular mechanism. If so, themethod100 loops back todecision block106 to see whether all failure mechanisms have then been processed. Assuming that all structures for a given failure mechanism have not been processed, another decision block (block112) determines, upon further breakdown of each structure into individual elements (e.g., bitlines, wordlines, cells, etc.), whether each element of the structure has been processed. If so, themethod100 loops back todecision block110 to again see whether all structures have been processed. If not, each of the elements is then further broken down into individual devices (e.g., transistors, vias, wires, etc.).Decision block114 represents an exit condition to determine whether each identified device has been processed, and either returns todecision block112 or proceeds todecision block116.
• Decision block116 represents a first criteria by which devices are “weeded out” from FIT evaluation. Specifically, it is determined whether the device is vulnerable to the particular failure mechanism under analysis. The determination of vulnerability depends on both the device under consideration and the failure mechanism itself. While specific analytic examples of device vulnerability are presented hereinafter, one example of a vulnerable device in the context of electromigration would be a via structure having unidirectional current passing therethrough. Conversely, a device such as a PFET is not vulnerable to electromigration, but is susceptible to (for example) TDDB or NBTI, depending on how the transistor is configured in its associated element or sub-circuit.
• In any event, if a given device is not considered vulnerable to the failure mechanism under examination, themethod100 loops back todecision block114. However, if the device is considered vulnerable to the failure mechanism under examination, a further inquiry is made atdecision block118. Specifically, it is determined whether a failure of such a vulnerable device constitutes a “fatal” failure. In so doing, only fatal failures are taken into account for the lifetime reliability of the microarchitecture, thereby providing a more accurate FIT rate estimation. As indicated above, a fatal failure is one in which the failure causes a circuit employing the given device to fail. If the failure of a vulnerable device is not a fatal failure, that device is also excluded from FIT analysis and the method loops todecision block114. On the other hand, if the failure of a vulnerable device is in fact a fatal failure, then themethod100 proceeds to block120 where the stress condition of the device is evaluated with respect to the failure mechanism in order to take into account only effective stress time or degree for accurate lifetime prediction. The effective stress time or degree is then expressed by architecture-level events or states. Using this condition, the FIT of the device is evaluated based on reliability models of the failure mechanism inblock122. Additional detail concerning specific FIT evaluations is presented hereinafter.
• Again, once all of the devices of the element are evaluated (decision block114), the next element is processed (decision block112). Once all the elements of the structure are processed, the same process is repeated for the next structure (i.e., returning to decision block110). When all the structures are processed for all the failure mechanisms (decision block106), the evaluated FIT rates of the structures due to the failure mechanisms are aggregated inblock108. As discussed below, exemplary approaches to aggregate the failure rates of structures include summation and weighted summation.
• Referring now toFIG. 2, there is shown a flow diagram illustrating a moredetailed subroutine200 to estimate the FIT rates of structures due to electromigration, in accordance with a further embodiment of the invention.Decision block202 is analogous to decision block110 ofFIG. 1, in that once all structures are processed for electromigration failure analysis, the EM subroutine is completed. Inblock204, it is determined whether the particular structure is an array or register file. For a relatively organized structure such as an array or register file, each port therein is further analyzed with respect to electromigration. Thus,decision block206 provides a return loop to the next structure once all ports in a structure are processed. If not, the subroutine proceeds to decision block208 for a further breakdown, in terms of processing bitlines.
• Array and register file structures include several elements such as bitlines, wordlines, and memory cells. However, among these elements, bitlines include vias having unidirectional current flow between the bitlines and pass transistors. These are the particular elements within such structures having vulnerability with respect to electromigration. Moreover, failures of bitline vias in arrays and register files represent fatal failures. Thus decision block determines whether each via for a bitline has been processed. If not, the subroutine proceeds to block212.
• Each via in every bitline of every port is evaluated for the FIT rate inblock212, based on current density through the via. For local read bitlines of register files, the current density of the via is the product of the number of reads of “1” of the cell through the bitline and the amount of local bitline capacitance discharged through the via for one read. For local bitlines for arrays, the current density of the via is the sum of current due to reads of “0” and current due to writes of “1.” For their complementary bitlines, the current density is the sum of current due to reads of “1” and current due to writes of “0.” For global bitlines of both structures, the current density of the via is the product of the total number of accesses of local bitlines associated to the global bitline and the amount of global bitline capacitance discharged through the via for one access. Once all the vias of the bitline are evaluated (block210), the next bitline is processed (block208). Once all the bitlines of the port are processed, the same steps are repeated for the next port (block206). Once all the ports of the array or register file structure are processed, the next structure is processed (block202).
• If the current structure in the electromigration subroutine is neither an array nor a register file, thesubroutine200 proceeds to decision block214, which is a return condition once all elements of the structure are processed. In particular, each via of every element of the structure is evaluated (decision block216) to see whether or not the via is subject to domination by unidirectional current flow. If the via is not dominated by unidirectional current (e.g., integration of the charge flowing through the cross section of the wire over the clock cycle) as reflected indecision block218, then thesubroutine200 loops back to decision block216 to check the next via. On the other hand, if the via is dominated by unidirectional current, the FIT of the via is evaluated inblock220 by calculating the amount of the current through the via. More specifically, the number of accesses of metal line employing the via is multiplied by the amount of metal line capacitance discharged or charged through the via due to each access.
• When all the structures of the microarchitecture are processed (block202), the FIT rate estimation with respect to the electromigration failure mechanism is completed. In terms ofFIG. 1, this represents a return todecision block106.
• Referring now toFIG. 3, there is shown a flow diagram illustrating a moredetailed subroutine300 to estimate the FIT rates of structures due to NBTI, in accordance with a further embodiment of the invention.Decision block302 is analogous to decision block110 ofFIG. 1, in that once all structures are processed for NBTI failure analysis, the NBTI subroutine is completed. Indecision block304, it is similarly determined whether each element of the structure has been processed. At the element level, only PFET devices are examined for NBTI failure analysis because they are the only devices vulnerable to NBTI, as reflected indecision block306. More specifically, for NBTI analysis purposes, PFET devices are considered under stress only when their gate voltage is low (e.g., ground) and their source voltage is high (e.g., V_dd).
• Accordingly, as shown indecision block308, each PFET device of every element of every structure is evaluated to see whether or not it is along a critical path such that the failure of the device (which results in an increased delay of zero-to-one and/or one-to-zero transitions thereof) is fatal. If not, the PFET is not further considered in the analysis (for accurate FIT rate estimation purposes) and thesubroutine300 loops back todecision block306. However, if so, then the stress time of the PFET device is evaluated inblock310, in terms of the relative duration the gate voltage is low and the source voltage is high. Then, inblock312, the FIT rate of the device is evaluated, based on its effective stress time or duty cycle. Once all the PFET devices of the element are evaluated (block306), the next element is processed (block304). Once all the elements of the structure are processed, the same steps are repeated for the next element (block302). When all the structures of the microarchitecture are processed (block110 ofFIG. 1), the FIT rate estimation due to the NBTI failure mechanism is complete (i.e., returning to block106 inFIG. 1).
• Referring now toFIG. 4, there is shown a flow diagram illustrating a moredetailed subroutine400 to estimate the FIT rates of structures due to TDDB, in accordance with a further embodiment of the invention.Decision block402 is analogous to decision block110 ofFIG. 1, in that once all structures are processed for TDDB failure analysis, the TDDB subroutine is completed. Indecision block404, it is similarly determined whether each element of the structure has been processed. Then, indecision block406, it is determined whether each device of the elements has been processed.
• At the device level, only FET devices are examined for TDDB failure analysis, as FETs include thin gate dielectrics. In other words, only FET devices are vulnerable to TDDB. As shown indecision block408, the polarity of the FET is determined (PFET versus NFET). If the device is a PFET, its stress time is evaluated by determining the relative duration the gate voltage is low and the source and drain voltage is high, as shown inblock410. Conversely, if the device is an NFET, its stress time is evaluated by determining the relative duration the gate voltage is high and the source and drain voltage is low, as shown inblock412. In either instance, thesubroutine400 proceeds to decision block414 to determine whether each possible breakdown of the device (e.g., gate to source, gate to drain) has been processed. The processing (i.e., fatal failure determination) is implemented indecision block416. That is,decision block416 evaluates whether the breakdown of the device leads to the failure of circuits employing the device. In the case of TDDB, a breakdown is fatal or causes circuit failure if gate leakage current (I_gl) due to the oxide breakdown exceeds that which can be tolerated by the logic driving the devices.
• Thus, if the device is vulnerable to TDDB and the failure of the device is fatal, the FIT rate of the device is evaluated inblock418, based on its effective stress time. Otherwise, the FIT of the breakdown need not be taken into account for accurate FIT rate estimation. Once all the breakdowns of the device are evaluated (block414), the next device is processed (block406). Once all the devices of the element are processed, the same steps are repeated for the next element (block404). When all the structures of the microarchitecture are processed (block402), the FIT rate estimation due to the TDDB failure mechanism is completed (i.e., the subroutine exits to block106 inFIG. 1).
• Referring now toFIG. 5, there is shown flow diagram illustrating a moredetailed subroutine500 to aggregate the estimated FIT rates of multiple structures due to various failure mechanisms, in accordance with a further embodiment of the invention. As indicated above,subroutine500 is initiated once all of the failure mechanisms have been processed. Thus,subroutine500 represents a more detailed exemplary implementation ofblock108 ofFIG. 1.
• In the above describedsubroutines200,300,400, for EM, NBTI and TDDB, respectively, the FIT or failure rates are computed in terms of the technology/environment-independent FORC metric defined for each of the failure mechanisms. The estimated FIT rates of multiple structures and failure mechanisms can be combined in absolute FIT values or, alternatively, relative failure rate to FORC. If, atdecision block502, relative failure rates to FORC are not desired (i.e., absolute FITs are desired), thesubroutine500 proceeds to block504, where power and temperature maps are utilized along with technology and implementation parameters. Based on calculated temperature, FIT rates are computed by calculating the value of FORC for every component (or sub-component) and multiplying the technology/environment-independent values of the failure rates for each of the components by the corresponding FORC values.
• On the other hand, if relative FIT rates to weighted FORC are desired (as reflected in decision block506), FIT rates are computed inblock508 by calculating the normalized value of FORC for every component (or sub-component) and multiplying the technology/environment-independent values of the failure rates for each of the components by the corresponding normalized FORC values. Then, regardless of whether absolute FIT values, FORC values or weighted FORC values are desired, thesubroutine500 proceeds to block510, where the adjusted FIT rates are summed up to produce the total FIT rate of the evaluated microarchitecture inblock512.
• Referring generally now toFIGS. 6 through 8, exemplary reference circuits for the above described failure mechanisms are illustrated, in conjunction with determining FORC expressions for each mechanism.
• Electromigration is a well-known and well-studied failure phenomenon that can occur on conductor lines. The portions of conductor lines most vulnerable to EM are vias interconnecting different metal layers that experience unidirectional current flow.FIG. 6 illustrates an example reference circuit vulnerable to EM. The outputs of the PFET and NFET devices are connected through a segment of M2 metal, as shown in the layout portion (b) ofFIG. 6. As a result, v_upand v_downvias abut the M1 metal lines to M2, connecting the outputs of the PFET and the NFET devices. When the clock transits from one to zero, the PFET device conducts, and current flows through v_upupward from M1 to M2 in order to charge the wire capacitance of the M2 line, given by C_ref. There is little current through v_downbecause the NFET device is non-conducting. Conversely, on the zero-to-one transition of the clock, the NFET device conducts, and current flows through v_downdownward from M2 to M1 in order to discharge C_ref, while little current flows through v_up. As a result, v_upand v_downare subject to an average unidirectional current of (C_ref·V_dd)/t, where t is the clock period. This causes the vias to be vulnerable to EM effects. Based on Black's equation, the FIT of the reference circuit (vias in this case) for EM failures is described by the following:
• ${\mathrm{FORC}}_{\mathrm{EM}}=\frac{{10}^9}{A_{\mathrm{EM}}}·{\left(\frac{C_{\mathrm{ref}}·V_{\mathrm{dd}}}{t}\right)}^n·{}^{-\frac{\mathrm{Ea\_EM}}{\mathrm{kT}}},$
• where A_EMand n are empirical constants, E_a—EMis the activation energy for EM, k is Boltzmann's constant, and T is absolute temperature in degrees Kelvin. Using this notion of FORC, failure rates of microarchitectural components due to EM can be expressed in relative terms of FORC_EM, in order to isolate the architect from low-level peculiarities associated with technological and environmental parameters such as A_EM, V_dd, t, E_a—EM, and T.
• NBTI occurs when the input to a gate is low while the output is high, resulting in an accumulation of positive charges at the interface between gate oxide and silicon. This accumulation causes the threshold voltage, V_T, of the PFET device to increase over time, which results in a slowdown in zero-to-one or one-to-zero transitions. Eventually, this can lead to circuit failure due to timing violations if the device is along a critical path. To capture this failure mechanism,FIG. 7 illustrates a reference circuit for NBTI that includes PFET devices under stress and limits allowable gate delay increase before timing violation occurs.
• As shown inFIG. 7, the reference circuit includes of a series of N_invinverters disposed between two latches. The input of one latch should propagate through the inverter chain and be latched into the other within one clock period. Because the value of the signal changes between V_ddand GND in passing through each inverter, the PFET device in every other inverter (shaded) is stressed and the V_Tof the device increases over time. This eventually can lead to a violation in the latch setup time and, ultimately, the capturing of a wrong value in the latch. In the following expression, it is assumed that microprocessors are built with a 1% timing margin. This delay margin can be converted to a maximum allowable V_Tincrease by using the alpha power law model:
• $\Delta V_{\mathrm{T\_ref}}=0.01·N_{\mathrm{inv}}·\frac{\left(V_{\mathrm{dd}}-V_T\right)}{\alpha }.$
• That is, a V_Tshift greater than ΔV_T—refcan cause the failure of the reference circuit. This enables the derivation of the FITs of the reference circuit by applying one of a number of NBTI V_Tshift equations proposed thus far as follows:
• ${\mathrm{FORC}}_{\mathrm{NBTI}}={10}^9·{\left(\frac{K}{\Delta V_{\mathrm{T\_ref}}}\right)}^{\frac{1}{n}},\mathrm{where}K=A_{\mathrm{NBTI}}·t_{\mathrm{ox}}·\sqrt{C_{\mathrm{ox}}·\left(V_{\mathrm{gs}}-V_T\right)}·{}^{\frac{E_{\mathrm{ox}}}{E_0}}·{}^{-\frac{\mathrm{Ea\_NBTI}}{\mathrm{kT}}}.$
• Here, A_NBTI, n, and E₀are empirical constants and t_ox, C_ox, E_ox, E_a—NBTI, and V_Tare oxide thickness, oxide capacitance, electric field, the activation energy for NBTI, and the original threshold voltage, respectively.
• TDDB is a failure mechanism causing a conductive path to form in gate oxide, which causes leakage current through the gate. There can be four types of gate oxide breakdown, as illustrated inFIG. 8: oxide breakdown at the PFET source, PFET drain, NFET source, and NFET drain area. The resistive path between the gate and the source or drain area leads to current flow through the gate. This can oppose the current of the logic stage that is driving the effected FET, leading to a slowdown in either zero-to-one or one-to-zero transitions, thus making the device vulnerable to timing violations. In the present model, it is assumed that for any circuit on the critical path, a single device failure is sufficient to lead to a timing violation.
• One of the MTTF models for TDDB proposed thus far is applicable to all four types of breakdown, assuming continuous device stress (i.e., 100% duty cycle). Thus, the FORC for TDDB assuming either a PFET or an NFET device along the critical path with 100% duty cycle is given by:
• ${\mathrm{FORC}}_{\mathrm{TDDB}}=\frac{{10}^9}{A_{\mathrm{TDDB}}}·V_{\mathrm{dd}}^{a-\mathrm{bT}}·{}^{-\frac{X+\frac{Y}{T}+\mathrm{ZT}}{\mathrm{kT}}},$
• where A_TDDB, a, b, X, Y and Z are fitting parameters derived empirically.
• Generally, the method for predicting semiconductor device lifetime reliability described herein is practiced with a general-purpose computer and the method may be coded as a set of instructions on removable or hard media for use by the general-purpose computer.FIG. 9 is a schematic block diagram of a general-purpose computer for practicing the present invention. InFIG. 9,computer system900 has at least one microprocessor or central processing unit (CPU)905.CPU905 is interconnected via asystem bus910 to a random access memory (RAM)915, a read-only memory (ROM)920, an input/output (I/O)adapter925 for a connecting a removable data and/orprogram storage device930 and a mass data and/orprogram storage device935, auser interface adapter940 for connecting akeyboard945 and amouse950, aport adapter955 for connecting adata port960 and adisplay adapter965 for connecting adisplay device970.
• ROM920 contains the basic operating system forcomputer system900. The operating system may alternatively reside inRAM915 or elsewhere as is known in the art. Examples of removable data and/orprogram storage device930 include magnetic media such as floppy drives and tape drives and optical media such as CD ROM drives. Examples of mass data and/orprogram storage device935 include hard disk drives and non-volatile memory such as flash memory. In addition tokeyboard945 andmouse950, other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected touser interface940. Examples of display devices include cathode-ray tubes (CRT) and liquid crystal displays (LCD).
• A computer program with an appropriate application interface may be created by one of skill in the art and stored on the system or a data and/or program storage device to simplify the practicing of this invention. In operation, information for or the computer program created to run the present invention is loaded on the appropriate removable data and/orprogram storage device930, fed throughdata port960 or typed in usingkeyboard945.
• In view of the above, the present method embodiments may therefore take the form of computer or controller implemented processes and apparatuses for practicing those processes. The disclosure can also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer or controller, the computer becomes an apparatus for practicing the invention. The disclosure may also be embodied in the form of computer program code or signal, for example, whether stored in a storage medium, loaded into and/or executed by a computer or controller, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits. A technical effect of the executable instructions is to implement the exemplary method described above and illustrated inFIGS. 1 through 5.
• While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (24)

1. A computer program product, comprising:

a computer-readable medium having computer-executable program code stored thereon that, when executed, causes a computer to implement a method for predicting the lifetime reliability of an integrated circuit device with respect to one or more defined failure mechanisms, the method comprising:

breaking down the integrated circuit device into microarchitecture structures;

further breaking down each structure into one or more of elements and devices, with a device comprising a sub-component of an element;

determining, for each vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into one of a fatal failure and a non-fatal failure, wherein a fatal failure of a given device is one in which the failure causes the element employing the given device to fail;

determining, for those devices whose failures are classified as fatal, one or more of an effective stress degree and an effective stress time based on one or more architecture-level events and states;

determining one or more of a failure rate and a probability of fatal failure for the devices, using the one or more of the associated effective stress degree and effective stress time; and

aggregating the one or more of the failure rate of the devices and the probability of fatal failures of the devices, across the structures for the one or more defined failure mechanisms.

2. The computer program product ofclaim 1, wherein the structures include one or more of: register files, arrays, control logic, data paths, multiplexers, latches, repeated wires, and logic gates.

3. The computer program product ofclaim 1, wherein the elements include one or more of: array/register file bitlines, array/register file wordlines, memory cells, gates of transistors, and wire repeaters.

4. The computer program product ofclaim 1, wherein the devices include one or more of: metal lines, vias, PFET devices, and NFET devices.

5. The computer program product ofclaim 1, wherein the failure mechanisms include one or more of: electromigration (EM), negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB).

6. The computer program product ofclaim 5, wherein the method further comprises evaluating each device to determine whether the device is vulnerable to the one or more defined failure mechanisms and eliminating from consideration those devices determined not to be vulnerable.

7. The computer program product ofclaim 6, wherein a device vulnerable to electromigration comprises at least one of a metal line and a via dominated by unidirectional current flow therethrough.

8. The computer program product ofclaim 6, wherein a device vulnerable to NBTI comprises a PFET device having a negative gate bias applied thereto.

9. The computer program product ofclaim 6, wherein a device vulnerable to TDDB comprises one or more of: a PFET device having a logic low gate voltage and one of a logic high source and drain, and an NFET device having a logic high gate voltage and one of a logic low source and drain.

10. The computer program product ofclaim 6, wherein a fatal failure of a device due to electromigration comprises a condition in which a failure of one of a metal line and a via leads to one or more of a short circuit, an open circuit, and a timing violation due to increased wire resistance.

11. The computer program product ofclaim 6, wherein a fatal failure of a device due to NBTI comprises a condition in which a failure of a PFET device along a critical path leads to a timing violation.

12. The computer program product ofclaim 6, wherein a fatal failure of a device due to TDDB comprises a condition in which one or more of a PFET device and an NFET device has leakage current through a gate oxide thereof exceeds a value that is able to be tolerated by logic driving the same.

13. The computer program product ofclaim 6, wherein a device under stress for the electromigration failure mechanism comprises a via having current generated therethrough during one of a logical one-to-zero and a logical zero-to-one value transition of metal lines.

14. The computer program product ofclaim 6, wherein a device under stress for the NBTI failure mechanism comprises a PFET device having a gate coupled to a logic low voltage and a source coupled to a logic high voltage.

15. The computer program product ofclaim 6, wherein a device under stress for the TDDB failure mechanism comprises one or more of a PFET device having a gate coupled to a logic low voltage and a source coupled to a logic high voltage, and an NFET device having a gate coupled to a logic high voltage and a source coupled to a logic low voltage.

16. The computer program product ofclaim 1, wherein architecture-level states comprise one or more of: a number of accesses to the device, a number of access patterns to the device, and data patterns of inputs and outputs of the device.

17. The computer program product ofclaim 1, wherein architectural configuration parameters include one or more of: a number of cells in an array, a number of read ports, a number of write ports, and a number of data paths.

18. The computer program product ofclaim 1, wherein defect density is calculated as the ratio of the number of fatal failures of the devices of each structure to the area of the structure.

19. The computer program product ofclaim 18, wherein defect density for the electromigration failure mechanism is calculated by counting the number of vias having unidirectional current of each structure and dividing the total number of vias by the area of the structure.

20. The computer program product ofclaim 18, wherein defect density for the NBTI failure mechanism is calculated by counting the number of PFETs along the critical paths of each structure and dividing the total number of PFETs by the area of the structure.

21. The computer program product ofclaim 18, wherein defect density for the TDDB failure mechanism is calculated by counting the number of gate oxide breakdowns of both PFET and NFET devices of each structure, and dividing the total number of breakdowns by the area of the structure.

22. The computer program product ofclaim 18, wherein the aggregating one or more of the failure rate of the devices and the probability of fatal failures of the devices is implemented by one or more of summation and weighted summation.

23. The computer program product ofclaim 6, wherein the failure rates are computed in terms of a technology and environment independent failures-in-time (FIT) of a reference circuit (FORC) defined for each of the failure mechanisms.

24. The computer program product ofclaim 23, wherein the failure rates are further computed in absolute values utilizing power and temperature maps along with technology and implementation parameters, by calculating the value of FORC for each component and multiplying the calculated FORC values by the technology/environment-independent values of the failure rates for each of the components.

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