US20080299738A1 - Method for forming inductor on semiconductor substrate - Google Patents
Method for forming inductor on semiconductor substrateDownload PDFInfo
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- US20080299738A1 US20080299738A1US12/191,307US19130708AUS2008299738A1US 20080299738 A1US20080299738 A1US 20080299738A1US 19130708 AUS19130708 AUS 19130708AUS 2008299738 A1US2008299738 A1US 2008299738A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/20—Inductors
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
Definitions
- the present inventionrelates to inductor fabrication on a semiconductor substrate. More particularly, the present invention relates to an inductor formed with insulator slots inside, and a method for forming such an inductor.
- Inductoris widely used for radio frequency (RF) application.
- the applicationcovers a very broad spectrum.
- Some applications, such as personal handy-phone system (PHS)require an inductor to work with frequencies below 1 GHz. Accordingly, the maximum quality factor (abbreviated as Q hereinafter) of the inductor has to move into the sub-GHz range.
- a conventional solutionis stacking metal layers in parallel.
- this solutionincreases sidewall capacitance coupling and consequently degrades the broadband performance of the quality factor.
- Another solutionis widening the coil of the inductor, but an over-wide coil tends to violate chemical-mechanical polishing (CMP) rules.
- CMPchemical-mechanical polishing
- the maximum quality factor of an inductorshould be as high as possible. Therefore it is desirable to have an inductor which works properly with a frequency less than 1 GHz and is without the drawbacks of conventional solutions.
- the present inventionis to provide an inductor formed on a semiconductor substrate and a method for forming such an inductor.
- the inductor provided by the present inventioncan be widened without violating CMP rules.
- the inductor provided by the present inventionfeatures acceptable inductance and maximum quality factor comparable to that of conventional inductors under a lower operation frequency (for example, a sub-GHz frequency). This inductor also alleviates the variation in the fabrication process.
- an inductor formed on a semiconductor substrateis provided in an embodiment of the present invention.
- the inductorcomprises a single metal layer and an insulator layer.
- the metal layerconstitutes the coil of the inductor.
- the insulator layercomprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.
- the insulator slotmay be formed using silicon oxide.
- the insulator layermay comprise a row of insulator slots arranged along the coil of the inductor.
- an inductor formed on a semiconductor substrateis provided in another embodiment of the present invention.
- the inductorcomprises a plurality of metal layers and an insulator layer.
- the metal layersconstitute the coil of the inductor.
- the insulator layercomprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers.
- each insulator slotmay be encompassed in the same one of the metal layers.
- the insulator layermay comprise a plurality of insulator slots, and the insulator slots may be distributed in each one of the metal layers.
- the metal layersmay be connected in parallel to constitute the coil of the inductor.
- the metal layersmay be connected in series to constitute the coil of the inductor.
- a method for forming an inductor on a semiconductor substratecomprises the following steps. First, form a plurality of metal layers on the semiconductor substrate, and then form an insulator layer on the semiconductor substrate.
- the metal layersconstitute the coil of the inductor.
- the insulator layercomprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers.
- FIG. 1is a schematic diagram showing a conventional inductor formed on a semiconductor substrate.
- FIGS. 2A and 2Bare schematic diagrams showing an inductor according to an embodiment of the present invention.
- FIGS. 3A and 3Bare schematic diagrams showing an inductor according to an embodiment of the present invention.
- FIGS. 4A and 4Bare schematic diagrams showing an inductor according to an embodiment of the present invention.
- FIG. 6 , FIG. 7 and FIG. 8are schematic diagrams showing inductors according to various embodiments of the present invention.
- FIG. 9is a plot of inductance versus frequency of a conventional inductor and an inductor according to an embodiment of the present invention.
- FIG. 10is a plot of quality factor versus frequency of a conventional inductor and an inductor according to an embodiment of the present invention.
- FIG. 1illustrates a conventional inductor 100 fabricated on a semiconductor substrate (not shown).
- Inductor 100is formed purely with metal, without any insulator material.
- FIG. 2Aillustrates an inductor 200 according to an embodiment of the present invention.
- Inductor 200is a metallic inductor with insulator slots embedded inside, which is also formed on a semiconductor substrate (not shown).
- Inductor 200comprises a single metal layer and an insulator layer.
- the metal layerconstitutes the coil of the inductor 200 .
- the insulator layercomprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.
- FIG. 2Bis an enlarged view of the lower left corner of inductor 200 .
- each of insulator slots 201 and 202is encompassed inside the metal layer.
- Each insulator slot 201is a slim rectangular in shape, while insulator slot 202 is L-shaped.
- the insulator slotsmay be formed using silicon oxide (for example, SiO 2 ).
- the insulator slotsare not limited to a single-row arrangement. Insulator slots may be arranged into multiple rows. The insulator slots of different rows may be placed in parallel with one another or be placed in an alternate fashion. There is no limitation to the relative positions of the insulator slots. There is also no limitation to the number of rows.
- FIG. 3Aillustrates an inductor 300 according to another embodiment of the present invention. There are two rows along the coil of inductor 300 .
- FIG. 3Bis en enlarged view of the lower left corner of inductor 300 . As can be seen, one of the rows includes the exemplary insulator slots 301 and the other row includes the exemplary insulator slots 302 .
- FIGS. 4A and 4Billustrate an inductor 400 with three rows of insulator slots according to another embodiment of the present invention.
- FIGS. 5A and 5Billustrate an inductor 500 with four rows of insulator slots according to yet another embodiment of the present invention.
- Each insulator slotmay be formed in arbitrary size and shape.
- the number and arrangement of insulator slotsare also arbitrary.
- insulator slotsmay be distributed either evenly or unevenly in the coil the inductor.
- insulator slotsmay be distributed either symmetrically or asymmetrically in the coil the inductor.
- FIG. 6is an example of uneven distribution. Insulator slots are embedded only in sections 601 and 602 of the coil of inductor 600 . However, it is preferred that insulator slots have an even and symmetrical distribution in the inductor coil. Furthermore, there is no limit regarding the position of an insulator slot relative to the boundary surface of the inductor.
- An insulator slotmay be at arbitrary distance from any boundary surface of the containing metal layer.
- An insulator slotmay be completely embedded in the metal layer, in other words, surrounded in every direction by the metal layer.
- an insulator slotmay be partially embedded in the metal layer. In such a case, an insulator slot may emerge from one or more boundary surfaces of the metal layer.
- each of inductors 700 and 800comprises at least an insulator layer.
- the insulator layercomprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers.
- the distribution of insulator slots among the metal layersis quite flexible in the scope of the present invention.
- each insulator slotmay be encompassed in the same metal layer.
- the insulator slotsmay be distributed in each of the metal layers, or be distributed only in part of the metal layers.
- the inductorhas to comply with CMP rules and the maximum quality factor of the inductor has to be in the desired low frequency range (for example, below 1 GHz).
- FIG. 9 and FIG. 10illustrate the effect of an embodiment of the present invention.
- FIG. 9is a plot of inductance versus frequency of inductor 100 in FIG. 1 and inductor 600 in FIG. 6 .
- Curve 901 in FIG. 9is the plot of inductor 100
- curve 902is the plot of inductor 600 .
- FIG. 10is a plot of quality factor versus frequency of inductor 100 and inductor 600 .
- Curve 1001 in FIG. 10is the plot of inductor 100
- curve 1002is the plot of inductor 600 .
- Inductor 100is formed using metal only, with a coil width of 10 micrometers and an inner diameter of approximately 200 micrometers.
- the present inventionalso provides a method for forming an inductor on a semiconductor substrate.
- the methodis for forming inductors in the embodiments above.
- the major steps of the methodare forming one or more metal layer on the semiconductor substrate, and then forming an insulator layer on the semiconductor substrate.
- the metal layersconstitute the coil of the inductor.
- the insulator layercomprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers.
- the coil of the inductor provided by the present inventioncan be widened without violating CMP rules.
- the inductor provided by the present inventionfeatures acceptable inductance and maximum quality factor comparable to that of conventional inductors under a lower operation frequency (for example, a sub-GHz frequency).
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Abstract
Description
- This application is a divisional of an application Ser. No. 11/468,789, filed on Aug. 31, 2006, now pending. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of Invention
- The present invention relates to inductor fabrication on a semiconductor substrate. More particularly, the present invention relates to an inductor formed with insulator slots inside, and a method for forming such an inductor.
- 2. Description of Related Art
- Inductor is widely used for radio frequency (RF) application. The application covers a very broad spectrum. Some applications, such as personal handy-phone system (PHS), require an inductor to work with frequencies below 1 GHz. Accordingly, the maximum quality factor (abbreviated as Q hereinafter) of the inductor has to move into the sub-GHz range.
- For an inductor to have acceptable inductance and maximum quality factor below 1 GHz, a conventional solution is stacking metal layers in parallel. However, this solution increases sidewall capacitance coupling and consequently degrades the broadband performance of the quality factor. Another solution is widening the coil of the inductor, but an over-wide coil tends to violate chemical-mechanical polishing (CMP) rules. In addition, although widening the coil lowers the resistance and improves the maximum quality factor, it also significantly accentuates the variation in the fabrication process.
- The maximum quality factor of an inductor should be as high as possible. Therefore it is desirable to have an inductor which works properly with a frequency less than 1 GHz and is without the drawbacks of conventional solutions.
- The present invention is to provide an inductor formed on a semiconductor substrate and a method for forming such an inductor. The inductor provided by the present invention can be widened without violating CMP rules. In addition, the inductor provided by the present invention features acceptable inductance and maximum quality factor comparable to that of conventional inductors under a lower operation frequency (for example, a sub-GHz frequency). This inductor also alleviates the variation in the fabrication process.
- For the purposes mentioned above, an inductor formed on a semiconductor substrate is provided in an embodiment of the present invention. The inductor comprises a single metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.
- In this embodiment, the insulator slot may be formed using silicon oxide. The insulator layer may comprise a row of insulator slots arranged along the coil of the inductor.
- For the purposes mentioned above, an inductor formed on a semiconductor substrate is provided in another embodiment of the present invention. The inductor comprises a plurality of metal layers and an insulator layer. The metal layers constitute the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers.
- In this embodiment, the insulator slot may be formed using silicon oxide. The insulator layer may comprise a row of insulator slots arranged along the coil of the inductor.
- In this embodiment, each insulator slot may be encompassed in the same one of the metal layers. Alternatively, the insulator layer may comprise a plurality of insulator slots, and the insulator slots may be distributed in each one of the metal layers.
- In this embodiment, the metal layers may be connected in parallel to constitute the coil of the inductor. Alternatively, the metal layers may be connected in series to constitute the coil of the inductor.
- For the purposes mentioned above, a method for forming an inductor on a semiconductor substrate is provided in another embodiment of the present invention. The method comprises the following steps. First, form a single metal layer on the semiconductor substrate, and then form an insulator layer on the semiconductor substrate. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.
- For the purposes mentioned above, a method for forming an inductor on a semiconductor substrate is provided in another embodiment of the present invention. The method comprises the following steps. First, form a plurality of metal layers on the semiconductor substrate, and then form an insulator layer on the semiconductor substrate. The metal layers constitute the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers.
- In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram showing a conventional inductor formed on a semiconductor substrate.FIGS. 2A and 2B are schematic diagrams showing an inductor according to an embodiment of the present invention.FIGS. 3A and 3B are schematic diagrams showing an inductor according to an embodiment of the present invention.FIGS. 4A and 4B are schematic diagrams showing an inductor according to an embodiment of the present invention.FIGS. 5A and 5B are schematic diagrams showing an inductor according to an embodiment of the present invention.FIG. 6 ,FIG. 7 andFIG. 8 are schematic diagrams showing inductors according to various embodiments of the present invention.FIG. 9 is a plot of inductance versus frequency of a conventional inductor and an inductor according to an embodiment of the present invention.FIG. 10 is a plot of quality factor versus frequency of a conventional inductor and an inductor according to an embodiment of the present invention.- Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 1 illustrates aconventional inductor 100 fabricated on a semiconductor substrate (not shown).Inductor 100 is formed purely with metal, without any insulator material. In contrast,FIG. 2A illustrates aninductor 200 according to an embodiment of the present invention.Inductor 200 is a metallic inductor with insulator slots embedded inside, which is also formed on a semiconductor substrate (not shown).Inductor 200 comprises a single metal layer and an insulator layer. The metal layer constitutes the coil of theinductor 200. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.FIG. 2B is an enlarged view of the lower left corner ofinductor 200. There is a row of insulator slots arranged along the entire length of the coil ofinductor 200. For example, each ofinsulator slots insulator slot 201 is a slim rectangular in shape, whileinsulator slot 202 is L-shaped. The insulator slots may be formed using silicon oxide (for example, SiO2).- In the scope of the present invention, the insulator slots are not limited to a single-row arrangement. Insulator slots may be arranged into multiple rows. The insulator slots of different rows may be placed in parallel with one another or be placed in an alternate fashion. There is no limitation to the relative positions of the insulator slots. There is also no limitation to the number of rows. For example,
FIG. 3A illustrates aninductor 300 according to another embodiment of the present invention. There are two rows along the coil ofinductor 300.FIG. 3B is en enlarged view of the lower left corner ofinductor 300. As can be seen, one of the rows includes theexemplary insulator slots 301 and the other row includes theexemplary insulator slots 302. Similarly,FIGS. 4A and 4B illustrate aninductor 400 with three rows of insulator slots according to another embodiment of the present invention.FIGS. 5A and 5B illustrate aninductor 500 with four rows of insulator slots according to yet another embodiment of the present invention. - The arrangement of insulator slots is quite flexible in the scope of the present invention. Each insulator slot may be formed in arbitrary size and shape. The number and arrangement of insulator slots are also arbitrary. For example, insulator slots may be distributed either evenly or unevenly in the coil the inductor. In other words, insulator slots may be distributed either symmetrically or asymmetrically in the coil the inductor.
FIG. 6 is an example of uneven distribution. Insulator slots are embedded only insections inductor 600. However, it is preferred that insulator slots have an even and symmetrical distribution in the inductor coil. Furthermore, there is no limit regarding the position of an insulator slot relative to the boundary surface of the inductor. An insulator slot may be at arbitrary distance from any boundary surface of the containing metal layer. An insulator slot may be completely embedded in the metal layer, in other words, surrounded in every direction by the metal layer. Alternatively, an insulator slot may be partially embedded in the metal layer. In such a case, an insulator slot may emerge from one or more boundary surfaces of the metal layer. - In the above embodiments, each inductor comprises a single metal layer. The present invention also provides inductors comprising multiple metal layers. The metal layers constitute the coil of such an inductor.
FIG. 7 illustrates aninductor 700 according to an embodiment of the present invention. As shown inFIG. 7 ,inductor 700 may comprise three, four or five metal layers. The metal layers (for example,701) are stacked in parallel and are connected by vias (for example,702). In contrast,FIG. 8 illustrates anotherinductor 800 according to another embodiment of the present invention. Three metal layers801-803 are connected in series byvias inductor 800. - For simplicity, insulator slots are not shown in
FIG. 7 andFIG. 8 . In fact, each ofinductors - As discussed above, there is no limitation regarding the sizes, shapes, positions, number, arrangement, distribution and other characteristics of the insulator slots. The only restriction is that the inductor has to comply with CMP rules and the maximum quality factor of the inductor has to be in the desired low frequency range (for example, below 1 GHz).
FIG. 9 andFIG. 10 illustrate the effect of an embodiment of the present invention.FIG. 9 is a plot of inductance versus frequency ofinductor 100 inFIG. 1 andinductor 600 inFIG. 6 .Curve 901 inFIG. 9 is the plot ofinductor 100, whilecurve 902 is the plot ofinductor 600.FIG. 10 is a plot of quality factor versus frequency ofinductor 100 andinductor 600.Curve 1001 inFIG. 10 is the plot ofinductor 100, whilecurve 1002 is the plot ofinductor 600.Inductor 100 is formed using metal only, with a coil width of 10 micrometers and an inner diameter of approximately 200 micrometers.Inductor 600 is formed using metal and insulator slots, with a coil width of 20 micrometers and an inner diameter of approximately 200 micrometers. As shown inFIG. 10 , this embodiment of the present invention moves the maximum quality factor from the conventional operation frequency of 2.488 GHz to the desired lower frequency of 0.981 GHz. Furthermore, the maximum quality factor ofinductor 600 does not decay too much from that ofinductor 100.- In addition to inductor structures as discussed in the embodiments above, the present invention also provides a method for forming an inductor on a semiconductor substrate. In fact, the method is for forming inductors in the embodiments above. The major steps of the method are forming one or more metal layer on the semiconductor substrate, and then forming an insulator layer on the semiconductor substrate. The metal layers constitute the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers. The technical details of the method are the same as those of the inductor structures discussed in the previous embodiments so they are not repeated here.
- Thanks to the insulator slots, the coil of the inductor provided by the present invention can be widened without violating CMP rules. In addition, the inductor provided by the present invention features acceptable inductance and maximum quality factor comparable to that of conventional inductors under a lower operation frequency (for example, a sub-GHz frequency).
- The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.
Claims (8)
1. A method for forming an inductor on a semiconductor substrate, comprising:
forming at least a metal layer on the semiconductor substrate; and
forming at least an insulator layer on the semiconductor substrate, wherein the at least metal layer constitutes the coil of the inductor, the at least insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers.
2. The method ofclaim 1 , wherein the insulator slot is formed by using silicon oxide.
3. The method ofclaim 1 , wherein the at least insulator layer comprises a row of insulator slots arranged along the coil of the inductor.
4. The method ofclaim 1 , wherein the at least metal layer includes a plurality of metal layers.
5. The method ofclaim 4 , wherein the at least insulator layer comprises a plurality of insulator slots, and the insulator slots are distributed in each one of the metal layers.
6. The method ofclaim 4 , wherein each insulator slot is encompassed in the same one of the metal layers.
7. The method ofclaim 4 , wherein the metal layers are connected in parallel to constitute the coil of the inductor.
8. The method ofclaim 4 , wherein the metal layers are connected in series to constitute the coil of the inductor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/191,307US20080299738A1 (en) | 2006-08-31 | 2008-08-14 | Method for forming inductor on semiconductor substrate |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/468,789US7948055B2 (en) | 2006-08-31 | 2006-08-31 | Inductor formed on semiconductor substrate |
| US12/191,307US20080299738A1 (en) | 2006-08-31 | 2008-08-14 | Method for forming inductor on semiconductor substrate |
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| Application Number | Title | Priority Date | Filing Date |
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| US11/468,789DivisionUS7948055B2 (en) | 2006-08-31 | 2006-08-31 | Inductor formed on semiconductor substrate |
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| US12/191,307AbandonedUS20080299738A1 (en) | 2006-08-31 | 2008-08-14 | Method for forming inductor on semiconductor substrate |
| US13/086,500AbandonedUS20110187487A1 (en) | 2006-08-31 | 2011-04-14 | Inductor formed on a semiconductor substrate |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20110187487A1 (en) | 2011-08-04 |
| US7948055B2 (en) | 2011-05-24 |
| US20080122028A1 (en) | 2008-05-29 |
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