US20080258245A1 - Semiconductor Constructions and Transistor Gates - Google Patents

Abstract

One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first layered defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second layer defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

Description

TECHNICAL FIELD
• The invention pertains to methods of forming semiconductor structures, including methods of forming transistor gates for field effect transistor and flash memory devices.
BACKGROUND OF THE INVENTION
• A continuing goal in semiconductor device fabrication is to create increasing densities of circuitry on semiconductor real estate. Such goal is realized through ever-decreasing dimensions of semiconductor circuit elements. For instance, in the early 1970's a typical gate length of a field effect transistor gate in a dynamic random access memory (DRAM) device was on the order of from 5 to 6 micrometers, and polysilicon was utilized as a sole conductive material of the gate. Advances in DRAM generation of the late 1980's reduced the gate length to approximately one micrometer. However, it was found that word line resistance was too high if conductively doped polysilicon was utilized as the sole conductive component of a gate line, and accordingly silicide (such as tungsten silicide, molybdenum silicide or titanium silicide) was deposited over the polysilicon. The term “polycide” was coined to describe a stack of gate materials which comprised conductively doped polysilicon having a silicide thereover.
• Technological advances of the 1990's reduced the gate length to less than 0.2 micrometers. It was found that the resistance of polycide materials was too high for such gates, and accordingly procedures were developed to provide a metal to replace the silicide of the polycide structure. Exemplary metals utilized are tungsten, molybdenum and titanium. Such gates would be considered modern structures in current technology.
• FIG. 1 shows asemiconductor wafer fragment10 comprising afield effect transistor12 having such a gate structure. More specifically,wafer fragment10 comprises asubstrate14 having agate structure16 formed thereover.Gate structure16 comprises a gate oxide layer20 (which typically comprises silicon dioxide), a conductively-doped-semiconductive material layer22 (which can comprise silicon and germanium, and which typically comprises conductively doped polysilicon), a conductive diffusion barrier layer24 (which typically comprises a metal nitride, such as, for example, WN_x, TiN), a metal layer26 (which can comprise, for example, tungsten, molybdenum or titanium), and an insulative cap28 (which can comprise, for example, silicon nitride or silicon dioxide).
• Semiconductive substrate14 can comprise, for example, conductively doped monocrystalline silicon. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
• Gate structure16 has opposingsidewalls30, andinsulative spacers32 are formed along such opposing sidewalls.Insulative spacers32 can comprise, for example, silicon nitride.
• Source/drain regions18 formedproximate gate structure16, and achannel region19 is defined beneathgate structure16.Spacers32 can be utilized during formation of source/drain regions18 to space an implant of a conductivity-enhancing dopant fromsidewall edges30, and to thereby control a location of heavily doped source/drain regions18 relative tosidewalls30. Lightly doped diffusion regions are formed beneathspacers32, and between heavily doped source/drain regions18 andchannel region19, to define gradedjunction regions33. The lightly doped diffusion regions are frequently formed prior to provision ofspacers32.
• A problem can occur in utilizing the fieldeffect transistor structure12 ofFIG. 1 in DRAM devices. DRAM devices normally operate with a wordline voltage in excess of power supply voltage (a so-called boosted wordline). Accordingly, transistor gates utilized in gated DRAM structures are exposed to larger electric fields than in other devices, and are more subject to breakdown and failure. Also, DRAM retention time depends on the storage node junction leakage, which in turn can be affected by the electric field at intersecting corners of the gate and the drain junction. The electric field between the gate and the drain junction often induces more junction leakage and is frequently referred to as Gate Induced Drain Leakage (GIDL). It is therefore desirable to have a thickened gate oxide region at the corner of the gate and the drain to reduce the electric field, and hence the leakage.
• One of the techniques utilized to enhance integrity of transistor gates is to oxidize a portion of a semiconductive material substrate proximate the gate to form small “bird's beak” structures beneathsidewall edges30. Such technique is illustrated inFIG. 2 whereinwafer fragment10 is illustrated at a processing step subsequent to the formation ofgate structure16, but prior to formation ofspacers32 and source/drain regions18. An upper surface ofsemiconductive material wafer14 has been oxidized to form asilicon dioxide layer34 which connects withgate oxide20.Silicon dioxide layer34 comprises small bird'sbeak regions36 which extend beneathsidewalls30.Silicon dioxide layer34 also extends along a portion ofsidewall30 corresponding to the sidewall edges of semiconductive-material layer22, as such edges are oxidized during the oxidation of the upper surface ofsemiconductive material14.
• A problem which occurs with the processing ofFIG. 2 is that sidewall edges ofmetal layer26 can be oxidized during the oxidation ofsemiconductive material14. Oxidation ofmetal layer26 formsmetal oxide regions38. The volume expansion associated with the formation ofmetal oxide regions38 can cause lifting of the metal lines, which can result in failure of field effect transistor structures incorporatinggate structure16.
• Among the techniques which have been utilized to avoid oxidation of the metal edge are wet hydrogen oxidation, and the utilization of silicon nitride or silicon dioxide to protect the edges. Additionally, silicon oxynitride has been utilized to cover edges of the metal material in the gate stack prior to oxidation of an upper surface ofsemiconductive material14.
• The above-described problems are not limited to field effect transistor technologies. The problems can also occur in stacks utilized for other memory devices, such as, for example, the gate stacks utilized in flash memory devices.FIG. 3 illustrates asemiconductor wafer fragment50 comprising asemiconductive material substrate52, and a flash memorydevice gate stack54 formed oversubstrate52.Substrate52 can comprise, for example, monocrystalline silicon lightly doped with a p-type background dopant.Gate stack54 comprises a gate oxide layer56 (which can comprise silicon dioxide), a floating gate58 (which comprises semiconductive material, which can comprise Si and Ge, and which typically comprises conductively doped polysilicon), an intergate dielectric layer60 (which can comprise silicon dioxide), a conductively doped-semiconductive-material layer62 (which can comprise conductively doped polysilicon), a barrier layer64 (which can comprise a metal nitride), a metal layer66 (which can comprise tungsten, titanium or molybdenum), and an insulative cap68 (which can comprise silicon nitride).FIG. 3 also shows anoxide layer69 oversubstrate52, and Lightly Doped Diffusion (LDD)regions71 implanted beneathoxide layer69 andproximate gate stack54.LDD regions71 can be formed by, for example, implanting n-type conductivity enhancing dopant (such as phosphorus or arsenic) intosubstrate52.
• Note thatlayers60,62,64,66 and68 comprise a stack identical to the stack utilized ingate structure16. Accordingly, oxidation ofsemiconductive material substrate52 can lead to problems similar to those discussed above regarding oxidation ofsemiconductive material14. Specifically, oxidation ofsemiconductive material52 can be accompanied by oxidation of sidewall edges ofmetal layer66 which can cause failure of a circuitdevice incorporating stack54.
• The above-describedFIGS. 1-3 illustrate cross-sectional views through the described stacks of conductive and insulative materials. Such cross-sectional views are utilized to illustrate various layers within the stacks. An alternative description of the stacks ofFIGS. 1-3 is to refer to the stacks as portions of patterned wordlines. In such alternative description, it is to be understood that the stacks can be portions of lines extending across the respective semiconductor material substrates (i.e., the stacks can be patterned in the shape of lines). Source/drain regions will be provided at various intervals along the lines, and the lines will thus have transistor gate regions functioning as gating structures between respective pairs of source/drain regions.
• It would be desirable to develop alternative methods of forming gate stacks and wordlines.
SUMMARY OF THE INVENTION
• One aspect of the invention includes a method of forming a conductive line. A line stack is formed of at least two different conductive material layers. At least one of the layers comprises a metal, and the line stack has at least one sidewall edge that includes the metal-comprising layer. The metal-comprising layer is reacted at the sidewall edge with silicon to form the metal-comprising layer to comprise a silicide at the sidewall edge and unreacted metal inwardly thereof. After the reacting, at least a portion of the line stack is oxidized.
• Another aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first layered defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second layer defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.
• In another aspect, the invention encompasses another method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layered-defined portion and a second layered defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layer-defined portion of the sidewall edge and the second layer defined portion of the sidewall edge. The silicon of the third layer is reacted with metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is provided to be different than the silicon of the first layer, and is selectively removed relative to the silicon of the first layer to leave the silicide along the second-layer-defined portion of the sidewall edge.
BRIEF DESCRIPTION OF THE DRAWINGS
• Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
• FIG. 1 is a fragmentary, diagrammatic, cross-sectional view of a semiconductor wafer fragment illustrating a prior art field effect transistor device.
• FIG. 2 is a fragmentary, diagrammatic, cross-sectional view of a semiconductor wafer fragment illustrating a prior art gate structure.
• FIG. 3 is a diagrammatic, fragmentary, cross-sectional view of a semiconductor wafer fragment illustrating a prior art gate structure for a flash memory device.
• FIG. 4 is a diagrammatic, fragmentary, cross-sectional view of a semiconductor wafer fragment illustrating a gate structure at a preliminary step of a method of the present invention.
• FIG. 5 is a view of theFIG. 4 wafer fragment illustrating the structure ofFIG. 4 at a processing step subsequent of that ofFIG. 4.
• FIG. 6 is a view of theFIG. 4 wafer fragment illustrating the structure ofFIG. 4 at a processing step subsequent to that shown inFIG. 5.
• FIG. 7 is a view of theFIG. 4 wafer fragment illustrating the structure ofFIG. 4 at a processing step subsequent to that ofFIG. 6.
• FIG. 8 is a view of theFIG. 4 wafer fragment illustrating the structure ofFIG. 4 processed according to another method of the present invention, and shown at a processing step subsequent to that ofFIG. 4.
• FIG. 9 is a view of theFIG. 4 wafer fragment shown at a processing step subsequent to that ofFIG. 8.
• FIG. 10 is a view of theFIG. 4 wafer fragment shown at a processing step subsequent to that ofFIG. 9.
• FIG. 11 is a view of theFIG. 4 wafer fragment shown at a processing step subsequent to that ofFIG. 4, and in accordance with yet another embodiment method of the present invention.
• FIG. 12 is a view of theFIG. 4 wafer fragment shown at a processing step subsequent of that ofFIG. 11.
• FIG. 13 is a view of theFIG. 4 wafer fragment shown at a processing step subsequent to that ofFIG. 12.
• FIG. 14 is a fragmentary, diagrammatic, cross-sectional view of a semiconductor wafer fragment shown at a preliminary processing step of yet another method of the present invention.
• FIG. 15 is a view of theFIG. 14 wafer fragment shown at a processing step subsequent to that ofFIG. 14.
• FIG. 16 is a view of theFIG. 14 wafer fragment shown at a processing step subsequent to that ofFIG. 15.
• FIG. 17 is a view of theFIG. 14 wafer fragment shown at a processing step subsequent to that ofFIG. 16.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
• In particular aspects, the invention encompasses methods of protecting a metal layer during oxidation of a proximate substrate by forming silicide structures over regions of the metal layer. The silicide protects regions of the metal layer from being exposed to oxidizing conditions.
• A first embodiment method of the present invention is described with reference toFIGS. 4-6. Referring initially toFIG. 4, such illustrates asemiconductor wafer fragment100 comprising asemiconductive material substrate102 having agate stack104 formed thereover.Semiconductive material substrate102 can comprise, for example, monocrystalline silicon lightly doped with a p-type background dopant.Gate stack104 comprises a gate dielectric layer106 (which can comprise, for example, silicon dioxide), a semiconductive-material layer108 (which can comprise silicon and germanium, and which typically comprises conductively doped polysilicon), a barrier layer110 (which can comprise, for example, a metal nitride, such as titanium nitride or tungsten nitride), a metal layer112 (which preferably comprises an elemental form of a metal, and which can comprise, for example, tungsten, titanium, cobalt or molybdenum), and an insulative cap114 (which can comprise, for example, silicon nitride and/or silicon dioxide).
• For purposes of interpreting this disclosure and the claims that follow, a layer which is referred to as a “silicon layer” is to be understood to comprise silicon and may consist essentially of silicon, but not necessarily to consist essentially of silicon unless it is expressly stated that such layer consists essentially of silicon. Accordingly, a “silicon layer” can comprise, for example, silicon and germanium. Additionally, a “metal layer” is to be understood to comprise metal and may consist essentially of metal, but not to necessarily consist essentially of metal unless it is specifically stated to consist essentially of metal.
• Gate stack104 comprisessidewalls116, and such sidewalls comprise portions of each oflayers106,108,110,112 and114. In particular aspects of the invention,layer108 can be referred to as a first layer andlayer112 as a second layer. The portion ofsidewall116 corresponding to layer112 can thus be referred to as a second layer defined portion, and the portion ofsidewall116 corresponding to layer108 can be referred to as a first layer defined portion.
• Substrate102 comprises anupper surface118, some of which is covered bygate stack104, and some of which extends beyondgate stack104. Anetch stop layer117 is formed overupper surface118 ofsubstrate102. Such etch stop layer can comprise, for example, silicon oxide or silicon nitride. Asilicon layer120 is formed overupper surface118 of substrate102 (and specifically on etch stop layer117), along sidewalls116 ofgate stack104, and over an upper surface ofgate stack104.Layer120 can comprise, for example, silicon in amorphous or polycrystalline form, and is typically formed to a thickness of from about 100 angstroms to about 200 angstroms.Silicon layer120 can be formed by chemical vapor deposition to providelayer120 to lie conformally over the sidewalls and top ofgate stack104. Generally, the difference between whetherlayer120 comprises amorphous silicon or polycrystalline silicon is determined by a temperature of deposition, with amorphous silicon being deposited at temperatures of from about 500° C. to about 550° C., and polycrystalline silicon being deposited at temperatures of from about 580° C. to about 625° C.
• In particular aspects of the invention,silicon layer120 comprises a different composition than silicon-containinglayer108. Such difference in composition can correspond to, for example, a difference in dopant concentration withinsilicon layer120 relative tosilicon layer108. For instance,layer108 preferably has a conductivity-enhancing impurity concentration of at least 1×10¹⁸atoms/cm³to renderlayer108 electrically conductive. Accordingly,layer120 can be provided with a conductivity-enhancing dopant concentration of less than 1×10¹⁸atoms/cm³to provide a difference betweenlayers120 and108. Such difference can be exploited in later steps of the method to enablelayer120 to be selectively removed relative to layer108. In particular embodiments,layer120 can be provided to be substantially undoped with conductivity-enhancing impurity, with the term “substantially undoped” understood to mean a dopant concentration of less than or equal to about 1×10¹⁵atoms/cm³. A “substantially undoped” silicon layer is different than an “undoped” silicon layer in that an “undoped” silicon layer would have a dopant concentration of about zero, whereas a “substantially undoped” silicon layer can have a dopant concentration from zero to as high as about10¹⁵atoms/cm³.
• In particular aspects of the invention,layer120 can be referred to as a third layer which extends along both the portion of thesidewall116 defined bysilicon layer108, and the portion defined bymetal layer112.
• FIG. 5 shows fragment100 after exposure to conditions which react silicon oflayer120 with metal oflayer112 to formsilicide regions122. Exemplary reaction conditions are to annealfragment100 at 900° C. for about 20 minutes in an inert atmosphere. Alternative reaction conditions comprise rapid thermal processing (RTP) for ten seconds to 950° C. The second reaction conditions can be preferred in order to avoid dopant redistribution betweensilicon layers120 and108.
• Referring toFIG. 6, layer120 (FIG. 5) has been removed to leavesilicide regions122 alongsidewalls116. Removal oflayer120 can be accomplished by, for example, a timed etch, such as, for example, a timed reactive ion etch, wet etch, or high density plasma etch. Preferably, the etch will not appreciably etch into the sidewalls ofsilicon layer108, (with the term “appreciable etching” meaning an etch of more than 5 angstroms into the sidewall), and also preferably the etch stops onetch stop layer117 rather extending intoupper surface118 ofsubstrate102. Particular etching methodology can be utilized in embodiments in which silicon layer120 (FIG. 5) comprises a different composition thansilicon layer108. In such embodiments, the etching preferably takes advantage of such differences in composition to selectively remove silicon oflayer120 relative to silicon oflayer108. For instance, iflayer120 comprises silicon which is less doped than the silicon oflayer108, such less doped silicon can be selectively removed utilizing a tetramethylammonium hydroxide (TMAH) etch solution.
• FIG. 7 shows fragment100 after exposure to oxidizing conditions. It is noted thatetch stop layer117 can be stripped from oversubstrate102 prior to the exposure of the substrate to oxidizing conditions, or can remain, and if it comprises silicon dioxide, be expanded upon exposure of the underlying substrate to oxidizing conditions. The oxidizing conditions incorporate silicon fromupper surface118 ofsubstrate102 into alayer130 of silicon dioxide, and also incorporate silicon from sidewalls oflayer108 into silicon dioxide. Further, the oxidation has formed small bird'sbeaks132 under sidewall edges116 ofgate stack104. However, in contrast to the prior art (FIG. 2 illustrates the result of an exemplary prior art process) the oxidation has not oxidized sidewalls ofmetal layer112. Rather,silicide regions122 have protected the sidewalls ofmetal layer112 during the oxidation.
• FIGS. 8-10 illustrate an embodiment of the invention wherein the silicon of layer120 (FIG. 5) is converted to a form which can be selectively removed relative to the silicon oflayer108. Referring initially toFIG. 8, such illustrateswafer fragment100 at a processing step subsequent to that shown inFIG. 5. Specifically,silicon layer120 ofFIG. 5 has been subjected to oxidizing conditions to convert the layer to asilicon dioxide layer140. Subsequent processing such as, for example, wet etching ofoxide layer140 in a diluted HF solution can selectively remove the oxide oflayer140 relative to non-oxidized silicon oflayer108 to form the structure ofFIG. 6 (although some etching intosidewall edge116 may occur).
• FIG. 9 showswafer fragment100 after asecond insulative layer143 has been formed over silicon dioxide layer140 (the second insulative layer can comprise, for example, silicon oxide or silicon nitride), and bothsilicon dioxide layer140 andsecond insulative layer143 have been exposed to an anisotropic etch to forminsulative spacers142. Exemplary conditions for anisotropically etching silicon dioxide are etching of the silicon dioxide in a magnetic loop discharge plasma, or utilization of a fluorine-containing plasma in a reactive ion etch. It is noted thatlayer117 is shown remaining oversubstrate102 after the anisotropic etch ofmaterials142 and143. In embodiments in whichlayer117 comprises silicon nitride andmaterials142 and143 both comprise silicon dioxide,layer117 can function as an etch stop layer to protectsubstrate102 during the anisotropic etch oflayers142 and143. Alternatively, iflayer117 comprises silicon dioxide, andmaterials142 and143 also comprise silicon dioxide,layer117 can form a buffer oversubstrate102 to protectsubstrate102 during a timed anisotropic etch ofmaterials142 and143.
• FIG. 10 shows adopant144 implanted intofragment100 to form source/drain regions146proximate gate stack104. Source/drain regions146 are aligned utilizingspacers142. In subsequent processing (not shown)spacers142 can be removed, andsubstrate102 can be oxidized to form small bird's beak structures analogous to thestructures132 ofFIG. 7. Further, graded junction regions can be implanted proximate source/drain regions146 subsequent to removal ofspacers142. Alternatively, graded junctions (such as LDD or “link-up” regions) can be implanted in a processing step prior to that shown inFIG. 4. Such processing a step can, for example, occur after formation ofgate stack104 and before deposition ofsilicon layer120.
• Yet another method of the present invention is described with reference toFIGS. 11-13. Referring toFIG. 11,wafer fragment100 is shown at a processing step subsequent to that ofFIG. 4, and specifically is shown after amaterial153 is provided over silicon layer120 (FIG. 4), and bothmaterial153 andsilicon layer120 have been subjected to anisotropic etching.Material153 can comprise, for example, silicon dioxide or silicon nitride. The anisotropic etching removes the silicon layer from overstack104 and leavesportions150 and152 of the silicon layer along sidewall edges116.
• Referring toFIG. 12,fragment100 is shown after exposure to suitable conditions to react silicon ofportions150 and152 with metal oflayer112 to formsilicide regions154. Such suitable conditions can comprise, for example, the conditions described above with reference toFIG. 5.
• Referring toFIG. 13, anisotropically etchedmaterial153 is utilized withportions150 and152 as spacers during an implant of adopant156. The implanted dopant forms source/drain regions158. Also shown are graded junction regions190 (such as, for example, LDD regions or halo regions), which can be formed by, for example, an angled implant. After formation of source/drain regions158 and gradedjunction regions190,stack104 comprises a gate for a field effect transistor which gatedly connects source/drain regions158 with one another.Stack104 defines achannel region160 thereunder which is between the source/drain regions158. In further processing (not shown)portions150 and152 can be removed. Such further processing can be similar to that described above with reference toFIG. 6, and can occur before or after formation ofdiffusion regions158.
• In yet other aspects of the invention, the utilization ofmaterial153 can be avoided, to leaveonly portions150 and152 alongstack104. Further,portions150 and152 can be removed prior to any implant of source/drain regions, to form a structure identical to that shown inFIG. 6. Such structure can be subjected to the oxidative processing described with reference toFIG. 7. Alternatively, such oxidative processing can occur after formation of source/drain regions158, and either withportions150 and152 in place, or afterportions150 and152 have been removed.
• Another method encompassed by the present invention is described with reference toFIGS. 14-17. In referring toFIGS. 14-17, similar numbering will be used as was utilized in describingFIGS. 4-13, with differences indicated by the suffix “a”.
• FIG. 14 shows a semiconductor wafer fragment100awhich is similar to thefragment100 ofFIG. 4. Fragment100aofFIG. 14 differs fromfragment100 ofFIG. 4 in that fragment100acomprises asilicon dioxide layer106ahaving portions which extend outwardly beyondstack104, as well as having a portion beneathstack104. In contrast,fragment100 ofFIG. 4 has asilicon dioxide layer106 which is patterned to have sidewalls coextensive with sidewalls ofsilicon layer108, and accordingly, part ofsidewalls116 ofgate stack104.
• Fragment100acomprises asilicon layer120 identical to that ofFIG. 4fragment100, and such silicon layer can be processed identically to the processing described above with reference toFIGS. 5-13. A particular processing sequence is described with reference toFIGS. 15-17. Referring toFIG. 15, wafer fragment100ais shown after silicon layer120 (FIG. 14) has been subjected to an anisotropic etch to convert the layer toextensions170 which extend along sidewall edges116 ofgate stack104. The shown etch has stopped atoxide layer106a. Such can be accomplished by timing an etch oflayer120 to stop atsilicon dioxide layer106a, or by utilizing etchant conditions which are selective for the silicon material oflayer120 relative to the silicon dioxide oflayer106a. In an alternative embodiment of the invention (not shown), etch conditions can be utilized which do not stop atlayer106a, but which rather extend throughlayer106atosubstrate102. Suchconditions pattern layer106ainto an insulative layer which is only beneathstack104 and extensions170 (i.e., which does not extend outwardly beyond extensions170).
• Referring toFIG. 16, fragment100ais subjected to conditions which react silicon fromextensions170 with metal fromlayer112 to formsilicide extensions172. Suitable conditions for reacting the silicon and metal are the conditions described above with reference toFIG. 5.
• Referring toFIG. 17, extensions170 (FIG. 16) are removed to leavesuicide regions172 protecting sidewalls ofmetal112. Portions ofsilicon dioxide layer106awhich were covered byextensions170 in the processing step ofFIG. 16 remain afterextensions170 are removed. After removal ofextensions170, fragment100acan be subjected to oxidation conditions such as those described above with reference toFIG. 7. In alternative embodiments of the present invention,extensions170 can be utilized as spacers during an implant of dopant to form source/drain regions in processing similar to that described above with reference toFIG. 13.
• Although the invention has been described with reference to methods of forming field effect transistor structures, it is to be understood that the invention can also be applied to methods of forming other memory devices, such as, for example, flash memory devices. An exemplary method of utilizing the techniques described with reference toFIGS. 4-17 to form flash memory devices is to form the gate stacks described inFIGS. 4-17 over floating gate structures (with an exemplary floating gate structure shown inFIG. 3). The gate stacks will, of course, generally be separated from a floating gate by an intergate dielectric, such as, for example, the dielectric60 described with reference toFIG. 3.
• In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (21)

1-40. (canceled)

41) A semiconductor construction comprising:

a semiconductive substrate having a metal mass thereover, the metal mass comprising opposing sidewalls; and

an oxide-comprising material above the substrate, wherein at least one sidewall of the metal mass is substantially free of metal oxide.

42) The semiconductor construction ofclaim 41 wherein the metal mass comprises tungsten.

43) The semiconductor construction ofclaim 41 wherein the oxide-comprising material comprises silicon oxide.

44) The semiconductor construction ofclaim 41 wherein the oxide-comprising material is between the metal mass and the substrate.

45) The semiconductor construction ofclaim 41 further comprising semiconductive material between the metal mass and the substrate, the semiconductive material having opposing sidewalls and forming a gate transistor with the metal mass.

46) The semiconductor construction ofclaim 45 wherein at least one of the sidewalls of the semiconductive material is oxidized.

47) The semiconductor construction ofclaim 45 wherein the semiconductive material comprises a dopant.

48) The semiconductor construction ofclaim 47 further comprising a silicide-comprising material along the at least one sidewall of the metal mass.

49) The semiconductor construction ofclaim 48 further comprising a barrier material between the metal mass and the semiconductive material, wherein the barrier material comprises opposing sidewalls, the sidewalls of the barrier material being substantially free of both the silicide-comprising and the metal oxide.

50) A transistor gate comprising a semiconductive layer having a metal layer thereover, the semiconductive and metal layers defining a stack having opposing sidewalls, wherein:

an oxide-comprising material is formed along at least one of the sidewalls of the semiconductive layer; and

at least one of the sidewalls of the metal layer is substantially free of metal oxide.

51) The transistor gate ofclaim 50 wherein the metal layer comprises tungsten.

52) The transistor gate ofclaim 50 wherein the semiconductive material comprises doped polysilicon.

53) The transistor gate ofclaim 50 wherein the semiconductive material comprise germanium.

54) The transistor gate ofclaim 50 further comprising an insulative cap over the metal layer.

55) The transistor gate ofclaim 54 wherein the insulative cap comprises opposing sidewalls, the oxide-comprising material being formed along at least one of the sidewalls of the insulative cap.

56) The transistor gate ofclaim 50 further comprising insulative material formed along the sidewalls of the stack.

57) The transistor gate ofclaim 50 further comprising a barrier layer between the semiconductive material and the metal layer.

58) The transistor gate ofclaim 57 wherein the barrier layer comprises metal nitride.

59) The transistor gate ofclaim 50 further comprising a silicide-comprising material along the at least one sidewall of the metal layer.

60) The transistor gate ofclaim 50 further comprising source/drain regions associated with the gate.

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