FIELDThis disclosure relates generally to generating oscillating signals, and in particular, to reducing time for an oscillating signal to reach a defined steady-state condition.
BACKGROUNDPrevious communication systems use techniques that are generally power inefficient. These systems typically employ transmitters and receivers that may require continuous power even during times when they are not transmitting or receiving communications. Such systems that remain idle while still consuming power are typically inefficient from a power perspective.
In some applications, power inefficient communication devices may present limitations as to their continuous use. For example, portable communication devices that rely on battery power generally provide relatively short continuous operation before the battery needs to be replaced or recharged. In some situations, this may result in adverse consequences, such as data loss, communication delays, dropped sessions, and down time.
On the other hand, communication systems that consume substantially lower power during idle times are able to operate for longer periods with a limited power source. Thus, communication systems that power on a transmitter only when the signal is to be transmitted will generally consume less power than a transmitter that is continuously powered. Similarly, communication systems that power on a receiver only when the signal is to be received will generally consume less power than a receiver that is continuously powered.
A pulse modulator may be used to control the times for transmitting and receiving signals. In this regard, a pulse modulator may power on a transmitter local oscillator (LO) for transmitting a signal only for the duration of a pulse. Similarly, a pulse modulator may power on a receiver LO for receiving a signal only for the duration of a pulse. In this capacity, the LO generates and sustains an oscillating signal within the duration of each pulse. If the pulse width is relatively short, such as in a low duty cycle application, the LO should respond quickly to generate a sufficiently stable oscillating signal.
SUMMARYA summary of sample aspects of the disclosure follows. For convenience, one or more aspects of the disclosure may be referred to herein simply as “some aspects.”
Some aspects of the disclosure relate to an apparatus for generating an oscillating signal. The apparatus comprises a first circuit to generate an oscillating signal, a second circuit too supply a first current to the first circuit; and a third circuit to supply a second current to the first circuit, wherein the first and second currents are adapted to reduce the time duration for the oscillating signal to reach a defined steady-state condition.
In some aspects, the apparatus may be configured as a voltage controlled oscillator (VCO). In this regard, the second circuit may be configured as a boost bias circuit to accelerate the time in which an oscillating signal reaches a defined steady-state condition from a cold start. This is particularly useful in communication systems and devices that use low duty cycle pulse modulation to establish one or more communications channels. In such applications, the VCO, serving as a local oscillator (LO), begins generating an oscillating signal at approximately the beginning of the pulse and terminates the oscillating signal at approximately the end of the pulse. For improved communication performance, the oscillating signal should reach a defined steady-state condition within a relatively short time period as compared to the width of the pulse.
In some aspects, the VCO comprises an oscillating circuit to generate an oscillating signal; a quiescent bias circuit to supply a quiescent current to the oscillating circuit; and a boost bias circuit to supply a boost current to the oscillating circuit, wherein the boost current and the quiescent current are adapted to reduce the time duration for the oscillating signal to reach a defined steady-state condition.
In some aspects, the first circuit of the apparatus may comprise a tank circuit coupled to a negative resistance generator. The tank circuit, in turn, may comprise an inductive element coupled to a capacitive element. The capacitive element may comprise a programmable switched capacitor bank for tuning the frequency of the oscillating signal.
In some aspects, the apparatus may further comprise a steady-state detector adapted to disable the third circuit from supplying the second current to the first circuit in response to detecting the defined steady-state condition of the oscillating signal. Thus, the third circuit may only be used upon start up to quickly achieve the defined steady-state condition of the oscillating signal. The defined steady-state condition of the oscillating signal may specify a stability requirement for the amplitude and/or frequency of the oscillating signal.
In some aspects, the apparatus may further comprise a frequency calibration unit adapted to tune the first circuit so that the oscillating signal cycles within a defined frequency range. In some communications systems, such as energy detection systems, the frequency of the LO need not be that precise. For example, the defined frequency range may be up to five (5) percent of a defined center frequency. The frequency calibration unit may be adapted to calibrate or tune the first circuit upon power up, upon detecting an ambient temperature change above a defined threshold, and/or upon receiving a new frequency specification for the oscillating signal.
In some aspects, one or more apparatuses may be used as local oscillators (LOs) in communication systems and devices to up convert and down convert signals. For example, the apparatus may be used to establish one or more ultra-wide band (UWB) channels for communicating with other devices using pulse division multiple access (PDMA), pulse division multiplexing (PDM), or other types of pulse modulation techniques. A UWB channel may be defined as having a fractional bandwidth on the order of 20% or more, a bandwidth on the order of 500 MHz or more, or both. The fractional bandwidth is a particular bandwidth associated with a device divided by its center frequency. For example, a device according to this disclosure may have a bandwidth of 1.75 GHz with center frequency 8.125 GHz and thus its fractional bandwidth is 1.75/8.125 or 21.5%.
In some aspects, the apparatus may be implemented in or comprise a headset, medical device, microphone, biometric sensor, heart rate monitor, pedometer, EKG device, user I/O device, watch, remote control, switch, tire pressure monitor, entertainment device, computer, point-of-sale device, hearing aid, set-top box, cell phone, or a device with some form of wireless signaling capability. In some aspects, the apparatus may be implemented in or comprise an access point such as a WiFi node. For example, the access point may provide connectivity to another network (e.g., a wide area network such as the Internet) via a wired or wireless communication link.
Other aspects, advantages and novel features of the present disclosure will become apparent from the following detailed description of the disclosure when considered in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1A illustrates a block diagram of an exemplary apparatus for generating an oscillating signal in accordance with some aspects of the disclosure;
FIG. 1B illustrates a block diagram of an exemplary apparatus for generating an oscillating signal in accordance with some aspects of the disclosure;
FIG. 1C illustrates a flow diagram of an exemplary method of generating an oscillating signal in accordance with some aspects of the disclosure;
FIG. 2 illustrates a flow diagram of an exemplary method of calibrating an apparatus for generating an oscillating signal in accordance with some aspects of the disclosure;
FIG. 3 illustrates a flow diagram of an exemplary method of enabling and disabling an apparatus for generating an oscillating signal in accordance with some aspects of the disclosure;
FIG. 4 illustrates a schematic diagram of an exemplary apparatus for generating an oscillating signal in accordance with some aspects of the disclosure;
FIG. 5 illustrates a block and schematic diagram of an exemplary communication device in accordance with some aspects of the disclosure;
FIGS. 6A-D illustrate timing diagrams of various pulse modulation techniques in accordance with some aspects of the disclosure; and
FIG. 7 illustrates a block diagram of various communication devices communicating with each other via various channels in accordance with some aspects of the disclosure.
DETAILED DESCRIPTIONVarious aspects of the disclosure are described below. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein are merely representative. Based on the teachings herein one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein.
As an example of some of the above concepts, in some aspects, the inventive device or apparatus according to this disclosure comprises a first circuit to generate an oscillating signal; a second circuit to supply a first current to the first circuit; and a third circuit to supply a second current to the first circuit, wherein the first and second currents are adapted to reduce a time duration for the oscillating signal to reach a defined steady-state condition. In other aspects, the inventive apparatus may comprise a VCO that in turn comprises a single circuit adapted to generate an initial higher current for the oscillating circuit to accelerate the generation of a defined steady-state oscillating signal, and a subsequent lower current for the oscillating circuit to sustain the generation of the defined steady-state oscillating signal. The term “defined” as used herein may be construed as “predetermined”, “predefined”, or “dynamically defined.”
FIG. 1A illustrates a block diagram of anexemplary apparatus100 for generating an oscillating signal in accordance with some aspects of the disclosure. Theapparatus100 is capable of generating an oscillating signal having a frequency dictated by a frequency input. In some aspect, theapparatus100 may be configured or comprise a voltage controlled oscillator (VCO). Theapparatus100 comprises an integrated circuit to generate first and second currents to accelerate the oscillating signal in reaching a defined steady-state condition from a start up condition. As discussed in more detail below, this is particularly useful for communication devices that use relatively low duty cycle pulse modulation to establish communication channels. In this regard, theapparatus100 begins generating the oscillating signal at approximately the beginning of the pulse and stops generating the oscillating signal at approximately the end of the pulse.
More specifically, theapparatus100 comprises an integrated circuit (IC)102 for generating a first current (e.g., a quiescent bias current), anIC104 for generating a second current (e.g., a boost bias current), and anIC106 for generating anoscillating signal106. Although in this example, theICs102,104, and106 are shown as separate ICs, it shall be understood that any of these may be configured into one or more ICs. TheIC106 generates an oscillating signal (e.g., a sinusoidal signal) cycling at a frequency dictated by a frequency input. TheIC102 provides a first current to theIC106 during start-up and steady-state conditions. TheIC104 provides a second current to theIC106 during start up to accelerate the oscillating signal in reaching a defined steady-state condition. The defined steady-state condition may specify a stability requirement for the frequency and/or the amplitude of the oscillating signal.
FIG. 1B illustrates a block diagram of anexemplary apparatus150 for generating an oscillating signal in accordance with some aspects of the disclosure. Theapparatus150 may be a more detailed implementation of theapparatus100 previously discussed. In particular, theapparatus150 comprises acircuit152 for generating a first current (e.g., a quiescent bias current), acircuit154 for generating a second current (e.g., a boost bias current), an output steady-state detector156, afrequency calibration unit158, acircuit160 for generating an oscillating signal (“oscillating circuit”), and anambient temperature sensor162. Thecircuit160 generates an oscillating signal cycling with a frequency that is tunable via a frequency tuning word received from thefrequency calibration unit158.
Thefrequency calibration unit158 receives a frequency input word that specifies the frequency or frequency range of the oscillating signal, and measures the actual frequency of the oscillating signal from a sample received from the output of theoscillating circuit160. Based on the frequency input word and the measured frequency, thefrequency calibration unit158 generates a frequency tuning word that tunes theoscillating circuit160 so that the frequency of the oscillating signal is within the requirement specified by the frequency input word. Thefrequency calibration unit158 may calibrate the frequency of the oscillating signal upon power up, upon receiving a new frequency input word, and/or upon detecting a change in ambient temperature that exceeds a defined threshold. Thefrequency calibration unit158 receives temperature information from theambient temperature sensor162.
Thecircuit152 provides a first current to theoscillating circuit160 during start-up and steady-state conditions. Theboost bias circuit154 provides a second current to theoscillating circuit160 during start up to accelerate the oscillating signal reaching a defined steady-state condition from a start up condition. The output steady-state detector156 samples the output of theoscillating circuit160 in order to disable thecircuit154 when thedetector156 detects the defined steady-state condition of the oscillating signal. Thus, thecircuit154 is used during start up of theoscillating circuit160 in order to reduce the time for the oscillating signal to reach the defined steady-state. As previously discussed, the defined steady-state condition may specify a stability requirement for the frequency and/or the amplitude of the oscillating signal.
FIG. 1C illustrates a flow diagram of anexemplary method170 of generating an oscillating signal in accordance with some aspects of the disclosure. According to themethod170, a first current (e.g., a quiescent bias current) is generated (block171). Additionally, a second current (e.g., a boost bias current) is generated (block174). Then, an oscillating signal is generated in response to the first and second currents (block176).
FIG. 2 illustrates a flow diagram of anexemplary method200 of calibrating theapparatus150 in accordance with some aspects of the disclosure. According to themethod200, thefrequency calibration unit158 detects power up of a unit (e.g., a communication device) that incorporates the apparatus150 (block202). Then, thefrequency calibration unit158 may receive a frequency input word that specifies a frequency or frequency range for the oscillating signal generated by the oscillating circuit160 (block204). In particular applications, as discussed in more detail below, the defined frequency range may be relatively large. That is, the output frequency of theapparatus150 need not be that accurate. For example, the specified frequency range may be as large as one percent of a defined center frequency.
Then, thefrequency calibration unit158 enables theoscillating circuit160 by sending an oscillator enable signal to thecircuits152 and154 to provide the first and second currents to the oscillating circuit160 (block206). Thefrequency calibration unit158 then generates an input frequency tuning word to cause theoscillating circuit160 to generate an oscillating signal that cycles with an initial frequency (block208). Thefrequency calibration unit158 measures the frequency of the oscillating signal from the sampled output of the oscillating circuit160 (block210).
Thefrequency calibration unit158 then determines whether the measured frequency of the oscillating signal is within the defined range (block212). If thefrequency calibration unit158 determines that the measured frequency is above the defined range, thefrequency calibration unit158 decrements the frequency tuning word so as to decrease the frequency of the oscillating signal (block214). If, on the other hand, thefrequency calibration unit158 determines that the measured frequency is below the defined range, thefrequency calibration unit158 increments the input frequency tuning word so as to increase the frequency of the oscillating signal (block216). After performingoperation214 or216, thefrequency calibration unit158 performs another frequency measurement and comparison peroperations210 and212, respectively.
If, inoperation212, thefrequency calibration unit158 determines that the measured frequency of the oscillating signal is within the defined range, thefrequency calibration unit158 stores the frequency tuning word (block218). Thefrequency calibration unit158 then sends a disable oscillator signal to thecircuit152 to cease generating the first current so as to disable the oscillating circuit (block220). Note, that thefrequency calibration unit158 need not send the disable oscillator signal to thecircuit154 because the output steady-state detector156 may have already disabled thecircuit154 after detecting the defined steady-state condition of the oscillating signal.
As previously discussed, thefrequency calibration unit158 may perform a frequency calibration of theoscillating circuit160 when it detects an ambient temperature change that exceeds a defined threshold or when it receives a new frequency input word. In this regard, thefrequency calibration unit158 receives ambient temperature information from the ambient temperature sensor162 (block222). Thefrequency calibration unit158 then determines whether the current ambient temperature has changed from the ambient temperature associated with the previous frequency calibration by a defined threshold (block224). If the frequency calibration determines that the change in the ambient temperature exceeds the threshold, thefrequency calibration unit158 enables the oscillating circuit160 (block228) and performs another calibration routine as specified byoperations210 through220.
If, on the other hand, thefrequency calibration unit158 determines that the change in the ambient temperature does not exceed the threshold, thefrequency calibration unit158 determines whether it has received a new frequency input word (block226). If thefrequency calibration unit158 has not received a new frequency input word, it may return tooperation222 to determine whether the ambient temperature has changed beyond the threshold. If, on the other hand, thefrequency calibration unit158 received a new frequency input word, thefrequency calibration unit158 enables theoscillating circuit160 again (block228) and performs another calibration routine as specified byoperations210 through220. Thefrequency calibration unit158 may proactively test for the ambient temperature change and/or the new frequency input word, or may merely react to it via an interrupt operation.
FIG. 3 illustrates a flow diagram of anexemplary method300 of enabling and disabling theapparatus150 in accordance with some aspects of the disclosure. According to themethod300, theapparatus150 receives an oscillator enable signal from an external device (block302). For example, the external device may be a pulse modulation device that is used to establish a communications channel by use of PDMA or PDM modulation techniques. In this regard, theapparatus150 is turned on for only approximately the duration of a pulse. Thus, the leading edge of the pulse may serve as the oscillator enable signal.
In response to the oscillator enable signal, thecurrent generating circuits152 and154 are activated (blocks304 and306) in any order or simultaneously. The activation of thecircuits152 and154 causes theoscillating circuit160 to begin generating an oscillating signal. As previously discussed, thecircuit154 assists in reducing the time for the oscillating signal to reach a defined steady-state condition. The defined steady-state condition may be based on the stability of the amplitude and/or frequency of the oscillating signal. For example, the defined steady-state condition may specify an amplitude stability of the oscillating signal of not varying more than 15 percent. The defined steady-state condition may also specify a frequency stability of the oscillating signal of not varying more than one (1) percent.
The output steady-state detector156 measures the steady-state condition of the oscillating signal generated by the oscillating circuit160 (block308). The output steady-state detector156 then determines whether the steady-state condition of the oscillating signal meets the requirements of the defined steady-state condition (block310). If the steady-state condition of the oscillating signal does not meet the requirements, the output steady-state detector156 continues to perform theoperations308 and310 until the defined steady-state condition is met. When the output steady-state detector156 determines that the steady-state condition of the oscillating signal meets specification, the output steady-state detector156 disables the circuit154 (block312). In this way, thecircuit154 is only enabled to accelerate the oscillating signal in reaching the defined steady-state condition, thereby conserving energy during steady-state oscillations.
Theapparatus150 may then receive an oscillator disable signal from the external device (block314). As previously discussed, the external device may disable theapparatus150 at the end of a pulse. Accordingly, the oscillator disable signal may be the trailing edge of the pulse. In response to the oscillator disable signal, thecircuit152 is deactivated (block316). One purpose of disabling thecircuit152 is to save power. However, the persistence of oscillation could be used to shut off thecircuit152 early, thereby saving even more power.
FIG. 4 illustrates a schematic diagram of anexemplary apparatus400 for generating an oscillating signal in accordance with some aspects of the disclosure. Theapparatus400 may be a detailed implementation of any of the aspects previously discussed. Theapparatus400 comprises anoscillating circuit412 including aninductor414 coupled in parallel with a switchedcapacitor bank416 and anegative resistance generator418. Theapparatus400 further comprises afrequency calibration circuit410 that is adapted to calibrate the frequency of the oscillating signal generated by theoscillating circuit412. More specifically, thefrequency calibration circuit410 generates a digital frequency word that selects which capacitors of the switchedcapacitor bank416 are coupled in parallel with theinductor414 and thenegative resistance generator418, thereby controlling the frequency of the oscillating signal. Thefrequency calibration circuit410 may include a counter (not shown) to count the periods of the oscillating signal in order to measure its frequency for tuning purposes.
Theapparatus400 further comprises a direct current (DC)power supply410, a first controllablecurrent source404, and a quiescentDC bias circuit402. Thepower supply409 supplies power to the first controllablecurrent source404. In response to receiving an enable signal, the quiescentDC bias circuit402 controls the quiescent bias current that is applied to theoscillating circuit412 by the first controllablecurrent source404. The quiescent bias current is used to start up and maintain theoscillating circuit412 generating the oscillating signal.
Theapparatus400 further comprises aboost bias circuit422, an output steady-state detector420, acontrollable amplifier424, and a second controllablecurrent source408. Thepower supply409 supplies power to the second controllablecurrent source408. In response to receiving the enable signal, theboost bias circuit422 enables generates a boost bias current that is applied to theoscillating circuit412 via thecontrollable amplifier424 and the second controllablecurrent source408. As previously discussed, theboost bias circuit422 assists in reducing the time for the oscillating signal to reach a defined steady-state condition. The output steady-state detector420 is coupled to theoscillating circuit412 to determine the steady-state condition of the oscillating signal. When the output steady-state detector420 determines that the amplitude, frequency or both the amplitude and frequency of the oscillating signal meet a defined specification, the output steady-state detector420 disables thecontrollable amplifier424 so that the boost bias current is no longer applied to theoscillating circuit412.
FIG. 5 illustrates a block diagram of anexemplary communication device500 that uses one or more apparatuses for an oscillating signal as local oscillators (LOs) in accordance with some aspects of the disclosure. Thecommunication device500 comprises a receiver portion including a low noise amplifier (LNA)502, amixer504, a receiver local oscillator (LO)510, abaseband amplifier506, and anenergy detector508. Thecommunication device500 further comprises a transmitter portion including abaseband amplifier528, amixer526, atransmitter LO522, and apower amplifier524. Thecommunication device500 further comprises anantenna512, and aswitch514 to selectively isolate the transmitter portion from the receiver portion during transmission. Additionally, thecommunication device500 comprises abaseband unit520, achannel controller518, and apulse modulator516. Thebaseband unit520 processes baseband signals received from the receiver portion, and processes baseband signals for transmission by the transmitter portion.
Thepulse modulator516 is coupled to thereceiver LO510 to enable the receiver LO at particular instances defined by pulses in order to establish a receiving communication channel (e.g., an ultra-wide band (UWB) communication channel) using pulse division multiple access (PDMA), pulse division multiplexing (PDM), or other type of pulse modulation. Thepulse modulator516 is also coupled to thetransmitter LO520 to enable the transmitter LO at particular instances defined by pulses in order to establish a transmitting communication channel (e.g., an ultra-wide band (UWB) communication channel) using PDMA, PDM, or other type of pulse modulation. The transmitting and receiving channels may be established concurrently, although the channels may be orthogonal so as not to interfere with each other. An ultra-wide band (UWB)) channel may be defined as a channel having a fractional bandwidth on the order of 20% or more, has a bandwidth on the order of 500 MHz or more, or has a fractional bandwidth on the order of 20% or more and has a bandwidth on the order of 500 MHz or more. The fractional bandwidth is a particular bandwidth associated with a device divided by its center frequency. For example, a device according to this disclosure may have a bandwidth of 1.75 GHz with center frequency 8.125 GHz and thus its fractional bandwidth is 1.75/8.125 or 21.5%.
Thechannel controller518 is coupled to thepulse modulator516 in order to establish the receiving and transmitting communication channels by pulse modulation techniques as discussed in more detail below. Thechannel controller518 is coupled to theswitch514 to set the switch to receive mode where it couples theantenna514 to theLNA502 or set the switch to the transmit mode where it couples thepower amplifier524 to theantenna512. If thecommunication device500 is configured as a wireless device, such as an IEEE 802.11 or 802.15 related wireless device, theantenna504 serves as an interface to a wireless medium for wirelessly transmitting and receiving information from other wireless device.
Using pulse modulation techniques to enable and disable the transmitter and receiver, improved power efficiency may be achieved for thecommunication device500. For example, during times when the transmitter is not transmitting and receiver is not receiving, these devices may be operated in low or no power mode to conserve power, such as power provided by a battery. With regard to the transmission of data, for example, data occupying a frequency bandwidth is transmitted during a first time period within the time interval, wherein when the data is transmitted during the first time interval varies such that the variation is associated with at least two time intervals, and power consumption of some components of thecommunication device500 is reduced during at least a second time period within the interval.
FIG. 6A illustrates different channels (channels1 and2) defined with different pulse repetition frequencies (PRF) as an example of a PDMA modulation. Specifically, pulses forchannel1 have a pulse repetition frequency (PRF) corresponding to a pulse-to-pulse delay period602. Conversely, pulses forchannel2 have a pulse repetition frequency (PRF) corresponding to a pulse-to-pulse delay period604. This technique may thus be used to define pseudo-orthogonal channels with a relatively low likelihood of pulse collisions between the two channels. In particular, a low likelihood of pulse collisions may be achieved through the use of a low duty cycle for the pulses. For example, through appropriate selection of the pulse repetition frequencies (PRF), substantially all pulses for a given channel may be transmitted at different times than pulses for any other channel. Thechannel controller518 andpulse position modulator516 may be configured to set up a pulse repetition frequency (PRF) modulation.
The pulse repetition frequency (PRF) defined for a given channel may depend on the data rate or rates supported by that channel. For example, a channel supporting very low data rates (e.g., on the order of a few kilobits per second or Kbps) may employ a corresponding low pulse repetition frequency (PRF). Conversely, a channel supporting relatively high data rates (e.g., on the order of a several megabits per second or Mbps) may employ a correspondingly higher pulse repetition frequency (PRF).
FIG. 6B illustrates different channels (channels1 and2) defined with different pulse positions or offsets as an example of a PDMA modulation. Pulses forchannel1 are generated at a point in time as represented byline606 in accordance with a first pulse offset (e.g., with respect to a given point in time, not shown). Conversely, pulses forchannel2 are generated at a point in time as represented byline608 in accordance with a second pulse offset. Given the pulse offset difference between the pulses (as represented by the arrows610), this technique may be used to reduce the likelihood of pulse collisions between the two channels. Depending on any other signaling parameters that are defined for the channels (e.g., as discussed herein) and the precision of the timing between the devices (e.g., relative clock drift), the use of different pulse offsets may be used to provide orthogonal or pseudo-orthogonal channels. Thechannel controller518 andpulse position modulator516 may be configured to set up a position or offset modulation.
FIG. 6C illustrates different channels (channels1 and2) defined with different timing hopping sequences. For example,pulses612 forchannel1 may be generated at times in accordance with one time hopping sequence whilepulses614 forchannel2 may be generated at times in accordance with another time hopping sequence. Depending on the specific sequences used and the precision of the timing between the devices, this technique may be used to provide orthogonal or pseudo-orthogonal channels. For example, the time hopped pulse positions may not be periodic to reduce the possibility of repeat pulse collisions from neighboring channels. Thechannel controller518 andpulse position modulator516 may be configured to set up a time hopping modulation.
FIG. 6D illustrates different channels defined with different time slots as an example of a PDM modulation. Pulses for channel L1 are generated at particular time instances. Similarly, pulses for channel L2 are generated at other time instances. In the same manner, pulse for channel L3 are generated at still other time instances. Generally, the time instances pertaining to the different channels do not coincide or may be orthogonal to reduce or eliminate interference between the various channels. Thechannel controller518 andpulse position modulator516 may be configured to set up the PDM modulation.
It should be appreciated that other techniques may be used to define channels in accordance with a pulse modulation schemes. For example, a channel may be defined based on different spreading pseudo-random number sequences, or some other suitable parameter or parameters. Moreover, a channel may be defined based on a combination of two or more parameters.
FIG. 7 illustrates a block diagram of various ultra-wide band (UWB) communication devices communicating with each other via various channels in accordance with some aspects of the disclosure. For example,UWB device1702 is communicating withUWB device2704 via twoconcurrent UWB channels1 and2.UWB device702 is communicating withUWB device3706 via asingle channel3. And,UWB device3706 is, in turn, communicating withUWB device4708 via asingle channel4. Other configurations are possible.
Any of these apparatuses described herein may take various forms. For example, in some aspects, the apparatus may be implemented in or comprise a phone (e.g., a cellular phone), a personal data assistant (“PDA”), a headset (e.g., a headphone, en earpiece, etc.), a microphone, a medical device (e.g., a biometric sensor, a heart rate monitor, a pedometer, an EKG device, etc.), a biometric sensor, a heart rate monitor, a pedometer, an EKG device, a user I/O device, a watch, a remote control, a switch, a light switch, a keyboard, a mouse, a tire pressure monitor, an entertainment device (e.g., a music or video device), a computer, a point-of-sale device, a hearing aid, a set-top box, or a device with some form of wireless signaling capabilities. Moreover, these apparatuses may have different power and data requirements. In some aspects, any apparatus described herein may be adapted for use in low power applications (e.g., through the use of a pulse-based signaling scheme and low duty cycle modes), and may support a variety of data rates including relatively high data rates (e.g., through the use of high-bandwidth pulses). In some aspects, any of the apparatuses described herein may be implemented in or comprise an access point such as a Wi-Fi node. For example, such an apparatus may provide connectivity to another network (e.g., a wide area network such as the Internet) via a wired or wireless communication link.
Any of these apparatuses may include various components that perform functions bases on signals transmitted or received via the wireless communication link. For example, a headset may include a transducer adapted to provide an audible output based on a signal received via the wireless communication link established by a receiver responsive to a local oscillator incorporating any of the aspects described herein. A watch may include a display adapted to provide a visual output based on a signal received via the wireless communication link by a receiver responsive to a local oscillator incorporating any of the aspects described herein. A medical device may include a sensor adapted to generate at least sensed signal or sensed data to be transmitted via the wireless communication link by a transmitter responsive to a local oscillator incorporating any of the aspects described herein.
Various aspects of the disclosure have been described above. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein is merely representative. Based on the teachings herein one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein. As an example of some of the above concepts, in some aspects concurrent channels may be established based on pulse repetition frequencies. In some aspects concurrent channels may be established based on pulse position or offsets. In some aspects concurrent channels may be established based on time hopping sequences. In some aspects concurrent channels may be established based on pulse repetition frequencies, pulse positions or offsets, and time hopping sequences.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, processors, means, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two, which may be designed using source coding or some other techniques), various forms of program or design code incorporating instructions (which may be referred to herein, for convenience, as “software” or a “software module”), or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented within or performed by an integrated circuit (“IC”) The IC may comprise a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, electrical components, optical components, mechanical components, or any combination thereof designed to perform the functions described herein, and may execute codes or instructions that reside within the IC, outside of the IC, or both. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
It is understood that any specific order or hierarchy of steps in any disclosed process is an example of a sample approach. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The steps of a method or algorithm described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module (e.g., including executable instructions and related data) and other data may reside in a data memory such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable storage medium known in the art. A sample storage medium may be coupled to a machine such as, for example, a computer/processor (which may be referred to herein, for convenience, as a “processor”) such the processor can read information (e.g., code) from and write information to the storage medium. A sample storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in user equipment. In the alternative, the processor and the storage medium may reside as discrete components in user equipment. Moreover, in some aspects any suitable computer-program product may comprise a computer-readable medium comprising codes relating to one or more of the aspects of the disclosure. In some aspects a computer program product may comprise packaging materials.
While the invention has been described in connection with various aspects, it will be understood that the invention is capable of further modifications. This application is intended to cover any variations, uses or adaptation of the invention following, in general, the principles of the invention, and including such departures from the present disclosure as come within the known and customary practice within the art to which the invention pertains.