US20080211077A1 - Low profile chip scale stacking system and method - Google Patents

Abstract

The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material.

Description

RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 10/873,847, filed Jun. 22, 2004, pending, which is a continuation-in-part of U.S. patent application Ser. No. 10/631,886, filed Jul. 11, 2003, now U.S. Pat. No. 7,026,708, issued Apr. 11, 2006, which is a continuation-in-part of U.S. patent application Ser. No. 10/453,398, filed Jun. 3, 2003, now U.S. Pat. No. 6,914,324 B2, issued Jul. 5, 2005, which is a continuation-in-part of U.S. patent application Ser. No. 10/005,581, filed Oct. 26, 2001, now U.S. Pat. No. 6,576,992 B2, issued Jun. 10, 2003.
• U.S. patent application Ser. No. 10/631,886, filed Jul. 11, 2003, now U.S. Pat. No. 7,026,708, issued Apr. 11, 2006, also is a continuation-in-part of U.S. patent application Ser. No. 10/457,608 filed Jun. 9, 2003, pending, which is a continuation-in-part of U.S. patent application Ser. No. 10/005,581, filed Oct. 26, 2001, now U.S. Pat. No. 6,576,992 B2, issued Jun. 10, 2003.
TECHNICAL FIELD
• The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages and mounting such devices on substrates.
BACKGROUND
• Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages known as chip scale packaging or “CSP” have recently gained market share.
• CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically are located along the planar bottom surface of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking. Not only is peripheral dimension an important consideration, but so too is profile height, particularly when CSPs are stacked. Additionally, methods to provide reliable strategies for mounting stacked devices are valuable in stacking.
• What is needed, therefore, is a technique and system for stacking CSPs that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods.
SUMMARY
• Provided is a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or the contacts of the packaged device. The integrated circuit device is positioned to contact the contacts of the substrate with the higher temperature solder alloy paste between. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments. Typically, the created joints are low in profile. In a method in accordance with the present invention, a first solder used to construct a stacked module has a higher melting point than a second solder used to populate a board with that module.
• Preferred embodiments may also employ low profile contact structures to provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts that may be employed. A consolidated low profile contact structure and technique is provided for use in alternative embodiments.
• Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers with preferred embodiments having two conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 depicts a typical prior art packaged integrated circuit device.
• FIG. 2 depicts the device ofFIG. 1 from which the solder ball contacts have been removed.
• FIG. 3 depicts a set of substrate contacts upon which a high temperature solder paste has been applied in accordance with a preferred embodiment of the present invention.
• FIG. 4 depicts portions of two flexible circuit connectors prepared for mounting of an integrated circuit device in accordance with a preferred embodiment of the present invention.
• FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention.
• FIG. 6 depicts a two-high integrated circuit module mounted to the two flexible circuit connectors depicted inFIG. 4 in accordance with a preferred embodiment of the present invention.
• FIG. 7 depicts a four-high stacked module devised in accordance with a preferred embodiment of the present invention.
• FIG. 8 is an elevation view of a high-density circuit module devised in accordance with a preferred four-high embodiment of the present invention.
• FIG. 9 is an elevation view of a stacked high-density circuit module devised in accordance with a preferred two-high embodiment of the present invention.
• FIG. 10 depicts, in enlarged view, the area marked “A” inFIG. 9 in a preferred embodiment of the present invention.
• FIG. 11 depicts, in enlarged view, one alternative construction for of the area marked “A” inFIG. 9.
• FIG. 12 depicts in enlarged view, the area marked “B” inFIG. 9 in a preferred embodiment of the present invention.
• FIG. 13 depicts, in enlarged view, a portion of a flex circuitry employed with the structure ofFIG. 11 in an alternative preferred embodiment of the present invention.
• FIG. 14 is an elevation view of a portion of an alternative construction step in an alternative embodiment of the present invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
• The methods and systems disclosed herein are used with CSP packages of a variety of types and configurations such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art. It may also be used with those CSP-like packages that exhibit bare die connectives on one major surface. Thus, the term CSP should be broadly considered in the context of this application. The methods and systems disclosed may be employed to advantage in the wide range of CSP configurations available in the art where an array of connective elements is available from at least one major surface. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation views of the Figs. are depicted with CSPs of a particular profile known to those in the art, but it should be understood that the figures are exemplary only. The invention is advantageously employed with CSPs that contain memory circuits, but may be employed to advantage with logic and computing circuits where added capacity without commensurate PWB or other board surface area consumption is desired.
• FIG. 1 depicts an exemplarintegrated circuit device18 havingupper surface20 andlower surface22.Device18 is an example of one type of the general class of devices commonly known in the art as chip-scale-packaged integrated circuits (“CSPs”). The present invention may employed with a wide variety of integrated circuit devices and is not, as those of skill in the art will understand, limited to devices having the profile depicted inFIG. 1. Further, although its preferred use is with plastic-bodied CSP devices, the invention provides advantages in mounting a variety of packaged integrated circuit devices in a wide variety of configurations including leaded and CSP topologies.
• Exemplar integrated circuit device (CSP)18 may include one or more integrated circuit die andbody27 and a set ofcontacts28. The illustratedCSP18 hasCSP ball contacts28 arrayed alongsurface22 of itsbody27. Typically, inCSP18,CSP ball contacts28 are, as depicted, balls that are a mixture of tin and lead with a common relative composition of 63% tin and 37% lead. Such contacts typically have a melting point of about 183° C. Other contacts are sometimes found along a planar surface of integrated circuit devices and such other contacts may also be treated in accordance with the present invention where the opportunity arises as will be understood after gaining familiarity with the present disclosure.
• In the depiction ofFIG. 2,CSP ball contacts28 have been removed, leavingCSP pads29 arrayed alonglower surface22.CSP pads29 will typically exhibit a residual thin layer of tin/lead mixture after removal ofCSP ball contacts28. As those of skill will know, CSPs may be received without attached balls and the process and structures described herein will then not require “removal” of balls. Further, embodiments of the present invention may be implemented with CSPs already bearing ball contacts comprised of high temperature solders.
• FIG. 3 depictsexemplar substrate23 on which are disposedcontacts25.Substrate23 is depicted as a rigid board such as a PWB or PCB such as are known in the art. In accordance with a preferred embodiment of the present invention, asolder paste27 is applied tosubstrate contacts25. In accordance with an alternative preferred embodiment of the invention,solder paste27 is applied to theCSP pads29 and not thesubstrate contacts25. However, as those of skill will recognize,solder paste27 may applied to both or eithersubstrate contacts25 and CSP pads29 (or a set of contacts of other configuration when devices that are not CSP are used in accordance with the invention.) As those of skill understand, solder paste is a mixture of solder particles and flux.
• Two or more of the elements lead, tin, silver, copper, antimony or indium may be employed in a variety of combinations to devise a solder to be employed insolder paste27 in accordance with the present invention. Therefore, in accordance with preferred embodiments of the present invention, a solder alloy employed insolder paste27 exhibits a melting point equal to or greater than 235° C. and, preferably between 235° C. and 312° C. The alloy chosen should not have a melting point so high that the IC package is adversely affected, but it should also not be so low as to remelt during board assembly operations.
• Some market participants are starting to implement lead-free solders. Such lead-free solders will typically have melting points higher than those found in lead inclusive solders. Typically, those who use lead-free solders to populate boards with stacked modules will, for example, employ temperatures up to 240° C. in the process of attachment of stacked modules to boards. Consequently, a HT joint implemented with a lead-free alloy will, in conformity with preferred embodiments of the present invention, exhibit a melting point greater than those lead-free solders used to populate boards. Consequently, a preferred implementation of the HT joints of the present invention will have a melting point range of between 245° C. and 265° C. The lead-free solder alloy employed in such HT joints will be comprised of at least two of the following elements: tin, silver, copper, or indium.
• Preferably, an alloy used as a solder in the present invention will melt over a narrow temperature range. Disintegration of the module during board attachment or population will be less likely if the melt range is narrow. Most preferably, the top of the melting point range of the solder used in board attachment should be exceeded by 15° C. by the melting point of the solder used to manufacture the stacked module although in the case of lead-free solders, this is reduced to ameliorate issues that could arise from exposure of the package to high temperatures.
• The following combinations have been found to exhibit the following melting points, and the below recited combinations are merely a representative, but not exhaustive, list of examples of solder alloys appropriate for use in the present invention. As those of skill will recognize, these examples are instructive in selecting other preferred particular combinations of lead, tin, silver, copper, antimony, and indium that are readily employed to advantage in the present invention so as to arrive at alloys of at least two of the following solder elements: lead, tin, silver, copper, antimony, and indium that have in their combined mixture, a preferred melting point between 235° C. to 312° C. inclusive.
• A combination of 95% Sn and 5% Sb melts over a range of 235° C. to 240° C.
• A combination of 83% Pb and 10% Sb and 5% Sn and 2% Ag melts over a range of 237° C. to 247° C.
• A combination of 85% Pb and 10% Sb and 5% Sn melts over a range of 245° C. to 255° C.
• A combination of 90% Pb and 10% Sb melts over a range of 252° C. to 260° C.
• A combination of 92.5% Pb, 5% Sn and 2.5% Ag melts over a range of 287° C. to 296° C.
• A combination of 90% Pb and 10% Sn melts over a range of 275° C. to 302° C.
• A combination of 95% Pb and 5% Sn melts over a range of 308° C. to 312° C.
• A combination of 75% Pb and 25% Indium melts over a range of 240° C. to 260° C.
• Those of skill will note that solder alloys or mixtures may also be employed in embodiments of the present invention that exhibit melting points lower than 235° C., as would be exhibited for example with a 97% Sn and a 3% Sb alloy, but preferred embodiments will employ solder mixtures or alloys that melt between 235° C. and 312° C. inclusive.
• FIG. 4 depicts portions of flex circuitry comprised of twoflexible circuit connectors30 and32 prepared for mounting of adevice10 in accordance with a preferred embodiment of the present invention.Exemplar flex circuits30 and32 may be simple flex circuitry or may exhibit the more sophisticated designs of flex circuitry such as those that are later described herein. For clarity of exposition, depictedflex circuits30 and32 exhibit a singleconductive layer64 and a firstouter layer50.Conductive layer64 is supported bysubstrate layer56, which, in a preferred embodiment, is a polyimide.Outer layer52 resides along the lower surface of theflex circuits30 and32. Optionalouter layers50 and52, when present, are typically a covercoat or solder mask material.Windows35 are created throughouter layer52 andintermediate layer56 to exposeflex contacts44.
• As depicted inFIG. 4,solder paste27 is applied to flexcontacts36 which are demarked at the level ofconductive layer64.Solder paste27 may also alternatively or in addition, be applied to theCSP pads29 of a CSP.Windows35 provide openings through which module contacts may be disposed in a later stacked module assembly step. Those of skill will recognize that the method of the present invention is applicable to a wide variety of substrates including solid PWB's, rigid flex, and flexible substrates such as flexible circuits, for example, and the substrate employed can be prepared in accordance with the present invention in a manner appropriate for the intended application. Where the invention is employed with rigid substrates such as a PWB, multilayer strategies and windowing in substrate layers are techniques which are useful in conjunction with the present invention, but not essential.
• FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention as may be employed in the construction of a low profile stacked module. The features depicted inFIG. 5 are not drawn to scale, and show various features in an enlarged aspect for purposes of illustration. As shown,CSP18 is disposed uponflex circuits30 and32 which have been, in a preferred embodiment of the method of the present invention, previously prepared as shown in earlierFIG. 4.Module contacts38 have been appended to flexcircuits30 and32 to provide connective facility for the device-flex combination whether as part of a stacked module or otherwise.
• High temperature joint contacts39 (“HT joints”) are formed by the melting of the lead alloy in previously appliedsolder paste27 and the application of a selected heat range appropriate for the solder mixtures identified previously. Thus, HT joints39 will, after solidification, typically not re-melt unless exposed subsequently to such temperature ranges. The temperature range applied in this step of assembly will not typically be subsequently encountered in a later assembly operation such as, for example, the application of a stacked module to a DIMM board. Consequently, in one embodiment, the present invention is articulated as a stacked module having HT joints that is appended to a DIMM board with traditional lower melting point solder.
• FIG. 6 depicts a two-high stacked module devised in accordance with a preferred embodiment of the present invention.Stacked module10 shown inFIG. 6 includeslower CSP18 andupper CSP16. A stackedmodule10 may be devised in accordance with the present invention that includes more than two CSPs.Flex circuits30 and32 are depicted connectinglower CSP18 andupper CSP16. Those of skill will also recognize thatmodule10 may be implemented with a single flexible circuit connector. Further, the flexible circuit connectors employed in accordance with the invention may exhibit one or more conductive layers.Flex circuits30 and32 may be any circuit connector structure that provides connective facility between two integrated circuits having a contact array. Those of skill will note thatflexible circuits30 and32 may exhibit single conductive layers (such as, for example, the flexible circuit connectors earlier illustrated herein inFIG. 5) or may exhibit multiple conductive layers such as those shown in the present figures, for example. Those of skill will readily appreciate how a variety of circuit structures may be employed in preferred embodiments. Further, the connective structures used to connect lowerintegrated circuit18 with upperintegrated circuit16 need not literally be flexible circuit connectors but may be flexible in portions and rigid in other portions.
• HT contacts39 are employed in the preferred embodiment ofFIG. 6 to provide connective facility between the respective integrated circuits and contacts borne by theflex circuits30 and32. Preferably, HT joints39 will exhibit a height dimension smaller than that ofCSP ball contacts28 shown earlier as part of typical CSPs inFIG. 1. As those of skill will recognize, HT joints39 are depicted in a scale that is enlarged relative to joint sizes that would typically be encountered in actual practice of preferred modes of the invention. Thus,module10 will preferably present a lower profile than stacked modules created employingtypical CSP contacts28 on each of the constituent integrated circuit packages employed in a stackedmodule10.
• FIG. 7 depictsmodule10 as lower (or level one)CSP18, upper (or level two)CSP16, 3^rd(or level three)CSP14, and 4^th(or level four)CSP12. When the present invention is employed between flex circuits in stacking multiple levels of CSPs, as for example inFIG. 7, some embodiments will present HT contacts that have minimal heights that do not cause appreciable separation between the flex circuitry associated withCSP18 andCSP16, for example, or betweenCSP16 andCSP14, for example. For such embodiments, the apparent height for illustrated HT joints39, particularly, that lie between respective layers of flex circuitry will be understood to be exaggerated in the depiction ofFIG. 7. Three sets of flex circuitry pairs30 and32 are also shown but, as in other embodiments, the invention may be implemented with a variety of substrates including single flex circuits in place of the depicted pair and with flexible circuits that have one or plural conductive layers.
• As shown, the HT joints provide connections between integrated circuit devices and substrates and the overall profile ofmodule10 is reduced by use of the present invention that provides advantages in subsequent processing steps such as, for example, affixation ofmodule10 to DIMM boards, for example.
• To construct a stacked module in accordance with a preferred embodiment of the present invention, if present,ball contacts28 are removed from a CSP leavingCSP contacts29 that typically exhibit a residual layer of solder. A high temperature solder paste composed from a lead alloy or mixture that has a preferable melting point equal to or higher than 235° C. and preferably less than 312° C. is applied tosubstrate contacts25 of a substrate such as a flexible circuit and/or the substrate contacts to which it is to be mounted. The CSP is positioned to place theCSP pads29 andsubstrate contacts25 in appropriate proximity. Heat is applied sufficient to melt the lead solder alloy ofsolder paste27 thus forming HT joints39. The flexible circuit is positioned to place portions of the flexible circuit connector between the first CSP and a second CSP that is connected to the substrate with HT joints created using the process described for creating HT joints.
• In understanding the present invention, it may be helpful to articulate the relative melting points in terms of variables to illustrate the relationships between the HT joints used to construct a stacked module and the solders used to populate a board with such a HT joint-implemented stacked module. In use in board population, the present invention will provide a stacked high module that is assembled using the HT joints that exhibit melting point ranges between X and Y degrees where X is less than Y. Attachment of the stacked module to a board is then implemented with a solder having a melting point between A and B degrees where A and B are less than X.
• FIG. 8 is an elevation view ofmodule10 devised in accordance with a preferred embodiment of the present invention.Exemplar module10 is comprised of four CSPs: level fourCSP12, level threeCSP14, level twoCSP16, and level oneCSP18. Each of the depicted CSPs has anupper surface20 and alower surface22 and opposite lateral sides oredges24 and26 and include at least one integrated circuit surrounded by abody27.
• Shown inFIG. 8 arelow profile contacts28 alonglower surfaces22 of the illustratedconstituent CSPs12,14,16, and18.Low profile contacts28 provide connection to the integrated circuit or circuits within the respective packages.
• CSPs often exhibit an array of balls alonglower surface22. Such ball contacts are typically solder ball-like structures appended to contact pads arrayed alonglower surface22. In many preferred embodiments of the present invention, CSPs that exhibit balls alonglower surface22 are processed to strip the balls fromlower surface22 or, alternatively, CSPs that do not have ball contacts or other contacts of appreciable height are employed. Only as a further example of the variety of contacts that may be employed in alternative preferred embodiments of the present invention, an embodiment is later disclosed inFIG. 11 and the accompanying text that is constructed using a CSP that exhibits ball contacts alonglower surface22. The ball contacts are then reflowed to create what will be called a consolidated contact.
• Embodiments of the invention may also be devised that employ both standard ball contacts and low profile contacts or consolidated contacts. For example, in the place of low profileinter-flex contacts42 or, in the place oflow profile contacts28, or in various combinations of those structures, standard ball contacts may be employed at some levels ofmodule10, while low profile contacts and/or low profile inter-flex contacts or consolidated contacts are used at other levels.
• A typical eutectic ball found on a typical CSP memory device is approximately 15 mils in height. After solder reflow, such a ball contact will typically have a height of about 10 mils. In preferred modes of the present invention,low profile contacts28 and/or low profileinter-flex contacts42 have a height of approximately 7 mils or less and, more preferably, less than 5 mils.
• Where present, the contact sites of a CSP that are typically found under or within the ball contacts typically provided on a CSP, participate in the creation oflow profile contacts28. One set of methods by which high-temperature types oflow profile contacts28 suitable for use in embodiments of the present invention have been disclosed herein. In other embodiments, more typical solders, in paste form for example, may be applied either to the exposed contact sites or pads alonglower surface22 of a CSP and/or to the appropriate flex contact sites of the designated flex circuit to be employed with that CSP.
• InFIG. 8, iterations of flex circuits (“flex”, “flex circuits,” “flexible circuit structures,” “flexible circuitry”)30 and32 are shown connecting various constituent CSPs. Any flexible or conformable substrate with an internal layer connectivity capability may be used as a preferable flex circuit in the invention. The entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in certain areas to allow conformability around CSPs and rigid in other areas for planarity along CSP surfaces may be employed as an alternative flex circuit in the present invention. For example, structures known as rigid-flex may be employed.
• Form standard34 is shown disposed adjacent toupper surface20 of each of the CSPs below level fourCSP12. Form standard34 may be fixed toupper surface20 of the respective CSP with an adhesive36 which preferably is thermally conductive. Form standard34 may also, in alternative embodiments, merely lay onupper surface20 or be separated fromupper surface20 by an air gap or medium such as a thermal slug or non-thermal layer.
• In other embodiments, a heat spreader may act as a heat transference media and reside between the flex circuitry and thepackage body27 or may be used in place ofform standard34. Such a heat spreader is shown inFIG. 14 as an example and is identified byreference numeral37. In still other embodiments, there will be noheat spreader37 or form standard34 and the embodiment may use the flex circuitry as a heat transference material.
• With continuing reference toFIG. 8, form standard34 is, in a preferred embodiment, devised from copper to create, as shown in the depicted preferred embodiment ofFIG. 8, a mandrel that mitigates thermal accumulation while providing a standard-sized form about which flex circuitry is disposed. Form standard34 may take other shapes and forms such as, for example, an angular “cap” that rests upon the respective CSP body. Form standard34 also need not be thermally enhancing although such attributes are preferable. Theform standard34 allowsmodules10 to be devised with CSPs of varying sizes, while articulating a single set of connective structures useable with the varying sizes of CSPs. Thus, a single set of connective structures such asflex circuits30 and32 (or a single flexible circuit in the mode where a single flex is used in place of theflex circuit pair30 and32) may be devised and used with the form standard34 method and/or systems disclosed herein to create stacked modules from CSPs having different sized packages. This will allow the same flexible circuitry set design to be employed to create iterations of a stackedmodule10 from constituent CSPs having a first arbitrary dimension X across attribute Y (where Y may be, for example, package width), as well asmodules10 from constituent CSPs having a second arbitrary dimension X prime across that same attribute Y. Thus, CSPs of different sizes may be stacked intomodules10 with the same set of connective structures (i.e. flex circuitry). In a preferred embodiment, form standard34 will present a lateral extent broader than the upper major surface of the CSP over which it is disposed. Thus, the CSPs from one manufacturer may be aggregated into astacked module10 with the same flex circuitry used to aggregate CSPs from another manufacturer into a differentstacked module10 despite the CSPs from the two different manufacturers having different dimensions.
• Further, as those of skill will recognize, mixed sizes of CSPs may be implemented into thesame module10, such as would be useful to implement embodiments of a system-on-a-stack.
• Preferably, portions offlex circuits30 and32 are fixed to form standard34 by adhesive35 which is preferably a tape adhesive, but may be a liquid adhesive or may be placed in discrete locations across the package. Preferably, adhesive35 is thermally conductive.
• In a preferred embodiment,flex circuits30 and32 are multi-layer flexible circuit structures that have at least two conductive layers examples of which are described herein. Other embodiments may, however, employ flex circuitry, either as one circuit or two flex circuits to connect a pair of CSPs, that have only a single conductive layer, examples of which are also shown herein.
• Preferably, the conductive layers employed in flex circuitry ofmodule10 are metal such as alloy110. The use of plural conductive layers provides advantages and the creation of a distributed capacitance acrossmodule10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize.
• Module10 ofFIG. 8 hasplural module contacts38 collectively identified asmodule array40. Connections between flex circuits are shown as being implemented with low profileinter-flex contacts42 which are, in preferred embodiments, low profile contacts comprised of solder-combined with pads and/or rings such as theflex contacts44 shown inFIG. 10 orflex contacts44 with orifices as shown inFIG. 11 being just examples.
• Form standard34, as employed in one preferred embodiment, is approximately 5 mils in thickness, whileflex circuits30 and32 are typically thinner than 5 mils. Thus, the depiction ofFIG. 8 is not to scale.
• FIG. 9 illustrates an exemplar two-high module10 devised in accordance with a preferred embodiment of the present invention. The depiction ofFIG. 9 identifies two areas “A” and “B”, respectively, that are shown in greater detail in later figures. In laterFIGS. 10 and 11, there are shown details of two alternative embodiments for the area marked “A” inFIG. 9. It should be understood that many different connection alternatives are available and within the scope of the invention.FIG. 12 depicts details of the area marked “B” inFIG. 9.
• FIG. 10 depicts, in enlarged view, one alternative for structures that may be used in the area marked “A” inFIG. 9.FIG. 10 depicts an example preferred connection between an examplelow profile contact28 andmodule contact38 throughflex contact44 offlex32 to illustrate a solid metal path from level oneCSP18 tomodule contact38 and, therefore, to an application PWB or memory expansion board to whichmodule10 is connectable.
• Flex32 is shown inFIG. 10 to be comprised of multiple conductive layers. This is merely an exemplar flexible circuitry that may be employed with the present invention. A single conductive layer and other variations on the flexible circuitry may, as those of skill will recognize, be employed to advantage in alternative embodiments of the present invention.
• Flex32 has a firstouter surface50 and a secondouter surface52.Preferred flex circuit32 has at least two conductive layers interior to first and secondouter surfaces50 and52. There may be more than two conductive layers inflex30 andflex32 and other types of flex circuitry may employ only one conductive layer. In the depicted preferred embodiment, firstconductive layer54 and secondconductive layer58 are interior to first and secondouter surfaces50 and52.Intermediate layer56 lies between firstconductive layer54 and secondconductive layer58. There may be more than one intermediate layer, but one intermediate layer of polyimide is preferred. The designation “F” as shown inFIG. 10 notes the thickness “F” offlex circuit32 which, in preferred embodiment, is approximately 3 mils. Thinner flex circuits may be employed, particularly where only one conductive layer is employed, and flex circuits thicker than 3 mils may also be employed, with commensurate addition to the overall height ofmodule10.
• As depicted inFIG. 10, anexample flex contact44 is comprised from metal at the level of secondconductive layer58 interior to secondouter surface52.
• FIG. 11 depicts an alternative structure for the connection in the area marked “A” inFIG. 9. In the depiction ofFIG. 11, aflex contact44 is penetrated byorifice59 which has a median opening of dimension “DO” indicated by the arrow inFIG. 11.Demarcation gap63 is shown inFIG. 11. This gap may be employed to separate or demarcate flex contacts such asflex contact44 from its respective conductive layer. Also shown inFIG. 11 is an optional adhesive or conformedmaterial51 betweenflex circuit32 andCSP18.
• The consolidated contact61 shown inFIG. 11 provides connection toCSP18 and passes throughorifice59. Consolidated contact61 may be understood to have twoportions61A that may be identified as an “inner” flex portion and,61B that may be identified as an “outer” flex portion, the inner and outer flex portions of consolidated contact61 being delineated by the orifice. Theouter flex portion61B of consolidated contact61 has a median lateral extent identified inFIG. 11 as “DCC” which is greater than the median opening “DO” oforifice59. The depicted consolidated contact61 is preferably created in a preferred embodiment, by providing a CSP with ball contacts. Those ball contacts are placed adjacent to flexcontacts44 that haveorifices59. Heat sufficient to melt the ball contacts is applied. This causes the ball contacts to melt and reflow in part through therespective orifices59 to create emergent from the orifices,outer flex portion61B, leavinginner flex portion61A nearer tolower surface22 ofCSP18.
• Thus, in the depicted embodiment,module10 is constructed with a level oneCSP18 that exhibits balls as contacts, but those ball contacts are re-melted during the construction ofmodule10 to allow the solder constituting the ball to pass throughorifice59 of therespective flex contact44 to create a consolidated contact61 that serves to connectCSP18 andflex circuitry32, yet preserve a low profile aspect tomodule10 while providing a contact formodule10. Those of skill will recognize that this alternative connection strategy may be employed with any one or more of the CSPs ofmodule10.
• As those skilled will note, a consolidated contact61 may be employed to take the place of alow profile contact28 andmodule contact38 in the alternative embodiments. Further, either alternatively, or in addition, a consolidated contact61 may also be employed in the place of alow profile contact28 and/or aninter-flex contact42 in alternative embodiments where the conductive layer design of the flex circuitry will allow the penetration of the flex circuitry implicated by the strategy.
• FIG. 12 depicts the area marked “B” inFIG. 9. The depiction ofFIG. 12 includes approximations of certain dimensions of several elements in a preferred embodiment ofmodule10. It must be understood that these are just examples relevant to some preferred embodiments, and those of skill will immediately recognize that the invention may be implemented with variations on these dimensions and with and without all the elements shown inFIG. 12.
• There are a variety of methods of creatinglow profile contacts28. One method that is effective is the screen application of solder paste to the exposed CSP contact pad areas of the CSP and/or to the contact sites of the flex circuitry. For screened solder paste, the reflowed joint height ofcontact28 will typically be between 0.002″ and 0.006″ (2 to 6 mils). The stencil design, the amount of solder remaining on ‘ball-removed’ CSPs, and flex planarity will be factors that could have a significant effect on this value.Low profile contact28 has a height “C” which, in a preferred embodiment, is between 2 and 7 mils.Flex circuitry32, with one or two or more conductive layers, has a thickness “F” of about 4 mils or less in a preferred embodiment.Adhesive layer35 has a thickness “A1” of between 1 and 1.5 mils in a preferred embodiment. Form standard34 has a thickness “FS” of between 4 and 6 mils in a preferred embodiment and,adhesive layer36 has a thickness “A2” of between 1 and 2 mils. Thus, the total distance betweenlower surface22 ofCSP16 andupper surface20 ofCSP18 passing through one oflow profile contacts28 ofCSP16 is approximated by formula 1:
• 
  (C+F+A1+FS+A2)−distancelow profile contact 28 penetrates intoflex 32.  (1)
• In practice, this should be approximately between 9 and 20 mils in a preferred embodiment. A similar calculation can be applied to identify the preferred distances between, for example,CSP14 andCSP16 in a four-high module10. In such cases, the height ofinter-flex contact42 and thickness of another layer offlex circuit32 will be added to the sum to result in a preferred range of between 13 and 31 mils. It should be noted that in some embodiments, not all of these elements will be present, and in others, added elements will be found. For example, some of the adhesives may be deleted, and form standard34 may be replaced or added to with aheat spreader37 and, in still other versions, neither a form standard34 nor aheat spreader37 will be found. As an example, where there is no use of aheat spreader37 or form standard34, the distance betweenlower surface22 ofCSP16 andupper surface20 ofCSP18 in a two-element module10 will be preferably between 4.5 and 12.5 mils and more preferably less than 11 mils. It is often desirable, but not required, to createlow profile contacts28 and low profileinter-flex contacts42 using HT joints as previously described.
• FIG. 13 depicts a plan view of a contact structure inflex32 that may be employed to implement the consolidated contact61 shown earlier inFIG. 11. Shown inFIG. 13 are twoexemplar flex contacts44 that each have anorifice59. It may be considered thatflex contacts44 extend further than the part visible in this view as represented by the dotted lines that extend intotraces45. The part offlex contact44 visible in this view is to be understood as being seen through windows in other layers offlex32 as previously described, depending upon whether the flex contact is articulated at a first conductive layer or, if it is present inflex32, a second conductive layer and intermediate layer and whether the flex contact is for connection to the lower one of two CSPs or the upper one of two CSPs in amodule10.
• FIG. 14 depicts a flexible circuit connective set offlex circuits30 and32 that has a singleconductive layer64. It should be understood with reference toFIG. 13, thatflex circuits30 and32 extend laterally further than shown and have portions which are, in the construction ofmodule10, brought about and disposed above the present,heat spreader37, a form standard34 (not shown), and/orupper surface20 ofCSP18. In this single conductive layer flex embodiment ofmodule10, there are shown first and secondouter layers50 and52 andintermediate layer56.
• Heat spreader37 is shown attached to thebody27 offirst level CSP18 throughadhesive36. In some embodiments, aheat spreader37 or a form standard34 may also be positioned to directly contactbody27 of the respective CSP.
• Heat transference from module can be improved with use of a form standard34 or aheat spreader37 comprised of heat transference material such as a metal and preferably, copper or a copper compound or alloy, to provide a significant sink for thermal energy. Although the flex circuitry operates as a heat transference material, such thermal enhancement ofmodule10 particularly presents opportunities for improvement of thermal performance where larger numbers of CSPs are aggregated in a single stackedmodule10.
• Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.

Claims (19)

1. A method of devising a high-density circuit module comprising the steps of:

providing a first-level CSP having contact sites along a major surface, an upper surface and a lower surface, and opposing lateral sides defining a lateral extent of the first-level CSP;

providing a second-level CSP having contact sites along a major surface;

providing flex circuitry comprising at least one flex circuit having first and second conductive layers, an intermediate layer between the first and second conductive layers, an outer set of plural flex contacts, and an inner set of plural flex contacts;

disposing high-temperature solder paste on the contact sites of the first-level CSP;

applying heat sufficient to connect selected contact sites of the first-level CSP to select ones of the inner set of plural flex contacts to form a reflowed contact having a height between 2 and 6 mils;

disposing high-temperature solder paste on the CSP contact sites of the second-level CSP;

applying heat sufficient to connect select ones of the second-level CSP contact sites to select ones of the outer set of plural flex contacts to form a reflowed contact having a height between 2 and 6 mils; and

wrapping the flex circuitry partially about at least one of the opposing lateral sides of the first-level CSP such that the outer set of plural flex contacts are disposed above the upper surface of the first-level CSP and the inner set of plural flex contacts are disposed below the lower surface of the first-level CSP, the first conductive layer being closer to the first-level CSP than is the second conductive layer subsequent to the step of wrapping the flex circuitry.

2. The method ofclaim 1 in which selected ones of the inner and outer sets of plural flex contacts are at the second conductive layer.

3. The method ofclaim 1 in which selected ones of the inner and outer sets of plural flex contacts are at the first conductive layer.

4. The method ofclaim 1 in which in which the inner and outer sets of plural flex contacts for connection of the second-level and first-level CSPs, respectively, are exhibited at a conductive layer of the flex circuitry.

5. A method of devising a high-density circuit module comprising the steps of:

providing a first-level CSP having a top major surface and a bottom major surface and contact sites along the bottom major surface;

providing a second-level CSP having contact sites along a major surface;

providing flex circuitry comprising at least one flex circuit having first and second conductive layers, an intermediate layer between the first and second conductive layers, an outer set of plural flex contacts, an inner set of plural flex contacts, and a thickness of about 4 mils or less;

disposing high-temperature solder paste on the first-level CSP contact sites;

applying heat sufficient to connect selected contact sites of the first-level CSP to select ones of the inner set of plural flex contacts to form a reflowed contact having a height between 2 and 6 mils;

disposing high-temperature solder paste on the contact sites of the second-level CSP;

applying heat sufficient to connect selected contact sites of the second-level CSP to select ones of the outer set of plural flex contacts; and

wrapping the flex circuitry partially about the first-level CSP such that the first conductive layer is closer to the first-level CSP than is the second conductive layer subsequent to the step of wrapping the flex circuitry.

6. A method of devising a high-density circuit module comprising the steps of:

providing a first CSP having a lateral extent defined by opposing lateral sides, and having a plurality of ball contacts disposed along a major surface;

providing flex circuitry comprising at least one flex circuit having first and second conductive layers, an intermediate layer between the first and second conductive layers, and a plurality of selected flex contacts each penetrated by an orifice;

disposing the first CSP proximal to the flex circuitry to place the plurality of ball contacts adjacent to the plurality of flex contacts;

applying heat sufficient to melt the plurality of ball contacts such that the ball contacts melt and reflow partially through respective ones of the orifices to present outer contact surfaces;

attaching a second CSP to the flex circuitry; and

wrapping the flex circuitry partially about the first-level CSP such that after the attaching and wrapping steps the second CSP is in a stacked disposition above the first CSP with the first conductive layer being closer to the first CSP than is the second conductive layer.

7. The method ofclaim 6 in which the flex circuitry is comprised of two flex circuits.

8. A method of devising a high-density circuit module comprising the steps of:

providing a first CSP having contact sites along a major surface;

providing a second CSP having contact sites along a major surface;

providing flex circuitry having plural flex contacts and at least two conductive layers; and

connecting selected contact sites of the first CSP to a first set of the plural flex contacts so that the shortest distance from the major surface of the first CSP to a surface of the flex circuitry is between 1 and 6 mils inclusive.

9. The method ofclaim 8 further comprising the step of connecting selected contact sites of the second CSP to a second set of the plural flex contacts so that the shortest distance from the major surface of the second CSP to a surface of the flex circuitry is between 1 and 6 mils inclusive.

10. A method of devising a high-density circuit module comprising the steps of:

providing a first CSP having a plurality of ball contacts disposed along a major surface;

providing flex circuitry having a plurality of selected flex contacts each penetrated by an orifice;

disposing the first CSP proximal to the flex circuitry to place the plurality of ball contacts adjacent to the plurality of flex contacts; and

applying heat sufficient to melt the plurality of ball contacts to pass through the respective orifices to form consolidated contacts each with an inner flex portion and an outer flex portion.

11. The method ofclaim 10 further comprising the step of disposing a second CSP above the first CSP and connecting the first and second CSPs with the flex circuitry.

12. The method ofclaim 10 in which the flex circuitry has two conductive layers.

13. The method ofclaim 10 in which the outer flex portion has a volume substantially greater than the volume of the inner flex portion.

14. A high-density circuit module comprising:

a first CSP having an upper surface and a lower surface, and along the lower surface there are plural first CSP low profile contacts, each of which plural first CSP low profile contacts extends no more than 7 mils from the surface of the first CSP;

a second CSP in stacked disposition with the first CSP, the second CSP having an upper surface and a lower surface, and along the lower surface there are plural second CSP low profile contacts, each of which plural second CSP low profile contacts extends no more than 7 mils from the surface of the second CSP;

a flex circuit that connects the first CSP and the second CSP, the flex circuit having at least two conductive layers and a portion that is disposed between the first and second CSPs.

15. The high-density circuit module ofclaim 14 in which the shortest distance from the lower surface of the second CSP to the upper surface of the first CSP that passes through one of the plural second CSP low profile contacts is less than 11 mils.

16. A high density circuit module comprising:

a first CSP;

a second CSP, the second CSP being disposed above the first CSP;

flex circuitry connecting the first CSP and the second CSP, the flex circuitry comprising

a conductive layer overlaid by an outer layer,

plural flex contacts disposed along the conductive layer and accessible through the outer layer, and

an orifice in at least one of the plural flex contacts, which orifice has a median opening extent of DO; and

a consolidated contact comprising an inner flex portion and an outer flex portion delineated by the orifice, the consolidated contact disposed to pass through the orifice and provide a connection between the first CSP and the conductive layer of the flex circuitry, with the outer flex portion being disposed adjacent to the outer layer of the flex circuitry and having a median lateral extent of DCC and DCC is larger than DO.

17. A high density circuit module comprising:

a first CSP;

flex circuitry having a first side and a second side; and

a second CSP in a stacked relationship with the first CSP, the second CSP having plural consolidated contacts, each of which consolidated contacts is one piece of metal comprising

an inner portion disposed between the first side of flex circuitry and the second CSP,

an outer portion that is larger than the inner portion, which outer portion is disposed along the second side of the flex circuitry, and

a portion disposed through the flex circuitry and in connection with a conductive layer of the flex circuitry.

18. The high density circuit module ofclaim 17 in which the flex circuitry comprises an outer layer that is disposed at least in part between the conductive layer of the flex circuitry and the outer portion of at least one of the consolidated contacts.

19. The high density circuit module ofclaim 17 in which the flex circuitry comprises at least two conductive layers, and one or more of the plural consolidated contacts is in electrical connection with only one of the conductuctive layers of the flex circuitry.

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