US20080185662A1 - Structure and method for forming asymmetrical overlap capacitance in field effect transistors - Google Patents

Abstract

A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a division of U.S. patent application Ser. No. 11/163,165, filed Oct. 7, 2005, the disclosure of which is incorporated by reference herein in its entirety.
TRADEMARKS
• IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
• The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a structure and method for forming asymmetrical overlap capacitance in field effect transistors (FETs).
• In the manufacture of semiconductor devices, there is a constant drive to increase the operating speed of certain integrated circuit devices such as microprocessors, memory devices, and the like. This drive is fueled by consumer demand for computers and other electronic devices that operate at increasingly greater speeds. As a result of the demand for increased speed, there has been a continual reduction in the size of semiconductor devices, such as transistors. For example, in a device such as a field effect transistor (FET), device parameters such as channel length, junction depth and gate dielectric thickness, to name a few, all continue to be scaled downward.
• Generally speaking, the smaller the channel length of the FET, the faster the transistor will operate. Moreover, by reducing the size and/or scale of the components of a typical transistor, there is also an increase in the density and number of the transistors that may be produced on a given amount of wafer real estate, thus lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
• Unfortunately, reducing the channel length of a transistor also increases “short channel” effects, as well as “edge effects” that are relatively unimportant in long channel transistors. One example of a short channel effect includes, among other aspects, an increased drain to source leakage current when the transistor is supposed to be in the “off” or non-conductive state, due to an enlarged depletion region relative to the shorter channel length. In addition, one of the edge effects that may also adversely influence transistor performance is what is known as Miller capacitance. The Miller capacitance is a parasitic overlap capacitance (C_ov) that arises as a result of the doped polycrystalline silicon gate electrode and gate dielectric that (almost invariably) overlaps with a conductive portion of the more heavily doped source/drain regions and/or the less heavily doped source/drain extension (SDE) regions (if present) of the FET.
• Moreover, as transistor dimensions continue to scale down, the gate to source/drain extension overlap needs to be kept relatively constant so that drive current can be maintained. For example, a minimum of about 20 nm/side of overlap is necessary to prevent transistor drive current (I_dsat) degradation. When an overlap is too small, a high resistance region will be created between the extension and the channel. As devices become smaller, the source extension to drain extension distance becomes narrower, resulting in a severe punchthrough problem.
• Accordingly, it would be desirable to be able to fabricate an FET device that maintains a low series resistance between the gate and the source of the device, while at the same time minimizing adverse consequences such as short channel effects, hot carrier effects, punchthrough and parasitic Miller capacitance formed by excessive gate to drain overlap.
SUMMARY
• The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for forming asymmetric spacer structures for a semiconductor device. In an exemplary embodiment, the method includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.
• In another embodiment, a method for forming field effect transistor (FET) structures for a semiconductor device includes forming at least a pair of adjacently spaced gate structures over a semiconductor substrate, and forming a spacer layer over the adjacently spaced gate structures. The gate structures are spaced such that the spacer layer is formed at first thickness in a region between the gate structures and at a second thickness elsewhere, the said second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures adjacent sidewalls of the pair of adjacently spaced gate structures, and the substrate is implanted with doped regions having asymmetric characteristics in accordance with the asymmetric spacer structures.
• In still another embodiment, a method for forming field effect transistor (FET) structures for a semiconductor device includes forming at least a pair of adjacently spaced gate structures over a semiconductor substrate, forming offset spacers adjacent sidewalls of the pair of adjacently spaced gate structures, and forming extension regions in the substrate. A second spacer layer is formed over the offset spacers, the gate structures and the substrate. The second spacer layer is subjected to a single, angled ion implantation of a neutral species, the angled ion implantation originating from a single direction. The second spacer layer is etched, wherein portions of the second spacer layer subjected to said angled ion implantation are etched at a faster rate than unexposed portions thereof, thereby forming asymmetrical second spacers adjacent the offset spacers. The substrate is then implanted with source and drain regions.
• In still another embodiment, a field effect transistor (FET) device, includes a gate structure formed over a semiconductor substrate, a first pair of spacer structures formed on sidewalls of the gate structure, and a second pair of spacer structures formed adjacent the first pair of spacer structures, the second pair of spacer structures having an asymmetrical thickness with respect to one another. A source region and extension thereof is implanted on one side of the gate structure, and a drain region and extension thereof is implanted on the other side of the gate structure. The extension of the source region has a different length than the extension of the drain region, in accordance with said asymmetrical thickness of the second pair of spacer structures.
BRIEF DESCRIPTION OF THE DRAWINGS
• Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
• FIGS. 1 through 3 are a series of a cross sectional views illustrating the formation of asymmetrical source and drain overlap regions in an FET device, in accordance with an exemplary embodiment of the invention;
• FIGS. 4 through 7 andFIG. 9 are a series of a cross sectional views illustrating the formation of asymmetrical source and drain extension regions in an FET device, in accordance with an alternative embodiment of the invention;
• FIG. 8 is an exemplary SEM image of a device formed in accordance with the processing step shown inFIG. 7;
• FIG. 10 is an exemplary SEM image of a portion of an SRAM cell having asymmetric spacers;
• FIGS. 11 through 14 are a series of a cross sectional views illustrating the formation of asymmetrical source and drain overlap regions in an FET device, in accordance with an alternative embodiment of the invention; and
• FIGS. 15 through 20 are a series of a cross sectional views illustrating the formation of asymmetrical source and drain extension regions in an FET device, in accordance with still another embodiment of the invention.
DETAILED DESCRIPTION
• Disclosed herein is a method and structure for reducing overlap capacitance in field effect transistors (FETs). In a conventional FET fabrication process, the spacer structures formed on opposite sides of the gate conductor are generally symmetrical, such that subsequently formed source and drain extensions have the same amount of overlap with respect to the gate. However, because the transistor drive current is primarily controlled by the amount of source side overlap (i.e., gate to source resistance), the amount of drain side overlap can still be reduced without adversely impacting drive current. On the other hand, the reduction in gate to drain overlap is beneficial in terms of short channel effects, punchthrough, hot carrier effects and parasitic capacitance, for example.
• Furthermore, as device dimensions shrink, the extension resistance becomes dominant. A shorter source side extension (as a result of a narrow spacer width) will reduce the series resistance and improve device performance, without also causing problems such as hot carrier effects, since the drain side extension (as a result of not reducing the spacer width) is still maintained at an appropriate length. This is in contrast to conventionally formed symmetrical extensions for the source and drain sides, which in turn result in symmetrical source and drain extension lengths.
• Accordingly, as described in further detail herein, the disclosed invention embodiments utilize various fabrication techniques to produce asymmetric spacer structures that in turn result in source and drain extension having long and short overlaps, as well as long and short extensions themselves.
• Referring initially toFIGS. 1 through 3, there is shown a series of a cross sectional views illustrating the formation of asymmetrical source and drain overlap regions for a pair ofFET devices100, in accordance with an exemplary embodiment of the invention. In particular,FIG. 1 illustrates a pair ofadjacent gate conductors102 formed over a semiconductor substrate104 (e.g., silicon), with thegates102 being formed on correspondinggate oxide layers106. Shallow trench isolation (STI)structures108 are also illustrated for electrically isolating individual devices from one another on thesubstrate104. As the basic FET structures are well known to one skilled in the art, certain features such as theSTIs108 andgate oxide layers106 are not discussed in further detail herein.
• As is also shown inFIG. 1, aspacer layer130 of non-uniform thickness is formed over a pair ofgate structures102. The embodiment ofFIG. 1 makes use of two neighboring gates in close proximity (e.g., a separation therebetween of about 1 to 3 times the gate height). By selectively tuning the deposition parameters in forming thespacer layer130, a thinner film will be formed over the region between the two gates with respect to the regions on the outside of the gates. As such, when thespacer layer130 is patterned and etched, theasymmetric spacers114a,114bwill result from the constant etch rate of a layer of non-uniform thickness, as illustrated inFIG. 2.
• Following the formation of the asymmetrical spacers,FIG. 3 illustrates a halo and extension implantation step in accordance with standard device processing. After an anneal to drive the implanted dopant materials, it is seen that theextensions116 corresponding to thethinner spacers114bhave longer overlaps than theextensions118 corresponding to thethicker spacers114a. In other words, the “long overlap”extensions116 extend further beneath the gate than do the “short overlap”extensions118. In a preferred embodiment, the source terminal of the FET structures will be located at the long overlap extension side of the gate (to maintain drive current) while the drain terminal is located at the short overlap extension side of the gate (to reduce overall overlap capacitance and improve short channel effects).
• The principles of asymmetric spacer formation through non-uniform layer formation may also be applied during the formation of the deep source and drain regions as well.FIGS. 4 through 7 andFIG. 9 are a series of a cross sectional views illustrating the formation of asymmetrical source and drain extension regions in an FET device, in accordance with another embodiment of the invention. Beginning inFIG. 4, offsetspacers114 are initially formed over the FET gate structures.
• Thespacers114 may be symmetrical (i.e., substantially equal thickness on both sides of the gate) as in a conventional process or, alternatively, thespacers114 could be formed asymmetrically as shown inFIG. 2. For purposes of illustration, the offsetspacers114 are depicted as symmetric in the present sequence.FIG. 5 illustrates a halo and extension implantation step in accordance with standard device processing, followed by an anneal to diffuse the implanted dopant materials. For symmetrical offsetspacers114, the resultingextensions120 on both sides of the gates will have substantially equal overlaps. On the other hand, if thespacers114 are formed in accordance with the processing shown inFIGS. 1-2, then asymmetrical extensions will appear as shown inFIG. 3.
• As then shown inFIG. 6, a non-uniform second spacer layer132 (e.g., Si₃N₄) is formed over the device. Similar to the embodiment ofFIG. 1, the second spacer layer132 (given a sufficiently close distance between gates and properly tuned process conditions) will be formed thinner in the region between the gates, and thicker in the regions outside the gates. Once thesecond spacer layer132 is patterned and etched inFIG. 7, theasymmetric spacers124a,124bare formed. By way of illustration,FIG. 8 is an exemplary SEM image of a device formed in accordance with the processing step shown inFIG. 7.
• Through the formation of theasymmetric spacers124a,124b, the source/drain ion implantation step shown inFIG. 9 results in extensions with different lengths. More specifically, theextensions120aon the outside of the gates are longer in comparison to theextensions120bbetween the gates. This is due to the fact that the deep source/drain implant comes closer to the gate where the second set of spacers is thinner, thus shortening the extension regions formed inFIG. 5. With such shorter extensions, there is a lower resistance to carriers (e.g., electrons or holes). In such an embodiment, it would be practical to have a common source terminal located between the gates to reduce the series resistance, while the drain terminals are located outside the gates where the extensions are longer.
• One suitable example of such an application could be the PFET device pair of an SRAM cell, which has the source terminals thereof connected to the supply voltage (V_DD).FIG. 10 is an exemplary SEM image of a portion of an SRAM cell having asymmetric spacers, similar to the embodiment shown inFIG. 9. As will be noted, the thinner spacers are located between the two gates.
• FIGS. 11 through 14 illustrate another technique for forming asymmetric spacers, in accordance with a further embodiment of the invention. As with the previous embodiments discussed above,FIG. 11 illustrates a pair ofgate conductors102 formed over asemiconductor substrate104, gate oxide layers106 andSTI structures108. In addition, a spacer layer110 (e.g., oxide, TEOS, silicon nitride) is formed over thedevices100 for the purpose of forming spacers prior to dopant implantation.
• Conventionally, thespacer layer110 ofFIG. 11 would then be patterned and uniformly etched to result in substantially symmetric spacers along the sidewalls of thegate conductors102. However, as shown inFIG. 12, the wafer is then subjected to an angled ion implantation (arrows112) of a neutral dopant species such as germanium (Ge) or xenon (Xe), for example. This results in thespacer layer110, on one side of the gate structures, having receiving the angled ion implant. In an exemplary embodiment, the implant angle may be on the order from about 10 degrees to about 35 degrees. The effect of such an implant is to increase the etch rate of implanted portions of thespacer layer110 with respect to the remainder of the layer. Thus, when the implantedspacer layer110 is subsequently patterned and etched, as shown inFIG. 13, each gate is left with a pair ofspacers114a,114b, wherein thespacers114bon the implanted side of the gate are thinner (i.e., asymmetrical) with respect to thespacers114aon the non-implanted side of the gate.
• Following the formation of the asymmetrical spacers,FIG. 14 illustrates a halo and extension implantation step to form the extensions having longer andshorter overlaps116,118, similar to the structure ofFIG. 3. However, whereas the longer overlaps116 ofFIG. 3 are located on the inside of the gates, the longer overlaps116 ofFIG. 14 are located on the right side of the gates.
• The principles of asymmetric spacer formation through ion implantation may also be applied during the formation of the source and drain regions as well.FIGS. 15 through 20 are a series of a cross sectional views illustrating the formation of asymmetrical source and drain extension regions in an FET device, in accordance with another embodiment of the invention. Beginning inFIG. 15, the FET structures are shown after the formation of offsetspacers114. As withFIG. 4, the offsetspacers114 may either by symmetrically formed or asymmetrically formed prior to the halo/extension ion implant step ofFIG. 5.
• FIG. 16 illustrates a halo and extension implantation step in accordance with standard device processing, followed by an anneal to diffuse the implanted dopant materials. For symmetrical offset spacers, the resultingextensions120 on both sides of the gates will have substantially equal overlaps. On the other hand, if thespacers114 are formed in accordance with the processing shown inFIGS. 12-13, then theextensions120 will appear as shown inFIG. 14. In either case, a second spacer layer122 (e.g., Si₃N₄) is then formed over the device as shown inFIG. 17.
• Then, as shown inFIG. 18, thesecond spacer layer122 is subjected to an angled ion implantation (arrows112) of a neutral dopant species, in a manner similar to that discussed in the previous embodiment. Again, this has the effect of increasing the etch rate of the implanted portions of thelayer122. Thus, when thelayer122 is patterned and etched as shown inFIG. 19, a second set ofspacers124a,124bis formed over the first set of offsetspacers114. Regardless of whether the first set of offsetspacers114 is symmetric or asymmetric, the second set of spacers will in fact be asymmetric due to the angled implantation shown inFIG. 18. In particular, the non-implanted side of the gate structures includethicker spacers124a, while the implanted side of the gate structure includesthinner spacers124b.
• As finally illustrated inFIG. 20, the wafer is then subjected to a (deep) source/drain implantation in accordance with conventional process doping. However, on the side of the gates corresponding to thethinner spacers124b, the resultingextensions120bthat remain after the deep source/drain implant become shorter in length than theextensions120aon the side of the gates corresponding to thethicker spacers124a. Thus, in a preferred embodiment, the source side of the FETs is located at the sides of the gate corresponding to thethinner spacers124b. In contrast, the drain side extensions are still maintained at a certain length in order to prevent hot carrier effects.
• Through the use of an angled, neutral dopant implantation step in order to increase the etch rate of a spacer layer, an FET device having asymmetrical spacer thicknesses may be achieved. This in turn allows for extensions with long/short overlaps, as well as longer and shorter extensions themselves. However, additional methods are also contemplated that will result in the asymmetric spacers such as discussed above.
• While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (13)

1. A semiconductor device, comprising:

at least a pair of field effect transistor (FET) structures including a pair of adjacently spaced gate structures formed over a semiconductor substrate;

each of said pair of FET structures having a pair of asymmetric spacer structures adjacent sidewalls thereof;

wherein inner spacer structures located in a region between said pair of gate structures are thinner than outer spacer structures located on the outside of said pair of gate structures.

2. The device ofclaim 1, wherein said asymmetric spacer structures further comprise offset spacers used in the definition of halo and extension implantation regions.

3. The device ofclaim 1, further comprising extensions implanted within said substrate, wherein said extensions corresponding to thinner offset spacers have a longer gate overlap than said extensions corresponding to thicker offset spacers.

4. The device ofclaim 1, wherein said asymmetric spacer structures further comprise second spacers formed over offset spacers, used in the definition of source and drain regions.

5. The device ofclaim 4, further comprising source and drain regions implanted within said substrate, wherein said source regions correspond to thinner second spacers and said drain regions correspond to thicker second spacers.

6. The device ofclaim 5, wherein said source regions have shorter extensions than said drain regions.

7. The device ofclaim 1, wherein a distance between said pair of adjacently spaced gate structures is about 1 to 3 times a height of said gate structures.

8. A field effect transistor (FET) device, comprising:

a gate structure formed over a semiconductor substrate;

a first pair of spacer structures formed on sidewalls of said gate structure;

a second pair of spacer structures formed adjacent said first pair of spacer structures, said second pair of spacer structures having an asymmetrical thickness with respect to one another;

a source region and extension thereof implanted on one side of said gate structure; and

a drain region and extension thereof implanted on the other side of said gate structure;

wherein the extension of said source region has a different length than the extension of said drain region, in accordance with said asymmetrical thickness of said second pair of spacer structures.

9. The FET device ofclaim 8, wherein said source region corresponds to a thinner one of said second pair of spacer structures and said drain regions corresponds to a thicker one of said second pair of spacer structures.

10. The FET device ofclaim 9, wherein the extension of said source region is shorter than the extension of said drain region.

11. The FET device ofclaim 8, wherein said first pair of spacer structures also have an asymmetrical thickness with respect to one another.

12. The FET device ofclaim 11, wherein one of said source and drain extensions corresponding to a thinner one of said first pair of spacer structures has a longer gate overlap than the other of said source and drain extensions corresponding to a thicker one of said first pair of spacer structures.

13. The FET device ofclaim 12, wherein the extension of said source region has a longer gate overlap than the extension of said drain region.

Images