US20080174579A1 - Display device and driving method thereof - Google Patents

Abstract

Regarding the time gradation method as the digital gradation expression method, it is an object of the invention to provide a display device which prevents a reduction of frame frequency and implements a low-power-consumption SRAM. The invention overcomes the aforementioned disadvantages of conventional technique by synchronizing a writing and reading by utilizing read and write signals of which states read at a certain timing to select which of two memories is efficient to be written.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The invention relates to a display device, and more particularly such a display device having a light emitting element and a memory control circuit. The memory control circuit controls a writing and reading to memories such as SRAM.
• 2. Description of the Related Art
• Hereinafter explained is a display device which disposes a light emitting element at each pixel and displays an image by controlling the emission of the light emitting elements.
• The explanation throughout this specification uses elements (OLED elements) having a structure in which an organic compound layer for emitting light when an electric field is generated is sandwiched between an anode and a cathode, for the light emitting elements, but the present invention is not limited to this structure.
• Further, the explanation within this specification uses elements that utilize light emitted when making a transition from singlet excitons to a base state (fluorescence), and those that utilize light emitted when making a transition from triplet excitons to a base state (phosphorescence).
• An organic compound layer includes a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injection layer, and the like. The basic structure of a light emitting element is a laminate of an anode, a light emitting layer, and a cathode layered in this order. The basic structure can be modified into a laminate of an anode, a hole injection layer, a light emitting layer, an electron injection layer, and a cathode layered in this order, or a laminate of an anode, a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injection layer, and a cathode layered in this order.
• A display device is constituted by a display and peripheral circuits for inputting signals to the display.
• The structure of the display is shown in a block diagram ofFIG. 8.
• InFIG. 8, thedisplay2000 is constituted by a source signalline driver circuit2107, a gate signalline driver circuit2108, and apixel portion2109. The pixel portion has pixels disposed in a matrix shape.
• Thin film transistors (hereafter referred to as TFTs) are arranged in each pixel. A method of placing two TFTs in each pixel and controlling light emitted from the light emitting element of each pixel is explained.
• FIG. 9 shows a structure of a pixel portion of a display device.
• Source signal lines S1 to Sx, gate signal lines G1 to Gy, and electric power source supply lines V1 to Vx are arranged in apixel portion2700, and x columns and y rows (where x and y are natural numbers) of pixels are also placed in the pixel portion. Eachpixel2705 has a switchingTFT2701, adriver TFT2702, astorage capacitor2703, and alight emitting element2704.
• The pixel is constituted by one source signal line S of the source signal lines S1 to Sx, one gate signal line G of the gate signal lines G1 to Gy, one electric power source supply line V of the electric power source supply lines V1 to Vx, the switchingTFT2701, the driver TFT2702, thestorage capacitor2703, and thelight emitting element2704.
• A gate electrode of the switchingTFT2701 is connected to the gate signal line G, and either a source region or a drain region of the switchingTFT2701 is connected to the source signal line S, while the other is connected to a gate electrode of thedriver TFT2702 and to one electrode of thestorage capacitor2703. Either a source region or a drain region of the driver TFT2702 is connected to the electric power source supply line V, while the other is connected to an anode or a cathode of thelight emitting element2704. The electric power source supply line V is connected to one of the two electrodes of thestorage capacitor2703, namely the electrode on a side to which the driver TFT2702 and the switchingTFT2701 are not connected.
• The anode of thelight emitting element2704 is referred to as a pixel electrode, and the cathode of thelight emitting element2704 is referred to as an opposing electrode, within this specification for cases in which the source region or the drain region of the driver TFT2702 is connected to the anode of thelight emitting element2704. On the other hand, if the source region or the drain region of the driver TFT2702 is connected to the cathode of thelight emitting element2704, then the cathode of thelight emitting element2704 is referred to as the pixel electrode, and the anode of thelight emitting element2704 is referred to as the opposing electrode.
• Further, an electric potential imparted to the electric power source supply line V is referred to as an electric power source electric potential, and an electric potential imparted to the opposing electrode is referred to as an opposing electric potential.
• The switchingTFT2701 and the driver TFT2702 may be either p-channel TFTs or n-channel TFTs. However, it is preferable that the driver TFT2702 is a p-channel TFT, and that the switchingTFT2701 is an n-channel TFT for cases in which the pixel electrode of thelight emitting element2704 is the anode. Conversely, it is preferable that the driver TFT2702 is an n-channel TFT, and that the switchingTFT2701 is a p-channel TFT if the pixel electrode is the cathode.
• Operations during display of an image with the aforementioned pixel structure are explained below.
• A signal is inputted to the gate signal line G, and the electric potential of the gate electrode of the switchingTFT2701 changes, then a gate voltage is changed. The signal is inputted to the gate electrode of thedriver TFT2702 by the source signal line S, via source and drain of the switchingTFT2701 which thus has been placed in a conductive state. Further, the signal is stored in thestorage capacitor2703. The gate voltage of thedriver TFT2702 changes in accordance with the signal inputted to the gate electrode of thedriver TFT2702, then the source and drain are placed in a conductive state. The electric potential of the electric power source supply line V is imparted to the pixel electrode of thelight emitting element2704 through the driver TFT2702. Thelight emitting element2704 thus emits light.
• A method of expressing gradations with pixels having such a structure is explained. Gradation expression methods can be roughly divided into an analog method and a digital method. The digital method has advantages of being good at variation of TFTs compared with the analog method. A digital gradation expression method is focused upon here. A time gradation method can be given as the digital gradation expression method. A time gradation driving method is explained in detail now.
• The time gradation driving method is a method of expressing gradations by controlling the period that each pixel of a display device emits light. If a period for displaying one image is taken as one frame period, then one frame period is divided into a plurality of subframe periods.
• Turn on and turn off, namely whether or not the light emitting element of each pixel is made to emit light or to not emit light, is performed for each subframe period. The period during which the light emitting element emits light in one frame period is controlled, and a gradation for each pixel is expressed.
• The time gradation driving method is explained in detail using timing charts ofFIGS. 10A and 10B. Note that an example of expressing gradation using a 4-bit digital image signal is shown inFIGS. 10A and 10B. Note also thatFIG. 9 may be referred to regarding the structure of the pixel portion and the structure of the pixels, respectively. In accordance with an external electric power source (not shown in the figure), the opposing electric potential can be switched over between an electric potential on the same order as the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential), and an electric potential difference of the electric power source supply lines V1 to Vx on an order sufficient to make thelight emitting element2704 emit light.
• One frame period F is divided into a plurality of subframe periods SF1 to SF4. The gate signal line G1 is selected first in the first subframe period SF1, and a digital image signal is inputted from the source signal lines S1 to Sx to each of the pixels having the switchingTFTs2701 with gate electrodes connected to the gate signal line G1. Thedriver TFT2702 of each pixel is placed in an ON state or an OFF state by the inputted digital image signal.
• The term “ON state” for a TFT in this specification indicates that the TFT is in a state in which there is a state of conduction between the source and the drain in accordance with a gate voltage. Further, the term “OFF state” for a TFT indicates that there is a non-conductive state between the source and the drain in accordance with a gate voltage.
• The opposing electric potential of thelight emitting elements2704 is set nearly equal to the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential) at this point, and therefore thelight emitting elements2704 do not emit light even in pixels having theirdriver TFT2702 in an ON state. The aforementioned operations are repeated for all of the gate signal lines G1 to Gy, and a write-in period Ta1 is completed. Note that a period for write-in during the first subframe period SF1 is called Ta1. In general, a write-in period of a j-th sub-frame period (where j is a natural number) is called Taj.
• The opposing electric potential changes when the write-in period Ta1 is complete, so as to have an electric potential difference from the electric power source electric potential on an order so that thelight emitting element2704 will emit light. A display period Ts1 thus begins. Note that the display period of the first subframe period SF1 is called Ts1. In general, a display period of the j-th sub-frame period (where j is a natural number) is denoted by using a reference symbol Tsj. Thelight emitting elements2704 of each pixel are placed in a light emitting state or a non-light emitting state, corresponding to the inputted signal, in the display period Ts1.
• The above operations are repeated for all of the subframe periods SF1 to SF4, one frame period F1 is completed. The length of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 are set appropriately here, and gradations are expressed by an accumulation of the display periods of the subframe period during which thelight emitting elements2704 emit light. In other words, the total amount of the turn on time within one frame period is used to express the gradations.
• A method of generally expressing 2ⁿgradations by inputting an n-bit digital video signal, is explained. One frame period is divided into n sub-frame periods SF1 to SFn at this point, for example, and the ratios of the lengths of the display periods Ts1 to Tsn of the sub-frame periods SF1 to SFn are set so as to be Ts1:Ts2: . . . :Tsn=2⁰:2⁻¹: . . . :2⁻ⁿ⁺²:2⁻ⁿ⁺¹. Note that the lengths of the write-in periods Ta1 to Tan are all the same.
• Within one frame period, the gradation of the pixels in the frame period is determined by finding the total of the display period Ts during which a light emitting state is selected in thelight emitting element2704. For example, if the brightness for a case in which a pixel emits light during all of the display periods is taken to be 100% when n=8, then a brightness of 1% can be expressed if the pixel emits light in the display period Ts8 and in the display period Ts7. A 60% brightness can be expressed for cases in which the pixel emits light in the display periods Ts6, Ts4, and Ts1.
• A circuit to convert signals is needed in order to display in such time gradation method as shown above. Schematic of the conventional control circuit is shown inFIG. 2. Acontrol circuit200 is constituted by memories A201 and B202 for storing data, a logic circuit for reading data and writing into the memory (W-LOGIC203), and a logic circuit for reading the memory and outputting data (R-LOGIC204).
• A timing chart of the conventional control circuit is shown inFIG. 3. Data is written and read alternately using memories A201 and B202, in order to make the digital data inputted to W-LOGIC203 synchronize with a time gradation method.
• When R-LOGIC204 reads a signal in the memory A201, a digital video signal for the next frame period is inputted to the memory B202 through W-LOGIC203 and starts being stored.
• In this way, thecontrol circuit200 includes the memories A201 and B202 which can store digital video signal of1 frame period each, to sample a digital video signal by using them alternately.
• Conventionally, however, there was a state of Wait until the next read signal occurred after writing into the memories A201 and B202. A switching function between writing and reading of the memories A201 and B202 was operated in timing with reading which takes more time. (FIG. 3)
SUMMARY OF THE INVENTION
• In the conventional method, a time for reading was set much longer than a time for writing. Therefore there was no problem with a method in which a writing occurs as needed and operating functions are switched after reading.
• However, there was a problem. In a driving method which has little difference between a time for reading and a time for writing of memory, a conventional method that there is a state of Wait until reading is done after writing pulled back the timing of writing to memory. As a result of this, a frame frequency decreases.
• To solve the above-mentioned problem of related art, the present invention took the following method. Namely, by reading states of reading signal and writing signal at a certain timing, synchronization is taken and which one of two memories will be written to is decided through the signals.
• Namely, by using a display device having:
• a first memory and a second memory which store data;
• a writing device which reads data and writes to the first memory and the second memory;
• a reading device which reads data from the first memory or the second memory, and outputs data;
• a means to decide the roles for writing and reading to the first memory and the second memory in accordance with the states of a writing device and a reading device; and
• a first memory selector and a second memory selector which select writing and reading to the first memory and the second memory;
• the writing device and the reading device can be synchronized to solve the problem.
• As a means to decide the roles for writing and reading to a first memory and a second memory from the states of a writing device and a reading device, a display device provides a circuit, wherein:
• state of a writing device is denoted by a first signal and state of a reading device is denoted by a second signal;
• a third signal decides the roles for writing and reading to a first memory and a second memory, and inverts to switch the roles of the first memory and the second memory when the first and second signals come into a second state;
• a fourth signal holds the third signal;
• said first and second memories are given the roles of writing and reading respectively;
• the first signal is inputted to the reading device and the second signal is inputted to the writing device;
• when the writing device is in a state of writing, the first signal and the second signal come into a first state, therefore, the third signal is not inverted and the fourth signal overwrites a state of the third signal;
• when the writing device is in a waiting state, the first signal comes into the second state and the second signal also comes into the second state to invert the third signal, therefore, the roles of writing and reading of two memories are switched. Then the second signal returns to the first state again. The fourth signal is compared with the third signal, and a state of the first signal is returned to the first state at the time the state of the third signal changes and the writing device starts writing.
• Then, the reading device and the writing device may be not only FPGAs but also LSIs. Furthermore, they may be constituted on the same substrate with the display device.
• Thereby, even when there is little difference between the time for reading and writing to memories, the operating functions can be switched in the optimum period. The problem that the frame frequency decreases can thus be solved.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a block diagram of the present invention.
• FIG. 2 is a block diagram of the conventional example.
• FIG. 3 is a timing chart of the operation of conventional example.
• FIG. 4 is a timing chart of the operation of the present invention.
• FIG. 5 is a timing chart of the operation of the present invention.
• FIG. 6 is a diagram showing an embodiment using the present invention.
• FIG. 7 is a diagram showing an example of a display device using the present invention.
• FIG. 8 is a block diagram of the conventional example.
• FIG. 9 is a circuit diagram of the pixels disposed in a matrix shape.
• FIGS. 10A and 10B are timing charts of the operation of the conventional example.
• FIG. 11 is a diagram showing an example of a display device using the present invention.
• FIGS. 12A to 12G are diagrams showing electric devices using the present invention.
• FIG. 13 is a diagram showing an example of a display device using the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• FIG. 1 shows a block diagram of a major structure of the present invention.
• Acontrol circuit100 has memories A101 and B102, aSelector103 for writing a memory, aSelector104 for output, a logic circuit for writing into a memory (W-LOGIC105), and a logic circuit for reading the memory and outputting the data (R-LOGIC106). When video data is inputted to W-LOGIC105, it writes data in either of memories A101 or B102 selected by theSelector103 for writing memory. Then theSelector104 selects the other memory which was not selected by theSelector103 as a memory for R-LOGIC106 to read.
• Signals of SYNC, WFLAG, RFLAG and RAM_SELECT are newly adopted to achieve a synchronization. W-LOGIC105 inputs the writing state WFLAG to R-LOGIC106, and the reading state RFLAG from memory is inputted to W-LOGIC105 as needed. RAM_SELECT selects a memory to write in accordance with each state of WFLAG and RFLAG. R-LOGIC106 holds RAM_SELECT and makes a comparison with the RAM_SELECT of the moment when SYNC is inputted.
• In the structure inFIG. 1, R-LOGIC106 holds RAM_SELECT particularly, however, W-LOGIC105 may hold RAM_SELECT as well.
• A timing chart of the operations of W-LOGIC105 and R-LOGIC106 is shown inFIG. 4.
• WFLAG is Low when W-LOGIC105 is in Write state and RFLAG also becomes Low when Low of WFLAG is inputted to R-LOGIC106.
• WFLAG is High when W-LOGIC105 is in the state of Wait, and when High of WFLAG is inputted to R-LOGIC106, RFLAG becomes High as well. RFLAG becomes Low when both WFLAG and RFLAG are High and R-LOGIC106 finishes reading data from the memory selected by theSelector104 for output. In timing with RFLAG becoming Low, RAM_SELECT is inverted and the memory selected by theSelectors103 and104 switches.
• When SYNC is inputted, RAM_SELECT at that point is compared with the RAM_SELECT stored in R-LOGIC106. During a Wait period, the RAM_SELECT is inverted and WFLAG becomes Low when the state of the inverted RAM_SELECT is different from the RAM_SELECT stored in R-LOGIC106, and again W-LOGIC105 becomes Write state.
• InFIG. 5, a timing chart regarding the synchronization and the timing of writing and reading is shown. When SYNC is inputted, R-LOGIC106 writes the state of the RAM_SELECT. During a Write (WFLAG is Low) period, a new state of RAM_SELECT is overwritten, and the state is kept during a Wait (WFLAG is High) period.
• Furthermore, when inverted RAM_SELECT during Wait period is different in state from RAM_SELECT stored in R-LOGIC106, WFLAG becomes Low and again W-LOGIC105 becomes Write state.
• As RFLAG is Low when RAM_SELECT is inverted, writing and reading can be synchronized at this point.
• Embodiments of the invention will be described.
Embodiment 1
• In this embodiment, an example of the constitution of a control circuit which outputs to a display for displaying using OLED elements referring toFIG. 6.
• 18 bits (6 bits×RGB) of Video_Data and control signals are inputted to acontrol circuit601. The operation from the input of Video_Data to the output to adisplay608 is described.
• Reading of each line is controlled by VCLK (a cycle is 148.8 μs). First, the input of Video_Data starts by being inputted a SYNC signal. After being inputted a SYNC signal and a certain period of off time passes, the input of Video_Data to W-LOGIC602 starts. One line of Video_Data is read per half cycle of VCLK. After inputting220 lines and a certain period of off time passes, a SYNC signal is inputted again, and Video_Data is inputted. An input cycle for full page is 18.1536 ms (122 cycles of VCLK).
• Reading to each block in one line is controlled by HCLK (a cycle is 400 ns). HCLK reads Video_Data during Video_Enable is high. After reading one line, more specifically, 176 blocks of data, and a certain period of off time (Video_Enable is Low) passes, then reading the next line of Video_Data. By repeating this for 220 lines, data for one screen is completed.
• On the other hand, a memory A606 and a memory B607 are connected to thecontrol circuit601, and a signal RAM_SELECT from thecontrol circuit601 decides which memory is written and read. Each memory is constituted of 24 (8×3) flip flops. Each flip-flop can store data (6 bits) for one color at a certain point. Data is moved to next flip flop sequentially by HCLK. When the memory has eight blocks of data, one memory is selected for writing and the other memory is selected for reading data in accordance with a value of RAM_SELECT. After finishing a cycle of reading data, and receive data, RAM_SELECT is switched.
• Because the display on adisplay608 is done by time gradation, data written to the memory A606 or the memory B607 are changed their orders for the output to the display and sequentially outputted to thedisplay608. R-LOGIC603 takes data for 8 blocks into the memory A606 and the memory B607, followed by reading the first period of 1 to 4 blocks, the first period of 5 to 8 blocks, the second period of 1 to 4 blocks, the second period of 5 to 8 blocks . . . up to the sixth period in this order, and outputs them to thedisplay608.
• In displaying on thedisplay608, Video_Data is processed in 12 bits (4×RGB). G1_CK, G2_CK, G1_CKB, G2_CKB are clocks whose cycles are 12 μs each. In timing with G1_CK and G1_CKB rising or dropping, the row where Video_Data is inputted moves.
• After 2 cycles after G1_SP drops, writing is done from the top row in sequence. Writing 220 lines makes a display for one screen, however, 4 dummy cycles (48 μs) come into to delay writing before displaying the next image. G2_SP is risen in cleaning the writing, as needed.
• S_CK and S_CKB are clocks whose cycles are 200 ns each. In timing with S_CK and S_CKB rising or dropping, the block where Video_Data is inputted moves. After 4 cycles (800 ns) after rising or dropping of G1_CLK, S_LAT becomes High to hold an electric charge, and then when S_SP changes from High to Low, the input of Video_Data starts. As input is done every 4 blocks, repeating it 44 times completes writing for one line.
• Inputting clocks from anoscillation element609 throughPLL610 take synchronization between W-LOGIC602 and R-LOGIC603. The timing of writing and reading to the memory A606 and the memory B607 is controlled by the rise and drop of the clocks throughPLL610.
• Known LSI as well as FPGA may be used for W-LOGIC602 and R-LOGIC603.
• The invention is used for W-LOGIC602, R-LOGIC603, the memory A606, the memory B607, andSelectors604 and605 which select memory.
Embodiment 2
• InFIG. 7, an example of a display device using OLED elements with a control circuit of theembodiment 1 is shown.
• A display device is constituted by apanel700, acontrol circuit701, a source signalline driving circuit702, a gate signalline driving circuits703 and704, adisplay portion705, anSRAM706, an FPC707, and aconnector708. Each circuit of the display device is formed over thepanel700, otherwise attached externally.
• Operation of the display device is now described. Data and a control signal sent from theFPC707 through theconnector708 are inputted to thecontrol circuit701 and the data are rearranged for output inSRAM706, and then sent to thecontrol circuit701 again. Thecontrol circuit701 sends signals for data and display to the source signalline driving circuit702 and the gate signalline driving circuits703 and704, and then image is displayed at thedisplay portion705 using OLED elements.
• The source signalline driving circuit702 and the gate signalline driving circuits703 and704 can be substituted for the known circuits. Furthermore, the gate signal line driving circuit can be reduced to one depending on the structure of the circuit.
• The invention is applied to thecontrol circuit701.
Embodiment 3
• In this embodiment, an example of the display device using OLED elements with a control circuit of theembodiment 1 which is different from theembodiment 2 is described inFIG. 13.
• Apanel900 is constituted by acontrol circuit901, a source signalline driving circuit902, a gate signalline driving circuits903 and904, adisplay portion905, anSRAM906, anFPC907, and aconnector908. Each circuit of the display device is formed over thepanel900, otherwise attached externally.
• Operation of the display device is now described. Data and a control signal sent from theFPC907 through theconnector908 are inputted to thecontrol circuit901 and their data are returned to theSRAM906 in theFPC907, and then rearranged for output and sent to thecontrol circuit901 again. Thecontrol circuit901 sends signals used for data and display to the source signalline driving circuit902 and the gate signalline driving circuits903 and904, and then display of the picture image is performed at thedisplay portion905 using OLED elements.
• The difference with theembodiment 2 is that theSRAM906 is incorporated in theFPC907. Display device can be made smaller thereby.
• As with theembodiment 2, the source signalline driving circuit902 and the gatesignal line circuits903 and904 can be substituted for the known circuits. Furthermore, the gate signal line driving circuit can be reduced to one depending on the structure of the circuit.
• The invention is applied to thecontrol circuit901.
Embodiment 4
• In this embodiment, an example of the control circuit for output to the display using OLED elements having the different structure from theembodiments 1 to 3 is described referring toFIG. 11.
• Time gradation method display naturally takes more operating frequencies compared with an analog display. In order to achieve a high image quality, pseudocontour needs to be avoided and subframe needs to be increased to 10 or more. Therefore, operating frequency also needs to be decupled or more.
• To drive the device with such an operating frequency, SRAM needs a high speed operation using an SRAM-IC for high speed operation.
• SRAM for high speed operation, however, consumes rather big power when storing, so that it is not appropriate for mobile devices. In order to use an SRAM of low-power-consumption, frequency needs to be more decreased.
• As shown inFIG. 11, a serial-parallel conversion circuit1702 is constituted which changes data from serial to parallel before writing digital image signals toSRAMs1703 and1704. Writing is made through aSwitch1706 thereafter.
• By taking such a measure, parallel calling can be made with low frequency. Hence, a low-power-consumption SRAM can be used with low frequency to achieve the low power consumption of mobile devices.
Embodiment 5
• The invention may be applied to electric devices such as a video camera, a digital camera, a goggle display (head mount display), a navigation system, a sound reproduction device (car audio, audio component and the like), a laptop personal computer, a game device, a Personal Digital Assistant (mobile computer, mobile phone, portable game device or a digital book and the like), picture reproducer with recording medium (specifically a device with a display which plays the recording medium such as Digital Versatile Disc (DVD) and display the images) and the like. Examples of those electric devices are shown inFIG. 12.
• FIG. 12(A) illustrates a liquid crystal display or an OLED display constituted by acase1001, astand1002, adisplay portion1003 and the like. The present invention can be applied to a driving circuit of the display device having thedisplay portion1003.
• FIG. 12(B) illustrates a video camera constituted by amain body1011, adisplay portion1012, anaudio input portion1013, operatingswitches1014, abattery1015, an image receiving portion and the like. The present invention can be applied to a driving circuit of the display device having thedisplay portion1012.
• FIG. 12(C) illustrates a laptop personal computer constituted by amain body1021, acase1022, adisplay portion1023, akeyboard1024 and the like. The present invention can be applied to a driving circuit of the display device having thedisplay portion1023.
• FIG. 12(D) illustrates a Personal Digital Assistant constituted by amain body1031, astylus1032, adisplay portion1033, operatingbuttons1034, anexternal interface1035 and the like. The present invention can be applied to a driving circuit of the display device having thedisplay portion1033.
• FIG. 12(E) illustrates a sound reproduction device, especially an audio device mounted in a motor vehicle constituted by a main body1041, adisplay portion1042, operatingswitches1043 and1044 and the like. The invention can be applied to a driving circuit of the display device including thedisplay portion1042. Furthermore, the invention can be applied to any of portable or home audio devices other than the above-described audio device mounted in a motor vehicle.
• FIG. 12(F) illustrates a digital camera constituted by amain body1051, a display portion (A)1052, anocular portion1053, operatingswitches1054, a display portion (B)1055, abattery1056 and the like. The present invention can be applied to a driving circuit of the display device having the display portions (A)1052 and (B)1055.
• FIG. 12(G) illustrates a mobile phone constituted by amain body1061, anaudio output portion1062, anaudio input portion1063, adisplay portion1064, operatingswitches1065, anantenna1066 and the like. The present invention can be applied to a driving circuit of the display device having thedisplay portion1064.
• A plastic substrate with high heat resistance other than a glass substrate can also be applied to the display device of these electronic devices. Further weight saving can be achieved thereby.
• It is to be noted that the above-described devices of this embodiment are only examples and that the invention is not exclusively applied to them.
• This embodiment can be freely combined with the embodiment mode as well as any ofembodiments 1 to 4.
• In the case of the display device with light emitting elements, the reduction of frame frequency can be prevented by switching writing and reading efficiently by utilizing the control circuit of the invention.

Claims (4)

1. A display device having a light emitting element and expressing a gradation with a length of lighting time,

said display device comprising:

first and second memories;

a conversion circuit to convert video signals from serial to parallel; and

first switch and second switch,

wherein the video signal is inputted to said first memory or said second memory through said first switch after converted to parallel by said conversion circuit, and

an output signal of said first memory or said second memory is inputted to a display through said second switch.

2. A display device according toclaim 1,

wherein said memory is implemented on FPC.

3. A display device according toclaim 1,

wherein said memory is implemented over a substrate.

4. An electronic device comprising the display device ofclaim 1.

Images