CROSS REFERENCE TO RELATED APPLICATIONThis application claims the benefit of prior filed co-pending Provisional Application No. 60/880,625 filed on Jan. 16, 2007 entitled “Line Card Power Management” (Attorney Docket: VELCP072P) which is incorporated herein by reference in its entirety as if fully set forth herein.
BACKGROUND OF THE INVENTION1. Field of Invention The field of the present invention relates to multi-tone transceivers.
2. Description of the Related Art
In a digital multi-tone (DMT) based digital subscriber line (DSL) systems (such as ADSL, ADSL2, ADSL2+, VDSL1, VDSL2), the central office (CO) of the telephone company typically includes racks of line cards each servicing many subscriber lines. Each line card includes many chips handling the digital and analog portions of communications over the subscriber lines. The power consumption will scale with the number of subscriber lines or ports which the line card is driving. What is needed is a method for reducing power consumption in XDSL line cards.
SUMMARY OF THE INVENTIONA method and apparatus for power management of one or more XDSL line cards is disclosed. Each line card is configured to couple to many digital subscriber lines to support multi-tone modulation of communications channels thereon. In an embodiment of the invention a line card is disclosed which includes an allocator for allocating power to the multi-tone modulated communications on each of the subscriber lines and for selecting control parameters sufficient to effect communications on each of the plurality of subscriber lines at a power level proximate to an allocated power level therefore. The line card also includes configurable components coupled to one another to form a transmit path and a receive path to couple to the digital subscriber lines. The configurable components are responsive to the control parameters selected by the allocator to initialize multi-tone communications over each of the subscriber lines at a power level proximate the allocated power level.
In an alternate embodiment of the invention a line card power management system for line cards configured to couple to digital subscriber lines to support multi-tone modulation of communications channels thereon is disclosed. The line card power management system includes an allocator and at least one line card having a plurality of configurable components. The allocator allocates power to the multi-tone modulated communications of the digital subscriber lines, and selects control parameters sufficient to effect communications on each of the digital subscriber lines at a power level proximate to an allocated power level therefore. The at least one line card is coupled to the allocator and includes a plurality of configurable components coupled to one another to form a transmit path and a receive path configured to couple to associated ones of the digital subscriber lines. The plurality of configurable components are responsive to the control parameters selected by the allocator to initialize multi-tone communications over each of the associated ones of digital subscriber lines at a power level proximate the allocated power level.
In an alternate embodiment of the invention a method for power management of at least one line card configured to support multi-tone communications over digital subscriber lines is also disclosed. The method comprises:
- identifying a number of digital subscriber lines coupled to the at least one line card;
- determining a total power available to the at least one line card for communications over the digital subscriber lines identified in the identifying act;
- allocating power to the at least one line card based at least on a number of digital subscriber lines coupled thereto; and
- initializing each subscriber line at a power level allocated in the allocating act.
BRIEF DESCRIPTION OF THE DRAWINGSThese and other features and advantages of the present invention will become more apparent to those skilled in the art from the following detailed description in conjunction with the appended drawings in which:
FIG. 1 is a system diagram of an XDSL communication system servicing homes and businesses from a central office;
FIG. 2 is a hardware block diagram showing an embodiment of the line cards of the current invention in the central office shown inFIG. 1.
FIG. 3 is a detailed hardware block diagram of an embodiment of a portion of one of the line cards shown inFIG. 2;
FIGS. 4A-4B show data structures maintained by different embodiments of the global power allocator for all line cards as shown inFIG. 2;
FIG. 5A shows a data structure maintained by an embodiment of the local power allocator of a line card as shown inFIGS. 2-3;
FIGS. 5B-5C show a data structure maintained by an embodiment of power optimizers shown inFIGS. 2-3;
FIG. 6 is a process flow diagram of an embodiment of the processes performed by the global and or local power allocators shown inFIGS. 2-3; and
FIG. 7 is a process flow diagram of an embodiment of the processes performed by the power optimizers shown in the line cards ofFIGS. 2-3.
DETAILED DESCRIPTION OF THE EMBODIMENTSA method and apparatus for power management of one or more XDSL line cards is disclosed. The line cards may be found in a central office, remote access terminal, business or home. The line cards may be coupled directly or indirectly to digital subscriber lines via one or more optical or wireless links. The line cards support communication channels with differing degrees of robustness for multi-tone protocols including: asymmetric digital subscriber line (ADSL); very high bit rate digital subscriber line (VDSL) and other orthogonal frequency division multiplexing (OFDM) plans including but not limited to the following:
| TABLE 1 |
|
| | Downstream | Upstream |
| Standard name | Common name | rate | rate |
|
|
| ANSI T1.413-1998 | ADSL | 8 | Mbit/s | 1.0 | Mbit/s |
| Issue |
| 2 |
| ITU G.992.1 | ADSL (G.DMT) | 8 | Mbit/s | 1.0 | Mbit/s |
| ITU G.992.1 Annex A | ADSL over POTS | 8 | Mbit/s | 1.0 | MBit/s |
| ITU G.992.1 Annex B | ADSL over ISDN | 8 | Mbit/s | 1.0 | MBit/s |
| ITU G.992.2 | ADSL Lite (G.Lite) | 1.5 | Mbit/s | 0.5 | Mbit/s |
| ITU G.992.3/4 | ADSL2 | 12 | Mbit/s | 1.0 | Mbit/s |
| ITU G.992.3/4 | ADSL2 | 12 | Mbit/s | 3.5 | Mbit/s |
| Annex J |
| ITU G.992.3/4 | RE-ADSL2 | 5 | Mbit/s | 0.8 | Mbit/s |
| Annex L |
| ITU G.992.5 | ADSL2+ | 24 | Mbit/s | 1.0 | Mbit/s |
| ITU G.992.5 | RE-ADSL2+ | 24 | Mbit/s | 1.0 | Mbit/s |
| Annex L[1] |
| ITU G.992.5 Annex M | ADSL2+M | 24 | Mbit/s | 3.5 | Mbit/s |
| ITU G.993.1 | VDSL |
| ITU G.993.2 | VDSL 2 |
| IEEE 802.16e | WiMax |
| IEEE 802.20 | Mobile Broadband | 1 | Mbit/s | 1 | Mbit/s |
| Wireless Access |
|
FIG. 1 is a system diagram of an XDSL communication system in which individual subscribers are coupled across public service telephone network (PSTN) subscriber lines with one or more high speed networks. Telephone company's central offices (CO)100,102,106 andremote access terminal104 are shown coupling various subscribers to one another and to ahigh speed network140. Thehigh speed network140 provides fiber optic links between the central office and remote access terminal. CO's100-102 are coupled to one another via fiberoptic link142.CO102 couples toremote access terminal104 via fiberoptic link146. CO also couples to subscribersite122 via fiberoptic link144.CO102 andCO106 couple to one another via a wireless link provided by correspondingwireless transceivers130 and132 respectively. The “last mile” connecting each subscriber, (except subscriber122) is provided by twisted copper PSTN telephone lines. On these subscriber lines voice band and data communication are provided. The data communication is shown as various X-DSL protocols including G.Lite, ADSL VDSL, and HDSL2.CO100 is coupled via G.Lite and ADSL modulatedsubscriber line connections160 withsubscribers110 and112.CO100 is also coupled via G.Lite and ADSL modulatedsubscriber line connections162 withsubscriber114.CO106 is also coupled via a subscriber line tosubscriber134. Remote access terminal is coupled viasubscriber line connections164 withsubscribers120. In each CO or remote access terminal one or more line cards including power allocation features in accordance with the current invention may advantageously be provided with the added benefit of decreased power consumption and an increased port count. The apparatus and method of the current invention is suitable for handling power allocation and optimization on any of these subscriber lines.
FIG. 2 is a hardware block diagram showing an embodiment of the line cards of the current invention in a representative one of the central offices shown inFIG. 1 including both digital subscriber line access modules (DSLAMs) and PSTN voice band modules. TheCO100 includes subscriber line connections to subscribers110-114. Each of these connections terminates in theframe room208 of the CO. From this room connections are made for each subscriber line via splitters and hybrids to both aDSLAM206 and to the voice band racks242. The splitter shunts voice band communications to dedicated line cards,e.g. line card220 or to a voice band modem pool (not shown). The splitter shunts higher frequency X-DSL communications on the subscriber line to a selectedline card220 withinDSLAM206. The line cards of the current invention are universal, meaning they can handle any current or evolving standard of X-DSL and may be upgraded on the fly to handle new standards.
Voice band call set up between subscribers on the public switched telephone network (PSTN)240 is controlled by aTelco switch matrix244 implementing a switching protocol such as the common channel signaling system 7 (SS7) for setting up and tearing down a connection via an associated one of the voice band line cards,e.g. line card246. This makes point-to-point connections to other subscribers for voice band communications. The X-DSL communications may be processed by a universal line card such asline card220. That line card includes a plurality of AFE's e.g.232-234 each capable of supporting a plurality of subscriber lines. The AFEs may be coupled directly or as in this embodiment of the invention via a packet basedbus230 to aDSP222 which is also capable of multi-protocol support for all subscriber lines to which the AFE's are coupled. The line card may include more than one DSP. Power allocation between line cards and among the subscriber lines to which each line card is coupled is handled by aglobal power allocator204 and optional local power allocators, e.g.local power allocator224, on each line card. The line card itself is coupled to a back-plane bus210 which may in an embodiment of the invention be capable of offloading and transporting low latency X-DSL traffic between other DSPs for load balancing. Communications between AFE's and DSP(s) are in an embodiment of the invention packet based which allows a distributed architecture such as will be set forth in the followingFIG. 3 to be implemented. Each of the DSLAM line cards operates under the control of aDSLAM controller202 which handles global provisioning, e.g. allocation of subscriber lines to AFE and DSP resources. Once an X-DSL connection is established between the subscriber and a selected one of the DSLAM sub modules, e.g. AFE and DSP, the subscriber will be able to access any network, e.g. theInternet140, to which the DSLAM is connected.
FIG. 3 is a detailed hardware block diagram of an embodiment of a portion of one of the line cards shown inFIG. 2 in which multiple analog front end (AFE) chips232-234 connect with one or more digital signal processing (DSP) chips, e.g. DSP,222 acrossbus230. In an alternate embodiment of the invention each AFE has separate ports for each subscriber line connection which are coupled directly to an associated port of the corresponding DSP, thereby obviating the need for a bus. These digital and analog chips are all mounted on theline card220 shown inFIG. 2. A single line card may currently support 64 to 128 ports each handling communications of an associated one of the digital subscriber lines. In the embodiment of the line card shown inFIG. 3, packets of raw data are shown being transported between the DSP and AFEs as well as within each DSP and AFE. Packet processing between the DSP and AFE chips involves transfer ofbus packets300. Packet processing within a DSP may involvedevice packets306. Packet processing within an AFE may involveraw data packets302. These will be discussed in the following text. In this embodiment of the invention, alocal power allocator224 is coupled to the DSP and through it to the AFEs to control power allocation for communications over each subscriber line services by the line card. In an alternate embodiment of the invention the global allocator204 (SeeFIG. 2) would directly couple to the DSP(s) on each line card and through them to the associated AFEs to control power allocation on a pro rata basis per digital subscriber line.
These modules, AFE and DSP, may be found on a single universal line card, such asline card220 inFIG. 2. They may alternately be displaced from one another on separate line cards linked by a DSP bus. In still another embodiment they may be found displaced from one another across an ATM network. There may be multiple DSP chipsets on a line card. In an embodiment of the invention the DSP and AFE chipsets may include structures set forth in the figure for handling of multiple line codes and multiple channels.
TheDSP chip222 includes an upstream (receive) and a downstream (transmit) processing path with both discrete and shared modulation and demodulation modules or components. The components are configurable on the fly to process each packet of data in a manner consistent with the characteristics of the corresponding subscriber line over which the packet will be transported, the assigned modulation protocol for that line and the service level assigned to the subscriber. The data rates of various components on the transmit and receive path are governed by one or more data clocks322. The modules or components may be implemented in hardware, firmware or software without departing from the scope of the claimed invention. In an embodiment of the invention selected ones of the modules are responsive to packet header information and/or control information to vary their processing of each packet to correspond with the X-DSL protocol and line code and channel which corresponds with the packet contents. Data for each of the channels is passed along either path in discrete packets the headers of which identify the corresponding channel and may additionally contain channel specific control instructions for various of the shared and discrete components along either the transmit or receive path.
On the upstream path, upstream packets containing digital data from various of the subscribers is received by the DSP medium access control (MAC)334 which handles packet transfers to and from the DSP bus. The MAC couples with a packet assembler/disassembler (PAD)332. For upstream packets, the PAD handles removal of the DSPbus packet header304 and the packaging of thedata312 into adevice packet306 which includes adevice header308 and acontrol header310. The content of these headers is generated by thecore processor326 using information downloaded from the DSLAM controller202 (SeeFIG. 2) as well as statistics such as gain tables gathered by the de-framer358, or embedded operations channel communications from the subscriber side. The processing rate of the core processor is determined byprocess clock324. These channel specific andcontrol parameters330 are stored inmemory328 which is coupled to the core processor. ThePAD332 embeds the required commands generated by the core processor in the header or control portions of the device packet header of the upstream data packets. The upstream packets may collectively include data from multiple channels each implementing various ones of the X-DSL protocols. Thus the header of each device packet identifies the channel corresponding with the data contained therein. Additionally, a control portion of the packet may, in an embodiment of the invention, include specific control instructions for any of the discrete or shared components which make up the upstream or downstream processing paths.
Upstream processing in the DSP begins with the removal of the cyclic prefix/suffix inmodule348. Next in the discrete Fourier transform module (DFT)350 received data from each subscriber line is transformed from the time to the frequency domain. In this embodiment of the invention, the information in the header of the packet is used to maintain channel identity of the data as it is demodulated. The DFT is responsive to the header information in each packet to setup the transform with the appropriate parameters for that channel, e.g. sample size, and to provide channel specific instructions for the demodulation of the data. The demodulated data is passed as a packet to the next component in the upstream path, i.e. the frequency error corrector (FEQ)352. Next constellation decoding, including Viterbi decoding, takes place incomponent354. Then the tones are reordered in the tone reorderer356 and deframed in the deframer andReed Solomon decoder358. This component reads each device packet header and processes the data in it in accordance with the instructions or parameters in its header. The demodulated, decoded and de-framed data is passed toPAD316. InPAD316 the device packet header is removed and the demodulated data contained therein is wrapped with an asynchronous transfer mode (ATM) or other network header and passed to the medium access control (MAC)314 for transmission over the ATM or other network to which the line card is coupled (SeeFIGS. 1-2).
On the downstream path, downstream packets containing digital data destined for various subscribers is received by theMAC314 and passed to thePAD316 where the ATM or other header is removed and thedownstream device packet306 is assembled. Using header content generated by thecore processor326 the PAD assembles data from the ATM or other network into channel specific packets each with theirown header308,data312 and control310 portions. The downstream packets are then passed to the Framer and Reed Solomon encoder336 where they are processed in a manner consistent with the control and header information contained therein. From the framer packets are subject to tone ordering in the tone orderer338 and to constellation encoding, including trellis encoding, in theconstellation encoder340. Gain scaling is performed in thegain scaler342. Next downstream packets are passed to the inverse discrete Fourier transform component/module344 for transformation from the frequency to the time domain. The setup of the IDFT is re-configured on the fly to match the requirements assigned to each packets corresponding channel or subscriber line. Next, each downstream packet with the modulated data contained therein is then passed to thePAD332. In thePAD332 the device packet header and control portions are removed, and aDSP bus header304 is added to thedata302. This header identifies the specific channel and may additionally identify the sending DSP, the target AFE, the packet length and such other information as may be needed to control the receipt and processing of the packet by the appropriate AFE. The packet is then passed to theMAC334 for placement on theDSP bus230 for transmission to the appropriate AFE.
In this embodiment of the invention each DSP includes one or more power monitors318 to measure overall power consumption of the DSP or discrete power consumption associated with communications over each subscriber line or port. In various embodiments of the invention the power monitor may be implemented thermally, inductively, or resistively. The DSP in this embodiment of the invention also includes apower optimizer320. The power optimizer is coupled directly or via thecore processor326 to selected configurable components on the transmit and receive path to optimize power consumption for each subscriber line at the assigned data rate. The power optimizer may operate during either or both the training or showtime phase of each communication channel or subscriber line's operation.
FIG. 3 also shows a more detailed view of the processing of upstream and downstream packets within theAFE234. In the embodiment of the invention shown, device packets are not utilized in the AFE. Instead, channel and protocol specific processing of each packet is implemented using control information for each channel stored in memory at session setup. EachAFE chip234 includes an upstream (receive) and a downstream (transmit) processing path with both discrete and shared modulation and demodulation modules or components. The components are configurable on the fly to process each packet of data in a manner consistent with the characteristics of the corresponding subscriber line over which the packet will be transported, the assigned modulation protocol for that line and the service level assigned to the subscriber. The data rates of various components on the transmit and receive path are governed by one or more data clocks368.
Downstream packets from the DSP are pulled off thebus230 by the corresponding AFE MAC,e.g. MAC360, on the basis of information contained in the header portion of that packet. Each downstream packet is passed toPAD362 which removes theheader304 and sends it to thecore processor372. The core processor matches the information in the header withchannel control parameters376 contained inmemory374. These control parameters may have been downloaded to the AFE at session setup. The processing rate of the core processor is determined byprocess clock370. Theraw data302 portion of the downstream packet is passed to interpolator andfilter378. The interpolator up-samples the data and low pass filters it to reduce the noise introduced by the DSP. Implementing interpolation in the AFE as opposed to the DSP has the advantage of lowering the bandwidth requirements of theDSP bus230. From the interpolator data is passed to a digital-to-analog converter (DAC)380 which processes each channel in accordance with commands received from thecore processor372 using the control parameters downloaded to the control table376 during channel setup. The analog output of the DAC is passed viaanalog mux382 to a corresponding one of sample and hold devices and analog filters384. Each sample and hold and filter is associated with a corresponding subscriber line. The sampled data may be amplified byline amplifiers386. The parameters for each of these devices, i.e. filter coefficients, amplifier gain etc. are controlled by the core processor using the above discussedcontrol parameters376. For example, where successive downstream packets carry downstream channels each of which implements different protocols, e.g. G.Lite, ADSL, and VDSL the sample rate of theanalog mux382 the filter parameters for the corresponding filter and the gain of the corresponding one ofanalog amplifiers386 will vary for each packet. This “on the fly” configurability allows a single downstream pipeline to be used for multiple concurrent protocols.
On the upstream path many of the same considerations apply. Individual subscriber lines couple toindividual line amplifiers388 through splitter and hybrids (not shown). Each channel is passed through analog filters and sample and holdmodules390 and dedicated analog-to-digital conversion (ADC) modules392-394. As discussed above in connection with the downstream/transmit path, each of these components is configured on the fly for each new packet depending on the protocol associated with it. From each ADC fixed amounts of data for each channel, varying depending on the bandwidth of the channel, are processed by the decimator andfilter module396. The amount of data processed for each channel is determined in accordance with theparameters376 stored inmemory374. Those parameters may be written to that table during the setup phase for each channel.
From the decimator and filter the rawupstream data302 is passed toPAD362 during each bus interval. The PAD wraps the raw data in aDSP header304 with channel ID and other information which allows the receiving DSP(s) to properly process it. The upstream packet is placed on the bus by theMAC360. A number of protocols may be implemented on the bus216. In an embodiment of the invention the DSP operates as a bus master governing the pace of upstream and downstream packet transfer and the AFE utilization of the bus.
In this embodiment of the invention each AFE includes one or more power monitors364 to measure overall power consumption of the DSP or discrete power consumption associated with communications over each subscriber line or port. In various embodiments of the invention the power monitor may be implemented thermally, inductively, or resistively. The DSP in this embodiment of the invention also includes apower optimizer366. The power optimizer is coupled directly or via thecore processor372 to selected configurable components on the transmit and receive path to optimize power consumption for each subscriber line at the assigned data rate. The power optimizer may operate during either or both the training or showtime phase of each communication channel or subscriber line's operation.
FIGS. 4A-4B show data structures maintained by different embodiments of theglobal power allocator204 for all line cards as shown inFIG. 2. The global allocator maintains records for each line card and associated subscriber lines which allow for intelligent power allocation among the subscriber lines. In the embodiment shown inFIG. 4A theserecords400 include: minimum service requirements such as service level and quality of service and data type; XDSL protocol and band plan; line characteristics such as loop length line length, available bandwidth, and interference; control and or operational parameters such as sampling rate, data rate, processing rate, power spectral density, codeword size, #of sub-channels or tones, etc; and allocated and actual power consumption for each line The per line breakdown of actual power per line on the type of power monitoring available and may in an embodiment of the invention be based on the incremental change in power requirements as each line is initialized, dropped, or re-initialized. The records are updated through feedback from the local power allocator on each line card and the power monitors, the power optimizers, and the core processor to which it is directly or indirectly coupled. As lines are initialized the corresponding actual power consumption record is updated to reflect the actual power required to drive communications on the corresponding subscriber line.FIG. 4B shows an alternateabbreviated record format420 maintained by the global power allocator in an alternate embodiment of the invention in which more detailed records are maintained exclusively by the local power allocators on each line card.
FIG. 5A shows adata structure500 maintained by an embodiment of the local power allocator, e.g.local power allocator224 ofline card220 shown inFIGS. 2-3. The records correspond to those discussed above in connection withFIG. 4A. In alternate embodiments of the invention the global power allocator couples directly to the DSP(s) on each line card to control power allocation for each channel and associated subscriber line, thus obviating the need for a local power allocator.
FIGS. 5B-5C show a data structure maintained by an embodiment ofpower optimizers320,366 shown online card220 inFIGS. 2-3. Each power optimizer is coupled directly or via the core processor of the associated DSP or AFE to selected configurable components on the transmit and receive path to optimize power consumption for each subscriber line at the assigned data rate. The power optimizer may operate during either or both the training or showtime phase of each communication channel or subscriber line's operation. The power optimizer utilizesrecords510 shown inFIG. 5B which correlate power and data rate with the performance parameters of various configurable components in the transmit and receive path. The components shown inrecords510 include: data and process clocks, DAC and ADC sampling rates, FFT tones, Reed Solomon codeword size, power spectral density masks and band plans. These correlations may be updated by the power optimizer during operation to increase their accuracy and allow for fine optimizations of power required to maintain an initial data rate assigned to XDSL communications over a given subscriber line. The optimizer maintains a setup table520 shown inFIG. 5C showing detailed component operational/control parameters for each channel and associated subscriber line. During operation these parameters may be feedback to the local allocator which in turn may update the corresponding records in the global allocator.
FIG. 6 is a process flow diagram of an embodiment of the processes performed by the global and or local power allocators shown inFIGS. 2-3. Processing begins atstartup600 in which the total power available to each line card of cabinet is specified. Next inprocess602 power allocations for each subscriber line are set on a pro-rata basis using aggregate and separate factors for each line to assure that the total power consumed by the associated line card(s) does not exceed an established limit. Aggregate factors include: the number of lines, the number of active lines, the number of inactive lines. Separate factors include: line length, modulation protocol, service level, quality of service, data type, data rate, bandwidth, band plan, # tones, sampling rate, clock rates, codeword sizes etc. These parameters are used to initialize the line card XDSL communications over each subscriber line.
Indecision process604 power allocations are subject to revision as each line is initialized and control is passed todecision process606. In decision process606 a determination is made as to whether the actual power consumed for the initialized line is equal to the budgeted power. If it is not, then control passes to process608 for an update of the corresponding record in the power allocation table and for a pro-rata increase or decrease in the power allocated to remaining non-initialized lines. Control in either case then passes todecision process610 for a determination as to the initialization of XDSL communications on all subscriber lines. If lines remain to be initialized the control returns todecision process604. Once all lines are initialized control passes to process612.
The performance parameters for all initialized lines are checked inprocess612. This check assures that the last initialized lines have sufficient power to meet their service requirements and that the first initialized lines are not consuming more power than required. Next in decision process622 a determination is made as to whether a targeted retraining is warranted. The targeted retraining may be triggered when one or more lines has suboptimal performance brought about by a power deficit, in which event the retraining may also target a line having a power surplus a reduction of power consumption by which on retraining will be used to supply the requisite power. Alternately, the targeted retraining may be triggered when one or more lines has a power surplus above that required to meet the required service level and data rate. If retraining is required control passes to process624 in which retraining of targeted lines is initiated, after which control returns to process602 for a re-allocation of power to associated records of the targeted subscriber lines.
Intermediate process612 anddecision process622 is anoptimization decision block614. The optional decision block is present in embodiments of the invention which include one or more power optimizers in the line card. If there is such a module then control passes todecision process616, in which feedback from the optimizer is detected. That feedback involves the identification of a channel or subscriber line and a power surplus for same as determined by the power optimizer. In an embodiment of the invention with autonomous power optimizers, the surplus may already have been established by the optimizer by reducing the power consumption of the XDSL communications over the associated subscriber line. In other embodiments of the invention the surplus identified by the optimizer may be prospective only, and may require retraining to take effect. In any event, the appropriate adjustment is made to the associated record in the power allocator and control then passes todecision process622 for a targeted retraining decision as discussed above.
FIG. 7 is a process flow diagram of an embodiment of the processes performed by the power optimizers shown in the line cards ofFIGS. 2-3. Each power optimizer optimizes power consumption for each subscriber line at the assigned data rate. The power optimizer may operate during either or both the training or showtime phase of each communication channel or subscriber line's operation. The power optimizer correlate power and data rate with the performance parameters of various configurable components in the transmit and receive path the adjustment of which during initialization or showtime reduces power consumption at the assigned data rate.
Afterstartup700 control passes todecision process702 in which a determination is made as to the onset of optimization for a next subscriber line. Control passes next to process704 in which the allocated power usage for that line is compared to the actual power usage as determined by information obtained from the power monitor. If actual power usage is substantially less than allocated then the lines power consumption may be optimal and control returns to decision process for the processing of the next line. Alternately, if actual power is proximate or greater than the allocated power than the line may benefit from power optimization and control passes to process708. Inprocess708 the power optimizer analyzes current transmit and receive path component setup parameters versus various alternate power optimization settings gleaned from its power optimization records (SeeFIG. 5B, reference510). In an embodiment of the invention in which the power optimizer operates autonomously, it then makes the requisite adjustments to the setup parameters of selected ones of the transmit and receive path components. It then stores the current and prior setup parameters inprocess712 and inprocess714 determines the actual or prospective power surplus realized thereby. This optimization information is then sent to the power allocator for updating its power allocation records.
The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously many modifications and variations will be apparent to practitioners skilled in this art. It is intended that the scope of the invention be defined by the following claims and their equivalents.