US20080121879A1 - High density integrated circuit apparatus, test probe and methods of use thereof - Google Patents

Abstract

The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving mi array of wires disposed in the elastomer and in electrical contact with the space transformer. The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

Description

FIELD OF THE INVENTION
• This invention relates to an apparatus and test probe for integrated circuit devices and methods of use thereof.
BACKGROUND OF THE INVENTION
• In the microelectronics industry, before integrated circuit (IC) chips are packaged in an electronic component, such as a computer, they are tested. Testing is essential to determine whether the integrated circuit's electrical characteristics conform to the specifications to which they were designed to ensure that electronic component performs the function for which it was designed.
• Testing is an expensive part of the fabrication process of contemporary computing systems. The functionality of every I/O for contemporary integrated circuit must be tested since a failure to achieve the design specification at a single I/O can render an integrated circuit unusable for a specific application. The testing is commonly done both at room temperature and at elevated temperatures to test functionality and at elevated temperatures with forced voltages and currents to burn the chips in and to test the reliability of the integrated circuit to screen out early failures.
• Contemporary probes for integrated circuits are expensive to fabricate and are easily damaged. Contemporary test probes are typically fabricated on a support substrate from groups of elongated metal conductors which fan inwardly towards a central location where each conductor has an end which corresponds to a contact location on the integrated circuit chip to be tested. The metal conductors generally cantilever over an aperture in the support substrate. The wires are generally fragile and easily damage and are easily displaceable from the predetermined positions corresponding to the design positions of the contact locations on the integrated circuit being tested. These probes last only a certain number of testing operations, after which they must be replaced by an expensive replacement or reworked to recondition the probes.
• FIG. 1 shows a side cross-sectional view of a priorart probe assembly2 for probingintegrated circuit chip4 which is disposed onsurface6 of support member8 forintegrated circuit chip4.Probe assembly2 consists of adielectric substrate10 having acentral aperture12 therethrough. Onsurface14 ofsubstrate10 there are disposed a plurality of electrically conducting beams which extend towardsedge18 ofaperture12.Conductors16 haveends20 which bend downwardly in a direction generally perpendicular to the plane ofsurface14 ofsubstrate10.Tips22 of downwardly projecting electrically conductingends20 are disposed in electrical contact with contact locations24 onsurface25 of integratedcircuit chip4.Coaxial cables26 bring electrical signals, power and ground throughelectrical connectors28 atperiphery30 ofsubstrate10.Structure2 ofFIG. 1 has the disadvantage of being expensive to fabricate and of having fragileinner ends20 ofelectrical conductors16. Ends20 are easily damaged through use in probing electronic devices. Since theprobe2 is expensive to fabricate, replacement adds a substantial cost to the testing of integrated circuit devices.Conductors16 were generally made of a high strength metal such as tungsten to resist damage from use. Tungsten has an undesirably high resistivity.
SUMMARY OF THE INVENTION
• It is an object of the present invention to provide an improved high density test probe, test apparatus and method of use thereof.
• It is another object of the present invention to provide an improved test probe for testing and burning-in integrated circuits.
• It is another object of the present invention to provide an improved test probe and apparatus for testing integrated circuits in wafer form and as discrete integrated circuit chips.
• It is an additional object of the present invention to provide probes having contacts which can be designed for high performance functional testing and for high temperature burn in applications.
• It is yet another object of the present invention to provide probes having contacts which can be reworked several times by resurfacing some of the materials used to fabricate the probe of the present invention.
• It is a further object of the present invention to provide an improved test probe having a probe tip member containing a plurality of elongated conductors each ball bonded to electrical contact locations on space transformation substrate.
• A broad aspect of the present invention is a test probe having a plurality of electrically conducting elongated members embedded in a material. One end of each conductor is arranged for alignment with contact locations on a workpiece to be tested.
• In a more particular aspect of the present invention, the other end of the elongated conductors are electrically connected to contact locations on the surface of a fan-out substrate. The fan-out substrate provides space transformation of the closely spaced electrical contacts on the first side of the fan-out substrate. Contact locations having a larger spacing are on a second side of the fan out substrate.
• In yet another more particular aspect of the present invention, pins are electrically connected to the contact locations on the second surface of the fan out substrate.
• In another more particular aspect of the present invention, the plurality of pins on the second surface of the fan-out substrate are inserted into a socket on a second fan-out substrate. The first and second space transformation substrates provide fan out from the fine pitch of the integrated circuit I/O to a larger pitch of electrical contacts for providing signal, power and ground to the workpiece to be tested.
• In another more particular aspect of the present invention, the pin and socket assembly is replaced by an interposer containing a plurality of elongated electrical connectors embedded in a layer of material which is squeezed between contact locations on the first fan-out substrate and contact locations on the second fan-out substrate.
• In another more particular aspect of the present invention, the test probe is part of a test apparatus and test tool.
• Another broad aspect of the present invention is a method of fabricating the probe tip of the probe according to the present invention wherein a plurality of elongated conductors are bonded to contact locations on a substrate surface and project away therefrom.
• In a more particular aspect of the method according to the present invention, the elongated conductors tire wire bonded to contact locations on the substrate surface. The wires project preferably at a nonorthogonal angle from the contact locations.
• In another more particular aspect of the method of the present invention, the wires are bonded to the contact locations on the substrate are embedded in a elastomeric material to form a probe tip for the structure of the present invention.
• In another more particular aspect of the present invention, the elongated conductors are embedded in an elastomeric material.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a schematic cross-section of a conventional test probe for an integrated circuit device.
• FIG. 2 is a schematic diagram of one embodiment of the probe structure of the present invention.
• FIG. 3 is a schematic diagram of another embodiment of the probe structure of the present invention.
• FIG. 4 is an enlarged view of an elastomeric connector electrically interconnecting two space transformation substrates of the structure ofFIG. 2.
• FIG. 5 is an enlarged view of the probe tip within dashedcircle100 ofFIGS. 2 or3.
• FIG. 6 shows the probe tip of the structure ofFIG. 5 probing an integrated circuit device.
• FIGS. 7-13 show the process for making the structure ofFIG. 5.
• FIG. 14 shows a probe tip structure without a fan-out substrate.
• FIG. 15 shows the elongated conductors of the probe tip fixed by solder protuberances to contact locations on a space transformation substrate.
• FIG. 16 shows the elongated conductors of the probe tip fixed by laser weld protuberances to contact locations on a space transformation substrate.
• FIG. 17 shows bothinterposer76 andprobe tip40 rigidly bonded tospace transformer60.
DETAILED DESCRIPTION
• Turning now to the figures,FIGS. 2 and 3 show two embodiments of the test assembly according to the present invention. Numerals common betweenFIGS. 2 and 3 represent the same thing.Probe head40 is formed from a plurality of elongated electrically conductingmembers42 embedded in amaterial44 which is preferably anelastomeric material44. The elongated conductingmembers42 haveends46 for probing contact locations on integratedcircuit devices48 ofwafer50. In the preferred embodiment, the workpiece is an integrated circuit such as a semiconductor chip or a semiconductor wafer having a plurality of chips. The workpiece can be any other electronic device. The opposite ends52 of elongatedelectrical conductors42 are in electrical contact with space transformer (or fan-out substrate)54. In the preferred embodiment,space transformer54 is a multilevel metal/ceramic substrate, a multilevel metal/polymer substrate or a printed circuit board which are typically used as packaging substrates for integrated circuit chips.Space transformer54 has, in the preferred embodiment, asurface layer56 comprising a plurality of thin dielectric films, preferably polymer films such as polyimide, and a plurality of layers of electrical conductors, for example, copper conductors. A process for fabricatingmultilayer structure56 for disposing it onsurface58 ofsubstrate60 to form aspace transformer54 is described in U.S. patent application Ser. No. 07/695,368, filed on May 3, 1991, entitled “MULTI-LAYER THIN FILM STRUCTURE AND PARALLEL PROCESSING METHOD FOR FABRICATING SAME” which is assigned to the assignee of the present invention, the teaching of which is incorporated herein by reference. Details of the fabrication ofprobe head40 and of the assembly ofprobe head40 and54 will be described herein below.
• As shown inFIG. 2, onsurface62 ofsubstrate60, there are, a plurality ofpins64.Surface62 is opposite the surface57 on whichprobe head40 is disposed.
• Pins64 are standard pins used on integrated circuit chip packaging substrates.Pins64 are inserted intosocket66 or plated through-holes in thesubstrate68 which is disposed onsurface70 ofsecond space transformer68.Socket66 is a type of pin grid array (PGA) socket such as commonly disposed on a printed circuit board of an electronic computer for receiving pins from a packaging substrate.Second space transformer68 can be any second level integrated circuit packaging substrate, for example, a standard printed circuit board.Socket66 is disposed onsurface70 ofsubstrate68. Onopposite surface70 ofsubstrate68 there are disposed a plurality of electrical connectors to whichcoaxial cables72 are electrically connected. Alternatively,socket68 can be a zero insertion force (ZIF) connector or thesocket68 can be replaced by through-holes in thesubstrate68 wherein the through-holes have electrically conductive material surrounding the sidewalks such as a plated through-hole.
• In the embodiment ofFIG. 3, thepin64 andsocket66 combination of the embodiment ofFIG. 2 is replaced by an interposer, such as,elastomeric connector76. The structure ofelastomeric connector76 and the process for fabricatingelastomeric connector76 is described in copending U.S. patent application Ser. No. 07/963,364 to B. Beaman et al., filed Oct. 19, 1992, entitled “THREE DIMENSIONAL HIGH PERFORMANCE INTERCONNECTION MEANS”, which is assigned to the assignee of the present invention, the teaching of which is incorporated herein by reference and of which the present application is a continuation-in-part thereof, the priority date of the filing thereof being claimed herein. The elastomeric connector can be opted to have one end permanently bonded to the substrate, thus forming a FRU (field replacement unit) together with the probe/substrate/connector assembly.
• FIG. 4 shows a cross-sectional view of structure of theelastomeric connector76 ofFIG. 3.Connector76 is fabricated of preferablyelastomeric material78 having opposing, substantially parallel andplanar surfaces80 and82. Throughelastomeric material78, extending fromsurface81 to83 there are a plurality of elongatedelectrical conductors85. Elongatedelectrical conductors84 are preferably at a nonorthogonal angle tosurfaces81 and83.Elongated conductors85 are preferably wires which haveprotuberances86 atsurface81 ofelastomeric material layer78 and flattenedprotuberances88 atsurface83 ofelastomeric material layer78. Flattenedprotuberances88 preferably have a projection on the flattened surface as shown for the structure ofFIG. 14.Protuberance86 is preferably spherical and flattenedprotuberance88 is preferably a flattened sphere.Connector76 is squeezed betweensurface62 ofsubstrate54 andsurface73 ofsubstrate68 to provide electrical connection betweenend88 ofwires85 andcontact location75 onsurface73 ofsubstrate68 and betweenend88 orwires85 andcontact location64 onsurface62 ofsubstrate54.
• Alternatively, as shown inFIG. 17,connector76 can be rigidly attached tosubstrate54 by solder bonding ends88 ofwires85 topads64 onsubstrate54 or by wire bonding ends86 ofwires85 topads64 onsubstrate54 in the same manner thatwires42 are bonded topads106 as described herein below with respect toFIG. 5.Wires85 can be encased in an elastomeric material in the same manner aswires42 ofFIG. 5.
• Space transformer54 is held in place with respect tosecond space transformer68 by clampingarrangement80 which is comprised ofmember82 which is perpendicularly disposed with respect to surface70 ofsecond space transformer68 andmember84 which is preferably parallely disposed with respect to surface86 offirst space transformer54.Member84 presses against surface87 ofspace transformer54 to holdspace transformer54 in place withrespect surface70 ofspace transformer64. Member S2 of clampingarrangement80 can be held in place with respect to surface70 by a screw which is inserted throughmember84 atlocation90 extending through the center ofmember82 and screw intosurface70.
• The entire assembly ofsecond space transformer68 and first space transformer withprobe head40 is held in place withrespect wafer50 byassembly holder94 which is part of an integrated circuit test tool or apparatus.Members82,84 and90 can be made from materials such as aluminum.
• FIG. 5 is a enlarged view of the region ofFIGS. 2 or3 closed in dashedcircle100 which shows the attachment ofprobe head40 tosubstrate60 ofspace transformer54. In the preferred embodiment,elongated conductors42 are preferably wires which are at a non-orthogonal angle with respect to surface87 ofsubstrate60. Atend102 ofwire42 there is preferably a flattenedprotuberance104 which is bonded (by wire bonding, solder bonding or any other known bonding technique) to electrically conductingpad106 on surface87 ofsubstrate60.Elastomeric material44 is substantially flush against surface87. At substantially oppositely disposedplanar surface108 elongated electrically conductingmembers42 have anend110. In the vicinity ofend110, there is optimally acavity112surrounding end110. The cavity is atsurface108 in theelastomeric material44.
• FIG. 6 shows the structure ofFIG. 5 used to probe integratedcircuit chip114 which has a plurality ofcontact locations116 shown as spheres such as a C4 solder balls. The ends110 ofconductors42 are pressed in contact withcontact locations116 for the purpose of electrically probingintegrated circuit114.Cavity112 provides an opening inelastomeric material44 to permit ends110 to be pressed towards and intosolder mounds116.Cavity112 provides a means forsolder mounds116 to self align toends110 and provides a means containing solder mounds which may melt, seep or be less viscous when the probe is operated at an elevated temperature. When the probe is used to test or burn-in workpieces have flat pads as contact locations thecavities112 can remain or be eliminated.
• FIGS. 7-13 show the process for fabricating the structure ofFIG. 5.Substrate60 withcontact locations106 thereon is disposed in a wire bond tool. Thetop surface122 ofpad106 is coated by a method such as evaporation, sputtering or plating with soft gold or Ni/Au to provide a suitable surface for thermosonic ball bonding. Other bonding techniques can be used such as thermal compression bonding, ultrasonic bonding, laser bonding and the like. A commonly used automatic wire bonder is modified to ball bond gold, gold alloy, copper, copper alloy, aluminum, Pt, nickel orpalladium wires120 to thepad106 onsurface122 as shown inFIG. 7. The wire preferably has a diameter of 0.001 to 0.005 inches. If a metal other than Au is used, a thin passivation metal such as Au, Cr, Co, Ni or Pd can be coaled over the wire by means of electroplating, or electroless plating, sputtering, e-beam evaporation or any other coating techniques known in the industry.Structure124 ofFIG. 7 is the ball bonding head which has awire126 being fed from a reservoir of wire as in a conventional wire bonding apparatus.FIG. 7 shows theball bond head124 in contact atlocation126 withsurface122 ofpad106.
• FIG. 8 shows theball bonding head124 withdrawn in the direction indicated byarrow128 from thepad106 and thewire126 drawn out to leave disposed on thepad106surface122wire130. In the preferred embodiment, thebond head124 is stationary and thesubstrate60 is advanced as indicated byarrow132. The bond wire is positioned at an angle preferably between 5 to 60° from vertical and then mechanically notched (or nicked) byknife edge134 as shown inFIG. 9. Theknife edge134 is actuated, thewire126 is clamped and thebond head124 is raised. The wire is pulled up and breaks at the notch or nick.
• Cutting thewire130 while it is suspended is not done in conventional wire bonding. In conventional wire bonding, such as that used to fabricate the electrical connector of U.S. Pat. No. 4,998,885, where, as shown inFIG. 8 thereof, one end a wire is ball bonded using a wire bonded to a contact location on a substrate bent over a loop post and the other of the wire is wedge bonded to an adjacent contact location on the substrate. The loop is severed by a laser as shown inFIG. 6 and the ends melted to form balls. This process results in adjacent contact locations having different types of bonds, one a ball bond the other a wedge bond. The spacing of the adjacent pads cannot be less than about ˜20 mils because of the need to bond the wire. This spacing is unacceptable to fabricate a high density probe tip since dense integrated circuits have pad spacing less than this amount. In contradistinction, according to the present invention, each wire is ball bonded to adjacent contact locations which can be spaced less than 5 mils apart. The wire is held tight andknife edge134 notches the wire leaving upstanding or flying leads120 bonded to contactlocations106 in a dense array.
• When thewire130 is severed there is left on thesurface122 ofpad106 an angled flyinglead120 which is bonded to surface122 at one end and the other end projects outwardly away from the surface. A ball can be formed on the end of thewire130 which is not bonded to surface122 using a laser or electrical discharge to melt the end of the wire. Techniques for this are described in co-pending U.S. patent application Ser. No. 07/963,346, filed Oct. 19, 1992, which is incorporated herein by reference above.
• FIG. 10 shows thewire126 notched (or nicked) to leavewire120 disposed onsurface122 ofpad106. Thewire bond head124 is retracted upwardly as indicated byarrow136. Thewire bond head124 has a mechanism to grip andrelease wire126 so thatwire126 can be tensioned against the shear blade to sever the wire.
• After the wire bonding process is completed, a castingmold140 as shown inFIG. 11 is disposed onsurface142 ofsubstrate60. The mold is a tubular member of any cross-sectional shape, such as circular and polygonal. The mold is preferably made of metal or organic materials. The length of the mold is preferably theheight144 of thewires120. A controlled volume ofliquid elastomer146 is disposed into the casting140 mold and allowed to settle out (flow between the wires until the surface is level) before curing as shown inFIG. 13. Once the elastomer has cured, the mold is removed to provide the structure shown inFIG. 5 except forcavities112. The cured elastomer is represented byreference numeral44. A mold enclosing thewires120 can be used so that the liquid elastomer can be injection molded to encase thewires120.
• The top surface of the composite polymer/wire block can be mechanically planarized to provide a uniform wire height and smooth polymer surface. A moly mask with holes located over the ends of the wire contacts is used to selectively ablate (or reactive ion etch) a cup shaped recess in the top surface of the polymer around each of the wires. The probe contacts can be reworked by repeating the last two process steps.
• A high compliance, high thermal stability siloxane elastomer material is preferable for this application. The compliance of the cured elastomer is selected for the probe application. Where solder mounds are probed a more rigid elastomeric is used so that the probe tips are pushed into the solder mounds where a gold coated aluminum pad is being probed a more compliant elastomeric material is used to permit the wires to flex under pressure so that the probe ends in contact with the pad will move to wipe over the pad so that good electrical contact is made therewith. The high temperature siloxane material is cast or injected and cured similar to other elastomeric materials. To minimize the shrinkage, the elastomer is preferably cured at lower temperature (T ≦60°) followed by complete cure at higher temperatures (T ≧80°).
• Among the many commercially available elastomers, such as ECCOSIL and SYLGARD, the use of polydimethylsiloxane based rubbers best satisfy both the material and processing requirements. However, the thermal stability of such elastomers is limited at temperatures below 200°C. and significant outgassing is observed above 100°C. We have found that the thermal stability can be significantly enhanced by the incorporation of 25 wt % or more diphenylsiloxane. Further, enhancement in the thermal stability has been demonstrated by increasing the molecular weight of the resins (oligomers) or minimizing the cross-link junction. The outgassing of the elastomers can be minimized at temperatures below 300°C. by first using a thermally transient catalyst in the resin synthesis and secondly subjecting the resin to a thin film distillation to remove low molecular weight side-products. For our experiments, we have found that 25 wt % diphenylsiloxane is optimal, balancing the desired thermal stability with the increased viscosity associated with diphenylsiloxane incorporation. The optimum number average molecular weight of the resin for maximum thermal stability was found to be between 18,000 and 35,000 g/mol. Higher molecular weights were difficult to cure and too viscous, once filled, to process. Network formation was achieved by a standard hydrosilylation polymerization using a hindered platinum catalyst in a reactive silicon oil carrier.
• InFIG. 10 whenbond head124 bonds thewire126 to thesurface122 ofpad106 there is formed a flattened spherical end shown as104 inFIG. 6.
• The high density test probe provides a means for testing high density and high performance integrated circuits in wafer form or as discrete chips. The probe contacts can be designed for high performance functional testing or high temperature burn-in applications. The probe contacts can also be reworked several times by resurfacing the rigid polymer material that encases the wires exposing the ends of the contacts.
• The high density probe contacts described in this disclosure are designed to be used for testing semiconductor devices in either wafer form or as discrete chips. The high density probe uses metal wires that are bonded to a rigid substrate. The wires are imbedded in a rigid polymer that has a cup shaped recess around each to the wire ends. The cup shapedrecess112 shown inFIG. 5 provides a positive self-aligning function for chips with solder ball contacts. A plurality of probe heads40 can be mounted onto aspace transformation substrate60 so that a plurality of chips can be probed an burned-in simultaneously.
• An alternate embodiment of this invention would include straight wires instead of angled wires. Another alternate embodiment could use a suspended alignment mask for aligning the chip to the wire contacts instead of the cup shaped recesses in the top surface of the rigid polymer. The suspended alignment mask is made by ablating holes in a thin sheet of polyimide using an excimer laser and a metal mask with the correct hole pattern. Another alternate embodiment of this design would include a interposer probe assembly that could be made separately from the test substrate as described in U.S. patent application Ser. No. 07/963,364, incorporated by reference herein above. This design could be fabricated by using a copper substrate that would be etched away after the probe assembly is completed and the polymer is cured. This approach could be further modified by using an adhesion de-promoter on the wires to allow them to slide freely (along the axis of the wires) in the polymer material.
• FIG. 14 shows an alternate embodiment ofprobe tip40 ofFIGS. 2 and 3. As described herein above,probe tip40 is fabricated to be originally fixed to the surface of a firstlevel space transformer54. Eachwire120 is wire bonded directly to apad106 onsubstrate60 so that theprobe assembly40 is rigidly fixed to thesubstrate60. The embodiment ofFIG. 14, theprobe bead assembly40 can be fabricated via a discrete stand alone clement. This can be fabricated following the process of U.S. patent application Ser. No. 07/963,348, filed Oct. 19, 1992, which has been incorporated herein by reference above. Following this fabrication process as described herein above,wires42 ofFIG. 14 are wire bonded to a surface. Rather than being wire bonded directly to a pad on a space transformation substrate,wire42 is wire bonded to a sacrificial substrate as described in the application incorporated herein. The sacrificial substrate is removed to leave the structure ofFIG. 14. At ends102 ofwires44 there is a flattenedball104 caused by the wire bond operation. In a preferred embodiment the sacrificial substrate to which the wires are bonded have an array of pits which result in aprotrusion150 which can have any predetermined shape such as a hemisphere or a pyramid.Protrusion150 provides a raised contact for providing good electrical connection to a contact location against which it is pressed. Theclamp assembly80 ofFIGS. 2 and 3 can be modified so thatprobe tip assembly40 can be pressed towardssurface58 ofsubstrate60 so that ends104 ofFIG. 14 can be pressed against contact locations such as106 ofFIG. 5 onsubstrate60.Protuberances104 are aligned topads100 onsurface58 ofFIG. 5 in a manner similar to how the conductor ends86 and88 of the connector inFIG. 4 are aligned topads75 and64 respectively.
• As shown in the process ofFIGS. 7 to 9,wire126 is ball bonded to pad106 onsubstrate60. An alternative process is to start with asubstrate160 as shown inFIG. 15 havingcontact locations162 having an electricallyconductive material164 disposed onsurface166 ofcontact location162. Electricallyconductive material164 can be solder. A bond lead such as124 ofFIG. 7 can be used to disposeend168 ofwire170 againstsolder mound164 which can be heated to melting.End168 ofwire170 is pressed into the molten solder mound to formwire172 embedded into a solidified solder mound174. Using this process a structure similar to that ofFIG. 5 can be fabricated.
• FIG. 16 shows another alternative embodiment of a method to fabricate the structure ofFIG. 5.
• Numerals common betweenFIGS. 15 and 16 represent the same thing.End180 elongatedelectrical conductor182 is held againsttop surface163 ofpad162 onsubstrate160. A beam of light184 fromlaser186 is directed atend180 ofelongated conductor182 at the location of contact withsurface163 ofpad162. Theend180 is laser welded to surface163 to formprotuberance186.
• In summary, the present invention is directed to high density test probe for testing high density and high performance integrated circuits in wafer form or as discrete chips. The probe contacts are designed for high performance functional testing and for high temperature burn in applications. The probe is formed from an elastomeric probe tip having a highly dense array of elongated electrical conductors embedded in an elastomeric material which is in electrical contact with a space transformer.
• While the present invention has been described with respect to preferred embodiments, numerous modifications, changes and improvements will occur to those skilled in the art without departing from the spirit and scope of the invention.

Claims (32)

1-48. (canceled)

49. A structure comprising:

a plurality of first substrates adapted to be mounted to a second substrate;

each of the first substrate having two opposite surfaces;

free standing flexible conductors extending from one of the two surfaces shaped so that a free end thereof laterally movers when pressed against a surface;

terminals on an other of the two opposite surfaces;

means, within each of the first substrates, for connecting the terminals to the contacts; and

the plurality of the first substrates are mounted on to the second substrate.

50-59. (canceled)

60. A probe card structure according toclaim 49 wherein said freestanding flexible conductors are shaped to flex and wipe the area of the electronic device, the freestanding flexible conductors substantially compliantly respond when the flexible contact elements are withdrawn from contacting the electronic component.

61. (canceled)

62. A structure according toclaim 60 wherein the flexible contact elements can be repeatably assembled and disassembled so that said flexible contact element can recontact, reflex and rewipe the area of the electronic device.

63. (canceled)

64. A structure according toclaim 60 wherein the rewiped area is an area selected from the group consisting of an area of the same or a different electronic device.

65. A structure according toclaim 60, wherein the electronic device is a semiconductor wafer.

66. (canceled)

67. A structure according toclaim 60, wherein there are electrical connections between the second substrates and the first substrate.

68. A structure according toclaim 60, wherein the first substrate is a space transformer.

69. A structure according toclaim 60, wherein the electronic device is a semiconductor wafer; and the flexible contact elements of the second substrate contact individual semiconductor dies on the semiconductor wafer.

70. A structure according toclaim 60, wherein the electronic device is a semiconductor wafer; and the flexible contact elements of the second substrate contacts at least one integrated circuit on the semiconductor wafer.

71. A structure according toclaim 60, wherein the first substrate with the second substrate mounted thereto is mounted to an electrical testing apparatus by a plurality of electrical connections.

72. A structure according toclaim 60, further including plurality of groups of said plurality of the flexible electrical contact elements.

73. A structure according toclaim 60, wherein there is selected from the group consisting of a least one of said second substrates mounted to said first substrate and a plurality of said second substrates mounted to said first substrate

74. (canceled)

75. A structure according toclaim 49 wherein said free standing flexible conductors comprise a coating.

76. A structure according toclaim 75 wherein said coating is selected from the group consisting of Au, Cr, Co, Ni and Pd.

77. A structure according toclaim 76 wherein said free standing flexible conductor comprises gold, gold alloy, copper, copper alloy, aluminum, nickel, palladium and platinum.

78. A structure comprising:

at least one first substrate adapted to be mounted to a second substrate;

said at least one first substrate has two opposite surfaces;

free standing flexible conductors extending from one of the two surfaces shaped so that a free end thereof laterally movers when pressed against a surface;

terminals on an other of the two opposite surfaces;

means, within each of the first substrates, for connecting the terminals to the contacts;

said at least one first substrate is mounted on to the second substrate; and

aligning the second substrate to the first substrate to align the flexible contact elements to the electronic component.

79. A structure according toclaim 78 wherein said freestanding flexible conductors comprise a coating.

80. A structure according toclaim 79 wherein said coating is selected from the group consisting of Au, Cr, Co, Ni and Pd.

81. A structure according toclaim 80 wherein said free standing flexible conductor comprises gold, gold alloy, copper, copper alloy, aluminum, nickel, palladium and platinum.

82. A structure according toclaim 78 wherein said freestanding flexible conductors are shaped to flex and wipe the area of the electronic device, the freestanding flexible conductors substantially compliantly respond when the flexible contact elements are withdrawn from contacting the electronic component.

83. A structure comprising:

a first substrate adapted to be mounted to a second substrate;

the first substrate having two opposite surfaces;

free standing flexible conductors extending from one of the two surfaces shaped so that a free end thereof laterally movers when pressed against a surface;

terminals on an other of the two opposite surfaces;

means, within the first substrate, for connecting the terminals to the contacts; and

the plurality of the first substrates are mounted on to the second substrate.

84. A structure according toclaim 83 wherein said freestanding flexible conductors comprise a coating.

85. A structure according toclaim 84 wherein said coating is selected from the group consisting of Au, Cr, Co, Ni and Pd.

86. A structure according toclaim 85 wherein said free standing flexible conductor comprises gold, gold alloy, copper, copper alloy, aluminum, nickel, palladium and platinum.

87. A structure according toclaim 83 wherein said freestanding flexible conductors are shaped to flex and wipe the area of the electronic device, the freestanding flexible conductors substantially compliantly respond when the flexible contact elements are withdrawn from contacting the electronic component.

88-90. (canceled)

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