US20080105919A1 - Non-volatile memory device having separate charge trap patterns and method of fabricating the same - Google Patents

Abstract

A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• Embodiments of the present invention relate to a non-volatile semiconductor device and a method of fabricating the same. More particularly, embodiments of the present invention relate to a non-volatile memory device having separate charge trap patterns and a method of fabricating the same.
• 2. Description of the Related Art
• Semiconductor memory devices storing data may be classified into volatile memory devices and non-volatile memory devices. While the volatile memory devices lose stored data when a power supply is interrupted, the non-volatile memory devices retain the stored data even when the power supply is interrupted. Accordingly, non-volatile memory devices, e.g., flash memory devices, find wide applications in portable storage devices or mobile telecommunication systems.
• Meanwhile, as electronic systems gradually become smaller and require low-power consumption components, the flash memory devices may have to be highly integrated. Therefore, the size of a gate constituting a unit cell of the flash memory device may also have to be scaled down.
• Recently, to scale down the size of the gate, a technology of fabricating the flash memory cell by forming a charge trap layer and a control gate on an active region having a fin structure has been developed. Also, a technology employing an insulating layer, e.g., a silicon nitride layer, as the charge trap layer may be considered. NAND-type flash memory devices may be especially amenable to high integration because a number of cells share one contact.
• FIG. 1 illustrates a cross-sectional view taken along a word line direction of unit cells of a related art NAND-type flash memory device having a charge trap layer.
• Referring toFIG. 1, first andsecond fins12A and12B may be formed on asemiconductor substrate11 by sinking anisolation trench13T. Anisolation layer13 may partially fill theisolation trench13T. The first andsecond fins12A and12B may thus each have a part that projects upward from theisolation layer13.
• Acharge trap layer17 may be applied along a surface of theisolation layer13, and surfaces of the first andsecond fins12A and12B may project upward from theisolation layer13. Thecharge trap layer17 may be, e.g., a silicon nitride layer. A first tunnel dielectric layer15A may be between thecharge trap layer17 and thefirst fin12A, and a second tunneldielectric layer15B may be between thecharge trap layer17 and thesecond fin12B.
• Acontrol gate electrode21 may cross over the first andsecond fins12A and12B. Thecontrol gate electrode21 may serve as a word line. A controldielectric layer19 may be between thecontrol gate electrode21 and thecharge trap layer17.
• Flash memory cells C1 and C2 may be provided at crossing points of thecontrol gate electrode21 and thefins12A and12B, respectively. That is, the first flash memory cell C1 may be provided at the crossing point of thecontrol gate electrode21 and thefirst fin12A, and the second flash memory cell C2 may be provided at the crossing point of thecontrol gate electrode21 and thesecond fin12B.
• Electrons may be injected into thecharge trap layer17 by a program operation of the memory cells C1 and C2. The electrons may be injected into thecharge trap layer17 between thefirst fin12A and thecontrol gate electrode21 by the program operation of the first flash memory cell C1. The electrons may also be similarly injected into thecharge trap layer17 between thesecond fin12B and thecontrol gate electrode21 by the program operation of the second flash memory cell C2.
• However, thecharge trap layers17 of the first and second flash memory cells C1 and C2 may have a connected structure. The connected structure of thecharge trap layers17 may provide a path for spreading charges. That is, the electrons injected into thecharge trap layer17 may be spread to an adjacent region due to the connected structure of thecharge trap layers17, as indicated by the arrows inFIG. 1. The charge spreading may lead to bad data retention of the memory cells C1 and C2 and malfunction of adjacent memory cells.
• The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
SUMMARY OF THE INVENTION
• Embodiments of the present invention are therefore directed to non-volatile memory device, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
• It is therefore a feature of an embodiment of the present invention to provide a non-volatile memory device having separate charge trap patterns in order to prevent charge spreading.
• It is therefore another feature of an embodiment of the present invention to provide a method of fabricating a non-volatile memory device having separate charge trap patterns in order to prevent charge spreading.
• At least one of the above and other features and advantages of the present invention may be realized by providing a non-volatile memory device that may include an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.
• The first and second charge trap patterns may each be an insulating layer. The first and second charge trap patterns may be each be a nitride layer. The first and second charge trap patterns may cover parts of the first and second fins projecting from the isolation layer. A distance between the first and second charge trap patterns may be smaller than a resolution limit of a photolithography process. A tunnel dielectric layer may be between the first and second charge trap patterns, and the first and second fins. The control gate electrode may cover parts of the first and second fins projecting from the isolation layer. A control dielectric layer may be at a lower part of the control gate electrode. The control dielectric layer may be between the first and second charge trap patterns and the control gate electrode, and the control dielectric layer may extend to be in contact with the isolation layer between the first and second charge trap patterns.
• At least one of the above and other features and advantages of the present invention may be realized by providing a method of fabricating a non-volatile memory device, which may include forming an isolation trench in a semiconductor substrate, the isolation trench defining first and second fins, forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.
• The charge trap patterns may each be an insulating layer. The charge trap patterns may each be a nitride layer. Forming the first and second charge trap patterns may include forming a charge trap layer along a surface of the isolation layer and surfaces of the fins projecting from the isolation layer, forming sacrificial patterns covering the charge trap layer on the fins and exposing the charge trap layer on the isolation layer, and removing the exposed charge trap layer. The sacrificial patterns may be formed of a material having an etch selectivity with respect to the charge trap layer. Forming the sacrificial patterns may include forming a sacrificial layer on the charge trap layer, forming a capping pattern partially filling a gap between the first and second fins, the sacrificial layer on the isolation layer being covered by the capping pattern and the sacrificial layer projecting from the capping pattern being exposed, oxidizing the exposed sacrificial layer, and removing the capping pattern and the sacrificial layer remaining under the capping pattern. The sacrificial layer may be formed from a material having an etch selectivity with respect to the charge trap layer. The sacrificial layer may be formed from silicon. Forming the capping pattern may include forming a capping layer filling a gap between the first and second fins, and etching-back the capping layer. The capping pattern may be formed of a material layer having an etch selectivity with respect to the sacrificial layer. The capping pattern may be formed from nitride.
BRIEF DESCRIPTION OF THE DRAWINGS
• The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
• FIG. 1 illustrates a cross-sectional view of a related art non-volatile memory device having a charge trap layer;
• FIG. 2 illustrates a plan view of a cell array region of a non-volatile memory device according to an exemplary embodiment of the present invention;
• FIG. 3 illustrates a cross-sectional view of a non-volatile memory device according to an exemplary embodiment of the present invention; and
• FIGS. 4 to 12 illustrate cross-sectional views of stages of a method of fabricating a non-volatile memory device according to an exemplary embodiment of the present invention.
• InFIGS. 3 to 12, section “1” is a cross-sectional view taken along line I-I′ ofFIG. 2, and section “2” is a cross-sectional view taken along line II-II′ ofFIG. 2.
DETAILED DESCRIPTION OF THE INVENTION
• Korean Patent Application No. 10-2006-0109534, filed on Nov. 7, 2006, in the Korean Intellectual Property Office, and entitled: “Non-Volatile Memory Device Having Separate Charge Trap Patterns and Method of Fabricating the Same,” is incorporated by reference herein in its entirety.
• The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
• In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
• According to the present invention, a non-volatile memory device may include a first charge trap pattern on a first fin, and a second charge trap pattern on a second fin. The first and second charge trap patterns may be spaced apart from each other. The first and second charge trap patterns may be formed of an insulating layer, e.g., a nitride layer. The charge trap patterns may be insulated from adjacent charge trap patterns by a tunnel dielectric layer and a control dielectric layer, respectively. Thus, spreading of electrons injected into the charge trap patterns may be prevented. The non-volatile memory device may thus prevent charge spreading.
• FIG. 2 illustrates a plan view of a cell array region of a NAND-type flash memory device according to an exemplary embodiment of the present invention, andFIG. 3 illustrates a cross-sectional view of a NAND-type flash memory device according to an exemplary embodiment of the present invention. InFIG. 3, section “1” is a cross-sectional view taken along line I-I′ ofFIG. 2, and section “2” is a cross-sectional view taken along line II-II′ ofFIG. 2.
• Referring toFIGS. 2 and 3, first tofourth fins55A,55B,55C, and55D may be formed by sinkingisolation trenches53T in asemiconductor substrate51. Thesemiconductor substrate51 may be, e.g., a silicon wafer, a silicon-on-insulator (SOI) wafer, etc. Anisolation layer53 may partially fill theisolation trenches53T between the first tofourth fins55A,55B,55C, and55D. That is, the first tofourth fins55A,55B,55C, and55D may include a part projecting from theisolation layer53. Theisolation layer53 may include an insulating layer, e.g., a silicon oxide layer.
• A string selection line SSL and a ground selection line GSL may cross over the first tofourth fins55A,55B,55C, and55D. When viewed from the plan view illustrated inFIG. 2, the first tofourth fins55A,55B,55C, and55D may be substantially parallel to each other in a column direction. The string and ground selection lines SSL and GSL may be parallel to each other in a row direction.
• Multiplecontrol gate electrodes75 may be provided between the string selection line SSL and the ground selection line GSL. Thecontrol gate electrodes75 may cross over the first tofourth fins55A,55B,55C, and55D. Thecontrol gate electrodes75 may be substantially parallel to each other in a row direction. Thecontrol gate electrodes75 may extend to fill gap regions between the first tofourth fins55A,55B,55C, and55D. Thecontrol gate electrodes75 may serve as word lines.
• Thecontrol gate electrodes75 may each include a firstconductive layer71, a secondconductive layer72 and a thirdconductive layer73, which may be sequentially stacked. The string and ground selection lines SSL and GSL may also include the first to thirdconductive layers71 to73. The firstconductive layer71 may be, e.g., a tantalum nitride (TaN) layer, the secondconductive layer72 may be, e.g., a tungsten nitride (WN) layer, and the thirdconductive layer73 may be, e.g., a tungsten (W) layer.
• Charge trap patterns59A and59B may be at crossing points of thecontrol gate electrodes75 and the first tofourth fins55A,55B,55C, and55D. Thecharge trap patterns59A and59B may be, e.g., an insulating layer. Thecharge trap patterns59A and59B may be, e.g., a nitride layer, a silicon nitride layer, etc.
• Thecharge trap patterns59A and59B may include a firstcharge trap pattern59A and a secondcharge trap pattern59B. The firstcharge trap pattern59A may cover a part of thefirst fin55A projecting from theisolation layer53. The secondcharge trap pattern59B may cover a part of thesecond fin55B projecting from theisolation layer53.
• As illustrated in the region shown in dotted line S ofFIG. 3, the first and secondcharge trap patterns59A and59B may be spaced apart. Adistance59W between the first and secondcharge trap patterns59A and59B may be smaller than a resolution limit of a photolithography process. That is, the first and secondcharge trap patterns59A and59B may have a structure advantageous to high integration.
• A firsttunnel dielectric layer57A may be between the firstcharge trap pattern59A and thefirst fin55A. A part of thefirst fin55A projecting from theisolation layer53 may be covered by the firsttunnel dielectric layer57A. A secondtunnel dielectric layer57B may be between the secondcharge trap pattern59B and thesecond fin55B. That is, the part of thesecond fin55B projecting from theisolation layer53 may also be covered by the secondtunnel dielectric layer57B.
• Thetunnel dielectric layers57A and57B may be, e.g., silicon oxide layers, thermal oxide layers, etc. Thecharge trap patterns59A and59B may be insulated from thefins55A and55B by thetunnel dielectric layers57A and57B.
• Acontrol dielectric layer69 may be under thecontrol gate electrodes75. Thecontrol dielectric layer69 may be a different material layer from thecharge trap patterns59A and59B. Thecontrol dielectric layer69 may be, e.g., a silicon oxide layer, a high-k dielectric layer, etc. Thecharge trap patterns59A and59B may be insulated from thecontrol gate electrodes75 by thecontrol dielectric layer69. Thecontrol dielectric layer69 may be in contact with theisolation layer53 between the first and secondcharge trap patterns59A and59B.
• Spacers85 may be on sidewalls of thecontrol gate electrodes75, the string selection line SSL, and the ground selection line GSL. Thespacers85 may be formed of an insulating layer, e.g., a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc.
• Source anddrain regions81 and83 may be in the first tofourth fins55A,55B,55C, and55D, which may be adjacent to both sides of thecontrol gate electrodes75, the string selection line SSL, and the ground selection line GSL. The source and drainregions81 and83 may be, e.g., high-concentration impurity regions.
• Thesemiconductor substrate51 having thecontrol gate electrodes75, the string selection line SSL and the ground selection line GSL may be covered by aninterlayer insulating layer91. The interlayer insulatinglayer91 may be, e.g., a silicon oxide layer.
• Bit lines BL may be on theinterlayer insulating layer91. The bit lines BL may be parallel to each other in a column direction. The bit lines BL may be electrically connected to the source and drainregions83, which may be adjacent to the string selection line SSL and opposite to the ground selection line GSL, by bit plugs93 passing through the interlayer insulatinglayer91. The bit lines BL and the bit plugs93 may be formed of, e.g., a conductive layer.
• According to the exemplary embodiment of the present invention described above, the firstcharge trap pattern59A may be insulated from the secondcharge trap pattern59B by the firsttunnel dielectric layer57A and thecontrol dielectric layer69. The secondcharge trap pattern59B may be insulated from the firstcharge trap pattern59A by the secondtunnel dielectric layer57B and thecontrol dielectric layer69. That is, each of thecharge trap patterns59A and59B may be insulated from adjacent charge trap patterns by thetunnel dielectric layers57A and57B, and thecontrol dielectric layer69.
• In the NAND-type flash memory device according to the exemplary embodiment of the present invention, electrons may be injected into thecharge trap patterns59A and59B by employing a program operation. The electrons injected into thecharge trap patterns59A and59B may be blocked from being spread into an adjacent region by thetunnel dielectric layers57A and57B, and thecontrol dielectric layer69. Accordingly, data retention characteristics of thecharge trap patterns59A and59B may be significantly improved. Also, malfunctions caused by interference between adjacent charge trap patterns may be prevented. Consequently, a NAND flash memory device which may prevent charge spreading may be obtained.
• FIGS. 4 to 12 illustrate cross-sectional views of a method of fabricating a NAND-type flash memory device according to an exemplary embodiment of the present invention. ThroughoutFIGS. 4 to 12, section “1” is a cross-sectional view taken along line I-I′ ofFIG. 2.
• Referring toFIGS. 2 and 4, first tofourth fins55A,55B,55C, and55D may be defined by formingisolation trenches53T in thesemiconductor substrate51. Thefins55A,55B,55C, and55D may include thefirst fin55A, thesecond fin55B, thethird fin55C and thefourth fin55D, which may be formed parallel to one another in a column direction. Theisolation trenches53T may be formed by, e.g., a well-known patterning technique.
• An insulating layer filling theisolation trench53T and covering a top surface of thesemiconductor substrate51 may be formed. The insulating layer may be recessed to form anisolation layer53, which may partially fill theisolation trench53T. Theisolation layer53 may remain at a lower region in theisolation trench53T. Recessing the insulating layer may be performed by, e.g., an etch-back process, a chemical mechanical polishing (CMP) process, a combination thereof, etc. As a result, the first tofourth fins55A,55B,55C, and55D may have parts projecting from theisolation layer53. Also, the parts of the first tofourth fins55A,55B,55C, and55D, which project from theisolation layer53, may be exposed.
• Theisolation layer53 may be an insulating layer formed from, e.g., silicon oxide. Theisolation layer53 may have a sidewall oxide layer (not illustrated) and a nitride layer liner (not illustrated), which may be formed along sidewalls of the first tofourth fins55A,55B,55C, and55D.
• Referring toFIGS. 2 to 5,tunnel dielectric layers57A and57B may be formed on exposed surfaces of the first tofourth fins55A,55B,55C, and55D. Thetunnel dielectric layers57A and57B may be a thermal oxide layer formed from, e.g., silicon oxide. In this case, the formation of the thermal oxide layer may be prevented on a surface of theisolation layer53. Thus, the firsttunnel dielectric layer57A may be formed along the surface of thefirst fin55A, which may project from theisolation layer53. The secondtunnel dielectric layer57B may similarly be formed along the surface of thesecond fin55B, which may project from theisolation layer53.
• Alternatively, the first and secondtunnel dielectric layers57A and57B may be formed by, e.g., a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, etc. Also, thetunnel dielectric layers57A and57B may be formed of, e.g., a high-k dielectric layer, a silicon oxide layer, a silicon oxynitride layer, a combination thereof, etc. The first and secondtunnel dielectric layers57A and57B may also be formed on the surface of theisolation layer53. The following description will assume that thetunnel dielectric layers57A and57B are thermal oxide layers.
• Acharge trap layer59 may be formed on thesemiconductor substrate51 having thetunnel dielectric layers57A and57B. Thecharge trap layer59 may be formed from a material layer that is different from thetunnel dielectric layers57A and57B. Thecharge trap layer59 may be, e.g., a nitride layer, a silicon nitride layer, etc. For example, the silicon nitride layer may be formed employing, e.g., a low pressure chemical vapor deposition (LPCVD) apparatus, an ALD apparatus, etc.
• Thecharge trap layer59 may be formed along the surfaces of thetunnel dielectric layers57A and57B and theisolation layer53. That is, thecharge trap layer59 may cover thetunnel dielectric layers57A and57B. Also, thecharge trap layer59 may cover the top surface of theisolation layer53. As a result, thecharge trap layer59 formed on thefirst fin55A and thecharge trap layer59 formed on thesecond fin55B may be connected to each other by thecharge trap layer59 covering the top surface of theisolation layer53.
• Referring toFIGS. 2 and 6, asacrificial layer61 may be formed along a surface of thecharge trap layer59. Thesacrificial layer61 may be a material layer having an etch selectivity with respect to thecharge trap layer59. Thesacrificial layer61 may also be a material layer having a high surface oxidation rate. Thesacrificial layer61 may be, e.g., a silicon layer. The silicon layer may be formed employing, e.g., an LPCVD apparatus, an ALD apparatus, etc.
• Acapping layer63 may be formed on thesemiconductor substrate51 having thesacrificial layer61. Thecapping layer63 may be a material layer with an etch selectivity with respect to thesacrificial layer61. By “etch selectivity,” different etch rates under the same conditions may be observed for thecapping layer63 and thesacrificial layer61. Thecapping layer63 may also be a material layer having a lower surface oxidation rate than thesacrificial layer61. Thecapping layer63 may be, e.g., a silicon nitride layer. Thecapping layer63 may fill gap regions between the first tofourth fins55A,55B,55C, and55D. Thecapping layer63 may be formed using, e.g., an LPCVD apparatus, a plasma-enhanced chemical vapor deposition (PECVD) apparatus, etc.
• Referring toFIGS. 2 and 7, thecapping layer63 may be etched-back, thereby forming acapping pattern63′. The etch-back of thecapping layer63 may be performed by a wet process employing, e.g., a phosphoric acid (H₃PO₄) solution. A dry etching process may also be used. Thecapping pattern63′ may cover thesacrificial layer61 on theisolation layer53. Thecapping pattern63′ may remain at lower parts in the gap regions between the first tofourth fins55A,55B,55C, and55D. As a result, thesacrificial layer61 covering the part projecting from thecapping pattern63′ may be exposed.
• Sacrificial patterns65A and65B may be formed in thesemiconductor substrate51 having the partially exposedsacrificial layer61 by employing, e.g., an oxidation process. The oxidation process may include, e.g., a thermal oxidation process, a plasma oxidation process, etc. When thesacrificial layer61 is, e.g., a silicon layer, thesacrificial patterns65A and65B may be formed of, e.g., a silicon oxide layer. Accordingly, the part of thecharge trap layer59 projecting from thecapping pattern63′ may be covered by the first and secondsacrificial patterns65A and65B. The firstsacrificial pattern65A may cover a top surface of thefirst fin55A, and the secondsacrificial pattern65B may cover a top surface of thesecond fin55B.
• In this case, thesacrificial layer61 may remain under thecapping pattern63′. The remainingsacrificial layer61′ may cover thecharge trap layer59 on theisolation layer53.
• During the oxidation process, formation of an oxidation layer on a surface of thecapping pattern63′ may be prevented. If an oxidation layer, which may be very thin, is formed on the surface of thecapping pattern63′, a surface of thecapping pattern63′ may be exposed by employing a cleaning or etching process. The cleaning or etching process may employ a solution containing, e.g., hydrofluoric acid.
• Referring toFIGS. 2 and 8, thecapping pattern63′ may be removed to expose the remainingsacrificial layer61′. The removal of thecapping pattern63′ may be performed by, e.g., a wet process using phosphoric acid (H₃PO₄) solution.
• Referring toFIGS. 2 and 9, the remainingsacrificial layer61′ may be removed to expose thecharge trap layer59 on theisolation layer53. A sufficient etch selectivity may be obtained between thesacrificial patterns65A and65B, and the remainingsacrificial layer61′. Accordingly, the removal of the remainingsacrificial layer61′ may be performed by either a dry or wet process.
• The exposedcharge trap layer59 may be removed to form first and secondcharge trap patterns59A and59B. The removal of the exposedcharge trap layer59 may be performed by an anisotropic etching process. Reactive ion etch (RIE) may be used as the anisotropic etching process. Alternatively, the removal of the exposedcharge trap layer59 may be performed by an isotropic etching process. Thedistance59W between the first and secondcharge trap patterns59A and59B may be determined by a gap between the first and secondsacrificial patterns65A and65B.
• As described above, the first and secondcharge trap patterns59A and59B may be formed without employing a separate photolithography process. Accordingly, the first and secondcharge trap patterns59A and59B may be self-aligned on the first andsecond fins55A and55B, respectively. Also, thedistance59W may be smaller than the resolution limit of the photolithography process. That is, the first and secondcharge trap patterns59A and59B may be formed to have a structure advantageous to high integration.
• Referring toFIGS. 2 and 10, thesacrificial patterns65A and65B may be removed to expose thecharge trap patterns59A and59B. Thesacrificial patterns65A and65B may be removed using a solution containing, e.g., hydrofluoric acid.
• Consequently, the firstcharge trap pattern59A may cover the part of thefirst fin55A projecting from theisolation layer53, and the secondcharge trap pattern59B may cover the part of thesecond fin55B projecting from theisolation layer53. Also, the firstcharge trap pattern59A may be insulated from thefirst fin55A by the firsttunnel dielectric layer57A. The secondcharge trap pattern59B may also be insulated from thesecond fin55B by the secondtunnel dielectric layer57B.
• Referring toFIGS. 2 and 11, acontrol dielectric layer69 may be formed on thesemiconductor substrate51 having thecharge trap patterns59A and59B. Thecontrol dielectric layer69 may be, e.g., a silicon oxide layer, a high-k dielectric layer, etc. For example, thecontrol dielectric layer69 may be, e.g., an aluminum oxide layer.
• Thecontrol dielectric layer69 may be formed along the surfaces of thecharge trap patterns59A and59B and theisolation layer53. Between the first andsecond fins55A and55B, thecontrol dielectric layer69 may be in contact with theisolation layer53.
• Control gate electrodes75 crossing over the first tofourth fins55A,55B,55C, and55D may be formed on thesemiconductor substrate51 having thecontrol dielectric layer69. Thecontrol gate electrodes75 may be formed by sequentially depositing and patterning a firstconductive layer71, a secondconductive layer72, and a thirdconductive layer73. The firstconductive layer71 may be, e.g., a TaN layer, the secondconductive layer72 may be, e.g., a WN layer, and the thirdconductive layer73 may be, e.g., a W layer.
• While forming thecontrol gate electrodes75, thecontrol dielectric layer69 may also be patterned. In this case, thecontrol dielectric layer69 may remain under thecontrol gate electrodes75. Thecontrol gate electrodes75 may also be formed to fill gap regions between the first tofourth fins55A,55B,55C, and55D. Thecharge trap patterns59A and59B may be insulated from thecontrol gate electrodes75 by thecontrol dielectric layer69.
• Referring toFIGS. 2 and 12, theinterlayer insulating layer91 may be formed on thesemiconductor substrate51 having thecontrol gate electrodes75. The interlayer insulatinglayer91 may be an insulating layer, e.g., a silicon oxide layer. Bit lines BL may be on theinterlayer insulating layer91. The bit lines BL may be, e.g., a conductive layer.
• Referring again toFIGS. 2 and 3, while forming thecontrol gate electrodes75, the string selection line SSL and the ground selection line GSL may be formed. For example, the string selection line SSL may be formed of the first to thirdconductive layers71 to73, which may be sequentially stacked.
• Then, source and drainregions81 and83 may be formed in the first tofourth fins55A,55B,55C, and55D, which may be adjacent to both sides of thecontrol gate electrodes75, the string selection line SSL, and the ground selection line GSL. The source and drainregions81 and83 may be high-concentration impurity regions.
• Thespacers85 may be formed on sidewalls of thecontrol gate electrodes75, the string selection line SSL, and the ground selection line GSL. Thespacers85 may be formed of an insulating layer, e.g., a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a combination thereof, etc.
• Bit contact holes BC may pass through the interlayer insulatinglayer91, and the bit plugs93 may fill the bit contact holes BC. The bit lines BL may be electrically connected to the source and drainregions83, which may be adjacent to the string selection line SSL and opposite to the ground selection line GSL, by the bit plugs93. The bit plugs93 may be formed of, e.g., a conductive material.
• Exemplary embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only, not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. For example, the present invention may also be applied to a NOR type non-volatile memory device and a method of fabricating the same.

Claims (20)

1. A non-volatile memory device, comprising:

an isolation trench in a semiconductor substrate;

an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench;

a control gate electrode crossing the first and second fins;

a first charge trap pattern between the first fin and the control gate electrode; and

a second charge trap pattern between the second fin and the control gate electrode.

2. The device as claimed inclaim 1, wherein the first and second charge trap patterns are each an insulating layer.

3. The device as claimed inclaim 2, wherein the first and second charge trap patterns are each a nitride layer.

4. The device as claimed inclaim 1, wherein the first and second charge trap patterns cover parts of the first and second fins projecting from the isolation layer.

5. The device as claimed inclaim 1, wherein a distance between the first and second charge trap patterns is smaller than a resolution limit of a photolithography process.

6. The device as claimed inclaim 1, further comprising a tunnel dielectric layer between the first and second charge trap patterns, and the first and second fins.

7. The device as claimed inclaim 1, wherein the control gate electrode covers parts of the first and second fins projecting from the isolation layer.

8. The device as claimed inclaim 1, further comprising a control dielectric layer at a lower part of the control gate electrode.

9. The device as claimed inclaim 8, wherein the control dielectric layer is between the first and second charge trap patterns and the control gate electrode, and the control dielectric layer extends to be in contact with the isolation layer between the first and second charge trap patterns.

10. A method of fabricating a non-volatile memory device, comprising:

forming an isolation trench in a semiconductor substrate, the isolation trench defining first and second fins;

forming an isolation layer partially filling the isolation trench;

forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer; and

forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.

11. The method as claimed inclaim 10, wherein the charge trap patterns are each an insulating layer.

12. The method as claimed inclaim 10, wherein the charge trap patterns are each a nitride layer.

13. The method as claimed inclaim 10, wherein forming the first and second charge trap patterns comprises:

forming a charge trap layer along a surface of the isolation layer and surfaces of the fins projecting from the isolation layer;

forming sacrificial patterns covering the charge trap layer on the fins and exposing the charge trap layer on the isolation layer; and

removing the exposed charge trap layer.

14. The method as claimed inclaim 13, wherein the sacrificial patterns are formed of a material having an etch selectivity with respect to the charge trap layer.

15. The method as claimed inclaim 13, wherein forming the sacrificial patterns comprises:

forming a sacrificial layer on the charge trap layer;

forming a capping pattern partially filling a gap between the first and second fins, the sacrificial layer on the isolation layer being covered by the capping pattern and the sacrificial layer projecting from the capping pattern being exposed;

oxidizing the exposed sacrificial layer; and

removing the capping pattern and the sacrificial layer remaining under the capping pattern.

16. The method as claimed inclaim 15, wherein the sacrificial layer is formed from a material having an etch selectivity with respect to the charge trap layer.

17. The method as claimed inclaim 15, wherein the sacrificial layer comprises silicon.

18. The method as claimed inclaim 15, wherein forming the capping pattern comprises:

forming a capping layer filling a gap between the first and second fins; and

etching-back the capping layer.

19. The method as claimed inclaim 15, wherein the capping pattern is formed of a material layer having an etch selectivity with respect to the sacrificial layer.

20. The method as claimed inclaim 15, wherein the capping pattern comprises nitride.

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