US20080102566A1 - Multiple layer and crystal plane orientation semiconductor substrate - Google Patents

Abstract

A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.

Description

• This application is a Division of and claims priority of copending U.S. patent application Ser. No. 10/906,557 filed on Feb. 24, 2005.
FIELD OF THE INVENTION
• The present invention relates to the field of semiconductor substrates; more specifically, it relates a method of fabricating a semiconductor substrate having multiple crystalline layers with different crystal plane orientations.
BACKGROUND OF THE INVENTION
• In advanced semiconductor devices, individual devices such as transistors are positioned on semiconductor substrates relative to the crystal orientation of the substrate in order to take advantage of the fact that certain device parameters change based on the alignment of device structures relative to the crystal planes of the substrate. However, this often leads to integrated circuit chip edges that are no longer aligned to preferred crystal cleavage planes of the substrate, making dicing of the substrate into individual integrated circuit chips difficult and often resulting in wafer breakage. What is needed is a semiconductor substrate and a method of fabricating the substrate that allows device structures that take advantage of particular crystal plane alignments that at the same time can be easily diced into individual integrated circuit chips.
SUMMARY OF THE INVENTION
• A semiconductor substrate of the present invention comprises an insulating layer between an upper semiconductor layer and a lower semiconductor layer. A first crystal direction in the upper layer is rotationally displaced from a second crystal direction in the lower semiconductor layer. The edges of integrated circuit chips formed in the upper semiconductor layer are aligned to the second crystal direction to enhance dicing while some or all of devices formed in the integrated circuit chips have structures aligned to the first crystal direction.
• A first aspect of the present invention is a substrate, comprising: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
• A second aspect of the present invention is a method of fabricating a substrate, comprising: providing a first crystalline semiconductor substrate, providing a second crystalline semiconductor substrate; aligning a first crystal direction of the first crystalline semiconductor substrate to a second crystal direction of the second crystalline semiconductor substrate, the first crystal direction different from the second crystal direction; and forming an insulating layer between a bottom surface of the first crystalline semiconductor substrate and a top surface of the second crystalline semiconductor substrate, the insulating layer bonding the first crystalline semiconductor substrate to the second crystalline semiconductor substrate,
• A third aspect of the present invention is an integrated circuit chip, comprising: a first crystalline semiconductor layer and a second crystalline semiconductor layer; an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction; a field effect transistor comprising a source region, a drain region and a channel region separating the source and drain regions, the source, drain and a channel regions formed in the first crystalline semiconductor layer, a lengthwise direction of the channel extending between the source and drain regions aligned with both the first and the second directions; and at least one edge of the integrated circuit chip aligned with the second direction.
• A fourth aspect of the present invention is a method of fabricating an integrated circuit chip, comprising: providing a semiconductor-on-insulator substrate comprising a first crystalline semiconductor layer and a second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor substrate aligned relative to a second crystal direction of the second crystalline semiconductor substrate, the first crystal direction different from the second crystal direction, an insulating layer formed between a bottom surface of the first crystalline semiconductor substrate and a top surface of the second crystalline semiconductor substrate, the insulating layer bonding the first crystalline semiconductor substrate to the second crystalline semiconductor; forming a field effect transistor comprising a source region, a drain region and a channel region separating the source and drain regions, the source, drain and a channel regions formed in the first crystalline semiconductor layer, a lengthwise direction of the channel extending between the source and drain regions aligned with both the first and the second directions; and dicing the semiconductor-on-insulator substrate along the second direction to form at least one edge of the integrated circuit chip.
BRIEF DESCRIPTION OF DRAWINGS
• The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
• FIG. 1 is a top view of an exemplary {100} surfaced semiconductor substrate;
• FIG. 2 illustrates an exemplary semiconductor substrate according to the present invention;
• FIGS. 3A through 3E are side views of the fabrication of an exemplary semiconductor substrate according to the present invention;
• FIG. 4 is a top view illustrating alignment of integrated circuit chips on the semiconductor substrate ofFIG. 2; and
• FIG. 5 is a top view illustrating alignment of a first type of device to an integrated circuit chip fabricated on a semiconductor substrate according to the present invention; and
DETAILED DESCRIPTION OF THE INVENTION
• For the purposes of the present invention, the term wafer should be considered as and exemplary version of the more general term substrate.
• In crystalline solids, the atoms which make up the solid are spatially arranged in a periodic fashion called a lattice. A crystal lattice contains a volume, which is representative of the entire lattice and is regularly repeated throughout the crystal. In describing crystalline semiconductor materials in the present disclosure, the following conventions will be used:
• The directions in a lattice are expressed as a set of three integers with the same relationship as the components of a vector in that direction. For example, in cubic lattices, such as silicon, that has a diamond crystal lattice, a body diagonal exists along the [111] direction with the [ ] brackets denoting a specific direction. Many directions in a crystal lattice are equivalent by a symmetry transformation, depending upon the arbitrary choice of orientation axes. For example, crystal directions in the cubic lattice [100], [010] and [001] are all crystallographically equivalent. A direction and all its equivalent directions are denoted by < > brackets. Thus, the designation of the <100> direction includes the equivalent [100], [010] and [001] positive directions as well as the equivalent negative directions [−100], [0−10] and [00−1].
• Planes in a crystal may also be identified with a set of three integers. They are used to define a set of parallel planes and each set of integers enclosed in ( ) parentheses identifies a specific plane. For example the proper designation for a crystal plane perpendicular to the [100] direction is (100). Thus, if either a direction or a plane of a cubic lattice is known, its perpendicular counterpart may be quickly determined without calculation. Many planes in a crystal lattice are equivalent by a symmetry transformation, depending upon the arbitrary choice of orientation axes. For example, the (100), (010) and (001) planes are all crystallographically equivalent. A plane and all its equivalent planes are denoted by { } parentheses. Thus, the designation of the {100} plane includes the equivalent (100), (010) and (001) positive planes as well as the equivalent planes (−100), (0−10) and (00−1).
• FIG. 1 is a top view of an exemplary {100} surfaced semiconductor substrate. InFIG. 1, a [100] direction of a {100}silicon substrate100 is seen to be rotated 45° from a
• crystal direction. A [010] crystal direction is seen to be rotated 90° from the [100] crystal direction and 45° from the [110] crystal direction. A [−110] crystal direction is seen to be rotated 90° from the [110] crystal direction. Aline105 passing through anotch110 in the edge ofsubstrate100 and acenter115 of the substrate marks the [110] direction. Inversion carrier flow is affected by the crystal orientation of the channel of a field effect transistor (FET). For {100} surfaced substrates the mobility of the electrons (inversion carriers) in the channels of NFETs is relatively unaffected by choice of channel direction between the <100> crystal directions and the <110> crystal directions.
• The mobility of holes (inversion carriers) in the channels of PFETs is highest in <100> crystal directions and significantly lower in <110> directions.
• In one method of dicing silicon wafers, a dicing saw is used to scribe a line into the silicon wafer between integrated chips and then the wafer cleaved along these scribed lines. In another method, the dicing saw is used to cut completely through the silicon wafer. However, crystalline silicon wafers have a preferred cleavage planes and are most easily and cleanly broken or cut along {110} crystal planes.
• FIG. 2 illustrates anexemplary semiconductor substrate120 according to the present invention. InFIG. 2, a {110} crystalline silicon layer100W1 is bonded to a {100} crystalline silicon layer100W2 by aninsulating layer125. A centralvertical axis130 is perpendicular to top surfaces135W1 and135W2 of silicon layers100W1 and100W2 respectively. Top surface135W1 is also the top surface ofsemiconductor substrate120. Semiconductor devices, such as transistors, are intended to be formed in silicon layer100W1 and/or on top surface135W1.
• Vertical axis130 passes through centers115W1 and115W2 of respective silicon layers100W1 and100W2. The [100] and [110] crystal directions of silicon layer100W1 are designated as [100]W1 and [110]W1 respectively. The [010] and [110] crystal directions of silicon layer100W2 are designated as [100]W2 and [110]W2 respectively. Crystal direction [100]W1 is aligned to crystal direction [110]W2 and crystal direction [110]W1 is aligned to crystal direction [010] W2 Another way of stating the relation ship between the crystal directions of silicon layers100W1 and100W2 is that (a first) crystal direction [100]W1 is rotated 45° aboutaxis130 relative to (a second) crystal direction [100]W2.
• The particular crystal plane alignment illustrated inFIG. 2 and described supra, should be considered exemplary and many variations are possible. For example, instead of two different crystal directions (for example, the [100] and [110] crystal directions) in two different silicon layers being aligned, the same crystal directions (for example, the [100] and [100] crystal directions) in the two different silicon layers may be rotationally offset from one another by a pre-selected angle of rotation about a vertical axis running through the centers of both wafers. Additionally, different orientation silicon layers may be used. For example silicon layer100W1 may be a {111} crystalline silicon layer and silicon layer100W2 may be a {100} crystalline silicon layer. Further, one or both of silicon layers100W1 and100W2 may be replaced with a layer comprising a group III-V semiconductor material such as GaAs, GaP, GaSb, InP, In As, InSb
• First silicon layer100W1 has a thickness D1, second silicon layer100W2 has a thickness D2 and insulatinglayer125 has a thickness D3. In one example, D1 is between about 10 nm and about 100 nm, D2 is greater than about 700 microns and D3 is between about 5 nm and about 1000 nm, preferably between 50 nm and 250 nm. In one example, insulatinglayer125 comprises silicon oxide.
• FIGS. 3A through 3E are side views of the fabrication of an exemplary semiconductor substrate according to the present invention. InFIG. 3A, afirst silicon wafer150 has atop surface155, abottom surface160 and anedge165. Anotch170 is formed inwafer150. Asilicon dioxide layer175 having a thickness between about 0.5 nm to about 200 nm is formed ontop surface155 ofwafer150. A hydrogen ion implantation performed to form a hydrogenrich layer180 inwafer150.
• InFIG. 3B, asecond silicon wafer185 has atop surface190, abottom surface195 and anedge200. Anotch205 is formed inwafer185. Asilicon dioxide layer210 having a thickness between about 0.5 nm to about 200 nm is formed ontop surface190 ofwafer185. Oxide layers175 and210 are cleaned, edges165 and200 are alignedoxide layers175 and200 are brought into contact.Notches170 and205 serve to locate particular crystal planes inrespective wafers150 and185.
• InFIG. 3C,wafers150 and185 (while in contact) are heated to a temperature of about 400° C. or greater. Hydrogen rich layer180 (seeFIG. 3B) is brittle and an upper layer ofwafer150 is cleaved off leaving asilicon layer215, having a roughtop surface220.
• For many applications the remainder ofwafer150 still attached towafer185 is too thick and/or has too rough a surface and needs to be planarized and/or thinned. InFIG. 3D, a chemical mechanical polishing (CMP) process is performed to form athin silicon layer225 having a planertop surface230. In one example,silicon layer225 has a thickness between about 5 nm to about 100 nm
• InFIG. 3E,wafers150 and185 are heated, for example to about 1000° C. in hydrogen in order to mergeoxide layers175 and210 (seeFIG. 3D) into asilicon dioxide layer235 which bonds the wafers together. In one example,silicon dioxide layer235 has thickness between about 5 nm to about 500 nm. The structure illustrated inFIG. 3E is a silicon on insulator (SOI) substrate.
• FIG. 4 is a top view illustrating alignment of integrated circuit chips onsemiconductor substrate120 ofFIG. 2. InFIG. 4,substrate120 hasnotches240 and245 formed in anedge250 of the substrate. A line passing throughcentral axis130 and notch240 locates the [110]W1 and [010]W2 crystal directions which are co-aligned. A line passing throughcentral axis130 and notch245 locates the [100]W1 and [110]W2 crystal directions which are co-aligned. A multiplicity ofintegrated circuit chips255 are formed on top surface135W1. A first set ofparallel edges260A and260B ofintegrated circuit chips255 are parallel to crystal direction [−110]W2, a second set ofparallel edges265A and265B ofintegrated circuit chips255 are parallel to crystal direction [110]W2 (and crystal direction [100]W1).Spaces270 betweenintegrated circuit chips255 form a dicing kerf where a dicing saw will cutsubstrate120 to separate individual integrated circuit chips.
• It should be noted that the dicing kerf is aligned with lower silicon layer100W2 (seeFIG. 2) which is the thicker layer of substrate120 (see description supra) and the preferred cleavage planes of the lower silicon layer, while critical structures of devices formed inintegrated circuit chips255 may be printed aligned to crystal direction [100]W1 and still be aligned withedges260A and260B as illustrated inFIG. 5 described infra.
• FIG. 5 is a top view illustrating alignment of a first type of device to an integrated circuit chip fabricated on a semiconductor substrate according to the present invention. InFIG. 5, a complementary metal oxide silicon (CMOS)PFET300 comprises a silicon channel region305 and source/drain regions310 formed in silicon layer100W1 (see FIG.2) and agate315 formed over channel region305. A gate dielectric (not shown) is formed undergate315. Channel region305 has a length “L” measured between source/drain regions310 and a width “W” perpendicular to the channel length.Edges265A and265B are aligned with the [−110]W2 crystal direction and edges270A and270B are aligned with the [110]W2 crystal direction providing improved dicing characteristics. The length “L” of channel region305 is aligned with the [100]W1 crystal direction, which provides maximum inversion carrier mobility for a PFET as well as withedges260A and260B. Improved printability of images during fabrication ofPFET300 and maximum device density of devices result as well.
• The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. For example, locating flats instead of locating notches or combinations of locating notches and locating flats may be used to locate the crystal directions. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims (15)

1. A method of fabricating a substrate, comprising:

providing a first crystalline semiconductor substrate,

providing a second crystalline semiconductor substrate;

aligning a first crystal direction of said first crystalline semiconductor substrate to a second crystal direction of said second crystalline semiconductor substrate, said first crystal direction different from said second crystal direction; and

forming an insulating layer between a bottom surface of said first crystalline semiconductor substrate and a top surface of said second crystalline semiconductor substrate, said insulating layer bonding said first crystalline semiconductor substrate to said second crystalline semiconductor substrate.

2. The method ofclaim 1, wherein said first and second s crystalline semiconductor substrates each comprise silicon.

3. The method ofclaim 1, wherein said first and second crystal directions are co-aligned.

4. The method ofclaim 3, wherein first and second crystalline semiconductors each comprise {100} silicon and said first crystal direction is a [100] direction and said second crystal direction is a [110] direction.

5. The method ofclaim 1, wherein inversion carriers have a higher mobility in said first crystal direction than any other direction in said first crystalline semiconductor substrate and a crystal plane perpendicular to said second crystal direction is more easily cleaved than any other crystal plane perpendicular to any other crystal direction in said second crystalline semiconductor substrate.

6. The method ofclaim 1, wherein said insulating layer comprises silicon oxide.

7. The method ofclaim 1, further including thinning said first crystalline semiconductor substrate.

8. The method ofclaim 6, wherein said first crystalline semiconductor substrate has a thickness of between about 10 nm to about 100 nm and said insulating layer has a thickness of between about 5 nm to about 500 nm.

9. A method of fabricating an integrated circuit chip, comprising:

providing a semiconductor-on-insulator substrate comprising a first crystalline semiconductor layer and a second crystalline semiconductor layer, a first crystal direction of said first crystalline semiconductor substrate aligned relative to a second crystal direction of said second crystalline semiconductor substrate, said first crystal direction different from said second crystal direction, an insulating layer formed between a bottom surface of said first crystalline semiconductor substrate and a top surface of said second crystalline semiconductor substrate, said insulating layer bonding said first crystalline semiconductor substrate to said second crystalline semiconductor;

forming a field effect transistor comprising a source region, a drain region and a channel region separating said source and drain regions, said source, drain and a channel regions formed in said first crystalline semiconductor layer, a lengthwise direction of said channel extending between said source and drain regions aligned with both said first and said second directions; and

dicing said semiconductor-on-insulator substrate along said second direction to form at least one edge of said integrated circuit chip.

10. The method ofclaim 9, wherein said first and second crystalline semiconductor layers each comprise silicon.

11. The method ofclaim 9, wherein said first and second crystal directions are co-aligned.

12. The method ofclaim 11, wherein first and second crystalline semiconductors each comprise {100} silicon and said first crystal direction is a [110] direction and said second crystal direction is a [100] direction.

13. The method ofclaim 11, wherein inversion carriers in said channel region have a higher mobility in said first crystal direction than any other direction in said first crystalline semiconductor layer and a crystal plane perpendicular to said second crystal direction is more easily cleaved than any other crystal plane perpendicular to any other crystal direction in said second crystalline semiconductor layer.

14. The method ofclaim 11, wherein said insulating layer comprises silicon oxide.

15. The method ofclaim 11, wherein said first crystalline semiconductor layer has a thickness of between about 10 nm to about 100 nm and said insulating layer has a thickness of between about 5 nm to about 500 nm.

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