US20080075888A1

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Publication number: US20080075888A1
Application number: US11/876,680
Authority: US
Inventors: Nagarajan Rajagopalan; Meiyee Shek; Kegang Huang; Bok Heon Kim; Hichem M'Saad; Thomas Nowak
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2003-05-20
Filing date: 2007-10-22
Publication date: 2008-03-27
Also published as: US7371427B2; US20040231795A1

Abstract

Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Description

BACKGROUND OF THE INVENTION

Due to its relatively low resistance and cost, copper is finding increasing use as a conductive layer in the interconnect metallization structures of integrated circuits and other semiconductor devices.FIGS. 1A-1E show simplified cross-sectional views of conventional steps for fabricating a damascene interconnect structure utilizing copper metallization.

InFIG. 1A, an interlayer dielectric (ILD)100 is formed over a first conductinglayer102 and then patterned to create opening104. While opening104 is generically shown inFIG. 1A as a via hole, in dual damascene approaches the opening can take the more complex form of a trench overlying a narrower via hole.

InFIG. 1B, afirst barrier layer106 is formed within opening104 and over patternedILD100.Barrier layer106 may be formed from a variety of materials, including but not limited to SiN, TiN, Ta, TaN, Ta/TaN, as well as the barrier low k (BLOK®) material manufactured by Applied Materials, Inc. of Santa Clara, Calif. The primary function of the barrier layer is to block diffusion of copper of the metallization structure. ILD100 andbarrier layer106 may be formed by such techniques such as chemical vapor deposition, as performed by the PRODUCER® tool manufactured by Applied Materials, Inc. of Santa Clara, Calif.

InFIG. 1C,copper metal interconnect108 is formed overfirst barrier layer106, within opening104 and over the top ofILD layer100. Thecopper metal108 may be formed by such techniques as electroplating, for example as is performed by the ELECTRA CU™ tool manufactured by Applied Materials, Inc. of Santa Clara, Calif.

InFIG. 1D, the wafer is removed from the electroplating device and transferred to a chemical mechanical polishing tool for removal ofcopper metal108 andbarrier layer106 outside of the now-filled opening inILD100, resulting in the formation of conducting copper viastructure110. InFIG. 1E, the wafer is transferred from the chemical mechanical polishing module to a chemical vapor deposition (CVD) module for formation of second barrier layer112 over copper via110. The function of second barrier layer112 to block any upward diffusion of copper metal from the via into successive dielectric layers of the interconnect structure.

The process sequence shown and described above in connection withFIGS. 1A-1E can be repeated to form additional metallization layers overlying and in contact with copper via110.

The process flow just shown and described is somewhat simplified. For example, FIGS.1CA-CC show detailed and enlarged views of the fabrication steps leading up to creation of the copper via shown inFIG. 1D. Specifically, removal of excess copper metal during the CMP step shown inFIG. 1C may be performed under oxidizing conditions. Thus, as shown inFIG. 1CB, at the conclusion of the CMP step and prior to formation of the second barrier layer, a thincopper oxide layer114 typically overlies copper viaplug110. Formation of such a copper oxide layer is not necessarily the result of CMP performed under oxidizing conditions, and copper oxide may also result from exposing the processed wafer to air, as may occur during transfer of the wafer between different processing tools.

Because thiscopper oxide layer114 is a dielectric material, it can degrade the conductive properties of the interconnect metallization Therefore, as shown inFIG. 1CC, the metallization layer may be exposed to a reactive ionized species from a plasma to remove the copper oxide prior to formation of the top barrier layer and additional portions of the interconnect structure. The oxide removal plasma may be generated in gases such as NH₃mixed with a carrier gas comprising N₂. The oxide removal plasma may be generated remote from the chamber or generated within the chamber. This plasma exposure may take place in the same chamber in which the upper barrier layer is subsequently deposited. Methods and apparatuses for removing copper oxide are described in detail in U.S. Pat. No. 6,365,518, coassigned with the present invention and hereby incorporated by reference for all purposes.

Another detail not shown in the generalized FIGS.1A-E is the potential undesirable formation of hillocks in the copper metallization layer. Hillock formation is shown and described in connection with FIGS.1DA-1DC.

FIG. 1DA shows a cross-sectional view of the interconnect structure after removal of the CuO layer by plasma exposure following removal of the unwanted CuO layer. As shown inFIG. 1DB, hillocks108amay undesirably grow out of the plane of thecopper layer108 prior to or during formation of the upper barrier layer. The growth and presence of hillocks108acan create issues regarding performance of the interconnect structure, such as elevated electrical resistance and/or shorting.

Therefore, there is a need in the art for methods and apparatuses which reduce the incidence of hillock formation during the fabrication of copper metallization structures.

BRIEF SUMMARY OF THE INVENTION

Unwanted hillocks arising in copper due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

An embodiment of method of preconditioning a processing chamber that is to be utilized to form a barrier layer on top of a copper layer comprises, causing a seasoning layer consisting of silicon oxide to be deposited on exposed surfaces of a processing chamber prior to introduction of a substrate bearing a copper layer.

Another embodiment of a method of preconditioning a processing chamber that is to be utilized to form a barrier layer on top of a copper layer comprises exposing a processing chamber to a plasma prior to prior to introduction of a substrate bearing a copper layer.

Another embodiment of a method of preconditioning a processing chamber that is to be utilized to form a barrier layer on top of a copper layer, comprises causing a seasoning layer consisting of silicon oxide to be deposited on exposed surfaces of a processing chamber prior to introduction of a substrate bearing a copper layer. The seasoning layer is exposed to a plasma prior to introduction of a substrate bearing a copper layer.

An embodiment of a substrate processing apparatus in accordance with the present invention comprises a processing chamber and a gas distribution system configured to receive and deliver gases to a gas distribution face plate located proximate to the substrate heater in the processing chamber. A substrate heater is configured to support a substrate within the processing chamber and moveable relative to the gas distribution face plate. A controller is configured to control the gas delivery system, the RF power system, and the substrate support. A memory, coupled to the controller, comprises a computer-readable medium having a computer-readable program embodied therein for directing operation of the substrate processing apparatus. The computer-readable program includes a first set of instructions for controlling the gas delivery system to deliver to the gas distribution face plate a first gas flow resulting in formation of a seasoning layer consisting of silicon oxide in the chamber and prior to insertion of a substrate into the chamber.

A further understanding of embodiments in accordance with the present invention can be made by way of reference to the ensuing detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS.1A-E show simplified cross-sectional views of steps of a conventional process flow for forming a copper Damascene interconnect structure.

FIGS.1CA-1CC and1DA-1DC show detailed, enlarged cross-sectional views of certain of the steps of the conventional process flow shown inFIGS. 1A-1E.

FIGS. 2A and 2B are atomic force micrographs of a blanket Cu layer showing hillock formation.

FIG. 3 is a simplified flow chart illustrating post-Cu formation steps that may give rise to hillock formation.

FIGS.4A-B shows optical micrographs of wafers bearing blanket Cu layers coated with deposited nitride, in seasoned chambers that have or have not been exposed to post-seasoning plasma treatment.

FIGS.5A-B show optical micrographs of wafers bearing blanket Cu layers coated with deposited nitride, that have or have not been placed into direct contact with the wafer heater during gas flow stabilization.

FIGS.6A-D show optical micrographs of wafers bearing blanket Cu layers coated with deposited nitride, after exposure of the Cu layers to plasma under various pressures and gas distribution faceplate to wafer spacings.

FIG. 7A-B show atomic force micrographs of wafers bearing blanket Cu layers after exposure to plasma for different durations to remove CuO.

FIGS.8A-D show optical micrographs of wafers bearing a blanket Cu layer coated with deposited nitride, after exposure of the Cu layer to plasma formed in different gases.

FIGS.9A-D show optical micrographs of wafers bearing a blanket Cu layer coated with a deposited nitride layer, after exposure of the Cu layer to plasma formed in different gases.

FIGS.10A-D show optical micrographs of the surfaces of wafers exposed to different process conditions.

FIGS.11A-B show optical micrographs of wafers bearing a nitride barrier deposited over a Cu blanket layer at different temperatures.

FIG. 12A shows a simplified cross-sectional view of one embodiment of a PECVD apparatus.

FIG. 12B is an illustrative block diagram of the hierarchical control structure of the system control software according to a specific embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Unwanted formation of hillocks in copper layers during the fabrication of semiconductor devices may be reduced in accordance with embodiments of the present invention by carefully controlling a number of process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the barrier layer deposition chamber prior to its receiving a wafer bearing a copper layer. A second set of process parameters may be controlled to minimize the energy to which the copper layer is exposed during removal of copper oxide prior to deposition of the barrier layer. A third set of process parameters may be controlled to minimize the thermal budget that the copper layer is exposed to after removal of the copper oxide. Control over each of these sets of parameters is discussed in detail below.

I. Reduction of Hillock Formation in Copper Layers

Research has indicated that the formation of hillocks in copper layers may be attributable to diffusion of copper along grain boundaries of the metallization layer in response to stress. Stress resulting in hillock formation may be imparted to the copper grains through application of thermal or other types of energy. Grains of the Cu layer may in turn release this stress by diffusing along grain boundaries and growing out of the plane of the copper layer to form the unwanted hillock features.

The formation of hillocks in copper is illustrated inFIG. 2A, which shows an atomic force micrograph at a scan size of 25μ×25μ of the surface of a wafer bearing a blanket copper layer which has been annealed at 330° C. for 60 seconds.FIG. 2B shows an atomic force micrograph for the same wafer at a scan size of 5μ×5μ. The hillocks shown in FIGS.2A-B are formed as the copper layer relaxes in response to the application of stress.

One source of such stress-inducing energy may be a semiconductor fabrication process occurring after initial formation of the Cu layer.FIG. 3 shows a flow chart of a series of processing steps that may take place after Cu is deposited on a substrate.

Instep300, a copper layer is deposited on a wafer or substrate. In step302, the wafer bearing the copper layer is exposed to chemical mechanical polishing conditions, which may result in formation of a layer of oxide over the copper.

In steps304a-b, a chamber in which deposition of a barrier layer is to take place is conditioned in preparation to receive the copper-bearing substrate. Specifically, in step304athe chamber is seasoned. In step304bthe chamber may be exposed to a plasma for cleaning purposes. The chamber seasoning and cleaning steps are independent in nature, and substrate processing may occur with either, none, or both steps304aand304bhaving been performed.

Instep306, the substrate is inserted into conditioned deposition chamber. Instep308, flow rates of gases to the deposition chamber are stabilized. Instep310, the stable flow of gases is excited by exposure to a plasma, such that oxide overlying the copper layer is removed. Instep312, the oxide removal plasma is replaced by a plasma containing reactive gases which react to deposit a barrier layer over the copper layer on the substrate.

As discussed in detail below, in accordance with embodiments of the present invention, at one or more points during the process shown inFIG. 3, the processing parameters may be altered to reduce the incidence of hillock formation in the copper layer.

A. Barrier Layer Deposition Chamber Pre-conditioning

Returning to step306 ofFIG. 3, following the chemical mechanical planarization of the copper layer, the wafer is transferred to a different chamber to form the overlying barrier layer by chemical vapor deposition. By employing certain chamber pre-conditioning steps alone or in combination, prior to the wafer entering the barrier layer deposition chamber, the incidence of hillock formation can be significantly reduced.

One such chamber pre-conditioning step in accordance with an embodiment of the present invention is formation of a silicon oxide seasoning layer within the CVD chamber after cleaning, as shown in step304aofFIG. 3. Conventionally, where a layer of silicon nitride is to be deposited on a substrate positioned within a chamber, a seasoning layer is first deposited within the empty chamber. This seasoning layer serves to entrap various particles and contamination already present within the chamber, preventing them from falling onto and compromising the substrate. Where a silicon nitride barrier layer is to be deposited within the chamber, the seasoning layer typically comprises silicon nitride alone, or as a part of a stack of silicon nitride and silicon oxide. In accordance with embodiments of the present invention however, the inventors have discovered that seasoning the cleaned deposition chamber with a layer of silicon oxide alone offers the best results.

Another chamber pre-conditioning step in accordance with an embodiment of the present invention is treatment of the seasoned chamber with a plasma prior to insertion of the wafer, as shown in step304bofFIG. 3. Conventionally, after the chamber in which the barrier layer is to be deposited has been seasoned, the wafer bearing the copper layer is inserted for additional processing. However, in accordance with embodiments of the present invention, it has been discovered that treatment of the seasoned chamber with a plasma prior to insertion of the wafer can reduce hillock formation. Specifically, this post-seasoning plasma treatment step involves the application of a low power density plasma treatment using N₂, N₂O, NH₃, NF₃, or Ar or other noble gases, alone or in various combinations. For purposes of this application, the term low power density plasma treatment refers to treatment by a plasma at 3.0 W cm²or less for 300 mm wafers. TABLE 1 lists typical process parameters which may be employed for a post-seasoning plasma treatment.

	TABLE 1


	PROCESS PARAMETER	RANGE

	Chamber Pressure (Torr)	0.1-100
	Chamber Power (W)	0.1-2000
	Faceplate-to-Wafer Spacing (mils)	100-2000
	N₂Gas Flow Rate (sccm)	100-20,000
	N₂O Gas Flow Rate (sccm)	100-20,000

FIGS.4A-B are electron micrographs showing formation of hillocks in copper layers of wafers processed in two chambers subjected to different pre-conditioning. FIGS.4A-B, and others of the instant application, show the surface of a silicon nitride layer deposited over a processed copper layer. Because subsequent processing of the Cu layer will alter its hillock profile, this deposited SiN layer preserves and accurately mirrors the hillock profile of the underlying Cu layer immediately after processing.

For example,FIG. 4A shows an optical micrograph of a surface of a wafer bearing a blanket Cu layer coated with a nitride layer, in a seasoned chamber that has not been exposed to a post-seasoning plasma treatment.FIG. 4B shows an optical micrograph of a blanket Cu layer coated with a nitride layer, in a seasoned chamber that has been exposed to a post-seasoning plasma treatment in an ambient of N₂and N₂O. Comparison ofFIGS. 4A and 4B indicates significantly fewer hillocks present on the surface of the wafer processed in the chamber having the post-seasoning plasma treatment.

The post-seasoning plasma treatment just described represents only one possible embodiment in accordance with the present invention. In alternative embodiments, the post-seasoning plasma may be generated remotely and then flowed into the processing chamber. In still other alternative embodiments, the post-seasoning plasma may be generated in gases other than N₂or N₂O, for example in NF₃or NH₃, or He or Ar or other noble gases, or combinations thereof.

Moreover, the post-seasoning plasma treatment just described may be utilized alone, or in combination with the silicon oxide seasoning step just described above. Similarly, the silicon oxide seasoning step can be utilized with or without the post-seasoning plasma treatment.

B. CuO Removal

As described above in connection with step302 ofFIG. 3, during or following chemical mechanical planarization of the copper layer, a thin film of CuO may form. This CuO film exhibits relatively high dielectric properties and may undesirably interfere with conductivity of the Cu interconnect metallization structure. Accordingly, duringstep310 the wafer bearing the Cu layer and the CuO film is typically exposed to a plasma prior to deposition of the barrier layer. This plasma reacts with and removes the CuO film.

However, exposing the Cu to plasma energy during the CuO film removal can impart stress to the Cu layer. Relaxation of the film in response to this stress can thereby contribute to formation of hillocks. Accordingly, another approach to reducing hillock incidence is to reduce the energy to which the wafer is exposed immediately prior to and during the CuO removal process.

Prior to exposure to the plasma that removes CuO, the flow of gases into the process chamber is stabilized. During this gas flow stabilization period, the Cu-bearing wafer is exposed to elevated temperatures and can undergo stress and relaxation resulting in hillock formation. Accordingly, one technique employed by embodiments in accordance with the present invention is to reduce the extent of physical contact between the wafer and the wafer heater during this gas flow stabilization phase.

As discussed below in connection with FIGS.12A-B, during loading and unloading of a wafer from the CVD chamber, the wafer is placed upon lift pins which extend upward from the surface of the wafer support/heater. The lift pins then retract into the surface of the support/heater prior to deposition of materials to place the wafer in contact with the surface of the support/heater structure.

The continuous heating and cooling of a substrate support would give rise to undesirable time delays and temperature variation. Accordingly, a voltage is generally constantly applied to the heater, even between wafer processing steps when the chamber is empty. To reduce stress imparted by contact between the substrate and the constantly-heated heater, during gas flow stabilization prior to formation of the plasma removing CuO, the apparatus may be operated in accordance with an embodiment of the present invention to place the wafer in contact with only the lift pins, elevated over the surface of the heater. This positioning of the wafer reduces physical contact between the wafer and the heater, and may potentially reduce by between about 100-150° C. the effective temperature experienced by the wafer. This reduction in the amount of thermal energy imparted to the wafer and the Cu layer formed thereon reduces the chance of stress relaxation and hillock formation. Immediately prior to actual plasma exposure the lift pins retract into the heater surface and place the back side of the wafer into direct contact with the heater.

FIG. 5A shows an optical micrograph of a wafer bearing a Cu blanket having an overlying deposited nitride layer, where the wafer was placed into direct contact with the wafer heater during the entire gas flow stabilization step.FIG. 5B shows an optical micrograph of a wafer bearing a deposited Cu blanket layer having an overlying deposited nitride layer, that has been supported above the surface of the wafer heater on lift pins during the gas flow stabilization period. Comparison ofFIGS. 5A and 5B reveals substantially reduced hillock formation on the wafer suspended over the heater during stabilization.

Research has indicated that bombardment of the Cu layer by ions during removal of the CuO by plasma exposure also imparts stress and relaxation in a Cu film, potentially creating hillocks. Thus another approach to reducing hillock formation in accordance with an embodiment of the present invention is to reduce ion bombardment of the Cu film during the CuO removal step.

Increasing the pressure at which the plasma is generated, and the spacing between the wafer and the gas distribution face plate during the CuO plasma removal step, may serve to reduce ion bombardment. This is illustrated in connection with FIGS.6A-D, which show optical micrographs of the surface of a wafer bearing a silicon nitride layer deposited over a blanket Cu layer that was exposed to plasma under various conditions.FIGS. 6A and 6C show edge and center portions respectively, of a wafer exposed to a plasma at a pressure of 4.2 torr and an N₂gas flow of 5000 sccm, with spacing between the gas distribution face plate and the wafer of about 350 mils (0.35″).FIGS. 6B and 6D show edge and center portions respectively, of a wafer exposed to a plasma at a pressure of 8 torr and an N₂gas flow of 9000 sccm, with a spacing between the gas distribution face plate and the wafer of about 560 mil (0.56″). Comparison ofFIG. 6A withFIG. 6B, and ofFIG. 6C withFIG. 6D, indicate that significantly fewer hillocks are present on the wafer that has been subjected to oxide removal by plasma at higher pressures at larger face plate-to-wafer spacings.

Still another approach to reducing hillock formation is to reduce the duration of the plasma treatment to remove CuO, such that the wafer is exposed to ion bombardment for a shorter period of time.FIG. 7A shows atomic force micrographs of a surface of a wafer bearing a blanket Cu layer after exposure to plasma for 15 seconds to remove CuO. The rms roughness of the layer ofFIG. 7A is 4.8 nm.FIG. 7B shows atomic force micrographs of a blanket Cu layer after exposure to plasma under the same conditions as inFIG. 7A, except for a duration of only 10 seconds. The rms roughness of the layer ofFIG. 7B is 4.1 nm, illustrating a reduction in the incidence of hillock formation.

Yet another approach to reducing hillock formation based upon plasma treatment to remove CuO is to control the composition of the gases present in the processing chamber during this plasma exposure step. For example, it is expected that removal of the CuO by exposure to plasma will be followed by deposition of the nitride barrier layer under plasma conditions. Hence, conventionally the step of removing the CuO through exposure to plasma takes place in a similar ambient as the subsequent deposition step, namely in an ambient containing ammonia (NH₃).

Typically however, carrier gases are also present in the chamber along with NH₃during the step of removing CuO through plasma exposure. In accordance with one embodiment of the present invention, it may therefore be possible to reduce ion bombardment by performing this CuO removal step in an ambient comprising NH₃only. FIGS.8A-D show optical micrographs of the surface of wafers bearing Cu blanket layers having deposited nitride layers, after exposure of the Cu layer to plasma under various conditions.FIGS. 8A and 8C show optical micrographs of center and edge portions respectively, of the surface of wafers bearing Cu blanket layers after exposure to a plasma for 15 seconds in an ambient of N₂and NH₃.FIGS. 8B and 8D show optical micrographs of center and edge portions respectively, of the surface of wafers bearing Cu blanket layers after exposure to a plasma in an ambient of NH₃only for a longer period (20 seconds). Comparison ofFIG. 8A withFIG. 8B, and ofFIG. 8C withFIG. 8D, indicates that significantly fewer hillocks are present on the wafer exposed to plasma in the lower molecular weight (NH₃only) ambient.

Moreover, as the role of the plasma in the CuO removal step is simply to react with and remove a thin layer of material, it may further be possible to substitute gases other than NH₃during this step, and thereby further reduce the energy of ion bombardment. FIGS.9A-D show photographs of a Cu blanket layer after exposure to plasma under various conditions.FIGS. 9A and 9C show optical micrographs of center and edge portions respectively, of the surface of wafers bearing Cu blanket layers having deposited nitride layers, where the Cu layer is exposed to a plasma for 15 seconds in a NH₃ambient.FIGS. 9B and 9D show optical micrographs of center and edge portions respectively, of the surface of wafers bearing Cu blanket layers having deposited nitride layers, where the Cu layer is exposed to a plasma in an ambient comprising molecular hydrogen (H₂) having a substantially lower molecular weight (M.W.=2) than ammonia (M.W.=17). Comparison ofFIG. 9A withFIG. 9B, and ofFIG. 9C withFIG. 9D, reveals significantly fewer hillocks on the wafer exposed to the H₂plasma.

C. Post-Cu Removal Processes

As shown instep312 ofFIG. 3, once the barrier layer deposition chamber has been conditioned and the CuO film removed by exposure to plasma, the chamber is operated to expose the wafer to conditions that result in deposition of a barrier layer over the Cu layer. In accordance with embodiments of the present invention, various post-CuO removal process parameters may also be controlled to minimize hillock formation.

Research has indicated that the hillocks grow on the Cu layer prior to deposition of the barrier layer, and that relative stiffness of the overlying deposited barrier layer will likely act as a physical barrier to inhibit growth of hillocks out of the plane of the Cu layer. This conclusion is supported by the experimental results shown in FIGS.10A-D.FIG. 10A shows an optical micrograph of a surface of a wafer bearing a blanket Cu layer prior to exposure of the Cu layer to any additional thermal energy.FIG. 10B shows an optical micrograph of a Cu blanket layer after the Cu layer has been heated at 400° C. for 60 seconds. Comparison ofFIGS. 10A and 10B show significant hillock formation in the blanket Cu layer exposed to the thermal treatment.

FIG. 10C shows an optical micrograph of a surface of a wafer bearing a nitride layer deposited over a Cu blanket layer prior to any heating of the Cu blanket layer. FIG.10D shows an optical micrograph of a Cu blanket layer bearing a deposited nitride layer, after the Cu/SiN stack has been exposed to thermal treatment at 450° C. for 60 seconds. Comparison ofFIGS. 10C and 10D show little significant hillock formation in the presence of the overlying nitride barrier layer. Thus in accordance with embodiments of the present invention, hillock growth can be suppressed by forming an overlying nitride layer prior to exposing the copper layer to additional thermal energy.

In one approach, thermal exposure of the Cu film immediately prior to barrier layer deposition may be minimized by reducing the time required for stabilization of the process gas. For some period prior to plasma reaction of the reactant gases to form the layer of the barrier material over the Cu metallization layer, some or all of the reactant gases may be flowed with the wafer present in the chamber in order to stabilize the gas flow rate. During this pre-deposition gas flow stabilization phase, the wafer is exposed to high temperatures and hence energy and stress may be imparted to the film. By reducing the duration of this gas flow stabilization phase, for example from 15 sec. to 5 sec. for deposition of a SiN barrier layer on a 200 mm wafer, or from 30 sec to 15 sec for deposition of a SiN barrier layer on a 300 mm wafer, the incidence of hillock formation can be substantially suppressed.

Another approach for reducing hillock formation during barrier layer deposition is to reduce the temperature at which deposition takes place.FIG. 11A shows an optical micrograph of the surface of a wafer bearing a nitride layer deposited over a Cu blanket layer at a temperature of 400° C. Under these conditions, the nitride layer exhibited an rms roughness of 6.2 nm.FIG. 11B shows an optical micrograph of the surface of a wafer bearing a nitride layer deposited over a Cu blanket layer at a temperature of 350° C. for the same period of time as the wafer ofFIG. 11A. Under deposition at these reduced temperature conditions, the nitride layer exhibited an rms roughness of 5.4 nm, a reduction of 10-20% relative to the sample exposed to 400° C. inFIG. 11A. Comparison ofFIGS. 11A and 11B reveals that the wafer exposed to the lower temperature exhibited less roughness and reduced hillock formation.

II. Processing Apparatuses

Embodiments of the invention may be performed in the processing chamber of any suitable processing apparatus, such as the PRODUCER® plasma enhanced chemical vapor deposition (PECVD) apparatus manufactured by Applied Materials Inc., of Santa Clara, Calif. In a PECVD apparatus, process gases are excited and/or dissociated by the application of energy such as radio frequency (RF) energy to form a plasma. The plasma contains ions of the process gases and reacts at the surface of the substrate to form a layer of material.

An example of a PECVD apparatus is shown inFIG. 12A.FIG. 12A shows a system10 including aprocessing chamber30, avacuum system88, a gas delivery system89, anRF power supply5, a heat exchanger system6, a substrate pedestal/heater32 and aprocessor85 among other major components. A gas distribution manifold (also referred to as an inlet manifold, a face plate, or “showerhead”)40 introduces process gases supplied from the gas delivery system89 into areaction zone58 of theprocessing chamber30. The heat exchange system6 may employ a liquid heat exchange medium, such as water or a water-glycol mixture, to remove heat from theprocessing chamber30 and maintain certain portions of theprocessing chamber30 at a suitable temperature.

The gas delivery system89 delivers gases to theprocessing chamber30 via gas lines92A-C. The gas delivery system89 includes agas supply panel90 and gas or liquid orsolid sources91A-C (additional sources may be added if desired), containing gases (such as SiH₄, ozone, halogenated gases, or N₂) or liquids (such as TEOS) or solids. Thegas supply panel90 has a mixing system that receives the process gases and carrier gases (or vaporized liquids) from thesources91A-C. Process gases may be mixed and sent to acentral gas inlet44 in a gas feed cover plate45 via the supply lines92A-C (other lines may be present, but are not shown).

Process gas is injected intoprocessing chamber30 through thecentral gas inlet44 in the gas-feed cover plate45 to a first disk-shaped space48. Heat exchanger passages79 may be provided in the cover plate45 to maintain the cover plate45 at a desired temperature. The process gas passes through passageways (not shown) in a baffle plate (or gas blocker plate)52 to a second disk-shaped space54 and then to the showerhead40. The showerhead40 includes a large number of holes orpassageways42 for supplying the process gas intoreaction zone58. Process gas passes from theholes42 in the showerhead40 into thereaction zone58 between the showerhead40 and thepedestal32. Once in thereaction zone58, the process gas reacts on the wafer36. Byproducts of the reaction then flow radially outward across the edge of the wafer36 and a flow restrictor ring46, which is disposed on the upper periphery ofpedestal32. Then, the process gas flows through a choke aperture formed between the bottom of an annular isolator and the top of chamber wall liner assembly53 into a pumping channel60.

Thevacuum system88 maintains a specified pressure in theprocess chamber30 and removes gaseous byproducts and spent gases from theprocess chamber30. Thevacuum system88 includes avacuum pump82 and athrottle valve83. Upon entering the pumping channel60, the exhaust gas is routed around the perimeter of theprocessing chamber30, and is evacuated by avacuum pump82. The pumping channel60 is connected through theexhaust aperture74 to apumping plenum76. Theexhaust aperture74 restricts the flow between the pumping channel60 and thepumping plenum76. Avalve78 gates the exhaust through anexhaust vent80 to thevacuum pump82.

Thepedestal32 may be made of ceramic and may include an embedded RF electrode (not shown), such as an embedded molybdenum mesh. A heating element such as a resistive heating element (e.g., an embedded molybdenum wire coil) or a coil containing a heating fluid may also be in thepedestal32. Alternatively or additionally, a cooling element (not shown) may be included in thepedestal32. Thepedestal32 may be made from aluminum nitride and is preferably diffusion bonded to a ceramic support stem26 that is secured to a water cooledaluminum shaft28 that engages a lift motor (not shown). Theceramic support stem26 and thealuminum shaft28 have a central passage that is occupied by anickel rod25 that transmits low frequency RF power to the embedded electrode.

Thepedestal32 may support the wafer36 in a wafer pocket34 when the wafer36 is on thepedestal32. Thepedestal32 may move vertically and may be positioned at any suitable vertical position. For example, when thepedestal32 is in a lower loading position (slightly lower than at slit valve56), a robot blade (not shown) in cooperation with the lift pins38 and a lifting ring transfers the wafer36 in and out ofchamber30 through aslit valve56. Theslit valve56 vacuum-seals theprocessing chamber30 to prevent the flow of gas into or out of theprocessing chamber30. When thepedestal32 is disposed in a lower position, the lift pins38 (which may be stationary) support the wafer36. The robot blade (not shown) used to transfer the wafer36 into the chamber is withdrawn. The wafer36 may remain on the lift pins38 so that the wafer36 can be processed according to the first process. Thepedestal32 may rise to raise the wafer36 off the lift pins38 onto the upper surface of thepedestal32 so that the wafer36 can be heated to a second temperature suitable for a second process. Thepedestal32 may further raise the wafer36 so that the wafer36 is any suitable distance from the gas distribution manifold40.

Motors and optical sensors (not shown) may be used to move and determine the position of movable mechanical assemblies such as thethrottle valve83 and thepedestal32. Bellows (not shown) attached to the bottom of thepedestal32 and the chamber body11 form a movable gas-tight seal around thepedestal32. Theprocessor85 controls the pedestal lift system, motors, gate valve, plasma system, and other system components overcontrol lines3 and3A-C. Theprocessor85 may execute computer code for controlling the apparatus. Amemory86 coupled to theprocessor85 may store the computer code. Theprocessor85 may also control a remote plasma system4. In some embodiments, the remote plasma system4 may include a microwave source and may be used to form a plasma that can be used to clean theprocess chamber30 or process the wafer36. Computer code may be used to control chamber components that may be used to load the wafer36 onto thepedestal32, lift the wafer36 to a desired height in thechamber30, control the spacing between the wafer36 and the showerhead40, and keep the lift pins38 above the upper surface of thepedestal32.

FIG. 12B is an illustrative block diagram of the hierarchical control structure of the system control software,computer program150, according to a specific embodiment. A processes for depositing a film, performing a clean, or performing reflow or drive-in can be implemented using a computer program product that is executed by theprocessor85. The computer program code can be written in any conventional computer readable programming language, such as 68000 assembly language, C, C++, Pascal, Fortran, or other language. Suitable program code is entered into a single file, or multiple files, using a conventional text editor and is stored or embodied in a computer-usable medium, such as the system memory.

If the entered code text is in a high-level language, the code is compiled, and the resultant compiler code is then linked with an object code of precompiled WINDOWS™ library routines. To execute the linked compiled object code, the user invokes the object code, causing the computer system to load the code in memory, from which the CPU reads and executes the code to configure the apparatus to perform tasks identified in the program.

A user enters a process set number and process chamber number into aprocess selector subroutine153 by using the light pen to select a choice provided by menus or screens displayed on a CRT monitor. The process sets, which are predetermined sets of process parameters necessary to carry out specified processes, are identified by predefined set numbers. Theprocess selector subroutine153 identifies the desired set of process parameters needed to operate the process chamber for performing the desired process. The process parameters for performing a specific process relate to process conditions such as, for example, process gas composition and flow rates, temperature, pressure, plasma conditions such as magnetron power levels (and alternatively to or in addition to high- and low-frequency RF power levels and the low-frequency RF frequency, for embodiments equipped with RF plasma systems), cooling gas pressure, and chamber wall temperature. Theprocess selector subroutine153 controls what type of process (e.g. deposition, wafer cleaning, chamber cleaning, chamber gettering, reflowing) is performed at a certain time in the chamber. In some embodiments, there may be more than one process selector subroutine. The process parameters are provided to the user in the form of a recipe and may be entered utilizing the light pen/CRT monitor interface.

Aprocess sequencer subroutine155 has program code for accepting the identified process chamber and process parameters from theprocess selector subroutine153, and for controlling the operation of the various process chambers. Multiple users can enter process set numbers and process chamber numbers, or a single user can enter multiple process set numbers and process chamber numbers, soprocess sequencer subroutine155 operates to schedule the selected processes in the desired sequence. Preferably, theprocess sequencer subroutine155 includes program code to perform the tasks of (i) monitoring the operation of the process chambers to determine if the chambers are being used, (ii) determining what processes are being carried out in the chambers being used, and (iii) executing the desired process based on availability of a process chamber and the type of process to be carried out.

Conventional methods of monitoring the process chambers, such as polling methods, can be used. When scheduling which process is to be executed, theprocess sequencer subroutine155 can be designed to take into consideration the present condition of the process chamber being used in comparison with the desired process conditions for a selected process, or the “age” of each particular user-entered request, or any other relevant factor a system programmer desires to include for determining scheduling priorities.

Once theprocess sequencer subroutine155 determines which process chamber and process set combination is going to be executed next, theprocess sequencer subroutine155 initiates execution of the process set by passing the particular process set parameters to a chamber manager subroutine157a-cwhich controls multiple processing tasks in the process chamber according to the process set determined by theprocess sequencer subroutine155. For example, thechamber manager subroutine157ahas program code for controlling CVD and cleaning process operations in the process chamber. Chamber manager subroutine157 also controls execution of various chamber component subroutines which control operation of the chamber components necessary to carry out the selected process set. Examples of chamber component subroutines aresubstrate positioning subroutine160, processgas control subroutine163,pressure control subroutine165,heater control subroutine167,plasma control subroutine170, endpoint detectcontrol subroutine159, and gettering control subroutine169.

Depending on the specific configuration of the CVD chamber, some embodiments include all of the above subroutines, while other embodiments may include only some of the subroutines. Those having ordinary skill in the art would readily recognize that other chamber control subroutines can be included depending on what processes are to be performed in the process chamber.

In operation, thechamber manager subroutine157aselectively schedules or calls the process component subroutines in accordance with the particular process set being executed. Thechamber manager subroutine157aschedules the process component subroutines much like theprocess sequencer subroutine155 schedules which process chamber and process set are to be executed next. Typically, thechamber manager subroutine157aincludes the steps of monitoring the various chamber components, determining components to be operated based on the process parameters for the process set to be executed, and initiating execution of a chamber component subroutine responsive to the monitoring and determining steps.

Operation of particular chamber component subroutines will now be described with reference to FIGS.12A-B. Thesubstrate positioning subroutine160 comprises program code for controlling chamber components that are used to load the substrate onto theheater32 and, optionally, to lift the substrate to a desired height in the chamber to control the spacing between the substrate and the gas distribution face plate. When a substrate is loaded into theprocess chamber30, theheater32 is lowered to receive the substrate and then theheater32 is raised to the desired height. In operation, thesubstrate positioning subroutine160 controls movement of theheater32 in response to process set parameters related to the support height that are transferred from thechamber manager subroutine157a. As discussed above, in certain embodiments thesubstrate positioning subroutine160 may be used to vary the height of the heater, and thus the spacing between the heater and the gas distribution plate40, during the post-seasoning plasma treatment to heat the face plate and thereby reduce the steepness of the thermal gradient between the face plate and a wafer positioned on the heater. As also discussed above, in certain other embodiments thesubstrate positioning subroutine160 may be used to suspend the substrate on lift pins at a height over the heater surface during gas stabilization, thereby reducing the thermal budget of the wafer during this step.

Processgas control subroutine163 controls the character of the process gases flowed into the chamber. Processgas control subroutine163 can be designed to vary over time the relative flow rates of the various process gases inlet to the chamber, and hence the pressure within the chamber. Such variation in pressure can result in desirable processing to suppress formation of hillocks, as has been described above.

The processgas control subroutine163 has program code for controlling process gas composition and flow rates, for example to flow only ammonia or low molecular weight gases to reduce ion bombardment during the plasma exposure step to remove CuO. The processgas control subroutine163 controls the state of safety shut-off valves, and also ramps the mass flow controllers up or down to obtain the desired gas flow rate. Typically, the processgas control subroutine163 operates by opening the gas supply lines and repeatedly (i) reading the necessary mass flow controllers, (ii) comparing the readings to the desired flow rates received from thechamber manager subroutine157a, and (iii) adjusting the flow rates of the gas supply lines as necessary. Furthermore, the processgas control subroutine163 includes steps for monitoring the gas flow rates for unsafe rates, and activating the safety shut-off valves when an unsafe condition is detected. Alternative embodiments could have more than one process gas control subroutine, each subroutine controlling a specific type of process or specific sets of gas lines.

In some processes, an inert gas, such as nitrogen or helium, is flowed into the chamber to stabilize the pressure in the chamber before reactive process gases are introduced. For these processes, processgas control subroutine163 is programmed to include steps for flowing the inert gas into the chamber for an amount of time necessary to stabilize the pressure in the chamber, and then the steps described above would be carried out.

Thepressure control subroutine165 comprises program code for controlling the pressure in the chamber by regulating the aperture size of the throttle valve in the exhaust system of the chamber. The aperture size of the throttle valve is set to control the chamber pressure at a desired level in relation to the total process gas flow, the size of the process chamber, and the pumping set-point pressure for the exhaust system. When thepressure control subroutine165 is invoked, the desired or target pressure level is received as a parameter from thechamber manager subroutine157a. Thepressure control subroutine165 measures the pressure in the chamber by reading one or more conventional pressure manometers connected to the chamber, compares the measure value(s) to the target pressure, obtains proportional, integral, and differential (“PID”) values corresponding to the target pressure from a stored pressure table, adjusting the throttle valve according to these values.

Alternatively, thepressure control subroutine165 can be written to open or close the throttle valve to a particular aperture size, i.e. a fixed position, to regulate the pressure in the chamber. Controlling the exhaust capacity in this way does not invoke the feedback control feature of thepressure control subroutine165.

Theheater control subroutine167 comprises program code for controlling the current to a heating unit that is used to heat the substrate. Theheater control subroutine167 is also invoked by thechamber manager subroutine157aand receives a target, or set-point, temperature parameter. As discussed above, in certain embodiments this temperature preset may be zero during the barrier layer deposition step to reduce thermal stress on the wafer. Theheater control subroutine167 measures the temperature by measuring voltage output of a thermocouple located in the heater, comparing the measured temperature to the set-point temperature, and increasing or decreasing current applied to the heating unit to obtain the set-point temperature. The temperature is obtained from the measured voltage by looking up the corresponding temperature in a stored conversion table, or by calculating the temperature using a fourth-order polynomial. Theheater control subroutine167 includes the ability to gradually control a ramp up or down of the heater temperature. This feature helps to reduce thermal cracking in the ceramic heater. Additionally, a built-in fail-safe mode can be included to detect process safety compliance, and can shut down operation of the heating unit if the process chamber is not properly set up.

Theplasma control subroutine170 comprises program code for controlling the application of rf power that is used to strike and maintain a plasma within the chamber. As discussed above, in connection with certain embodiments theplasma control subroutine170 may direct the application of a power to generate a low density plasma within the chamber following cleaning and seasoning.Plasma control subroutine170 may also direct the application of power to generate the subsequent plasmas utilized for CuO removal and barrier layer deposition.

To summarize: utilizing the techniques of the present invention alone or in combination, the incidence of hillock formation in copper layers of processed semiconductor wafers can be significantly reduced. This result was accomplished by controlling a first set of process parameters to condition the barrier layer deposition chamber prior to insertion of the wafer bearing the copper layer. Examples of this first set of process parameters include but are not limited to seasoning the deposition chamber with an oxide layer, and post-seasoning treatment of the chamber with plasma to densify the seasoning layer present therein.

A second set of process parameters may be controlled to minimize the energy to which the copper layer is exposed during removal of an overlying residual copper oxide layer. Examples of this second set of process parameters include but are not limited to the pressure and showerhead-to-wafer spacing during generation of an oxide removal plasma, the composition of gases present during this plasma exposure step, and the duration and position of the wafer during the gas flow stabilization step immediately preceding plasma formation.

Finally, a third set of process parameters may be controlled to minimize the thermal budget to which the copper layer is exposed during formation of the barrier layer. Examples of this third set of process parameters include but are not limited to the temperature preset of the wafer heater, the duration of gas flow stabilization, and the deposition temperature.

The above-described experimental results were obtained utilizing a Applied Materials PRODUCER® system. As a person of ordinary skill in the art would understand however, techniques for minimizing hillock formation in accordance with embodiments of the present invention are not limited to this particular apparatus, and could be employed in conjunction with other systems.

The above description is illustrative and not restrictive, and as such the process parameters listed above should not be limiting to the claims as described herein. For example, the various techniques employed for reducing hillock formation are separate and distinct, and thus it should be recognized that they may be employed alone or in various combinations to reduce the incidence of hillock formation.

In addition, while the embodiment described above discusses removal of the CuO layer through plasma exposure in the same chamber as subsequent deposition of the barrier layer, this is not required by the present invention. Alternative embodiments in accordance with the present invention could remove the CuO film through plasma exposure in a separate processing chamber, with transfer of the wafer to the barrier deposition chamber accomplished under non-oxidizing conditions to prevent the CuO film from re-forming. In such an embodiment, two distinct periods of gas flow stabilization would be used, with the duration of one or more of these periods reduced to minimize stress on the wafer. In addition, the inserted wafer could be suspended above the heater surface on lift pins during one or both of these periods of gas flow stabilization.

Moreover, while the invention has been illustrated above with particular reference to the reduction of the incidence of hillock formation in copper metallization layers following formation of a barrier layer comprising silicon nitride, one of ordinary skill in the art would recognize that the present invention is not limited to this particular type of dielectric barrier layer. Methods and apparatuses in accordance with embodiments of the present invention apply to silicon nitride, silicon carbide, SiCN, oxygen doped SiC, and other dielectric barrier materials such as the BLOK® and Black Diamond® materials produced by Applied Materials, Inc.

While the above discussion has focused upon the reduction of incidence of hillock formation during the formation of copper metallization layers utilized in the formation of damascene interconnect structures, the present invention is not limited to this particular type of metallization material or application. Rather, embodiments in accordance with the present invention are generally applicable to controlling the microstructure of other metals utilized in other metallization schemes.

The scope of the invention may be determined with reference to the above description and to the appended claims, along with their full scope of equivalents.