US20080073769A1 - Semiconductor package and semiconductor device - Google Patents
Semiconductor package and semiconductor deviceDownload PDFInfo
- Publication number
- US20080073769A1 US20080073769A1US11/828,351US82835107AUS2008073769A1US 20080073769 A1US20080073769 A1US 20080073769A1US 82835107 AUS82835107 AUS 82835107AUS 2008073769 A1US2008073769 A1US 2008073769A1
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- substrate
- top surface
- height
- molding compound
- chip
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Definitions
- the present inventionrelates to a semiconductor package and a method of making the same, and particularly to a semiconductor package comprising a molding compound with different heights and a semiconductor device comprising the semiconductor package and methods of making the same.
- FIG. 1showing a schematic diagram of a conventional semiconductor device consisting of stacked packages.
- the conventional semiconductor device 1comprises a first package 10 and a second package 20 .
- the first package 10comprises a first substrate 11 , a first chip 12 , a plurality of first conductive wires 13 , a first molding compound 14 , and a plurality of first solder balls 15 .
- the first substrate 11has an upper surface 111 , a lower surface 112 , and a plurality of first pads 113 .
- the first pads 113are disposed on the upper surface 111 of the first substrate 11 .
- the first chip 12is adhered to the upper surface 111 of the first substrate 11 and electrically connected to the upper surface 111 of the first substrate 11 by the first conductive wires 13 .
- the first molding compound 14encapsulates the first chip 12 , the first conductive wires 13 , and a part of the upper surface 111 of the first substrate 11 , and the first pads 113 are exposed.
- the first solder balls 15are on the lower surface 112 of the first substrate 11 .
- the second package 20is stacked on the first package 10 .
- the second package 20comprises a second substrate 21 , a second chip 22 , a plurality of second conductive wires 23 , a second molding compound 24 , and a plurality of second solder balls 25 .
- the second substrate 21has an upper surface 211 , a lower surface 212 , and a plurality of second pads 213 .
- the second pads 213are disposed on the lower surface 212 of the second substrate 21 .
- the second chip 22is adhered to the upper surface 211 of the second substrate 21 and electrically connected to the upper surface 211 of the second substrate 21 by the second conductive wires 23 .
- the second molding compound 24encapsulates the second chip 22 , the second conductive wires 23 , and the upper surface 211 of the second substrate 21 .
- the upper ends of the second solder balls 25are connected to the second pads 213 on the lower surface 212 of the second substrate 21 , and the lower ends are connected to the first pads 113 on the upper surface 111 of the first substrate 11 .
- One of the drawbacks of the conventional semiconductor device 1is that the area encapsulated by the first molding compound 14 in the first package 10 is smaller than that encapsulated by the second molding compound 24 in the second package 20 .
- two different moldsare required in the molding processes for the first package 10 and the second package 20 .
- the costis high for making a mold. Molds of different sizes are often needed for molding processes to make different package devices. Accordingly, the production cost will be dramatically increased.
- the included angleis namely the draft angle of the mold.
- the top surface of the first molding compound 14has a mold insert gate mark.
- the first molding compound 14tends to overflow onto the upper surface 111 of the first substrate 11 to pollute the first pads 113 .
- One main objective of the present inventionis to provide a method of making a semiconductor package comprising the following steps of: providing a first substrate having a first surface and a second surface; attaching a first chip to the first surface of the first substrate; forming a plurality of first connecting elements for electrically connecting the first chip and the first substrate; forming a plurality of first conductive bodies on the first surface of the first substrate; forming a first molding compound for encapsulating the first surface of the first substrate, the first chip, the first connecting elements, and the first conductive bodies; and removing a part of a border portion of the first molding compound, so that the first molding compound has at least two heights and one end of each of the first conductive bodies is exposed.
- Another objective of the present inventionis to provide a semiconductor package, which comprises a substrate, a chip, a plurality of connecting elements, a plurality of first conductive bodies, and a molding compound.
- the substratehas a first surface and a second surface.
- the chipis attached to the first surface of the substrate.
- the connecting elementselectrically connect the chip and the substrate.
- the first conductive bodiesare disposed on the first surface of the substrate.
- the molding compoundencapsulates the first surface of the substrate, the chip, the connecting elements, and the first conductive bodies.
- the molding compoundhas at least two heights and one end of each of the first conductive bodies is exposed. Thereby, the molding compound encapsulates the entire first surface of the substrate, and the pads on the first surface will not be polluted.
- Still another objective of the present inventionis to provide a semiconductor device, which comprises a first package and a second package.
- the first packageis the semiconductor package as described above.
- the second packageis stacked on the first package.
- the size of the second packageis the same as that of the first package.
- FIG. 1shows a schematic diagram of a conventional semiconductor device consisting of stacked packages
- FIG. 2shows a flow chart of the method of making a semiconductor device according to the present invention.
- FIGS. 3 to 8show schematic step by step diagrams illustrating the method of making a semiconductor device according to the present invention.
- Step S 201a first substrate 31 is provided.
- the first substrate 31has a first surface 311 , a second surface 312 , a plurality of first pads 313 , and a plurality of second pads 314 .
- the first pads 313are on the first surface 311
- the second pads 314are on the second surface 312 .
- Step S 202a first chip 32 is attached to the first surface 311 of the first substrate 31 .
- a first chip 32is attached to the first surface 311 of the first substrate 31 .
- a plurality of first connecting elements(such as a plurality of first conductive wires 33 ) electrically connect the first chip 32 and the first surface 311 of the first substrate 31 .
- a plurality of first conductive bodies(such as a plurality of first solder balls 34 ) are formed on the first pads 313 on the first surface 311 of the first substrate 31 .
- the first conductive bodiesmay be solder balls; however, it may be realized that the first conductive bodies can be solder bumps, gold stud bumps, or metal pins and each in a shape of pillar or column, in addition to a shape of ball.
- Step S 204is performed and followed by Step S 202 and Step S 203 . That is, the first conductive bodies (such as the first solder balls) may be formed on the first pads 313 on the first surface 311 of the first substrate 31 before the first chip 32 is attached to the first surface 311 of the first substrate 31 . Thereafter, the first conductive elements (such as the first conductive wires 33 ) are formed for electrically connecting the first chip 32 and the first surface 311 of the first substrate 31 .
- the first conductive bodiessuch as the first solder balls
- the first conductive elementssuch as the first conductive wires 33
- Step S 205a first molding compound 35 for encapsulating the first surface 311 of the first substrate 31 , the first chip 32 , the first conductive wires 33 , and the first solder balls 34 .
- the first molding compound 35encapsulates the entire first surface 311 of the first substrate 31 .
- the top surface of the first molding compound 35is higher than the top of the first solder balls 34 ; however, it may be realized that the top surface of the first molding compound 35 can be at the same height with the top of the first solder balls 34 , or the top surface of the first molding compound 35 can be lower than the top of the first solder balls 34 .
- the included angle between the sidewall of the first molding compound 35 and the first substrate 31is about 85 to 95 degrees, and preferably 90 degrees, because the draft angle is almost not needed for the mold in the present invention.
- a plurality of the first chips 32may be encapsulated with the first molding compound 35 and thereafter divided into a plurality of packages having a shape like tofu. Thereby, the top surface of the first molding compound 35 in the packages will not have a mold insert gate mark.
- Step S 206a plurality of second solder balls 36 are formed on the second pads 314 on the second surface 312 of the first substrate 31 . It should be noted that this step is an optional step.
- Step S 207a part of a border portion of the first molding compound 35 is removed, so that the first molding compound 35 has at least two heights and one end of each of the first solder balls 34 is exposed to make a first package 3 .
- the removal in this stepmay be accomplished by laser cutting, chemical etching, cutting with a cutting tool, or cutting with a water jet.
- the way of cutting with a cutting toolis used to remove the upper part 351 of the border portion of the first molding compound 35 , and the lower part 352 of the border portion is remained.
- the central portion 353 of the first molding compound 35is not cut away and is entirely remained.
- the molding compound 35has a first height H 1 , a second height H 2 , a central portion 353 , a lower part 352 of a border portion, a first top surface 354 , and a second top surface 355 .
- the first height H 1is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33 .
- the second height H 2is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34 .
- the first height H 1is greater than the second height H 2 .
- the first top surface 354is corresponding to the first height H 1 , that is, the first top surface 354 is the top surface of the central portion 353 .
- the first top surface 354has a first surface roughness.
- the second top surface 355is corresponding to the second height H 2 , that is, the second top surface 355 is the top surface of the lower part 352 of the border portion.
- the second top surface 355has a second surface roughness.
- the first surface roughnessis different from the second surface roughness.
- the second top surface 355is a cutting surface and has a plurality of cutting lines 37 after the cutting.
- the upper parts of the first solder balls 34are removed along with the removal of the upper part 351 of the border portion of the first molding compound 35 . Therefore, only the lower parts of the first solder balls 34 are remained to form a hemispherical shape (as shown in FIG. 6 ). Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37 . As shown in FIG.
- the cutting lines 37 located at each of the four sides of the second top surface 355are substantially parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
- the first package 3comprises a first substrate 31 , a first chip 32 , a plurality of first connecting elements (such as a plurality of first conductive wires 33 ), a plurality of first conductive bodies (such as a plurality of first solder balls 34 ), a first molding compound 35 , and a plurality of second solder balls 36 .
- the first substrate 31has a first surface 311 , a second surface 312 , a plurality of first pads 313 on the first surface 311 , and a plurality of second pads 314 on the second surface 312 .
- the first chip 32is attached to the first surface 311 of the first substrate 31 .
- the first chip 32is attached to the first surface 311 of the first substrate 31 .
- the first conductive wires 33electrically connect the first chip 32 and the first substrate 31 .
- the first solder balls 34are in a hemispherical shape and disposed on the first pads 313 of the first surface 311 of the first substrate 31 .
- the second solder balls 36are disposed on the second pads 314 of the second surface 312 of the first substrate 31 .
- the molding compound 35encapsulates the first surface 311 of the first substrate 31 , the first chip 32 , the first conductive wires 33 , and the first solder balls 34 .
- the molding compound 35has a first height H 1 , a second height H 2 , a central portion 353 , a lower part 352 of a border portion, a first top surface 354 , and a second top surface 355 .
- the first height H 1is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33 .
- the second height H 2is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34 .
- the first height H 1is greater than the second height H 2 .
- the first top surface 354is corresponding to the first height H 1 , that is, the first top surface 354 is the top surface of the central portion 353 .
- the first top surface 354has a first surface roughness.
- the second top surface 355is corresponding to the second height H 2 , that is, the second top surface 355 is the top surface of the lower part 352 of the border portion.
- the second top surface 355has a second surface roughness. The first surface roughness is different from the second surface roughness.
- the second top surface 355is a cutting surface and has a plurality of cutting lines 37 after the cutting. Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37 . As shown in FIG. 7 , the cutting lines 37 located at each of the four sides of the second top surface 355 are parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
- a second package 4is stacked on the first solder balls 34 and electrically connected to the first solder balls 34 , to make a semiconductor device 5 .
- the second package 4may be any kind of semiconductor packages.
- the second package 4comprises a second substrate 41 , a second chip 42 , a plurality of second conductive wires 43 , a second molding compound 44 , and a plurality of third solder balls 45 .
- the second substrate 41has a first surface 411 and a second surface 412 .
- the second chip 42is attached to the first surface 411 of the second substrate 41 .
- the second conductive wires 43electrically connect the second chip 42 and the second substrate 41 .
- the second molding compound 44encapsulates the first surface 411 of the second substrate 41 , the second chip 42 , and the second conductive wires 43 .
- the third solder balls 45are disposed on the second surface 412 of the second substrate 41 and electrically connected to the first solder balls 34 .
- the size of the second molding compound 44 of the second package 4is the same as that of the first molding compound 35 of the first package 3 .
- only one molding machineis required to perform both the molding processes for the second package 4 and the first package 3 .
- the production costcan be reduced.
- the first molding compoundencapsulates the entire first surface 311 of the first substrate 31 , and accordingly the pads on the first surface 311 are not polluted.
- the semiconductor device 5comprises a first package 3 and a second package 4 .
- the second package 4is stacked on the first package 3 .
- the first package 3comprises a first substrate 31 , a first chip 32 , a plurality of first connecting elements (such as a plurality of first conductive wires 33 ), a plurality of first conductive bodies (such as a plurality of first solder balls 34 ), a first molding compound 35 , and a plurality of second solder balls 36 .
- the first substrate 31has a first surface 311 , a second surface 312 , a plurality of first pads 313 on the first surface 311 , and a plurality of second pads 314 on the second surface 312 .
- the first chip 32is attached to the first surface 311 of the first substrate 31 .
- the first conductive wires 33electrically connect the first chip 32 and the first substrate 31 .
- the first solder balls 34are in a hemispherical shape and disposed on the first pads 313 of the first surface 311 of the first substrate 31 .
- the molding compound 35encapsulates the first surface 311 of the first substrate 31 , the first chip 32 , the first conductive wires 33 , and the first solder balls 34 .
- the molding compound 35has a first height H 1 , a second height H 2 , a central portion 353 , a lower part 352 of a border portion, a first top surface 354 , and a second top surface 355 .
- the first height H 1is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33 .
- the second height H 2is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34 .
- the first height H 1is greater than the second height H 2 .
- the first top surface 354is corresponding to the first height H 1 , that is, the first top surface 354 is the top surface of the central portion 353 .
- the first top surface 354has a first surface roughness.
- the second top surface 355is corresponding to the second height H 2 , that is, the second top surface 355 is the top surface of the lower part 352 of the border portion.
- the second top surface 355has a second surface roughness. The first surface roughness is different from the second surface roughness.
- the second top surface 355is a cutting surface and has a plurality of cutting lines 37 after the cutting. Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37 . As shown in FIG. 7 , the cutting lines 37 located at each of the four sides of the second top surface 355 are parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
- the second package 4comprises a second substrate 41 , a second chip 42 , a plurality of second conductive wires 43 , a second molding compound 44 , and a plurality of third solder balls 45 .
- the second substrate 41has a first surface 411 and a second surface 412 .
- the second chip 42is attached to the first surface 411 of the second substrate 41 .
- the second conductive wires 43electrically connect the second chip 42 and the second substrate 41 .
- the second molding compound 44encapsulates the first surface 411 of the second substrate 41 , the second chip 42 , and the second conductive wires 43 .
- the third solder balls 45are disposed on the second surface 412 of the second substrate 41 and electrically connected to the first solder balls 34 .
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor package and a method of making the same, and particularly to a semiconductor package comprising a molding compound with different heights and a semiconductor device comprising the semiconductor package and methods of making the same.
- 2. Description of the Prior Art
- Please refer to
FIG. 1 showing a schematic diagram of a conventional semiconductor device consisting of stacked packages. The conventional semiconductor device1 comprises afirst package 10 and asecond package 20. Thefirst package 10 comprises a first substrate11, afirst chip 12, a plurality of firstconductive wires 13, afirst molding compound 14, and a plurality offirst solder balls 15. The first substrate11 has anupper surface 111, alower surface 112, and a plurality offirst pads 113. Thefirst pads 113 are disposed on theupper surface 111 of the first substrate11. Thefirst chip 12 is adhered to theupper surface 111 of the first substrate11 and electrically connected to theupper surface 111 of the first substrate11 by the firstconductive wires 13. Thefirst molding compound 14 encapsulates thefirst chip 12, the firstconductive wires 13, and a part of theupper surface 111 of the first substrate11, and thefirst pads 113 are exposed. Thefirst solder balls 15 are on thelower surface 112 of the first substrate11. - The
second package 20 is stacked on thefirst package 10. Thesecond package 20 comprises asecond substrate 21, asecond chip 22, a plurality of secondconductive wires 23, asecond molding compound 24, and a plurality ofsecond solder balls 25. Thesecond substrate 21 has anupper surface 211, alower surface 212, and a plurality ofsecond pads 213. Thesecond pads 213 are disposed on thelower surface 212 of thesecond substrate 21. Thesecond chip 22 is adhered to theupper surface 211 of thesecond substrate 21 and electrically connected to theupper surface 211 of thesecond substrate 21 by the secondconductive wires 23. Thesecond molding compound 24 encapsulates thesecond chip 22, the secondconductive wires 23, and theupper surface 211 of thesecond substrate 21. The upper ends of thesecond solder balls 25 are connected to thesecond pads 213 on thelower surface 212 of thesecond substrate 21, and the lower ends are connected to thefirst pads 113 on theupper surface 111 of the first substrate11. - One of the drawbacks of the conventional semiconductor device1 is that the area encapsulated by the
first molding compound 14 in thefirst package 10 is smaller than that encapsulated by thesecond molding compound 24 in thesecond package 20. As a result, two different molds are required in the molding processes for thefirst package 10 and thesecond package 20. The cost is high for making a mold. Molds of different sizes are often needed for molding processes to make different package devices. Accordingly, the production cost will be dramatically increased. Moreover, in thefirst package 10, there is an included angle of about 60 degrees between the sidewall of thefirst molding compound 14 and the first substrate11. The included angle is namely the draft angle of the mold. Furthermore, the top surface of thefirst molding compound 14 has a mold insert gate mark. In addition, in the molding process for thefirst package 10, thefirst molding compound 14 tends to overflow onto theupper surface 111 of the first substrate11 to pollute thefirst pads 113. - Therefore, it is necessary to provide a novel and progressive semiconductor package and semiconductor device and method of making the same to solve the aforesaid problems.
- One main objective of the present invention is to provide a method of making a semiconductor package comprising the following steps of: providing a first substrate having a first surface and a second surface; attaching a first chip to the first surface of the first substrate; forming a plurality of first connecting elements for electrically connecting the first chip and the first substrate; forming a plurality of first conductive bodies on the first surface of the first substrate; forming a first molding compound for encapsulating the first surface of the first substrate, the first chip, the first connecting elements, and the first conductive bodies; and removing a part of a border portion of the first molding compound, so that the first molding compound has at least two heights and one end of each of the first conductive bodies is exposed.
- Another objective of the present invention is to provide a semiconductor package, which comprises a substrate, a chip, a plurality of connecting elements, a plurality of first conductive bodies, and a molding compound. The substrate has a first surface and a second surface. The chip is attached to the first surface of the substrate. The connecting elements electrically connect the chip and the substrate. The first conductive bodies are disposed on the first surface of the substrate. The molding compound encapsulates the first surface of the substrate, the chip, the connecting elements, and the first conductive bodies. The molding compound has at least two heights and one end of each of the first conductive bodies is exposed. Thereby, the molding compound encapsulates the entire first surface of the substrate, and the pads on the first surface will not be polluted.
- Still another objective of the present invention is to provide a semiconductor device, which comprises a first package and a second package. The first package is the semiconductor package as described above. The second package is stacked on the first package. In an embodiment, the size of the second package is the same as that of the first package. Thus, only one mold is required to perform both the molding processes for the second package and the first package. Accordingly, the production cost will be reduced.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
FIG. 1 shows a schematic diagram of a conventional semiconductor device consisting of stacked packages;FIG. 2 shows a flow chart of the method of making a semiconductor device according to the present invention; andFIGS. 3 to 8 show schematic step by step diagrams illustrating the method of making a semiconductor device according to the present invention.- Please refer to
FIG. 2 showing a flow chart of the method of making a semiconductor device according to the present invention. Also refer toFIG. 3 . In Step S201, afirst substrate 31 is provided. Thefirst substrate 31 has afirst surface 311, asecond surface 312, a plurality offirst pads 313, and a plurality ofsecond pads 314. Thefirst pads 313 are on thefirst surface 311, and thesecond pads 314 are on thesecond surface 312. In Step S202, afirst chip 32 is attached to thefirst surface 311 of thefirst substrate 31. In this embodiment, afirst chip 32 is attached to thefirst surface 311 of thefirst substrate 31. In Step S203, a plurality of first connecting elements (such as a plurality of first conductive wires33) electrically connect thefirst chip 32 and thefirst surface 311 of thefirst substrate 31. In Step204, a plurality of first conductive bodies (such as a plurality of first solder balls34) are formed on thefirst pads 313 on thefirst surface 311 of thefirst substrate 31. In this embodiment, the first conductive bodies may be solder balls; however, it may be realized that the first conductive bodies can be solder bumps, gold stud bumps, or metal pins and each in a shape of pillar or column, in addition to a shape of ball. - It should be noted that, in other applications, after Step S201 is performed, Step S204 is performed and followed by Step S202 and Step S203. That is, the first conductive bodies (such as the first solder balls) may be formed on the
first pads 313 on thefirst surface 311 of thefirst substrate 31 before thefirst chip 32 is attached to thefirst surface 311 of thefirst substrate 31. Thereafter, the first conductive elements (such as the first conductive wires33) are formed for electrically connecting thefirst chip 32 and thefirst surface 311 of thefirst substrate 31. - Please refer to
FIG. 2 andFIG. 4 . In Step S205, afirst molding compound 35 for encapsulating thefirst surface 311 of thefirst substrate 31, thefirst chip 32, the firstconductive wires 33, and thefirst solder balls 34. It should be noted that thefirst molding compound 35 encapsulates the entirefirst surface 311 of thefirst substrate 31. In this embodiment, the top surface of thefirst molding compound 35 is higher than the top of thefirst solder balls 34; however, it may be realized that the top surface of thefirst molding compound 35 can be at the same height with the top of thefirst solder balls 34, or the top surface of thefirst molding compound 35 can be lower than the top of thefirst solder balls 34. - The included angle between the sidewall of the
first molding compound 35 and thefirst substrate 31 is about 85 to 95 degrees, and preferably 90 degrees, because the draft angle is almost not needed for the mold in the present invention. Furthermore, in the present invention, a plurality of thefirst chips 32 may be encapsulated with thefirst molding compound 35 and thereafter divided into a plurality of packages having a shape like tofu. Thereby, the top surface of thefirst molding compound 35 in the packages will not have a mold insert gate mark. - Please refer to
FIG. 2 andFIG. 5 . In Step S206, a plurality ofsecond solder balls 36 are formed on thesecond pads 314 on thesecond surface 312 of thefirst substrate 31. It should be noted that this step is an optional step. - Please refer to
FIG. 2 andFIG. 6 . In Step S207, a part of a border portion of thefirst molding compound 35 is removed, so that thefirst molding compound 35 has at least two heights and one end of each of thefirst solder balls 34 is exposed to make afirst package 3. The removal in this step may be accomplished by laser cutting, chemical etching, cutting with a cutting tool, or cutting with a water jet. In this step of this embodiment, the way of cutting with a cutting tool is used to remove theupper part 351 of the border portion of thefirst molding compound 35, and thelower part 352 of the border portion is remained. Thecentral portion 353 of thefirst molding compound 35 is not cut away and is entirely remained. - Therefore, after the cutting, the
molding compound 35 has a first height H1, a second height H2, acentral portion 353, alower part 352 of a border portion, a firsttop surface 354, and a secondtop surface 355. The first height H1is the height of thecentral portion 353 corresponding to the positions of thefirst chip 32 and the firstconductive wires 33. The second height H2is the height of thelower part 352 of the border portion corresponding to the positions of thefirst solder balls 34. The first height H1is greater than the second height H2. The firsttop surface 354 is corresponding to the first height H1, that is, the firsttop surface 354 is the top surface of thecentral portion 353. The firsttop surface 354 has a first surface roughness. The secondtop surface 355 is corresponding to the second height H2, that is, the secondtop surface 355 is the top surface of thelower part 352 of the border portion. The secondtop surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness. - Please refer to
FIG. 7 showing a top view ofFIG. 6 . The secondtop surface 355 is a cutting surface and has a plurality of cutting lines37 after the cutting. In the embodiment, the upper parts of thefirst solder balls 34 are removed along with the removal of theupper part 351 of the border portion of thefirst molding compound 35. Therefore, only the lower parts of thefirst solder balls 34 are remained to form a hemispherical shape (as shown inFIG. 6 ). Furthermore, all the part of themolding compound 35 and the parts of thefirst solder balls 34 included in the secondtop surface 355 have the cutting lines37. As shown inFIG. 7 , the cutting lines37 located at each of the four sides of the secondtop surface 355 are substantially parallel, and the cutting lines37 located in each of the four corners of the secondtop surface 355 perpendicularly cross each other, since the four corners of the secondtop surface 355 are cut twice. - Please still refer to
FIG. 6 showing a schematic diagram the first package of the present invention. Thefirst package 3 comprises afirst substrate 31, afirst chip 32, a plurality of first connecting elements (such as a plurality of first conductive wires33), a plurality of first conductive bodies (such as a plurality of first solder balls34), afirst molding compound 35, and a plurality ofsecond solder balls 36. Thefirst substrate 31 has afirst surface 311, asecond surface 312, a plurality offirst pads 313 on thefirst surface 311, and a plurality ofsecond pads 314 on thesecond surface 312. Thefirst chip 32 is attached to thefirst surface 311 of thefirst substrate 31. In this embodiment, thefirst chip 32 is attached to thefirst surface 311 of thefirst substrate 31. The firstconductive wires 33 electrically connect thefirst chip 32 and thefirst substrate 31. Thefirst solder balls 34 are in a hemispherical shape and disposed on thefirst pads 313 of thefirst surface 311 of thefirst substrate 31. Thesecond solder balls 36 are disposed on thesecond pads 314 of thesecond surface 312 of thefirst substrate 31. - The
molding compound 35 encapsulates thefirst surface 311 of thefirst substrate 31, thefirst chip 32, the firstconductive wires 33, and thefirst solder balls 34. Themolding compound 35 has a first height H1, a second height H2, acentral portion 353, alower part 352 of a border portion, a firsttop surface 354, and a secondtop surface 355. The first height H1is the height of thecentral portion 353 corresponding to the positions of thefirst chip 32 and the firstconductive wires 33. The second height H2is the height of thelower part 352 of the border portion corresponding to the positions of thefirst solder balls 34. The first height H1is greater than the second height H2. The firsttop surface 354 is corresponding to the first height H1, that is, the firsttop surface 354 is the top surface of thecentral portion 353. The firsttop surface 354 has a first surface roughness. The secondtop surface 355 is corresponding to the second height H2, that is, the secondtop surface 355 is the top surface of thelower part 352 of the border portion. The secondtop surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness. - Please refer to
FIG. 7 . In this embodiment, the secondtop surface 355 is a cutting surface and has a plurality of cutting lines37 after the cutting. Furthermore, all the part of themolding compound 35 and the parts of thefirst solder balls 34 included in the secondtop surface 355 have the cutting lines37. As shown inFIG. 7 , the cutting lines37 located at each of the four sides of the secondtop surface 355 are parallel, and the cutting lines37 located in each of the four corners of the secondtop surface 355 perpendicularly cross each other, since the four corners of the secondtop surface 355 are cut twice. - Please refer to
FIG. 2 andFIG. 8 . In Step S208, a second package4 is stacked on thefirst solder balls 34 and electrically connected to thefirst solder balls 34, to make asemiconductor device 5. The second package4 may be any kind of semiconductor packages. In this embodiment, the second package4 comprises asecond substrate 41, asecond chip 42, a plurality of secondconductive wires 43, asecond molding compound 44, and a plurality ofthird solder balls 45. Thesecond substrate 41 has afirst surface 411 and asecond surface 412. Thesecond chip 42 is attached to thefirst surface 411 of thesecond substrate 41. The secondconductive wires 43 electrically connect thesecond chip 42 and thesecond substrate 41. Thesecond molding compound 44 encapsulates thefirst surface 411 of thesecond substrate 41, thesecond chip 42, and the secondconductive wires 43. Thethird solder balls 45 are disposed on thesecond surface 412 of thesecond substrate 41 and electrically connected to thefirst solder balls 34. - In this embodiment, the size of the
second molding compound 44 of the second package4 is the same as that of thefirst molding compound 35 of thefirst package 3. Thus, only one molding machine is required to perform both the molding processes for the second package4 and thefirst package 3. As a result, the production cost can be reduced. In addition, in the molding process for thefirst package 3, the first molding compound encapsulates the entirefirst surface 311 of thefirst substrate 31, and accordingly the pads on thefirst surface 311 are not polluted. - Please still refer to
FIG. 8 , showing a schematic diagram of the semiconductor device according to the present invention. Thesemiconductor device 5 comprises afirst package 3 and a second package4. The second package4 is stacked on thefirst package 3. Thefirst package 3 comprises afirst substrate 31, afirst chip 32, a plurality of first connecting elements (such as a plurality of first conductive wires33), a plurality of first conductive bodies (such as a plurality of first solder balls34), afirst molding compound 35, and a plurality ofsecond solder balls 36. Thefirst substrate 31 has afirst surface 311, asecond surface 312, a plurality offirst pads 313 on thefirst surface 311, and a plurality ofsecond pads 314 on thesecond surface 312. Thefirst chip 32 is attached to thefirst surface 311 of thefirst substrate 31. The firstconductive wires 33 electrically connect thefirst chip 32 and thefirst substrate 31. Thefirst solder balls 34 are in a hemispherical shape and disposed on thefirst pads 313 of thefirst surface 311 of thefirst substrate 31. - The
molding compound 35 encapsulates thefirst surface 311 of thefirst substrate 31, thefirst chip 32, the firstconductive wires 33, and thefirst solder balls 34. Themolding compound 35 has a first height H1, a second height H2, acentral portion 353, alower part 352 of a border portion, a firsttop surface 354, and a secondtop surface 355. The first height H1is the height of thecentral portion 353 corresponding to the positions of thefirst chip 32 and the firstconductive wires 33. The second height H2is the height of thelower part 352 of the border portion corresponding to the positions of thefirst solder balls 34. The first height H1is greater than the second height H2. The firsttop surface 354 is corresponding to the first height H1, that is, the firsttop surface 354 is the top surface of thecentral portion 353. The firsttop surface 354 has a first surface roughness. The secondtop surface 355 is corresponding to the second height H2, that is, the secondtop surface 355 is the top surface of thelower part 352 of the border portion. The secondtop surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness. - Please also refer to
FIG. 7 . In this embodiment, the secondtop surface 355 is a cutting surface and has a plurality of cutting lines37 after the cutting. Furthermore, all the part of themolding compound 35 and the parts of thefirst solder balls 34 included in the secondtop surface 355 have the cutting lines37. As shown inFIG. 7 , the cutting lines37 located at each of the four sides of the secondtop surface 355 are parallel, and the cutting lines37 located in each of the four corners of the secondtop surface 355 perpendicularly cross each other, since the four corners of the secondtop surface 355 are cut twice. - The second package4 comprises a
second substrate 41, asecond chip 42, a plurality of secondconductive wires 43, asecond molding compound 44, and a plurality ofthird solder balls 45. Thesecond substrate 41 has afirst surface 411 and asecond surface 412. Thesecond chip 42 is attached to thefirst surface 411 of thesecond substrate 41. The secondconductive wires 43 electrically connect thesecond chip 42 and thesecond substrate 41. Thesecond molding compound 44 encapsulates thefirst surface 411 of thesecond substrate 41, thesecond chip 42, and the secondconductive wires 43. Thethird solder balls 45 are disposed on thesecond surface 412 of thesecond substrate 41 and electrically connected to thefirst solder balls 34. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Claims (19)
1. A semiconductor package, comprising:
a substrate having a first surface and a second surface;
a chip attaching to the first surface of the substrate;
a plurality of connecting elements electrically connecting the chip and the substrate;
a plurality of first conductive bodies disposed on the first surface of the substrate; and
a molding compound for encapsulating the first surface of the substrate, the chip, the connecting elements, and the first conductive bodies, wherein the molding compound has at least two heights and one end of each of the first conductive bodies is exposed.
2. The semiconductor package ofclaim 1 , wherein the first conductive bodies comprise a plurality of first solder balls.
3. The semiconductor package ofclaim 2 , wherein each of the first solder balls is in a hemispherical shape.
4. The semiconductor package ofclaim 1 , wherein, the molding compound has a first height and a second height, the first height is in a position corresponding to the chip and the conductive elements, the second height is in a position corresponding to the first conductive bodies, and the first height is greater than the second height.
5. The semiconductor package ofclaim 4 , wherein the molding compound has a first top surface and a second top surface, the first top surface is corresponding to the first height, the second top surface is corresponding to the second height, and the second top surface is a cutting surface having a plurality of cutting lines.
6. The semiconductor package ofclaim 5 , wherein, the first top surface has a first surface roughness, the second top surface has a second surface roughness, and the first surface roughness is different from the second surface roughness.
7. The semiconductor package ofclaim 5 , wherein, the cutting lines located at each of the four sides of the second top surface are parallel, and the cutting lines located in each of the four corners of the second top surface perpendicularly cross each other.
8. The semiconductor package ofclaim 1 , further comprising a plurality of second solder balls on the second surface of the substrate.
9. The semiconductor package ofclaim 1 , wherein the included angle between the sidewall of the molding compound and the substrate is 90 degrees.
10. A semiconductor device, comprising:
a first package comprising:
a first substrate having a first surface and a second surface;
a first chip attaching to the first surface of the first substrate;
a plurality of first connecting elements electrically connecting the first chip and the first substrate;
a plurality of first conductive bodies disposed on the first surface of the first substrate; and
a first molding compound for encapsulating the first surface of the first substrate, the first chip, the first connecting elements, and the first conductive bodies, wherein the first molding compound has at least two heights and one end of each of the first conductive bodies is exposed; and
a second package stacked on the first package and electrically connected to the first conductive bodies.
11. The semiconductor device ofclaim 10 , wherein the first conductive bodies comprise a plurality of first solder balls.
12. The semiconductor device ofclaim 11 , wherein each of the first solder balls is in a hemispherical shape.
13. The semiconductor device ofclaim 10 , wherein, the first molding compound has a first height and a second height, the first height is in a position corresponding to the chip and the conductive elements, the second height is in a position corresponding to the first conductive bodies, and the first height is greater than the second height.
14. The semiconductor device ofclaim 13 , wherein, the first molding compound has a first top surface and a second top surface, the first top surface is corresponding to the first height, the second top surface is corresponding to the second height, and the second top surface is a cutting surface having a plurality of cutting lines.
15. The semiconductor device ofclaim 14 , wherein, the first top surface has a first surface roughness, the second top surface has a second surface roughness, and the first surface roughness is different from the second surface roughness.
16. The semiconductor device ofclaim 14 , wherein, the cutting lines located at each of the four sides of the second top surface are parallel, and the cutting lines located in each of the four corners of the second top surface perpendicularly cross each other.
17. The semiconductor device ofclaim 10 , further comprising a plurality of second solder balls disposed on the second surface of the second substrate.
18. The semiconductor device ofclaim 10 , wherein the second package comprises:
a second substrate having a first surface and a second surface;
a second chip attaching to the first surface of the second substrate;
a plurality of second conductive wires electrically connecting the second chip and the second substrate;
a second molding compound for encapsulating the first surface of the second substrate, the second chip, and the second conductive wires; and
a plurality of third solder balls disposed on the second surface of the second substrate and electrically connected to the first conductive bodies.
19. The semiconductor device ofclaim 10 , wherein the included angle between the sidewall of the first molding compound and the first substrate is 90 degrees.
Priority Applications (1)
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|---|---|---|---|
| US14/266,433US20140312496A1 (en) | 2006-09-27 | 2014-04-30 | Semiconductor package and semiconductor device |
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| TW095135866 | 2006-09-27 | ||
| TW095135866ATWI336502B (en) | 2006-09-27 | 2006-09-27 | Semiconductor package and semiconductor device and the method of making the same |
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| US20080073769A1true US20080073769A1 (en) | 2008-03-27 |
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| US11/828,352Active2027-08-02US7642133B2 (en) | 2006-09-27 | 2007-07-26 | Method of making a semiconductor package and method of making a semiconductor device |
| US14/266,433AbandonedUS20140312496A1 (en) | 2006-09-27 | 2014-04-30 | Semiconductor package and semiconductor device |
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| US14/266,433AbandonedUS20140312496A1 (en) | 2006-09-27 | 2014-04-30 | Semiconductor package and semiconductor device |
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| TW (1) | TWI336502B (en) |
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| US20080230887A1 (en)* | 2007-03-23 | 2008-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and the method of making the same |
| US20080258289A1 (en)* | 2007-04-23 | 2008-10-23 | Pendse Rajendra D | Integrated circuit package system for package stacking |
| US20090174081A1 (en)* | 2008-01-09 | 2009-07-09 | Ibiden Co., Ltd. | Combination substrate |
| US20100000775A1 (en)* | 2008-07-03 | 2010-01-07 | Advanced Semiconductor Engineering, Inc. | Circuit substrate and method of fabricating the same and chip package structure |
| US20100038781A1 (en)* | 2008-08-14 | 2010-02-18 | Dongsam Park | Integrated circuit packaging system having a cavity |
| US20100171206A1 (en)* | 2009-01-07 | 2010-07-08 | Chi-Chih Chu | Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20080076208A1 (en) | 2008-03-27 |
| US20140312496A1 (en) | 2014-10-23 |
| TWI336502B (en) | 2011-01-21 |
| US7642133B2 (en) | 2010-01-05 |
| TW200816330A (en) | 2008-04-01 |
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