US20080072129A1 - Communications digital signal processor and digital signal processing method - Google Patents

Abstract

A digital signal processor includes an instruction executer configured to execute instructions. The instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The instruction executer outputs a processed data including the first minimum data and the second minimum data. A bit length of the first minimum data is equal to n bits in length. A bit length of the second minimum data is equal to n bits in length. A bit length of the processed data is equal to at least 2n bits in length.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of pending U.S. patent application Ser. No. 11/022,811, filed Dec. 28, 2004, which is a continuation of U.S. patent application Ser. No. 10/748,242, filed Dec. 31, 2003, which is a divisional of U.S. patent application Ser. No. 10/252,394, filed Sep. 24, 2002, now U.S. Pat. No. 6,735,714, which is a continuation of U.S. patent application Ser. No. 09/974,807, filed Oct. 12, 2001, now U.S. Pat. No. 6,477,661, which is a divisional of U.S. patent application Ser. No. 09/147,663, filed Feb. 9, 1999, now U.S. Pat. No. 6,330,684, which is the National Stage of International Application No. PCT/JP98/02909, filed Jun. 29, 1998, the disclosures of which are expressly incorporated herein by reference in their entireties.
TECHNICAL FIELD
• The present invention relates to a processing unit, which is incorporated into a mobile communication apparatus, for performing an ASC (Addition, Comparison, and Selection) operation of particularly a Viterbi decoding.
BACKGROUND ART
• In data communications in a mobile radio communication network, since a bit error frequently occurs, an execution of an error correction processing is needed. In the error correction methods, there is a method in which a convolutional code generated from an input bit is decoded by Viterbi decoding on a receiver side. In the error correction processing, a digital signal processor (hereinafter referred to as “DSP”) is used.
• The Viterbi decoding repeats the simple processing such as addition, comparison, and selection and performs a trace-back operation for finally data, thereby realizing a maximum likelihood decoding of the convolutional code.
• The following will briefly explain the Viterbi decoding processing. The convolutional code is generated bymode2 addition of input bits and a fixed number of bits precedent thereto. Then, a plurality of coding data is generated to correspond to one bit of the input bits. A number of input information bits having influence upon the coding data is called constraint length (K). The number of input information bits is equal to a number of stages of shift registers used inmode2 addition.
• The coding data is determined by the input bits and a state of the preceding (K−1) input bits. When a new information bit is input, the state of the input bits transits to a new state. The state in which coding data transits is determined by whether the new input bit is “0” or “1.” Since the respective (K−1) bits are “1” or “0” a number of states in which coding data transits becomes 2^[K−1].
• In the Viterbi decoding, received coding data sequence is observed, and the most-likely state is estimated from all obtainable state transitions. For this reason, every time when coding data (received data sequence) corresponding to one bit of information bits, an inter-signal distance (metric) of the respective paths to each state at that point is computed. Then, operations for leaving a path having a smaller metric among the paths reaching the same state as a survivor are sequentially repeated.
• As shown in a state transition diagram ofFIG. 1, in a convolutional encoder having a constraint length K, two paths each showing a state transition from each of state S[n] and S[n+2^[K−2] at one previous point extend to a state S[2n] (n=positive integer) at a certain point. For example, in a case of K=3, a transition from each of S[1] (state S0) and S[3] (state S11) to S[2] (state S10) (state in which preceding two bits are input in order of “1” and “0”) at the time of n=1 is possible. Also, at the time of n=2, a transition from each of S[2] (state S10) and S[4] (state S00) to S[4] (state S00) (state shown by low-order two bits) is possible.
• A path metric “a” is a sum of an inter-signal distance (branch metric) “x” between an output symbol of the path inputting to the state S[2n] and the received data sequence and a path metric “A.” The path metric “A” is the total sum of branch metrics of the survivor paths up to the state S[n] at one previous state. Similarly, a path metric “b” is a sum of an inter-signal distance (branch metric) “y” between an output symbol of the path inputting to the state S[2n] and the received data sequence and a path metric “B.” The path metric “B” is the total sum of branch metrics of the survivor paths up to the state S[n+2^(K−2)] at one previous point. In the Viterbi decoding, the path metrics “a” and “b” inputting to the state S[2n] are compared with each other, and the smaller path is selected as a survivor path.
• In the Viterbi decoding, each processing of addition for obtaining the path metric, comparison between the path metrics and the selection of path is executed with respect to 2^(K−2)states at each point Moreover, in the selection of path, a history showing which path has been selected is left as a path select signal PS[i], [I=0 to 2^(K−2)−1].
• At this time, if a subscript (e.g., n) of one previous state of the selected path is smaller than a subscript (n+2^(K−2)) of one previous state of the non-selected other path, PS[i]=0 is established. If the subscript (n) it is larger than the subscript (n+2^(K−2)), PS[i]=1 is established.
• In the case ofFIG. 1, since n<(n+2^(K−2)) is established, the state S[n+2^(K−2)] is selected at the time of a>b and PS[S2n]=1 is established, and the state S[n] is selected at the time of a≦b and PS[S2n]=0 is established.
• Then, in the Viterbi decoding, data is decoded while being traced back to the path finally survived based on the path select signal.
• The following will explain the conventional processing unit for Viterbi decoding, TMS320C54x, which is a general processing unit, (manufactured by TEXAS INSTRUMENTS, hereinafter referred to as ‘C54x’) being given as one example. In a GSM cellular radio system, equation (1) set forth below is used as a convolutional code.
  G1(D)=1+D3+D4
  G2(D)=1+D+D3+D4   (1)
• The above convolutional code is expressed by a trellis diagram of a butterfly structure shown inFIG. 2. The trellis diagram shows a state in which the convolutional code transits from a certain state to another state. Let us assume that constraint length K is 5. States of 2^(K−2)=16 or 8 butterfly structures are present for each symbol section. Then, two branches are input in each state, and a new path metric is determined by the ACS operations.
• The branch metric can be defined as the following equation (2).
  M=SD(2*i)*B(J,0)+SD(2*i+1)*B(j,1)   (2)
  where SD(2*i) denotes a first symbol of a symbol metric showing a soft decision input, and SD(2*i+1) denotes a second symbol of the symbol metric. B(J,0) and B(j,1) conform to codes generated by a convolutional encoder as shown inFIG. 3.
• In C54x, an arithmetic logic section (hereinafter referred to as “ALU”) is set to a dual 16-bit mode, thereby processing the butterfly structure at high speed. The determination of a new path metric (j) can be obtained by calculating two path metrics (2=J and 2*J+1) and the branch metrics −(M and −M) in parallel based on a DSADT instruction and executing a comparison based on a CMPS instruction. The determination of a new path metric (j+8) can be obtained by calculating two path metrics and the branch metrics (M and −M) in parallel based on the DSADT-instruction. The calculation results are stored in high and low order bits of a double-precision accumulator, respectively.
• The CMPS instruction compares the high and low order bits of the accumulator and stores a larger value in a memory. Also, every time when the comparison is executed, which value is selected is written in a 16-bit transition register (TRN). The content written to the TRN is stored in the memory every time when each symbol processing is ended. Information to be stored in the memory is used to search a suitable path in the trace-back processing.FIG. 4 shows a macro program for a butterfly operation of the Viterbi decoding.
• The values of the branch metrics are stored in the T register before the macro is called.FIG. 5 shows an example of a memory mapping of the path metrics.
• 8 butterfly operations are executed in one symbol section and 16 new states are obtained. This series of processing is repeatedly computed over several sections. After the end of the processing, the trace-back is executed so as to search a suitable path from 16 paths. Thereby, a decoding bit sequence can be obtained.
• The mechanism of the ACS operations of the C54x, which is the general DSP, can be thus explained. Then, in C54x, and the updates of two path metrics are realized with 4 machine cycles from the example of the macro program ofFIG. 4.
• In the future, there is expected an increase in demand for non-voice communications requiring high quality transmission with a lower bit error rate than voice communications. As means for achieving the low bit error rate, there is means for increasing the constraint length K of the Viterbi decoding.
• However, if the constraint length is increased by a value corresponding to one bit, a number of path metrics (number of states) doubles. For this reason, a number of operations in the Viterbi decoding using DSP double. Generally, an amount of information in non-voice communications is larger than the amount of information in voice communications. If the amount of information increases, the number of operations in the Viterbi decoding including the ACS operation also increases. An increase in number of operations using DSP makes it difficult to maintain a battery for a portable terminal for a long period of time.
• For the purpose of downsizing the portable terminal, reducing the weight, and lowering the cost, an area processed by a special LSI has been also designed to be implemented in one chip form using a DSP processing in recent years.
• However, an increase in the number of operations using DSP exceeds the processing capability of the existing DSP, thereby making it impossible to be implemented in one chip form using DSP.
• Moreover, if the function of DSP is highly enhanced to increase the number of operations, an increase in the cost of DSP itself is brought about. As a result, the reduction in the cost of the portable terminal cannot be realized.
DISCLOSURE OF INVENTION
• A first object of the present invention is to provide a processing unit for efficiently processing an ACS operation of the Viterbi decoding by use of DSP with a small investment in software.
• The above object can be attained by arranging two pairs of comparing sections, an adding section, and a storing section for storing a comparison result in the processing unit and by executing the ACS operation in parallel.
BRIEF DESCRIPTION OF DRAWINGS
• FIG. 1 is a trellis diagram-showing a path of a state transition of a convolutional encoder in Viterbi decoding;
• FIG. 2 is a schematic diagram showing a butterfly structure of the trellis diagram;
• FIG. 3 is a schematic view showing an example of codes generated by the convolutional encoder;
• FIG. 4 is a program view showing an example of a Viterbi operation for channel coding;
• FIG. 5 is a schematic view showing a pointer control and an example of path metric storage;
• FIG. 6 is a block diagram showing the structure of the processing unit of the first embodiment of the present invention;
• FIG. 7 is a block diagram showing an example of the convolutional encoder having a code rate ½;
• FIG. 8 is a schematic view showing the butterfly structure where a constraint length K=4;
• FIG. 9 is a block diagram showing the structure of the processing unit of the second embodiment of the present invention;
• FIG. 10 is a timing view explaining a pipe line operation of the processing unit of the second embodiment of the present invention;
• FIG. 11 is a schematic view showing an example of a memory access operation of RAM of the second embodiment of the present invention;
• FIG. 12 is a block diagram showing the structure of the processing unit of the third embodiment of the present invention;
• FIG. 13 is a schematic view showing an example of a memory access operation of a dual port RAM of the third embodiment of the present invention;
• FIG. 14 is a block diagram showing the structure of the processing unit of the fourth embodiment of the present invention;
• FIG. 15 is a timing view explaining a pipe line operation of the processing unit of the fourth embodiment of the present invention;
• FIG. 16 is a block dram showing the structure of the processing unit of the fifth embodiment of the present invention;
• FIG. 17 is a view showing ACS operation results of the processing unit of the sixth embodiment of the present invention;
• FIG. 18 is a block diagram showing the structure of the processing unit of the sixth embodiment of the present invention;
• FIG. 19 is a block diagram showing the structure of the processing unit of the seventh embodiment of the present invention;
• FIG. 20 is a block diagram showing the structure of the processing unit of the eighth embodiment of the present invention;
• FIG. 21 is an input/output view of a 4:2 compressor of the eighth embodiment of the present invention;
• FIG. 22 is a block diagram showing the structure of the processing unit of the ninth embodiment of the present invention;
• FIG. 23 is a view showing a carry control of a double-precision AU;
• FIG. 24 is a block diagram showing the structure of the processing unit of the tenth embodiment of the present invention;
• FIG. 25 is a block diagram showing the structure of the processing unit of the eleventh embodiment of the present invention;
• FIG. 26 is block diagram showing the structure of a mobile station apparatus of the twelfth embodiment of the present invention;
• FIG. 27 is a block diagram showing the structure of the mobile station apparatus of the thirteenth embodiment of the present invention;
• FIG. 28 a block diagram showing the structure of a base station apparatus of the fourteenth embodiment of the present invention; and
• FIG. 29 a block diagram showing the structure of the base station apparatus of the fifteenth embodiment of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
• Embodiments of the present invention will now be described with reference to the accompanying drawings.
First Embodiment
• FIG. 6 is a block diagram showing the structure of the processing unit of the first embodiment of the present invention. InFIG. 6, a pathmetric storing section1 stores path metrics, and a data supply and a transfer of an operation result are executed via abus2. A branchmetric storing section3 stores branch metrics and a data supply is executed via abus4.
• Comparingsections5 and9 compare data input from the pathmetric storing section1 and the branchmetric storing section3 via thebuses2 and4, respectively.
• Addingsections6 and10 add data read from the pathmetric storing section1 and the branchmetric storing section3 via thebuses2 and4, respectively.
• A comparisonresult storing section7 stores a comparison result of the comparingsection5, and a comparisonresult storing section11 stores a comparison result of the comparingsection9. Then, the comparisonresult storing sections7 and11 transfer the comparison results in the pathmetric storing section1 via thebus2.
• A selectingsection8 inputs an adding result of the addingsection6 and determines an output based on the comparison result of the comparingsection5. A selectingsection12 inputs an adding result of the addingsection10 and determines an output based on the comparison result of the comparingsection9. Then, the selectingsections8 and12 transfer the outputs determined based on the comparison results to the pathmetric storing section1 via abus13.
• Next, the following will explain ACS operation of the processing unit of the first embodiment with reference to the drawings. In the explanation set forth below, it is assumed that data to be decoded is ones that are coded by a convolutional encoder ofFIG. 7 where a constraint length K=4 and a code rate ½. Also, data type of the path metrics and that of the branch metrics are single-precision data. Then, when double-precision data is set to (X, Y) for the sake of convenience, a high order position of the double-precision data is set to X and a low order position thereof is set to Y.
• Four branch metrics are set to BM0, BM1, BM2, BM3, respectively. If a state transition is illustrated using these branch metrics, the butterfly structure is shown as inFIG. 8.
• Here, attention should be paid to nodes N0 and N1 of an old state. The transition destinations of the nodes N0 and N1 are nodes N′0 and N′4, respectively.
• Then, a branch metric, which is obtained at the time of the transition from the node N0 to the node N′0, is BM0, and a branch metric, which is obtained at the time of the transition from the node N1 to the node N′0, is BM1. Also, a branch metric, which is obtained at the time of the transition from the node N0 to the node N′4, is BM1, and a branch metric, which is obtained at the time of the transition from the node N1 to the node N′4, is BM0.
• Thus, the path metric PM0 of the node N0 and the path metric PM1 of the node N1 are replaced with branch metrics BM0 and BM1, respectively, and these metrics are added. Thereby, path metric PM′0 of the node N′0 and path metric PM′4 of the node N′4 are obtained.
• Then, this relationship can be applied to the other pairs of nodes (a pair of nodes N2 and N3, a pair of nodes N4 and N5, a pair of nodes N6 and N7).
• The inventor of the present invention paid attention to this relationship, and found out that two path metrics could be updated simultaneously by processing the ACS operation in parallel and that processing time could be reduced. This led to the present invention.
• The ACS operation of the node N′0 to N′3 in the first half is executed by the comparingsection5, the addingsection6, the comparisonresult storing section7, and the selectingsection8. In parallel with this operation, the ACS operation of the node N′4 to N′8 in the second half is executed by the comparingsection9, the addingsection10, the comparisonresult storing section11, and the selectingsection12. The following will specifically explain the ACS operation from nodes N0 and N1 to nodes N′0 and N′4.
• First, two path metrics (PM1, PM0) are output to thebus2 from the pathmetric storing section1. On the other hand, two branch metrics (BM1, BM0) are output to thebus4 from the branchmetric storing section3.
• The comparingsection5 inputs two path metrics (PM1, PM0) from thebus2 and two branch metrics (BM1, BM0) from thebus4 so as to calculate PM1+BM1−PM0−BM0.
• The addingsection6 inputs two path metrics (PM1, PM0) from thebus2 and two branch metrics (BM1, BM0) from thebus4 so as to calculate PM1+BM1 and PM0+BM0. Then, the calculation results (as PM1+BM1, PM0+BM0) are output to the selectingsection8.
• The selectingsection8 inputs the most significant bit (hereinafter referred to as “MSB”) which is the code bit of the comparison result of the comparingsection5, PM1+BM1−PM0−BM0. Then, the selectingsection8 selects as to whether the high order PM1+BM1 is output to thebus13 or the low order PM0+BM0 is output thereto from the value of the MSB.
• In other words, if the equation (3) shown below is established, the MSB is 0 and the selectingsection8 outputs the low order PM0+BM0 to thebus13 as PM′0. Conversely, if the equation (3) is not established, the MSB is 1 and the selectingsection8 outputs the high order PM1+BM1 thereto as PM′0.
  PM1+BM1≧PM0+BM0   (3)
• Also, the MSB, which is the comparison result of the comparingsection5, is stored in the comparisonresult storage section7 at the same time.
• The comparingsection9 inputs two path metrics (PM1, PM0) from thebus2 and two branch metrics (BM1, BM0) from thebus4 so as to calculate PM1+BM0−PM0−BM1.
• The addingsection10 inputs two path metrics (PM1, PM0) from thebus2 and two branch metrics (BM1, BM0) from thebus4 so as to calculate PM1+BM0 and PM0+BM1. Then, the calculation results (as PM1+BM0, PM0+BM1) are output to the selectingsection12.
• The selectingsection12 inputs the MSB of the comparison result of the comparingsection9, PM1+BM1−PM0−BM1. Then, the selectingsection12 selects as to whether the high order PM1+BM0 is output to thebus13 or the low order PM0+BM1 is output thereto from the value of the MSB.
• In other words, if the equation (4) shown below is established, the MSB is 0 and the selectingsection12 outputs the low order PM0+BM1 to thebus13 as PM′4. Conversely, if the equation (4) is not established, the MSB is 1 and the selectingsection12 outputs the high order DM1+BM0 thereto as PM′4.
  PM1+BM0≧PM0+BM1   (4)
• Also, the MSB, which is the comparison result of the comparingsection9, is stored in the comparisonresult storage section11 at the same time.
• The above processing is subjected to the other node pairs in the same way. As a result, the ACS operation of the Viterbi coding using DSP can be executed in parallel and the operation processing can be performed with relatively a small amount of processing at high speed.
• The above embodiment explained the case of the constraint length K=4 and the code rate ½. However, even if the constraint length and the code rate are the other values, the above relationship is established. Therefore, the change corresponding thereto is suitably provided, so that the same advantage can be obtained.
Second Embodiment
• FIG. 9 is a block diagram showing the structure of the processing unit of the second embodiment of the present invention. In the processing unit ofFIG. 9, the same reference numerals are added to the portions common to the processing unit ofFIG. 6 and the explanation is omitted.
• In the processing unit ofFIG. 9, the storing section for storing the path metrics is formed by aRAM14 having four banks.
• The processing unit ofFIG. 9 is suitable for the operation processing of a pipeline structure shown inFIG. 10.
• For example, for executing the ACS operation at an operation execution stage of n-th+1 cycle in aninstruction1, it is required that addresses of the path metrics to be read at a memory access stage of n-th cycle should be supplied to theRAM14 in advance.
• It is assumed that theRAM14 is a double-precision readable RAM that can read an even address and an odd address continuously. Then, if the following conditions (a) and (b) are satisfied, two path metrics used in the operation can be read by only designating the even address.
• (a) The path metrics of one state are stored at continuous addresses in order of the even address and the odd address.
• (b) The path metrics of one state are divided into the first and second halves, and each is stored in a different bank.
• For example, the path metrics (PM0, PM1, PM2, PM3 inFIG. 8) of the first half of the old state are stored in thebank0 of theRAM14. Then, the path metrics (PM4, PM5, PM6, PM7 inFIG. 8) of the second half of the old state are stored in thebank1. In this case, two path metrics are generated by executing the ACS operation at one cycle, and these metrics are stored inbanks2 and3 via thebus13, respectively. At this time, double-precision data is transferred from thebus13, the path metric of the node N′3 is stored in thebank2 from the node N′0, and the path metric of the node N′7 is stored in thebank3 from the node N′.
• FIG. 11 is a schematic view showing an example of a memory access operation of theRAM14 corresponding toFIG. 8.
• When the ACS operation of one state is ended, in a next state, the path metrics of the old state are read from thebanks2 and3 and the path metrics of a new state are stored in thebanks0 and1.
• Thus, every time when the ACS operation of one state is ended, the pair of banks for reading the path metrics and the pair of banks for storing the path metrics are switched usingRAM14 having four banks as the storing section for storing the path metrics. Thereby, the ACS operation of the Viterbi decoding using DSP can be executed in parallel.
• In the above explanation, thebanks0 and1 and thebanks2 and3 were paired, respectively. However, even if the other combinations are used, the similar operation can be executed by only changing the address to be used in supplying the metrics at the memory access stage and the address to be used in storing the metrics. Moreover, in the second embodiment, theRAM14 was formed by four banks. However, the similar operation can be executed if the number of banks is more than four.
Third Embodiment
• FIG. 12 is a block diagram showing the structure of the processing unit of the third embodiment of the present invention. In the processing unit ofFIG. 12, the same reference numerals are added to the portions common to the processing unit ofFIG. 6 and the explanation is omitted.
• In the processing unit ofFIG. 12, thestoring section3 for storing the path metrics is formed by adual RAM15 having three banks.
• The processing unit ofFIG. 12 is suitable for the operation processing of the pipe line structure shown inFIG. 10.
• Since the storing section for storing the path metrics is thedual port RAM15 in the processing unit ofFIG. 12, designation of reading and writing to the same bank can be executed with one instruction. For example, for executing the ACS operation at an operation execution stage of n-th+1 cycle in aninstruction1, an address for reading the path metric at a memory access stage of n-th cycle and an address for writing the path metric are supplied to thedual port RAM15. Thereby, at the n-th+1 cycle, an even address and an odd address can be continuously read from thedual port RAM15 so as to execute the ACS operation. Moreover, one path metric can be written to the same bank.
• In the processing unit of the third embodiment, if the following conditions (a) and (b) are satisfied, two path metrics used in the operation can be read by only designating the even address.
• (a) The path metrics of one state are stored at continuous addresses in order of the even address and the odd address.
• (b) The path metrics of one state are divided into the first and second halves, and each is stored in a different bank.
• For example, the path metrics (PM0, PM1, PM2, PM3 inFIG. 8) of the first half of the old state are stored in thebank0 of thedual port RAM15, and the path metrics (PM4, PM5, PM6, PM7 inFIG. 8) of the second half of the old state are stored in thebank1. In this case, two path metrics are generated by executing the ACS operation at one cycle, and these metrics are stored inbanks0 and2 via thebus13, respectively. At this time, thebus13 transfers double-precision data, the path metric of the node N′3 is stored in thebank0 from the node N′0, and the path metric of the node N′7 is stored in thebank2 from the node N′4.
• FIG. 13 is a schematic view showing an example of a memory access operation of theRAM15 corresponding toFIG. 8.
• In the processing unit ofFIG. 12, when the ACS operation of one state is ended, only thebanks1 and2 are switched. Then, the ACS operation of the Viterbi decoding using DSP can be executed in parallel without switching thebank0.
• In the third embodiment, thedual port RAM15 was formed by three banks. However, the similar operation can be executed if the number of banks is more than three.
Fourth Embodiment
• FIG. 14 is a block diagram showing the structure of the processing unit of the fourth embodiment of the present invention. In the processing unit ofFIG. 14, the same reference numerals are added to the portions common to the processing unit ofFIG. 6 and the explanation is omitted.
• The processing unit ofFIG. 14 comprises input registers16 and17 for inputting data from thebus2 and for outputting data to the comparingsections5,9, and the addingsections6,10.
• The processing unit ofFIG. 14 is suitable for the operation processing of the pipe line structure shown inFIG. 15.
• For example, for executing the ACS operation at an operation execution stage of n-th+2 cycle in aninstruction1, an address for reading the path metric at an memory access stage of n-th cycle is supplied to theRAM14 in advance. Then, data output from theRAM14 is latched to the input registers16 and17 via thebus2 at a data transfer stage of n-th+1.
• The pipe shown inFIG. 15 is structured so that one data transfer stage is inserted between a memory access stage and an operation execution stage of the pipe line shown inFIG. 10. In other words, data output from theRAM14 is determined at the input registers placed at the front of the respective operation devices (comparingsections5,9, and addingsections6,10) at a starting point of the operation execution stage. As a result, time required for data transfer from theRAM14 can be omitted.
• Therefore, according to this embodiment, the ACS operation of the Viterbi decoding using DSP can be executed in parallel at relatively high speed. Note that the similar operation can be executed if the dual port RAM is used as the storing section for storing the path metrics.
Fifth Embodiment
• FIG. 16 is a block diagram showing the structure of the processing unit of the fifth embodiment of the present invention. In the processing unit ofFIG. 16, the same reference numerals are added to the portions common to the processing unit ofFIG. 14 and the explanation is omitted.
• In the processing unit ofFIG. 16, aswap circuit18 is added as compared with the processing unit ofFIG. 14. Theswap circuit18 directly outputs data input from the branchmetric storing section3 or swaps the high order position and the low order position so as to be output.
• The processing unit ofFIG. 16 is suitable for the operation processing of the pipe line structure shown inFIG. 15.
• For example, let us assumed that data is input as double-precision data in a form of {BM1, BM0} from the branchmetric storage3. In this case, theswap circuit18 has a function of switching whether values of two branch metrics are directly output as {BM1, BM0} or the high order position and the low order position are swapped so as to be output as {BM0, BM1} by an instruction.
• The following will explain an operation of theswap circuit18 using the convolutional encoder ofFIG. 7 and the path metric transition state of the butterfly structure ofFIG. 8 where the constraint length K=4 and the code rate is ½.
• As shown inFIG. 17, the ACS operation, which is executed at the time of the transition from the nodes N0 and N1 of the old state to the nodes N′0 and N′4, and the ACS operation, which are executed at the time of the transition from the nodes N6 and N7 of the old state to the nodes N′3 and N′7, are compared with each other. As a result, in both ACS operations, common branch metrics BM0 and BM1 are used and the relationship in which BM0 and BM1 are swapped is established.
• The ACS operation, which is executed at the time of the transition from the nodes N0 and N1 to the node N′0, and the ACS operation, which is executed at the time of the transition from the nodes N6 and N7 to the node N′3 are performed by the comparingsection5 and the addingsection6. On the other hand, the ACS operation, which is executed at the time of the transition from the nodes N3 and N1 to the node N′4, and the ACS operation, which is executed at the time of the transition from the nodes N6 and N7 to the node N′7, are performed by the comparingsection9 and the addingsection10.
• For this reason, if the branch metrics are stored in the branchmetric storing section3 in both forms of {BM0, BM1} and {BM1, BM0}, the branchmetric storing section3 results in a redundant hardware source.
• Theswap circuit18 is used to solve such redundancy. For example, the branch metrics are stored in the branchmetric storing section3 in only the form of {BM0, BM1}. Then, the metrics in the form of {BM0, MB1} are input to theswap circuit18. Theswap circuit18 swaps the metrics in the form of {BM0, BM1} or the metrics in the form of {BM1, BM0} so as to be output by an instruction. Thereby, redundancy of the branchmetric storing section3 can be omitted.
• The above embodiment was explained using the nodes N0, N1, N6, N7 of the old state where the constraint length K=4 and the code rate was ½. However, the aforementioned relationship can be established using even the nodes N2, N3, N4, N5. Also, the aforementioned relationship can be established using the other combinations of the constraint length K and the code rate. Therefore, the similar operation can be executed. Moreover, the similar operation can be executed even if the dual port RAM is used as the storing section for storing the path metrics.
Sixth Embodiment
• FIG. 18 is a block diagram showing the structure of the processing unit of the sixth embodiment of the present invention. In the processing unit ofFIG. 18, the same reference numerals are added to the portions common to the processing unit ofFIG. 16 and the explanation is omitted.
• As compared with the processing unit ofFIG. 16, in the processing unit ofFIG. 18, the comparingsection5 comprisesadders19,20, and acomparator21, and the addingsection6 comprisesadders22 and23. Also, the comparingsection9 comprisesadders24,25, and acomparator26, and the addingsection10 comprisesadders27 and28.
• InFIG. 18, theadders19 and20 input data from thebus4 and theinput register16 and add these input data. Thecomparator21 inputs addition results from theadders19 and20 and compares the addition results, and outputs a comparison result to the comparisonresult storing section7 and the selectingsection8. Theadders22 and23 input data from thebus4 and theinput register16 and add these input data, and output addition results to the selectingsection8.
• Theadders24 and25 input data from thebus4 and theinput register17 and add these input data. Thecomparator26 inputs addition results from theadders24 and25 and compares the addition results, and outputs a comparison result to the comparisonresult storing section11 and the selectingsection12. Theadders27 and28 input data from thebus4 and theinput register17 and add these input data, and output addition results to the selectingsection12.
• The processing unit ofFIG. 18 is suitable for the operation processing of the pipe line structure shown inFIG. 15.
• Next, the ACS operation of the sixth embodiment will be explained. This explanation will be given using the convolutional encoder ofFIG. 7 and the butterfly structure ofFIG. 8 where the constraint length K=4 and the code rate is ½, and the ACS operation result ofFIG. 17.
• As shown inFIG. 18, two metrics are output as {A, B} from the input registers16 and17, and two branch metrics are output as {C, D} from theswap circuit18. At this time, theadder19 inputs the path metric {A} and the branch metric {C}, and outputs an addition result {A+C}. Theadder20 inputs the path metric {B} and the branch metric {D}, and outputs an addition result {B+D}. Thecomparator21 inputs the addition result {A+C} of theadder19 and the addition result {B+D} of theadder20, compares {A+C−{B+D)}, and outputs the MSB of the comparison result. Theadder22 inputs the path metric {A} and the branch metric {C}, and outputs the addition result {A+C}. Theadder23 inputs the path metric {B} and the branch metric {D}, and outputs the addition result {B+D}.
• On the other hand, theadder24 inputs the path metric {A} and the branch metric {D}, and outputs an addition result {A+D}. Theadder25 inputs the path metric {B} and the branch metric {C}, and outputs an addition result {B+C}. The comparator.26 inputs the addition result {A+D} of theadder24 and the addition result {B+C} of theadder25, compares {A+D−{B+C)}, and output the MSB of the comparison result. Theadder27 inputs the path metric {A} and the branch metric {D}, and outputs the addition result {A+D}. Theadder28 inputs the path metric {B} and the branch metric {C}, and outputs the addition result {B+C}.
• By the above structure and the operation, if two path metrics of the input registers16 and17 are set to {A, B}={PM1, PM0} and the outputs of theswap circuit18 are set to {C, D}={BM1, BM0}, the ACS operation, which is executed at the time of the transition from the nodes N0 and N1 of the old state to the nodes N′0 and N′4, can be realized.
• Also, if two path metrics of the input registers16 and17 are set to {A,B}={PM1,PM0} and the outputs of theswap circuit18 are set to {C,D}={BM0,BM1}, the ACS operation, which is executed at the time of the transition from the nodes N0 and N1 of the old state to the nodes N′0 and N′4, can be realized.
• Therefore, according to the sixth embodiment, the update of two path metrics can be realized at one machine cycle by the pipe line operation using DSP. The above embodiment was explained using the nodes N0, N1, N6, N7 of the old state where the constraint length K=4 and the code rate was ½. However, the aforementioned relationship can be established using even the nodes N2, N3, N4, N5. Also, the aforementioned relationship can be established using the other combinations of the constraint length K and the code rate. Therefore, the similar operation can be executed. Moreover, the similar operation can be executed even if the dual port RAM is used as the storing section for storing the path metrics.
Seventh Embodiment
• FIG. 19 is a block diagram showing the structures of the processing unit of the seventh embodiment of the present invention. In the processing unit ofFIG. 19, the same reference numerals are added to the portions common to the processing unit ofFIG. 18 and the explanation is omitted.
• As compared with the processing unit ofFIG. 18, in the processing unit ofFIG. 19, an arithmetic logic section (hereinafter referred as “ALU”)29 is used in place of thecomparator21. Then, the processing unit ofFIG. 19 comprises input registers30,31,buses32,33,37,38, andselectors34 and35.
• InFIG. 19, theregister30 inputs data from theRAM14 via thebus37. Theregister31 inputs data from theRAM14 via thebus38. The buses32 and33 input data from aregister file36. Theselector34 selects an output of input data from the bus32, theadder19, and theinput register30. Theselector35 selects an output of input data from the bus33, theadder20, and theinput register31. TheALU29 inputs data from theselectors34 and35 and executes an arithmetic logic operation, and outputs a result of the arithmetic logic operation to thebus13. Also, theALU29 outputs the MSB of the result of the arithmetic logic operation to the comparisonresult storing section7 and the selectingsection8.
• The processing unit ofFIG. 19 is suitable for the operation processing of the pipe line structure shown inFIG. 15.
• In the case where theALU29 performs the ACS operation, theselector34 selects an output of theadder19 and inputs the selected output to theALU29. Theselector35 selects an output of theadder20 and inputs the selected output to theALU29. Then, theALU29 subtracts input two data, and the MSB of the subtraction result to the comparisonresult storing section7 and the selectingsection8.
• In the case where theALU29 performs the arithmetic logic operation between the register-register, theselectors34 and35 select the buses32 and33, respectively. Then, data, which is output to the buses32 and33 from theregister file36, is input to theALU29.
• Also, in the case where theALU29 performs the arithmetic logic operation between the register-memory, theselectors34 and35 select the bus32 and theinput register31, respectively. Then, data, which is output to the bus32 from theregister file36, and data, which is output to the input register31 from theRAM14 via thebus38, are input to theALU29.
• Conversely, in the case where theALU29 performs the arithmetic logic operation between the memory-register, theselectors34 and35 select theinput register30 and the bus33, respectively. Then, data, which is output to theregister30 from theRAM14 via thebus37, and data, which is output to the bus33 from theregister file36, are input to theALU29.
• Also, in the case where theALU29 performs the arithmetic logic operation between the memory-memory, theselectors34 and35 select the input registers30 and31, respectively. Then, data, which is input to the input registers30 and31 from theRAM14 via thebuses37 and38, is input to theALU29
• Thus, according to the seventh embodiment, for implementing the processing unit in an LSI form, one of the comparators for executing the ACS operations is used as ALU. Thereby, a chip area can be decreased, and the manufacturing cost can be reduced. Note that the similar operation can be executed even if the dual port RAM is used as the storing section for storing the path metrics.
Eighth Embodiment
• FIG. 20 is a block diagram showing the structure of the processing unit of the eighth embodiment of the present invention. In the processing unit ofFIG. 20, the same reference numerals are added to the portions common to the processing unit ofFIG. 19 and the explanation is omitted.
• As compared with the processing unit ofFIG. 19, in the processing unit ofFIG. 20, twoadders19 and20 are formed by a 4:2compressor39, and twoadders24 and25 are formed by a 4:2compressor40. In the 4:2compressors39 and40, single blocks, shown inFIG. 21, corresponding to a number of single precision bits, are connected in series. The 4:2compressors39 and40 execute an addition processing at higher speed than the general full adders.
• InFIG. 20, the 4:2compressor39 inputs data from thebus4 and theinput register16, and outputs an operation result to theselectors34 and35. The 4:2compressor40 inputs data from thebus4 and theinput register17, and outputs an operation result to thecomparator26 The processing unit ofFIG. 20 is suitable for the operation processing of the pipe line structure shown inFIG. 15.
• Next, the ACS operation of the eighth embodiment will be explained. This explanation will be given using the convolutional encoder ofFIG. 7 and the butterfly structure ofFIG. 8 where the constraint length K=4 and the code rate is ½, and the ACS operation result ofFIG. 17.
• First of all, two metrics are output as {A, B} from the input registers16 and17, and two branch metrics are output as {C, D} from theswap circuit18.
• Then, the 4:2compressor39 inputs the path metric {A} and the branch metric {C}, a reverse {⁻B} for path metric {B}, and a reverse {⁻D} for branch metric D, and outputs {A+C} and {B+D}. Two outputs {A+C} and {B+D} of the 4:2compressor39 are input to theALU29 via theselectors34 and35 so as to be added. In this case, to realize two complements {B} and {D}, “1” is input to the 4:2compressor39 and the least significant carry input of theALU29. As a result, {A+C−{B+D)} is obtained and the MSB is output from theALU29.
• Also, theadder22 inputs the path metric {A} and the branch metric {C}, and outputs the addition result {A+C}. Similarly, theadder23 inputs the path metric {B} and the branch metric {D}, and outputs the addition result {B+D}.
• On the other hand, the 4:2compressor40 inputs the path metric {A} and the branch metric {D}, a reverse {⁻B} for path metric {B}, and a reverse {⁻C} for branch metric C, and outputs {A+C} and {B+D}. Two outputs {A+C} and {B+D} of the 4:2compressor40 are input to thecomparator26 so as to be added. In this case, to realize two complements {B} and {C}, “1” is input to the 4:2compressor40 and the least significant carry input of thecomparator26. As a result, {A+D−{B+C)} is obtained and the MSB is output From thecomparator26.
• Also, theadder27 inputs the path metric {A} and the branch metric {D}, and outputs the addition result {A+D}. Similarly, theadder28 inputs the path metric {B} and the branch metric {C}, and outputs the addition result {B+C}.
• By the above structure and the operation, if two path metrics {A,B} of the input registers16 and17 are set to {PM1,PM0} and the outputs {C,D} of theswap circuit18 are set to {BM1,BM0}, the ACS operation, which is executed at the time of the10 transition from the nodes N0 and N1 of the old state ofFIG. 17 to the nodes N′0 and N′4, can be realized.
• Also, if two path metrics {A,B} of the input registers16 and17 are set to {PM1,PM0} and the outputs {C,D} of theswap circuit18 are set to {BM0,BM1}, the ACS operation, which is executed at the time of the transition from the nodes N0 and N1 of the old state ofFIG. 17 to the nodes N′0 and N′4, can be realized. Therefore, the update of two path metrics can be realized at one machine cycle by the pipe line operation using DSP.
• Thus, according to the eighth embodiment, the use of the 4:2 compressors as the comparing section for executing the ACS operation can realize the higher speed computation than the case using two adders. The above embodiment was explained using the nodes N0, N1, N6, N7 of the old state where the constraint length K=4 and the code rate was ½.
• However, the aforementioned relationship can be established using even the nodes N2, N3, N4, N5. Also, the aforementioned relationship can be established using the other combinations of the constraint length K and the code rate. Therefore, the similar operation can be executed. Moreover, the similar operation can be executed even if the dual port RAM is used as the storing section for storing the path metrics.
Ninth Embodiment
• FIG. 22 is a block diagram showing the structure of the processing unit of the seventh embodiment of the present invention. In the processing unit ofFIG. 22, the same reference numerals are added to the portions common to the processing unit ofFIG. 20 and the explanation is omitted.
• As compared with the processing unit ofFIG. 20, in the processing unit ofFIG. 22, double-precision adders41 and42 are used as adding sections, and at least one of the adders uses a double-precision AU41.
• InFIG. 22, the double-precision AU41 inputs data in a double-precision form from theinput register16 and thebus4 and executes a double-precision arithmetic operation. The double-precision adder42 inputs data in a double-precision form from theinput register17 and thebus4 and executes a double-precision adding operation. The double-precision AU41 outputs an operation result to the selectingsection8 and thebus13, and the output of the double-precision adder42 is output to the selectingsection12.
• The processing unit ofFIG. 22 is suitable for the operation processing of the pipe line structure shown inFIG. 15.
• For executing the ACS operation in the ninth embodiment, the double-precision AU41 inputs two path metrics as {A, B} in a double-precision form from theinput register16. Then, the double-precision AU41 inputs two branch metrics as {C, D} in a double-precision form from theswap circuit18 via thebus4, and executes a double-precision addition. At this time, the double-precision AU41, as shown inFIG. 23, forcibly zeros the carry from the bit position of the single-precision MSB to a next stage, and executes two additions of the path metrics and the branch metrics, {A+C, B+D}, simultaneously.
• On the other hand, the double-precision adder42 inputs two path metrics as {A, B} in a double-precision form from theinput register17.
• Then, the double-precision adder42 inputs two branch metrics as {D, C} in a double-precision form from theswap circuit18 via thebus4. Then, the double-precision adder42 forcibly zeros the carry from the bit position of the single-precision MSB to a next stage, and executes two additions of the path metrics and the branch metrics, {A+C, B+D}, simultaneously.
• Thus, according to the ninth embodiment, the double-precision AU41 is used as the adding section for executing the ACS operation. At the time of the ACS operation, the double-precision AU41 forcibly zeros the carry from the bit position of the single-precision MSB to the next stage. At the time of the double-precision arithmetic operation other than the ACS operation, the control for propagating the carry is added. Thereby, for example, the double-precision AU41 can be used as a double-precision accumulation adder at the time of product and addition operations. Therefore, in the case of implementing the processing unit in an LSI form, the chip area can be further decreased, and the manufacturing cost can be reduced. Note that the similar operation can be executed even if the dual port RAM is used as the storing section for storing the path metrics.
Tenth Embodiment
• FIG. 24 is a block diagram showing the structure of the processing unit of the tenth embodiment of the present invention. In the processing unit ofFIG. 24, the same reference numerals are added to the portions common to the processing unit ofFIG. 22 and the explanation is omitted.
• As compared with the processing unit of FIG.22, in the processing unit ofFIG. 20, shift registers43 and44 are used as a comparison result storing section.
• InFIG. 24, theshift register43 inputs the MSB of the operation result of theALU29 so as to be output to thebus2. Theshift register44 inputs the MSB of the operation result of thecomparator26 so as to be output to thebus2.
• The processing unit ofFIG. 24 is suitable for10 the operation processing of the pipe line structure shown inFIG. 15.
• For executing the ACS operation in the tenth embodiment, the BSM of the comparison result of theALU29 is shifted in theshift register43 at any time. The BSM of the comparison result of thecomparator26 is shifted in theshift register44 at any time. Thereby, a path select signal can be stored in theRAM14. In this case, the path select signal shows which path of two paths has been selected, and is used in executing the trace-back after the end of the ACS operation.
• For example, in a case where the bit width of theshift register43 and that of theshift register44 are single-precision data widths, the path select signal can be stored when the ACS operation corresponding to a number of single-precision bits are executed.
• Thus, according to the tenth embodiment, the shift registers are used as storing means for executing the ACS operations and for storing the comparison result. Thereby, for example, the shift registers can be used as an operation instruction for using a shift register of a division system. Therefore, in the case of implementing the processing unit in an LSI form, the chip area can be further decreased, and the manufacturing cost can be reduced. Note that the similar operation can be executed even if the dual port RAM is used as the storing section for storing the path metrics.
Eleventh Embodiment
• FIG. 25 is a block diagram showing the structure of the processing unit of the eleventh embodiment of the present invention. In the processing unit ofFIG. 25, the same reference numerals are added to the portions common to the processing unit ofFIG. 24 and the explanation is omitted.
• As compared with the processing unit ofFIG. 24, in the processing unit ofFIG. 25, theinput register17 swaps the path metric data so as to be input from thebus2. Then, 4:2compressor40 directly inputs the branch metric data without swapping the branch metric data, and a negate value of the comparison result of thecomparator26 is shifted in theshift register44.
• The processing unit ofFIG. 25 is suitable for the operation processing of the pipe line structure shown inFIG. 15.
• For executing the ACS operation in this embodiment, two path metrics {A,B} are directly input to theinput register16 as {A,B}, and input to theinput register17 as {B,A} in a swapped state. After that, two branch metrics are input from theswap circuit18 to the 4:2compressor40 as {C} and {⁻D}, and two path metrics are input from theinput register17 to the 4:2compressor40 as {B} and {⁻A}, and {A+B} and {B+C} are output.
• Then, thecomparator26 inputs two outputs {A+B} and {B+C} so as to calculate {A+D−B−C}.
• On the other hand, the double-precision adder42 inputs two branch metrics as {C, D} from theswap circuit18, and inputs two path metrics as {B, A} from the input register. Then, {B+C} and {A+D} are simultaneously computed in parallel, and output to the selectingsection12 in the form of {B+C, A+D}.
• Then, the MSB of the comparison result is output to the selectingsection12 from thecomparator26, and the MSB of the negate value of the comparison result is output to theshift register44.
• Thus, according to the eleventh embodiment, one of the input registers for storing two path metrics swaps data to be input. As a result, since the need of the swapping operation at the input of the 4:2compressor40 and that of the double-precision adder42 can be eliminated at the operation execution (EX) stage, the ACS operation can be executed at higher speed. Note that the similar operation can be executed even if the dual port RMA is used as the means for storing the path metrics.
Twelfth Embodiment
• FIG. 26 is a block diagram showing the structure of a mobile station apparatus in the twelfth embodiment. Amobile station apparatus45 shown inFIG. 26 comprises anantenna section46 for both reception and transmission, aradio section47 having a receivingsection48 and a transmittingsection49, a base bandsignal processing section50 for executing a signal modulation and demodulation, and a signal coding and decoding, aspeaker58 for outputting a sound, amicrophone59 for inputting a sound, a data input/output section60 for inputting/outputting data to be received and transmitted from/to an outer device, adisplay section61 for displaying an operation state, anoperation section62 such as a 10-button keypad, and acontrol section63 for controlling the respective parts.
• The base bandsignal processing section50 comprises ademodulation section51 for demodulating a received signal, amodulation section52 for modulating a transmitted signal, and aDSP53 of one chip.
• TheDSP53 comprises aViterbi decoding section55, which is formed by any one of the processing units of the first to eleventh embodiments, aconvolutional coding section56 for convolutional coding the transmitted signal, avoice codec section57 for executing a voice signal coding and decoding, and atiming control section54 for controlling timing for sending the received signal to theViterbi decoding section55 from thedemodulation section51 and timing for sending the transmitted signal to themodulation section52 from theconvoltional coding section56. These devices are formed by software, respectively.
• Thecontrol section63 displays a signal input from theoperation section62 to thedisplay section61, receives the signal input from theoperation section62. Then, thecontrol section63 outputs a control signal for performing a calling operation to theantenna section46, theradio section47, and the base bandsignal processing section50 in accordance with a communication sequence.
• If the voice is transmitted from themobile station apparatus45, the voice signal input from themicrophone59 is AD converted by an AD converter (not shown). Then, the converted signal is coded by thevoice codec section57 so as to be input to theconvolutional coding section56. If data is transmitted, date input from the outer section is input to theconvolutional coding section56 through the data input/output section60.
• Data input to theconvolutional coding section56 is convolutional coded, and thetiming control section54 sorts data and adjusts the transmission output timing so as to output data to themodulation section52. Data input to themodulation section52 is digitally modulated, AD converted, and output to the transmittingsection49 of theradio section47. Data input to the transmittingsection49 is converted to radio signals, and output to theantenna section46 as radio waves.
• On the other hand, for outputting data received by themobile station apparatus45, the radio waves received by theantenna portion46 are received by the receivingsection48 of theradio potion47, AD converted, and output to thedemodulation section51 of the base bandsignal processing section50. Data demodulated by thedemodulation section51 is sorted by thetiming control section54, thereafter being decoded by theViterbi decoding section55.
• In the case of voice communications, decoded data is voice decoded by thevoice codec section57, and is DA converted, thereafter being output to thespeaker58 as a voice. In the case of data communications, data decoded by theViterbi decoding section55 is output to the outer section through the data input/output section60.
• In themobile station apparatus45 of the twelfth embodiment, the respective parts of theViterbi decoding section55, theconvolutional coding section56, thevoice codec section57, and thetiming control section54 are formed by software of onechip DSP53. Thus, themobile station apparatus45 can be assembled by a small number of parts. Also, since theViterbi decoding section55 is formed by any one of the processing units of the first to eleventh embodiments, the update of two path metrics can be realized with one machine cycle in the pipe lineprocessing using DSP53. Thereby, the high speed ACS operation of the Viterbidecoding using DSP53 can be realized with relative a small amount of processing.
• In this embodiment, thedemodulation section51 and themodulation section52 are shown to be differentiated fromDSP53. However, these devices can be formed by software ofDSP53. Also, the DSP of the sixth embodiment can be used asDSP53, and theconvolutional coding section56, thevoice codec section57, and thetiming control section54 can be formed by the other parts, respectively.
Thirteenth Embodiment
• FIG. 27 is a block diagram showing the structure of a mobile station apparatus in the thirteenth embodiment. In amobile station apparatus45A ofFIG. 27, the same reference numerals are added to the portions common to the portions of themobile station apparatus45 ofFIG. 26, and the explanation is omitted.
• As compared with themobile station apparatus45 ofFIG. 26, in themobile station apparatus45A ofFIG. 27, a spreadingsection65 is provided in amodulation section52A, and adespreading section64 is provided in ademodulation section51A, so that a base bandsignal processing section50A of a CDMA communication system is formed. In the case of the CDMA communication system, in some cases, a RAKE receiving section, in which a plurality of fingers selected from a delay profile are adjusted to each other, is included in thetiming control section54.
• Thus, in themobile station apparatus45A in the thirteenth embodiment, thedespreading section64 is provided in thedemodulation section51A and the spreadingsection65 is provided in themodulation section52A. Thereby, themobile station apparatus45A of the thirteenth embodiment can be applied to the CDMA communication system.
Fourteenth Embodiment
• FIG. 28 is a block diagram showing the structure of a base station apparatus in the fourteenth embodiment.
• InFIG. 28, abase station apparatus68 of the fourteenth embodiment comprises theantenna section46 having anantenna66 for receiving and anantenna67 for transmitting, theradio section47 having the receivingsection48 and the transmittingsection49, a base bandsignal processing section69 for executing a signal modulation and demodulation and a signal coding and decoding, the data input/output section60 for inputting/outputting data to be received and transmitted from/to a cable network, and thecontrol section63 for controlling the respective parts.
• The base bandsignal processing section69 comprises thedemodulation section51 for demodulating the received signal, themodulation section52 for modulating the transmitted signal, and onechip DSP53A. TheDSP53A comprises theViterbi decoding section55, which is formed by any one of the processing units of the first to eleventh embodiments, theconvolutional coding section56 for convolutional coding the transmitted signal, and thetiming control section54 for controlling timing for sending the received signal to theViterbi decoding section55 from thedemodulation section51 and timing for sending the transmitted signal to themodulation section52 from theconvolutional coding section56. These devices are formed by software, respectively.
• When data is received to thebase station apparatus68 from the cable network, data is input to theconvolutional coding section56 through the data input/output section60. Then, data input to theconvolutional coding section56 is convolutional coded, and thetiming control section54 sorts input data and adjusts the transmission output timing so as to output data to themodulation section52. Data input to themodulation section52 is digitally modulated, AD converted, and is converted to radio signals by the transmittingsection49. Then, the radio signals are transmitted from theantenna section46 as radio waves.
• On the other hand, if data is received to thebase station apparatus68 from the radio network, the radio waves received by theantenna portion46 are AD converted by the receivingsection48 and demodulated by thedemodulation section51 of the base bandsignal processing section69. Demodulated data is sorted by thetiming control section54, and decoded by theViterbi decoding section55, thereafter being output to the cable network via the data input/output section60.
• In thebase station apparatus68 of the fourteenth embodiment, the respective parts of theViterbi decoding section55, theconvolutional coding section56, and thetiming control section54 are formed by software of onechip DSP53A. Thus, thebase station apparatus68 can be assembled by a small number of parts. Also, since theViterbi decoding section55 is formed by any one of the processing units of the first to eleventh embodiments, the update of two path metrics can be realized with one machine cycle in the pipe lineprocessing using DSP53A. Thereby, the high speed ACS operation of the Viterbidecoding using DSP53A can be realized with relatively a small amount of processing.
• In this embodiment, thedemodulation section51 and themodulation section52 are shown to be differentiated fromDSP53A. However, these devices can be formed by software ofDSP53A. Also, the DSP of the sixth embodiment can be used asDSP53A, and theconvolutional coding section56, thevoice codec section57, and thetiming control section54 can be formed by the other parts, respectively.
Fifteenth Embodiment
• FIG. 29 is a block diagram showing the structure of a base station apparatus in the fifteenth embodiment in abase station apparatus68A ofFIG. 29, the same reference numerals are added to the portions common to the portions of thebase station apparatus68 ofFIG. 28, and the explanation is omitted.
• As compared with themobile station apparatus45 ofFIG. 26, in themobile station apparatus45A ofFIG. 27, the spreadingsection65 is provided in themodulation section52A, and thedespreading section64 is provided in thedemodulation section51A, so that the base bandsignal processing section50A of the CDMA communication system is formed. In the case of the CDMA communication system, in some cases, the RAKE receiving section, in which the plurality fingers selected from the delay profile are adjusted to each other, is included in thetiming control section54.
• Thus, in thebase station apparatus68A of the fifteenth embodiment, thedespreading section64 is provided in thedemodulation section51A and the spreadingsection65 is provided in themodulation section52A. Thereby, thebase station apparatus68A of the fifteenth embodiment can be applied to the CDMA communication system.
• As mentioned above, the update of two path metrics can be realized with one machine cycle in the pipe line processing using DSP. Thereby, the high speed ACS operation of the Viterbi decoding using DSP can be realized with relative a small amount of processing. This makes it possible to downsize the portable terminal, reducing the weight, lowering the cost, and increasing the life of a battery.

Claims (11)

1. A digital signal processor, comprising:

an instruction executer configured to execute instructions;

wherein the instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data;

wherein the instruction executer outputs a processed data including the first minimum data and the second minimum data;

wherein a bit length of the first minimum data is equal to n bits in length;

wherein a bit length of the second minimum data is equal to n bits in length; and

wherein a bit length of the processed data is equal to at least 2n bits in length.

2. The digital signal processor according toclaim 1, further comprising:

an instruction fetcher that fetches instructions; and

a decoder that decodes the instructions fetched by the instruction fetcher.

3. The digital signal processor according toclaim 2,

wherein the digital signal processor provides the processed data by one instruction.

4. The digital signal processor according toclaim 3,

wherein the digital signal processor provides the first data when the first data is equal to the second data, and provides the third data when the third data is equal to the fourth data.

5. A digital signal processor, comprising:

an instruction executer configured to execute instructions;

wherein the instruction executer is used to determine a first minimum data of a first data and a second data, in a single cycle in which a second minimum data of a third data and a fourth data is also determined, and

wherein the instruction executer is configured to perform a register-register operation.

6. The digital signal processor according toclaim 5, further comprising:

an instruction fetcher that fetches instructions; and

a decoder that decodes the instructions fetched by the instruction fetcher.

7. The digital signal processor according toclaim 6,

wherein the instruction executer outputs a processed data including the first minimum data and the second minimum data, and

wherein the digital signal processor provides the processed data by one instruction.

8. The digital signal processor ofclaim 7,

wherein the instruction executer is configured to perform a first addition, a second addition, a third addition and a fourth addition in parallel.

9. The digital signal processor according toclaim 8,

wherein the digital signal processor provides the first data when the first data is equal to the second data, and provides the third data when the third data is equal to the fourth data.

10. The digital signal processor according toclaim 9,

wherein the digital signal processor provides the first minimum data as a high part of the processed data, and

wherein the digital signal processor provides the second minimum data as a low part of the processed data.

11. The digital signal processor according toclaim 8, further comprising:

a plurality of registers, including a first register and a second register, for storing data,

wherein the first register stores a result of determining the first minimum data, and

wherein the second register stores a result of determining the second minimum data.

Images