US20080034361A1 - Method and apparatus for generating multiple processor- specific code segments in a single executable - Google Patents

Abstract

A computer-implemented method analyzes a source code segment which is to be compiled for execution by any one of several different processor types. The method determines whether a performance advantage would be achieved by generating a customized version of object code that can be executed by one of the processor types compared with generating a non-customized version. If a performance advantage would be achieved, the method generates at least one customized object code version and a non-customized version for the source code segment, and it generates a control section that causes one of the object code versions to be called during execution of the object code in accordance with an executing processor's processor type. If no performance advantage would be achieved, the method generates a non-customized version of the object code that can be executed by any of the different processor types.

Description

RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 10/215,429, filed Aug. 9, 2002, which is a continuation of U.S. patent application Ser. No. 09/474,714, filed Dec. 29, 1999, now issued as U.S. Pat. No. 6,473,897, which is a continuation-in-part of U.S. patent application Ser. No. 09/059,601, filed Apr. 13, 1998, now issued as U.S. Pat. No. 6,049,668, all of which are incorporated herein by reference.
TECHNICAL FIELD
• Embodiments of the present invention pertain to compilers and software programming and, more particularly, to generating multiple processor-specific code segments in a single executable.
BACKGROUND INFORMATION
• Modern computer systems can have any of a wide range and variety of configurations. One important component of a computer system is the processor, also referred to as the central processing unit (CPU). The processor executes instructions from a software program, a process referred to as “running” the program. Although typically all processors perform this basic task, a wide variety of different processors are available from a number of different manufacturers. These different processors, especially those from different manufacturers, have different internal designs, also referred to as the processor “architecture”, and thus operate in different ways. Although the results from running a program on two different processors are typically the same, the way in which the processor obtains the result, as well as its speed, typically differ.
• Many conventional processors, such as the Pentium® Pro processor and Pentium® processor with MMX™ technology (both available from Intel Corporation of Santa Clara, Calif.) are based on an architecture referred to as “x86”. Software programs can be written which are executable by any x86-compatible processor. However, various changes can also be made to a software program in order to allow it to be executed faster by a particular processor type. By way of example, a Pentium® processor with MMX™ technology is capable of executing additional instructions, i.e., those associated with the MMX™ technology, which a Pentium® Pro processor is not capable of executing. Given the advantages of using such instructions, it would be beneficial to provide a way for a programmer to include code customized to both the Pentium® processor with MMX™ technology and the Pentium® Pro processor in the same program.
• However, a software programmer also typically wants his or her code to be executable by as many processors as possible, thereby allowing a greater share of the market to purchase his or her product. This desire, then, is balanced against the programmer's desire to write code that works efficiently and makes the best use of the processor which is executing it. One way to do so is to write a separate program for each possible processor which might execute the program. However, such a solution is problemsome in that it is time-intensive and costly, often resulting in a large amount of unnecessary duplication.
• Another solution is to write a single program which includes different routines or functions designed to take advantage of the various capabilities of the processors which may run the program. However, one problem with this solution is that most programming languages do not allow multiple functions to have the same function name. Thus, the programmer must give the different functions for the different processors different names and correctly manage these different names throughout the rest of the program. This can be particularly difficult due to the requirement that all portions of the code must correctly identify the different functions by their different names.
• Thus, a need exists for an improved way to customize programs for specific processors.
BRIEF DESCRIPTION OF THE DRAWINGS
• Embodiments of the present invention are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which:
• FIG. 1 illustrates the generation of machine executable code according to one embodiment of the present invention;
• FIG. 2 illustrates multiple code segments incorporating the processor-specific and dispatch constructs according to one embodiment of the present invention;
• FIG. 3 is a flowchart illustrating the steps followed in compiling high-level language according to one embodiment of the present invention;
• FIG. 4 illustrates sample assembly code generated according to one embodiment of the present invention;
• FIG. 5 illustrates an example hardware system suitable for use with one embodiment of the present invention;
• FIG. 6 is a block diagram illustrating a device on which one embodiment of the present invention can be implemented;
• FIG. 7 is a flowchart illustrating the steps followed in compiling high-level language when a compiler switch for automatic CPU dispatch is turned off, according to an alternate embodiment of the invention;
• FIG. 8 is a flowchart illustrating the steps followed in compiling high-level language when a compiler switch for automatic CPU dispatch is set, according to an alternate embodiment of the invention;
• FIG. 9 illustrates sample source code segments that can be compiled by an automatic CPU dispatch construct according to an alternate embodiment of the invention;
• FIG. 10 illustrates sample assembly code for CPU-dispatch testing that is generated using automatic CPU dispatch according to an alternate embodiment of the invention;
• FIG. 11 illustrates sample assembly code optimized for a high performance CPU that is generated using automatic CPU dispatch according to an alternate embodiment of the invention;
• FIG. 12 illustrates sample assembly code optimized for a medium performance CPU that is generated using automatic CPU dispatch according to an alternate embodiment of the invention; and
• FIG. 13 illustrates sample assembly code with no CPU-specific optimizations that is generated using automatic CPU dispatch according to an alternate embodiment of the invention.
DETAILED DESCRIPTION
• In the following detailed description numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. However, it will be understood by those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances well known methods, procedures, components, and circuits have not been described in detail so as not to obscure embodiments of the present invention.
• Some portions of the detailed descriptions which follow are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present disclosure, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
• Modern programmers typically write programs in what are referred to as “high-level” programming languages. Examples of such high-level programming languages include C, C++, PASCAL, and Fortran. High-level programming languages make it easier for the programmer to write his or her code; however, they also must be converted into a form which can be interpreted by a processor in order for it to run the program. The form of a program which can be interpreted by a processor is typically referred to, and will be referred to herein, as “object code”. (This should not be confused with an object file which contains object code.)
• In one embodiment, the present invention allows a programmer to create multiple code segments with the same identifier but different processor-specific instructions. These code segments are typically a “function” or “procedure” of the high-level programming language in an illustrated embodiment, but they can be larger or smaller blocks of code. As used herein, “code segment” refers to one or more software instructions or statements. The code segment identifiers are typically the function or procedure name, but different identifiers can be used in alternate embodiments.
• Thus a programmer is able to customize different code segments, all with the same identifier, for different processor types. The object code corresponding to a particular one of these different code segments is then executed when the program runs, with the particular one of the different code segments being based on the type of processor which is running the program. Each of the several types of processors can be a different processor architecture.
• In another embodiment, the present invention comprises a computer-implemented method that analyzes a source code segment which is to be compiled for execution by any one of several different processor types. The method determines whether a performance advantage would be achieved by generating a customized version of object code that can be executed by one of the processor types compared with generating a non-customized version. If a performance advantage would be achieved, the method generates at least one customized object code version and a non-customized version for the source code segment, and it generates a control section that causes one of the one or more object code versions to be called during execution of the object code in accordance with an executing processor's processor type. If no performance advantage would be achieved, the method generates a non-customized version of the object code that can be executed by any of the different processor types. Again, each of the several types of processors can be a different processor architecture.
• FIG. 1 illustrates the generation of machine executable code according to one embodiment of the present invention. High-level code100 is coded or code generated from an application generator in a high-level programming language and is input to acompiler110. Additional functions and procedures fromlibraries105 may also be used bycompiler110 in compiling high-level code100. Such additional functions are typically identified within the high-level code100 and are typically general-purpose routines (for example, input/output (I/O) routines) which many programs will use. It is to be appreciated that although embodiments of the present invention are discussed with reference to the high-level code100, they may also be used with the code in thelibraries105.
• Compiler110 is informed of the available processor types that will execute machine-executable object code compiled bycompiler110, for example by a list or table103 of available processor types such as Table I discussed below.
• Compiler110 generatesassembly code115 from high-level code100 and possiblylibraries105.Assembly code115 provides a more human-readable version of the architectural- or processor-dependent object code, discussed below, and is also referred to as “assembly language”.Assembly code115 can be thought of as a mid-level programming language in relation to the high-level languages discussed above. Theassembly code115 can optionally be saved bycompiler110 as a separate file during the compilation process. Somecompilers110 make at least two or three “passes” through the high-level code100 when creating theassembly code115. Various customizations may also be made bycompiler110 in generating theassembly code115 during these passes. The customizations are compiler-specific and conventionally have been identified by the programmer.
• For example, in one embodiment of the invention, thecompiler110, in one pass, analyzes the high-level code100 function-by-function to determine which functions, if any, represent an opportunity to take advantage of CPU-specific instructions. Examples of such CPU-specific instructions are instructions from a particular CPU's instruction set that can execute the function faster and/or more efficiently or provide data in a unique format for further processing.
• For example, a high performance CPU such as a Pentium® III processor can execute vectorizable loops using single-precision floating-point single-instruction-multiple-data (SIMD) instructions, whereas a Pentium® processor cannot do so. As another example, integer floating-point SIMD instructions can be processed by a Pentium® III processor, a Pentium® II processor, or a Pentium® processor with MMX™ technology, but not by a Pentium® Pro processor, a Pentium® processor, or an Intel®486 processor.
• In yet another example, a Pentium® II processor or a Pentium® processor with MMX™ technology is capable of executing instructions associated with MMX™ technology, which a Pentium® Pro processor is not capable of executing. One of ordinary skill in the programming arts will understand how to write compiler code that implements the analytical features of embodiments of the present invention.
• Thus, in a first pass, thecompiler110 identifies those functions that can be optimized. Depending upon the number of CPU types that will potentially be used to execute the object code,compiler110 can identify a number N of possible optimizations for any given function up to and including the number N of CPU types.
• In a subsequent pass,compiler110 compiles the high-level code100 into assembly code, compiling up to N separate versions, depending upon the number of opportunities for optimization. For example, if N=6, i.e. there are potentially six different types of CPU's that will be used to execute the object code, there could potentially be five different customized versions of assembly code, one for each of the CPU's that have a higher performance level than the base CPU, plus one non-customized version for the lowest performance CPU.
• Ifcompiler110 determines, regarding a particular function, that customization of assembly code would not provide a sufficient performance advantage, then it compiles a non-customized version of that particular function so that it is capable of being executed by any of the N CPU types.
• It will be apparent that some compilers convert high-level code directly to object code without first converting it to assembly language, and that embodiments of the present invention are intended to cover all types of compilers.
• Assembly code115 is input to anassembler120.Assembler120 converts theassembly code115 into machine-executable object code125.Object code125 is a stream of binary values which can be executed by a processor.Object code125 is also referred to as an “executable”.
• Except for the incorporation of the teachings of the present disclosure,compiler110 andassembler120 are intended to represent a wide range of compilers and assemblers well-known to those skilled in the art.
• In one illustrated embodiment,compiler110 andassembler120 are implemented in software.
• In one of the illustrated embodiments, two “constructs” are added to the high-level programming language in order to provide support for multiple code segments with the same identifier. These constructs can be incorporated into the programming language in any of a wide variety of conventional manners, including making the constructs “extensions” to a pre-existing language as discussed in more detail below. The first construct is a “processor-specific” construct which identifies a function as being specific to a particular processor type. The syntax of this processor-specific construct is:
• cpu_specific (cpu_specifier) function_definition
• where the “function definition” is the particular function being written by the programmer and the “cpu_specifier” is an identifier of a particular processor type for that particular function. The processor type refers to a particular processor architecture. Examples of processor types that can be supported by one implementation of the present invention are listed below in Table I. Although specific examples are listed in Table I, it should be noted that additional processor types and cpu_specifiers can be used with embodiments of the present invention, including future processor types.

  TABLE I
  cpu_specifier	Processor Type
  pentium_iii	Pentium ® III processor
  pentium_ii	Pentium ® II processor
  pentium_pro	Pentium ® Pro processor
  pentium_mmx	Pentium ® processor with MMX ™ technology
  pentium	Pentium ® processor
  generic	A “generic” processor, other than one of the Pentium ®
  	processor family or Pentium ® Pro processor family

  
  The second construct is a “dispatch” construct which is used during compilation to identify the processor-specific constructs and the different processor types to which they correspond. The syntax of this dispatch construct is:
• cpu_dispatch (cpu_specifier [, cpu_specifier [ . . . ]]) empty_function_definition
  The “empty_function_definition” is an empty function (no code) having the same name as the function_definition. Multiple cpu_specifier identifiers may be included in the cpu_dispatch construct, one for each cpu_specific construct for the function_definition.
• According to one embodiment of the present invention, the cpu_specific and cpu_dispatch constructs are implemented as an “extension” to the C and C++ programming languages. Although these extension constructs are not part of the original programming language, they can be added to the language and used as if they were a part of the original language, such as by using the Microsoft™ “_declspec” keyword. The “_declspec” keyword can be used to identify a function as an extension to the language. According to one implementation, the syntax for doing so is as follows:
• _declspec (cpu_specific (cpu_specifier))function definition
• _declspec (cpu_dispatch (cpu_specifier [, cpu_specifier [ . . . ]]) empty_function_definition
  The cpu_specifier, function_definition, and empty_function_definition are the same as discussed above.
• FIG. 2 illustrates multiple code segments written in the C++ programming language incorporating the cpu_specific and cpu_dispatch constructs. As illustrated,software program200 includes afirst cpu_specific construct201 which identifies aprint_cpu function205 customized to the Pentium® III processor (as indicated by cpu_specifier identifier208). Similarly,program200 also includes a second cpu_specific construct211 which identifies a print_cpu function215 customized to a Pentium® II processor, a third CPU-specific construct221 which identifies aprint_cpu function225 customized to the Pentium® Pro processor, a fourth cpu_specific construct241 which identifies aprint_cpu function245 customized to the Pentium® processor with MMX™ technology, and a fifth print_cpu construct261 which identifies aprint_cpu function265 customized to the Pentium® processor. As illustrated, each of the five print_cpu functions has the same function name but different instructions which are customized to particular processor types.
• Software program200 also includes acpu_dispatch construct281. The cpu_dispatch construct281 includes a list of identifiers which includes each of the processor types listed in the cpu_specific constructs201,211,221,241, and261. The cpu_dispatch construct281 identifies aprint_cpu function287, the name of which is the same as the function in the cpu_specific constructs201,211,221,211, and261. The cpu_specific constructs and the cpu_dispatch constructs allow embodiments of the present invention to be used multiple times within the same program on different function names. Thus, other processor-specific functions (not shown) can be included along withconstructs201,211,221,241,261, and281 inprogram200.
• It should be noted that thecpu_specific functions201,211,221,241, and261 ofFIG. 2 may be located adjacent one another as illustrated inprogram200, or alternatively may be distributed throughout different locations ofprogram200.
• FIG. 3 is a flowchart illustrating the steps followed in compiling the high-level language according to one embodiment of the present invention. During compilation, a dispatch construct is first identified,step305. In one illustrated embodiment, this is the cpu_dispatch construct281 ofFIG. 2. Processor-specific constructs corresponding to the dispatch construct are then identified,step310. In one illustrated embodiment, the empty_function_definition of the cpu_dispatch construct is the same name as the function_definition of the cpu_specific construct. Thus, the compiler is able to search through the high-level program to identify each of the different processor-specific constructs which correspond to the dispatch construct, which areconstructs201,211,221,241, and261 ofFIG. 2.
• The compiler then modifies the names of each of the processor-specific functions,step315. This is done in order for the assembler to distinguish between each of the different functions. However, this step is done by the compiler and is not visible to the high-level language programmer, who views each of the functions as having the same name. In one embodiment, this is accomplished by a “name mangling” algorithm, which modifies function names as necessary during compilation. In this embodiment, the compiler is pre-programmed with possible processor types and an appropriate modification for each function name based on processor type. By way of example, the characters “$B” can be added to the end of a function name for a Pentium® processor type, while the characters “$F” can be added to the end of a function name for a Pentium® III processor type. In one illustrated embodiment, at least one character which is an invalid character for a function name in the high-level language is added to the function name in the object code. This use of an invalid high-level language character in the object code ensures that the compiler does not modify the name to be the same as another function name created by the programmer.
• The compiler then generates multiple assembly code processor tests corresponding to the dispatch construct, step390. These multiple tests access an intel_cpu_indicator variable to identify the processor type. According to one embodiment of the present invention, the intel_cpu_indicator is a bit vector which encodes the processor type. The bit vectors and their corresponding processor types according to one embodiment of the present invention are illustrated in Table II below. Alternate embodiments can include a lesser or greater number of bits.

  TABLE II
  Bit Vector	Processor Type
  00000000000000000000000000000001	generic
  00000000000000000000000000000010	Pentium ® processor
  00000000000000000000000000000100	Pentium ® Pro processor
  00000000000000000000000000001000	Pentium ® processor with
  	MMX ™ technology
  00000000000000000000000000010000	Pentium ® II processor
  00000000000000000000000000100000	Pentium ® III processor

• The compiler then adds a “call to dispatch fail function” instruction to the assembly code,step325. This dispatch fail instruction identifies a course of action to take when the processor type is not identifiable. In one illustrated embodiment, the dispatch fail instruction is a jump instruction to a dispatch fail function which is a library function that is programmer-replaceable. Thus, the programmer is able to display, for example, an error message indicating the program cannot be executed by the current processor, or alternatively provide a “bare minimum” amount of code which will allow the program to continue running.
• The compiler then adds a “call to processor identification function” instruction to the assembly code,step330. The processor identification instruction identifies a course of action to take when the processor type has not yet been identified. In one illustrated embodiment, the processor identification instruction is a call to a cpu_indicator initialization function which loads the processor type information into the intel_cpu_indicator variable. Thus, once the processor type is loaded into the intel_cpu_indicator variable, the code will be able to access and identify the processor type.
• The cpu_indicator initialization function obtains the processor type information using the CPUID instruction, supported by many Intel processors. The CPUID instruction identifies the processor family (e.g., Pentium® processor family or Pentium® Pro processor family), as well as whether the processor is enabled with MMX™ technology (e.g., the Pentium® processor with MMX™ technology, the Pentium® II processor, or Pentium® III processor), thereby indicating whether the processor type is a Pentium® processor, Pentium® II processor, Pentium® III processor, Pentium® Pro processor, or Pentium® processor with MMX™ technology. Additional information may also be returned by the CPUID instruction, such as the stepping of the processor. This additional information can be used in alternate embodiments of the present invention to distinguish between different processor types. By way of example, a particular stepping of a processor may have a “bug” which is not present in subsequent steppings, and thus different code segments can be written customized to the different steppings.
• During initialization of the program, the intel_cpu_indicator variable is initialized to zero. The processor type is then stored in the intel_cpu_indicator variable when the cpu_indicator initialization function is called. Thus, in one illustrated embodiment the cpu_indicator initialization function need not be called more than once during program execution.
• FIG. 4 illustrates sample assembly code generated according to one embodiment of the present invention by a compiler from theprogram code200 ofFIG. 2. The assembly code provides a series of tests for processor types. The tests are performed during execution by checking a value stored at the memory location identified by intel_cpu_indicator (i.e., the intel_cpu_indicator variable). If the test succeeds, then the code jumps to the appropriate address for the beginning of the function for the identified processor type. However, if a test fails, then the code checks for another processor type.
• As illustrated, the code initially checks withtest402 whether the processor type is a Pentium® III processor. If the processor type is a Pentium® III processor, then thejump instruction404 transfers program execution to the memory location indicated by _print_cpu$F, which is the memory address of the section of code for the _print_cpu function customized to the Pentium® III processor (function205 ofFIG. 2). The assembly code contains similar tests for the Pentium® II processor, Pentium® Pro processor, Pentium® processor with MMX™ technology, and the Pentium® processor.
• Thefinal test412 checks whether there is a non-zero value stored in the intel_cpu_indicator variable. If there is a non-zero value, then jumpinstruction414 jumps program execution to a dispatch fail function located at the address intel_cpu_dispatch_fail. However, if there is not a non-zero value stored in the intel_cpu_indicator variable, then acall416 to the cpu_indicator initialization function located at the address intel_cpu_indicator is made. Upon return from the cpu_indicator initialization function, the program execution continues in a jump to testinstruction402, thereby repeating the process. However, now that the intel_cpu_indicator variable has been initialized, one of the tests for processor type will be successful, indicating either a particular processor type or a dispatch fail.
• In one illustrated embodiment, the compiler orders the test instructions so that the program execution jumps to the most “advanced” function (that is, the function customized to the most advanced processor architecture) which can be executed by the processor executing the program. By way of example, if two customized functions are generated, one for a Pentium® processor and one for a Pentium® processor with MMX™ technology, and if the process processor executing the program is a Pentium® II processor, then the test for the Pentium® processor with MMX™ technology is successful, thereby causing program execution to jump to the function customized for the Pentium® processor with MMX™ technology.
• Also in one illustrated embodiment, the compiler orders the test instructions in the assembly code such that the highest performance processor is tested for first. This reduces the overhead (the additional tests) of embodiments of the present invention for higher performance processors. However, alternate embodiments can use different orderings. In one such alternate embodiment, the test instructions are ordered so that the most likely processor to be executing the program is tested for first.
• The assembly code illustrated inFIG. 4 is a sample of assembly code which is generated according to one embodiment of the present invention. Alternate embodiments can generate different assembly code. By way of example, the ordering of the test instructions can be changed, the test values (−32, −16, −8, −12, and −2) can be changed, different types of testing or comparing instructions can be used, etc.
• For ease of explanation, embodiments of the present invention have been described in terms of the assembly code generated by the compiler. Those skilled in the art will appreciate that this assembly code is subsequently converted to object code which is executed by the processor.
• FIG. 5 illustrates an example hardware system suitable for use with one embodiment of the present invention.Hardware system500 includesprocessor502 andcache memory504 coupled to each other as shown. Additionally,hardware system500 includes high performance input/output (I/O) bus506 and standard I/O bus508.Host bridge510couples processor502 to high performance I/O bus506, whereas I/O bus bridge512 couples the two buses506 and508 to each other. Coupled to bus506 are network network/communication interface524,system memory514, andvideo memory516. In turn,display device518 is coupled tovideo memory516. Coupled to bus508 aremass storage520, keyboard andpointing device522, and I/O ports526. Collectively, these elements are intended to represent a broad category of hardware systems, including but not limited to general purpose computer systems based on the Pentium® processor, Pentium® Pro processor, Pentium® II processor, Pentium® III processor, or Pentium® processor with MMX™ technology, available from Intel Corporation of Santa Clara, Calif.
• These elements502-524 perform their conventional functions known in the art. In particular, network/communication interface524 is used to provide communication betweensystem500 and any of a wide range of conventional networks, such as an Ethernet, token ring, the Internet, etc. It is to be appreciated that the circuitry ofinterface524 is dependent on the type of network thesystem500 is being coupled to.
• Mass storage520 is used to provide permanent storage for the data and programming instructions to implement the above described functions, whereassystem memory514 is used to provide temporary storage for the data and programming instructions when executed byprocessor502. I/O ports526 are one or more serial and/or parallel communication ports used to provide communication between additional peripheral devices which may be coupled tohardware system500.
• It is to be appreciated that various components ofhardware system500 may be rearranged. For example,cache504 may be on-chip withprocessor502. Alternatively,cache504 andprocessor502 may be packed together as a “processor module”, withprocessor502 being referred to as the “processor core”. Furthermore, certain implementations of the present invention may not require nor include all of the above components. For example,mass storage520, keyboard andpointing device522, and/ordisplay device518 andvideo memory516 may not be included insystem500. Additionally, the peripheral devices shown to standard I/O bus508 may be coupled to high performance I/O bus506; in addition, in some implementations only a single bus may exist with the components ofhardware system500 being coupled to the single bus. Furthermore, additional components may be included insystem500, such as additional processors, storage devices, or memories.
• In one embodiment, the compiling and assembling of instructions according to the present invention is implemented as a series of software routines run byhardware system500 ofFIG. 5. In this embodiment,compiler110 andassembler120 ofFIG. 1 are each implemented as a series of software routines. These software routines comprise a plurality or series of instructions to be executed by a processor in a hardware system, such asprocessor502 ofFIG. 5. Initially, the series of instructions are stored on a storage device, such asmass storage520. It is to be appreciated that the series of instructions can be stored using any conventional storage medium, such as a diskette, CD-ROM, magnetic tape, DVD, laser disk, ROM, flash memory, etc. It is also to be appreciated that the series of instructions need not be stored locally, and could be received from a remote storage device, such as a server on a network, via network/communication interface524. The instructions are copied from the storage device, such asmass storage520, intomemory514 and then accessed and executed byprocessor502. In one implementation, these software routines are written in the C++ programming language. It is to be appreciated, however, that these routines may be implemented in any of a wide variety of programming languages.
• FIG. 6 is a block diagram illustrating a device on which one embodiment of the present invention can be implemented. Thedevice600 is meant to represent a wide variety of devices in which embodiments of the present invention can be implemented, including conventional storage media (such as a floppy disk, hard disk, or a random access memory), as well as discrete hardware or firmware. Thedevice600 includes acompiler portion602 and anassembler portion604.Compiler portion602 includes the instructions, to be executed by a processor, for carrying out the process of compiling a high-level language into assembly code, whereasassembler portion604 includes the instructions, to be executed by a processor, for carrying out the process of converting the assembly code into object code.
• According to an alternate embodiment, referred to as “automatic CPU dispatch”, the compiler automatically and dynamically analyzes the source code and customizes the object code for particular processor types. In this embodiment, the compiler analyzes the source code on a code segment by code segment basis to determine whether a performance advantage can be obtained over the non-customized version of the function by customizing the function to a particular processor type. If greater than a threshold performance advantage can be obtained, then the compiler compiles the source code customized for particular processor types in addition to compiling the source code for a “generic” processor. Otherwise, only a “generic”, non-processor-specific compilation is performed.
• This alternate embodiment will now be described with reference toFIGS. 7 through 13.
• FIG. 7 is a flowchart illustrating the steps followed in compiling high-level language when a compiler switch for automatic CPU dispatch is turned off, according to an alternate embodiment of the invention. The automatic CPU dispatch embodiment is implemented by a compiler that analyzes source code written for any of a set of N potential CPU types and, depending upon whether a particular compiler switch is set or turned off, either looks for opportunities to optimize the compiled code to any or all of the set of N potential CPU types, or simply compiles in the normal way, generating generic compiled code that will execute on each CPU of the set of N CPU types.
• If the compiler switch is turned off, as shown inblock700 ofFIG. 7, the compiler analyzes each source code file function-by-function (block710), compiling a generic version of each function (block720) with no CPU-specific optimization. When all functions in the particular source code file have been analyzed (block730), the method returns to block710 and analyzes another source code file, until all source code files have been analyzed (block740), and the compiling method ends.
• FIG. 8 is a flowchart illustrating the steps followed in compiling high-level language when a compiler switch for automatic CPU dispatch is set, according to an alternate embodiment of the invention. If the compiler switch is set, as shown inblock800 ofFIG. 8, the compiler analyzes each source code file function-by-function (block805), and the compiler determines whether there is a performance advantage in customizing a particular source code function to a particular processor type (block810).
• If so, the method generates a dispatch function (block815) that indicates which processor type(s) will execute one or more object code optimizations of the function. For example, if the compiler determines that the function could be performed faster by optimizing object code for the Pentium® III processor and Pentium® II processor than by merely compiling generic object code, the compiler will embed a construct in the compiled code indicating which processors types to test for and which specific compiled code to call for each of those processor types.
• Inblock820, the compiler compiles one or more CPU-specific optimized versions of the function, depending upon how many opportunities for optimization it determined inblock810. The method then proceeds to block825.
• If, inblock810, the compiler found no opportunities for customization, the method proceeds directly to block825. Inblock825, the compiler compiles a generic version of the function that will execute on any processor type in the set of N processor types. In the context of the CPU's described herein, this means that the compiled function can be executed by any CPU from a Pentium® processor to a Pentium® III processor.
• When all functions in the particular source code file have been analyzed (block830), the method returns to block805 and analyzes another source code file, until all source code files have been analyzed (block835), and the compiling method ends.
• FIG. 9 illustrates sample source code segments that can be compiled by an automatic CPU dispatch construct according to an alternate embodiment of the invention. The sample source code segments inFIG. 9 comprise a plurality of source code files, i.e. File_A, File_B, File_C, through File_N, identified by900,930,940, and950 respectively. Each offiles900,930,940, and950 can comprise one or more functions. For example, File_A (900) can comprise Function_A_—1 (910), Function_FOO (915), and Function_A_M (920).
• FIG. 10 illustrates sample assembly code for CPU-dispatch testing that is generated using automatic CPU dispatch according to an alternate embodiment of the invention. As inFIG. 4, the assembly code provides a series of tests for processor types. The tests are performed during execution by checking a value stored at the memory location identified by intel_cpu_indicator (i.e., the intel_cpu_indicator variable). If the test succeeds, then the code jumps to the appropriate address for the beginning of the function for the identified processor type. However, if a test fails, then the code checks for another processor type.
• The operation of the sample assembly code shown inFIG. 10 will be explained below with reference toFIGS. 11-13, each of which will first be briefly described
• FIG. 11 illustrates sample assembly code (1105,1110) optimized for a high performance CPU that is generated using automatic CPU dispatch according to an alternate embodiment of the invention.
• FIG. 12 illustrates sample assembly code (1205,1210) optimized for a medium performance CPU that is generated using automatic CPU dispatch according to an alternate embodiment of the invention.
• FIG. 13 illustrates sample assembly code (1305,1310) with no CPU-specific optimizations that is generated using automatic CPU dispatch according to an alternate embodiment of the invention.
• With reference once again toFIG. 10, the code initially checks withtest1000 to see whether the processor type is a Pentium® III processor. If the processor type is a Pentium® III processor, then thejump instruction1005 transfers program execution to the memory location indicated by Function_FOO_$F (1100), which is the memory address of the section of assembly code for the Function_FOO function customized to the Pentium® III processor (function915 ofFIG. 9). The assembly code for Function_FOO_$F comprises code which has been specifically optimized for, and requires execution on, the Pentium® III processor and indicated generally for illustration purposes by1105 and1110. This assembly code can also be executed on future, higher performance processors, provided that they are backward-compatible with the Pentium® III processor, i.e. they can execute any code that the Pentium® III processor can execute.
• If the processor type is not a Pentium® III processor, the code next checks withtest1010 to see whether the processor type is a Pentium® II processor. If the processor type is a Pentium® II processor, then thejump instruction1015 transfers program execution to the memory location indicated by Function_Foo_$E (1200), which is the memory address of the section of assembly code for the Function_FOO function customized to the Pentium® II processor (function915 ofFIG. 9). The assembly code for Function_FOO_$E comprises code which has been specifically optimized for, and requires execution on, the Pentium® II processor and indicated generally for illustration purposes by1205 and1210. This optimized code can also be executed by CPU types, including future CPU types, which are more advanced than the Pentium® II processor, such as the Pentium® III processor, provided that they are backward-compatible with the Pentium® II processor.
• Thefinal test1020 checks whether the processor type has already been determined. If so, then jump instruction1025 jumps program execution to the memory location indicated by Function_FOO_$B (1300), which is the memory address of the section of assembly code for the non-customized or generic version of Function_FOO, indicated generally for illustration purposes by1305 and1310. This generic code can also be executed by all CPU types, including future CPU types, provided that they are backward-compatible.
• If the processor type is not yet set in the intel_cpu_indicator variable, then a call1030 to the intel_cpu_indicator initialization function located at the address intel_cpu_indicator_init is made. Upon return from the intel_cpu_indicator initialization function, the program execution continues in a jump to testinstruction1000, thereby repeating the process. However, now that the intel_cpu_indicator variable has been initialized, one of the tests for processor type will be successful, and the appropriate version of the object code will be executed, depending upon the processor type.
• As mentioned earlier, the compiler orders the test instructions so that the program execution jumps to the most “advanced” function (that is, the function customized to the most advanced processor architecture) which can be executed by the processor executing the program. Also in one illustrated embodiment, the compiler orders the test instructions in the assembly code such that the highest performance processor is tested for first. This reduces the overhead (the additional tests) of such embodiment of the present invention for higher performance processors. However, alternate embodiments can use different orderings. In one such alternate embodiment, the test instructions are ordered so that the most likely processor to be executing the program is tested for first.
• Embodiments of the present invention can be implemented by a computer-readable medium containing instructions for instructing a processor. The instructions can include analyzing a source code segment, and determining whether generating a customized version of object code for the source code segment to execute on one of several types of processors would provide a performance advantage over generating a non-customized version of object code. If so, the customized version of object code is generated; otherwise, the non-customized version of object code is generated. The computer-readable medium further includes computer instructions that generate a control section that causes one of the versions of object code to be called during execution in accordance with an executing processor's type.
• The computer-readable medium can also include instructions that determine whether generating two or more customized versions of object code to execute on two or more types of processors would provide performance advantages over a non-customized version of object code. If so, the two or more customized versions of object code are generated; otherwise, the non-customized version of object code is generated.
• A control section is generated that causes a first customized version of object code to be called during execution if the executing processor is a first type, and that causes a second customized version of object code to be called during execution if the executing processor is a second type. The control section causes a non-customized version of object code to be called during execution if the executing processor is neither the first or second type.
• If the first customized version of object code is more advanced than the second customized version of object code, the control section causes the first customized version to be executed if the control section examines the processor type variable and it corresponds to a processor type that can execute either the first or second customized versions of object code.
• It should be noted that, although specific syntax for an embodiment of the present invention is discussed above, alternate embodiments can use variations on this syntax. According to one such alternate embodiment, the empty_function_definition of the cpu_dispatch construct is not empty, rather, it contains the code the user wishes for the compiler to make processor-specific. The compiler generates a different piece of object code for each of the different processors, based on the code of the cpu_dispatch construct. Each of these different pieces of code is optimized by the compiler for the particular processor types (e.g., by setting of specific compiler switches).
• Various examples of processor types are given in the discussions above. Although different Intel-architecture processors are discussed, embodiments of the present invention may also be used to customize code for processors made by different manufacturers or for different processor types of another manufacturer.
• Additionally, embodiments of the present invention are discussed above with reference to the C or C++ programming language. In alternate embodiments, the processor-specific and dispatch constructs are provided in other programming languages, such as PASCAL, Fortran, Java, etc.
• Furthermore, other modifications can be made bycompiler110 to further enhance the processor-specific customization of embodiments of the present invention. In an alternate embodiment, one such customization is the setting and clearing of particular processor optimization switches. In this embodiment, when compiling the cpu_dispatch and cpu_specific constructs, additional switches or compiler options are set by the compiler which correspond to the processor type of the function being compiled (as identified by the cpu_specific construct). These additional switches and/or compiler options cause the compiler to further customize the source code generated for the particular processor type.
• In addition, embodiments of the invention can be implemented by any suitable processor or other type of computational circuit, such as but not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLW) microprocessor, a graphics processor, a digital signal processor, an application-specific integrated circuit (ASIC), or any other type of processor or processing circuit, or combination thereof.
• Thus, embodiments of the present invention support multiple processor-specific code segments in a single executable. In one embodiment, the present invention allows a programmer to write multiple different code segments, each customized to a particular type of processor, yet each advantageously having the same identifier. During program execution, the proper customized code segment is advantageously selected based on the type of processor that is executing the program.
• Additionally, in another embodiment, the present invention allows a programmer to write a single code segment and advantageously have that single code segment analyzed and customized to different object code versions, executable by different processor types, automatically by the compiler. Again, during program execution, the proper customized code segment is advantageously selected based on the type of processor that is executing the program. When a new processor type is released that has new and/or different instructions, source code programs do not have to be rewritten. Instead, a simple re-compilation is all that is necessary, assuming that a new compiler supports the desired instructions.
• One significant advantage of embodiments of the present invention is that they enable independent software vendors (ISVs) to take advantage of different high performance instructions available on different types of processors while simultaneously allowing them to generate applications that can be executed on several types of processors. ISVs are more likely to take advantage of new instructions, because their application code is readily portable.
• Thus, a method and apparatus for supporting and/or generating multiple processor-specific code segments in a single executable have been described. Whereas many alterations and modifications of embodiments of the present invention will be comprehended by a person skilled in the art after having read the foregoing description, it is to be understood that the particular embodiments shown and described by way of illustration are in no way intended to be considered limiting. References to details of particular embodiments are not intended to limit the scope of the claims.
• It is emphasized that the Abstract is provided to comply with 37 C.F.R. §1.72(b) requiring an Abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
• In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate preferred embodiment.

Claims (25)

1. A method comprising:

analyzing a source code segment that is to be compiled for execution by any one of a plurality of types of processors;

determining whether generating a customized version of object code for the source code segment to execute on a particular one of the plurality of types of processors would provide a performance advantage over generating a non-customized version of object code; and

if so, generating the customized version of object code.

2. The method ofclaim 1 further comprising:

generating a non-customized version of object code that can be executed by more than one type of processor.

3. The method ofclaim 2 further comprising:

generating a control section to examine a processor variable and to cause a version of object code to be called during execution in accordance with an executing processor's type, and wherein the control section examines the processor variable.

4. The method ofclaim 1 wherein, in determining, a determination is made whether generating two or more customized versions of object code to execute on two or more types of processors would provide performance advantages over a non-customized version of object code; and

if so, generating the two or more customized versions of object code and a non-customized version of object code.

5. The method ofclaim 4 further comprising:

generating a control section that causes a first customized version of object code to be called during execution if the executing processor is a first type, the control section causing a second customized version of object code to be called during execution if the executing processor is a second type, and the control section causing the non-customized version of object code to be called during execution if the executing processor is neither the first or second type.

6. The method ofclaim 5 wherein the first customized version of the object code is more advanced than the second customized version of object code, and wherein the control section causes the first customized version of object code to be executed if the processor type variable corresponds to a processor type that can execute either the first or second customized versions of object code.

7. A system comprising:

a bus coupling elements of the system;

a memory coupled to the bus to store instructions; and

a processor coupled to the bus, the processor to execute instructions to perform operations comprising:

analyzing a source code segment that is to be compiled for execution by any one of a plurality of types of processors;

determining whether generating a customized version of object code for the source code segment to execute on a particular one of the plurality of types of processors would provide a performance advantage over generating a non-customized version of object code; and

if so, generating the customized version of object code.

8. The system ofclaim 7 wherein the operations further comprise the operation of generating a non-customized version of object code that can be executed by more than one type of processor.

9. The system ofclaim 7 wherein the operations further comprise the operation of generating a control section to examine a processor type variable, the control section to cause a version of object code to be called during execution in accordance with an executing processor's type.

10. A processor to execute a compiler program to perform operations comprising:

analyzing a source code segment that is to be compiled for execution by any one of a plurality of types of processors;

determining whether generating a customized version of object code for the source code segment to execute on a particular one of the plurality of types of processors would provide a performance advantage over generating a non-customized version of object code; and

if so, generating the customized version of object code.

11. The compiler program ofclaim 10 further comprising the operation of generating a non-customized version of object code that can be executed by more than one type of processor.

12. The compiler program ofclaim 11 further comprising the operation of generating a control section that causes one of the versions of object code to be called during execution in accordance with an executing processor's type.

13. The compiler program ofclaim 10 wherein, in determining, a determination is made whether generating two or more customized versions of object code to execute on two or more types of processors would provide performance advantages over a non-customized version of object code; and

if so, the compiler program generates the two or more customized versions of object code.

14. The compiler program ofclaim 13 wherein the compiler program further comprises the operation of generating a non-customized version of object code that can be executed by more than one type of processor.

15. The compiler program ofclaim 14 wherein the compiler program further comprises the operation of generating a control section that causes a first customized version of object code to be called during execution if the executing processor is a first type, the control section causing a second customized version of object code to be called during execution if the executing processor is a second type, and the control section causing the non-customized version of object code to be called during execution if the executing processor is neither the first or second type.

16. The compiler program ofclaim 15 wherein the control section examines a processor type variable.

17. The compiler program ofclaim 16 wherein the first customized version of the object code is more advanced than the second customized version of object code, and wherein the control section causes the first customized version of object code to be executed if the processor type variable corresponds to a processor type that can execute either the first or second customized versions of object code.

18. An article comprising a computer-accessible medium having associated instructions, wherein the instructions, when accessed, result in a machine performing a method comprising:

analyzing a source code segment that is to be compiled for execution by any one of a plurality of types of processors;

determining whether generating a customized version of object code for the source code segment to execute on a particular one of the plurality of types of processors would provide a performance advantage over generating a non-customized version of object code; and

if so, generating the customized version of object code.

19. The article ofclaim 18 wherein the method further comprises generating a non-customized version of object code.

20. The article ofclaim 19 wherein the non-customized version of object code can be executed by more than one type of processor.

21. The article ofclaim 20 wherein the method further comprises generating a control section that causes one of the versions of object code to be called during execution in accordance with an executing processor's type.

22. The article ofclaim 18 wherein the determining further comprises determining whether generating two or more customized versions of object code to execute on two or more types of processors would provide performance advantages over a non-customized version of object code; and

if so, generating the two or more customized versions of object code.

23. The article ofclaim 22 wherein the method further comprises generating a non-customized version of object code.

24. The article ofclaim 23 wherein the method further comprises:

generating a control section to examine a processor type variable and to cause a first customized version of object code to be called during execution if the executing processor is a first type, the control section causing a second customized version of object code to be called during execution if the executing processor is a second type, and the control section causing the non-customized version of object code to be called during execution if the executing processor is neither the first or second type.

25. The article ofclaim 24 wherein the first customized version of the object code is more advanced than the second customized version of object code, and wherein the control section causes the first customized version of object code to be executed if the processor type variable corresponds to a processor type that can execute either the first or second customized versions of object code.

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