US20080023805A1 - Array-Processed Stacked Semiconductor Packages - Google Patents

Abstract

One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (1412, 1422,etc.), which adheres to the substrate, embeds the connected components. Metal posts (1431, 1432, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

Description

FIELD OF THE INVENTION
• The present invention is related in general to the field of semiconductor devices and processes, and more specifically to array-processed stacked semiconductor packages creating 3-dimensionally interconnected chips.
DESCRIPTION OF THE RELATED ART
• The long-term trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's “law”) has several implicit consequences. First, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Second, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. Third, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly.
• As for the challenges in semiconductor packaging, the major trends are efforts to shrink the outline of a discrete package so that the package consumes less area and less height when it is mounted onto the circuit board, and to reach these goals with minimum cost (both material and manufacturing cost). Recently, another requirement was added to this list, namely the need to design packages so that stacking of chips and/or packages becomes an option to increase functional density and reduce device thickness. Furthermore, it is expected that a successful strategy for stacking chips and packages would shorten the time-to-market of innovative products, which utilize available chips of various capabilities (such as processors and memory chips) and would not have to wait for a redesign of chips.
• Recent applications especially for hand-held wireless equipments, combined with ambitious requirements for data volume and high processing speed, place new, stringent constraints on the size and volume of semiconductor components used for these applications. Consequently, the market place is renewing a push to shrink discrete semiconductor devices both in two and in three dimensions, and this miniaturization effort includes packaging strategies for semiconductor devices as well as electronic systems.
SUMMARY OF THE INVENTION
• Applicants recognize the need for a fresh concept of achieving a coherent, low-cost method of assembling high lead count, yet low contour devices. The concept includes substrates and packaging methods for stacking devices and package-on-package options as well as assembly options for flip-chip and wire bond interconnections. The device can be the base for a vertically integrated semiconductor system, which may include integrated circuit chips of functional diversity and passive components. The resulting system should have excellent electrical performance, especially speed, and high product reliability. Further, it will be a technical advantage that the fabrication method of the system is flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations.
• One embodiment of the invention is a semiconductor system of arrays of packaged devices. Each array includes a sheet-like substrate made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chip, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound, which adheres to the substrate, embeds the connected components. Metal posts traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.
• In another embodiment of the invention, the system includes a distribution of the encapsulation compound so that the compound thickness over the components is about equal to the substrate thickness. A balanced distribution of insulators is thus created, which and thus an overall system with a high degree of robustness against thermomechanical stress and distortion.
• Another embodiment of the invention is a method for fabricating a semiconductor system, in which arrays of semiconductor packages are processed and then stacked to produce a 3-dimensional system of packaged components. The system can be sawed into individual stacks of packaged devices. The method starts with a substrate such as a laminate tape with metal traces patterned on the top layer. A chip is attached to the top layer; the attachment may be performed by flip-chip technique, or by wire bonded technique. In the flip-chip version, metal posts are built up on suitable pads on the top substrate layer; the posts need to be high enough to allow connection to the next package layer to be stacked. In the wire bond version, wire loops are created on the top chip layer in addition to metal posts; these loops need to be high enough to allow connection to the next package layer to be stacked. The wire bond option allows direct chip connect to the upper stacked package.
• The assembly is then overmolded so that the mold compound reaches about the same thickness as the height of the posts and wire bonds and loops. The posts and bond wires are exposed using a post mold etch (wet or dry) or a polishing procedure. For the exposed wire bond version, s landing pad is deposited on the exposed wire to enable the package interconnect; the pad can also be used for routing. The molding step can be performed so that a balanced distribution of compound is achieved. The balanced stack option yields a mechanically resilient solution for the package stacks.
• The array is bonded to the next array using solder attachment on the metallization (alternatively, thermo-compression bonding may be used). The reflow of multiple stacked packages occurs at one time for the whole array. To enhance the strength of the package, the substrate (laminate tape) can be glued or bonded to a mold cap; a mask protecting the posts/bondwires would be required for this step. Between two package levels, a single ground plane can be shared.
• The technical advances represented by certain embodiments of the invention will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 shows a schematic cross section of a portion of an array including a semiconductor component flip-assembled on a substrate and embedded in encapsulation compound, which is traversed by metal posts.
• FIG. 2 depicts the schematic array portion ofFIG. 1 for the case of equal thicknesses of the substrate and the encapsulation compound on top of the component.
• FIG. 3 shows a schematic top view of the array portion ofFIG. 1 along the cut line A-A.
• FIG. 4 shows a schematic top view of the array portion ofFIG. 1 along the cut line B-B.
• FIG. 5 is a schematic cross section of a stacked system of arrays including units assembled in the manner as illustrated inFIG. 1.
• FIG. 6 is a schematic top view of the system shown inFIG. 5.
• FIG. 7 shows a schematic cross section of a portion of an array including a semiconductor component attached to a substrate, wire bonded for electrical connection, and embedded in encapsulation compound, which is traversed by metal posts.
• FIG. 8 shows a schematic top view of the array portion ofFIG. 7 along the cut line A-A.
• FIG. 9 shows a schematic top view of the array portion ofFIG. 7 along the cut line B-B.
• FIG. 10 is a schematic cross section of a stacked system of arrays including units assembled in the manner as illustrated inFIG. 7.
• FIG. 11 illustrates a schematic cross section of a stacked system of arrays including units with semiconductor components of different sizes or thicknesses.
• FIG. 12 depicts a schematic cross section of a balanced stacked system of arrays.
• FIG. 13 shows a schematic cross section of a stacked system of arrays, which share an electrical ground plane.
• FIG. 14 illustrates a schematic cross section of a stacked system of arrays, wherein the arrays include semiconductor components of different sizes or thicknesses and of different assembly techniques.
• FIG. 15 shows a schematic cross section of a portion of an array including a stack of two semiconductor components; the first component is flip-assembled on a substrate and the second component is wire bonded to the substrate; the stack is embedded in encapsulation compound, which is traversed by metal posts.
• FIG. 16 shows a schematic top view of the array portion ofFIG. 15 along the cut line A-A.
• FIG. 17 shows a schematic top view of the array portion ofFIG. 15 along the cut line B-B.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• FIG. 1 illustrates a portion, generally designated100, of an array shown more fully inFIG. 5. Actually it is, inFIG. 5, the first array of several arrays, which together form a semiconductor system. The first array consists of one or more assembly sites as depicted inFIG. 1; inFIG. 5, each array includes four assembly sites; arrays with considerably higher number of assembly sites can be manufactured. In addition, the sites may be arranged in x-direction as well as in y-direction; the number of sites may be different in x- and y-direction.
• The assembly site depicted inFIG. 1 shows asubstrate101, which has afirst surface101aand asecond surface101b. The substrate is preferably made of a sheet-like insulating material such as polyimide- and/or epoxy-based compounds and has athickness101cin the range from about 10 to 1000 μm. Betweensurfaces101aand101barelayers102 of conductive horizontal lines (preferably copper), and extending fromsurfaces101ato surface101bis a network of conductive vertical vias103 (preferably copper).
• Substrate101 has on thefirst surface101atwo sets of terminals. Theterminals104 of the first set are attachment sites and have a metallurgical surface composition suitable for metallic connection such as solder bumps or gold studs. A preferred surface composition is a layer of nickel with a top layer of palladium or gold.Substrate101 further has a second set ofterminals105 on thefirst surface101a, and a third set ofterminals106 on thesecond surface101b. Preferred metal forterminals105 and106 is copper;terminals106 are suitable for attachment of solder bodies.
• InFIG. 1, asemiconductor component110 with I/O ports111 is flip-attached to the substrate attachment sites (first set terminals104) by means ofconnector bodies112, preferably metal studs such as gold of copper bumps.Component110 may be a discrete component, an integrated circuit chip, or it may include a passive component such as capacitor, an inductor, or a resistor. Thethickness110aof the component may vary from 10 to 400 μm; thicker or thinner components can be assembled.
• It should be stressed that in an array, the type of chips, the size of the chips, and the thickness of the chips may vary from assembly site to assembly site; consequently, one assembly site may have an integrated circuit, the adjacent site a passive component, the next site a silicon controlled rectifier, etc.
• Component110 is attached ontosubstrate101 by the flip-chip technique, active face down.FIG. 1 also shows an example of anelectrical connection113 from thecomponent110 tosubstrate terminals105 onfirst surface101a.
• On at least portions of thesecond set terminals105 on thefirst substrate surface101aaremetal posts130, preferably made of copper or a copper alloy. The location of the posts matches at least portions of thethird set terminals106 on thesecond substrate surface101b.Posts130 are preferably about vertical to thefirst substrate surface101aand have aheight130ataller than thecomponent thickness110a. The posts serve the vertical electrical connectivity and have, therefore, a diameter sufficiently wide to keep losses from inductive and capacitive resistance minimal. The posts rest onterminals105; on the top end, the posts are capped bypads131.
• InFIG. 1,encapsulation compound120 adheres tofirst substrate surface101aand embeds the connectedcomponent110. Thethickness121 of the compound is preferably at least equal to, but more preferably greater than the sum of the thicknesses of component, connectors, and terminals;thickness121 is about equal to postheight130a. Preferably, theencapsulation material120 is an epoxy-based molding compound, which is processed by the transfer molding technique.
• The most preferable structure has anencapsulation compound thickness122 on top of thecomponent110 about equal to thethickness201cofsubstrate201.FIG. 2 illustrates an embodiment with this “balanced distribution” of polymers (encapsulation compound and insulating substrate). Experience has shown that a balanced distribution of polymers embedding a semiconductor component contributes to equalize compressive stress on the component and to yield a mechanically resilient array structure.
• Referring now toFIG. 1, attached topads131 arereflow metal bodies140, preferably made of tin or a tin alloy. These reflowbodies140 have a first reflow temperature and interconnect the first array with other arrays. After the assembly of all arrays into the semiconductor system,reflow bodies150 may be attached toterminals106 on thesecond substrate surface101b. The reflow temperature ofbodies150 is lower than the reflow temperature ofbodies140.
• A cross section along cut line A-A inFIG. 1 will provide a top view as illustrated inFIG. 3. The rows ofpads131 are shown in x- and y-direction. A cross section along cut line B-B inFIG. 1 will provide a bottom view as illustrated inFIG. 4. The rows ofposts130 are shown in x- and y-direction. In addition, the two-dimensional array ofmetal studs112 on I/O ports111 are indicated as round entities.
• The first array of the embodiment under discussion is composed of units as described inFIG. 1. A complete array composed of 4 such units is illustrated inFIG. 5 in a simplified manner; the array is designated501. The array has the same type component flip-assembled in each of the four units. In other embodiments, components for different sizes, thicknesses, and device types may be assembled as an array (an embodiment using different assembly technique is shown inFIG. 11).
• Asecond array502 of packaged devices is structured analogous toarray501, based on units assembled as shown inFIG. 1. The array has a sheet-like substrate511 with athird surface511aand afourth surface511b, and terminals on the both surfaces. Theterminals512 on the fourth surface match the pads131 (covered with reflow metal) of thefirst array501.
• Thesecond array502 is aligned and connected with thefirst array501 at thematching terminals512 and131 to form a 3-dimensional system of packaged devices.
• A third array to an n^tharray of packaged devices has a structure analogous to the structure ofarray502 and501. InFIG. 5, these arrays are designated503,504,505, and506. These arrays have reflow metal of the same reflow temperature on all pads. After alignment, the reflow metals of all arrays are thus connected in one process step (see below). The result is a 3-dimensional system of packaged devices. In the side view ofFIG. 5, 4 devices in the x-direction and 6 devices in the y-direction are shown. Taking a top view of thepads531 on the metal posts oftop array506 deliversFIG. 6. In the top view ofFIG. 6, 4 devices in the x-direction and 4 devices in the z-direction are shown. Combining the views ofFIG. 5 andFIG. 6 indicates that the complete 3-dimensional system includes 4×6×4=96 packaged devices.
• In the embodiment ofFIGS. 5 and 6, the devices have identical components; as stated earlier, other embodiments have components of different types, sizes, and thicknesses; see alsoFIG. 11.
• The system ofFIGS. 5 and 6 may be singulated into vertical stacks of devices. Preferably using a saw, a cut alongline540 singulates astack541 including 1×6×4=24 packaged devices. A cut alongline550 singulates another stack of 1×6×4=24 packaged devices. The remainingstack561 includes 2×6×4=48 packaged devices.
• Another embodiment of the invention is depicted inFIGS. 7 to 14.FIG. 7 illustrates a portion, generally designated700, of a first array shown more fully inFIG. 10. Actually it is, inFIG. 10, the first array of several arrays, which together form a semiconductor system. The first array consists of one or more assembly sites as depicted inFIG. 7; inFIG. 10, each array includes four assembly sites; arrays with considerably higher number of assembly sites can be manufactured. In addition, the sites may be arranged in x-direction as well as in y-direction; the number of sites may be different in x- and y-direction.
• The assembly site depicted inFIG. 7 shows asubstrate701, which has afirst surface701aand asecond surface701b. The substrate is preferably made of a sheet-like insulating material such as polyimide- and/or epoxy-based compounds and has athickness701cin the range from about 10 to 1000 μm. Betweensurfaces701aand701barelayers702 of conductive horizontal lines (preferably copper), and extending fromsurfaces701ato surface701bis a network of conductive vertical vias703 (preferably copper).
• Substrate701 may have an array of assembly sites; one of these sites is illustrated inFIG. 7.Substrate701 has on thefirst surface701aachip attachment location704 and two sets of terminals. Theterminals705 of the first set are in proximity ofcomponent710, preferably made of copper and have a metallurgical surface composition suitable for wire bonding (for example gold surface layer).Substrate701 further has a second set ofterminals706 on thefirst surface701a, preferably made of copper and with a metallurgical surface composition for metal post deposition (preferably copper).
• A third, a fourth, and a fifth set of terminals are on thesecond surface701b. Preferred metal for these terminals is copper; they are suitable for attachment of solder bodies. The location of thethird set terminals707 match themetal posts730; the location of thefourth set terminals708 match thecontact pads732 on the wire span tops; and the location of thefifth set terminals709 match thecontact pads733 on the wire loop tops.
• InFIG. 7, asemiconductor component710 has anactive surface710a, apassive surface710b, and athickness710c.Component710 is attached with itspassive surface710bontosubstrate attachment location704. On theactive surface710a, the component has a first set of I/O ports711, which serve as bond pads for the wire spans, and a second set of I/O ports712, which serve as bond pads for the wire loops.Component710 may be a discrete component, an integrated circuit chip, or it may include a passive component such as capacitor, an inductor, or a resistor. Thethickness710cof the component may vary from 10 to 400 μm; thicker or thinner components can be assembled.
• FIG. 7 shows two modes of electrical connection forcomponent710. Bond wire spans713 connect thefirst set ports711 with the respectivefirst set terminals705. The wire spans reach a certain height over the active component surface.Bond wire loops714 are on eachsecond set port712. The tops of allloops714 are in the same plane as the tops of the wire spans713; theloops714 reach the same height over the active component surface as the wire spans713.
• On at least portions of thesecond set terminals706 on thefirst substrate surface701aaremetal posts730, preferably made of copper or a copper alloy. The location of the posts matches thethird set terminals707 on thesecond substrate surface701b.Posts730 are preferably about vertical to thefirst substrate surface701aand have aheight730ataller than the sum of thecomponent thickness710cand the wire loop height. The posts serve the vertical electrical connectivity and have, therefore, a diameter sufficiently wide to keep losses from inductive and capacitive resistance minimal. The posts rest onterminals706; on the top end, the posts are capped bypads731. These pads match the locations of thethird set terminals707 on thesecond substrate surface701b.
• In addition, the tops of the wire spans and the wire loops have contact pads. InFIG. 7,pads732, contacting the wire span tops, match the locations of thefourth set terminals708;pads733, in contact with the wire loop tops, match thefifth set terminals709.
• InFIG. 7,encapsulation compound720 adheres tofirst substrate surface701aand embeds the connectedcomponent710. Thethickness721 of the compound is about equal to postheight730a. Preferably, theencapsulation material720 is an epoxy-based molding compound, which is processed by the transfer molding technique.
• The most preferable structure has anencapsulation compound thickness722 on top of theactive surface710aofcomponent710 about equal to thethickness701cofsubstrate701. Experience has shown that a “balanced distribution” of polymers (encapsulation compound and insulating substrate) embedding a semiconductor component contributes to equalize compressive stress on the component and to yield a mechanically resilient array structure.
• Attached topads731 arereflow metal bodies740, preferably made of tin or a tin alloy. These reflowbodies740 have a fist reflow temperature and interconnect the first array with other arrays. After the assembly of all arrays into the semiconductor system,reflow bodies750 may be attached toterminals707,708, and709 on thesecond substrate surface701b. The reflow temperature ofbodies750 is lower than the reflow temperature ofbodies740.
• A cross section along cut line A-A inFIG. 7 provides a top view as illustrated inFIG. 8. The rows ofposts730 are shown in x- and y-direction. A cross section along cut line B-B inFIG. 7 provides a bottom view as illustrated inFIG. 9. The rows offirst set terminals705 andsecond set terminals706 are shown in x- and y-direction.
• The first array of the embodiment under discussion is composed of units as described inFIG. 7. A complete array composed of 4 such units is illustrated inFIG. 10 in a simplified manner; the array is designated1001. The array has the same type component wire-assembled in each of the four units. In other embodiments, components for different sizes, thicknesses, and device types may be assembled as an array (an embodiment is shown inFIG. 11).
• Asecond array1002 of packaged devices is structured analogous toarray1001, based on units assembled as shown inFIG. 7.Array1002 has a sheet-like substrate1011 with athird surface1011aand afourth surface1011b, and terminals on the both surfaces. Theterminals1012 on the fourth surface match thepads731,732, and733 (covered with reflow metal, seeFIG. 7) of thefirst array1001.
• Thesecond array1002 is aligned and connected with thefirst array1001 at thematching terminals1012 and731,732, and733 to form a 3-dimensional system of packaged devices.
• A third array to an n^tharray of packaged devices has a structure analogous to the structure ofarray1002 and1001. InFIG. 10, these arrays are designated1003,1004,1005,1006, and1007. These arrays have reflow metal of the same reflow temperature on all pads. After alignment, the reflow metals of all arrays are thus connected in one process step (see below). The result is a 3-dimensional system of packaged devices. In the side view ofFIG. 10, 4 devices in the x-direction and 7 devices in the y-direction are shown.
• In the embodiment ofFIG. 10, the devices have identical components; as stated earlier, other embodiments have components of different types, sizes, and thicknesses. An example of these embodiments is illustrated inFIG. 11.Arrays1101,1102,1104,1105, and1106 includecomponents1110 of equal size and thickness, assembled by bond wires; the device type may be different, however.Arrays1103 and1107 includecomponents1110,1111,1112 of different size and thickness, assembled by wire bonds.
• The systems ofFIGS. 10 and 11 may be singulated into vertical stacks of devices. Preferably using a saw, a cut alongline1040 inFIG. 10 andline1140 inFIG. 11 singulates a stack of packaged devices. InFIG. 10, the stack is designated1041; it includes 1×7×1=7 packaged devices under the assumption that there is only 1 device in the z-direction. InFIG. 11, the stack is designated1141; it includes 1×7×1=7 packaged devices under the assuming that there is only one device in the z-direction. The remaining stacks inFIG. 10 andFIG. 11 include 3×7×1=21 packaged devices each.
• The schematic and simplifiedFIG. 12 illustrates another embodiment of array-processed stacked semiconductor packages, which emphasizes the balancing of the stack for a mechanically resilient stack-up solution. Insubassembly1201, three arrays of packaged devices are assembled as a system using the method described inFIG. 10. Similarly, insubassembly1202, three arrays of packaged of packaged devices are assembled as a system using the process described inFIG. 10. Then,subassembly1202 is flipped relative tosubassembly1201 and soldered ontosubassembly1201, using the matchingreflow bodies1210. As pointed out above, the reflow temperature ofbodies1210 is lower than the reflow temperature of the reflow bodies used earlier in the assembly of the subassemblies; see description forFIG. 10. A cut alongline1220singulates stack1230. This stack exhibits carefully balanced mechanical characteristics for resiliency and stress robustness.
• FIG. 13 depicts an embodiment, in which asingle ground plane1301 is shared by two or more array-assembled packages in a stack. As an example, after singulating thestack1310 from the assembled arrays along cut-line1320, theground plane portion1301aserves the seven packaged devices ofstack1310.
• FIG. 14 illustrates another embodiment, generally designated1400, of the invention. In this example, thearrays1401,1402,1403, and1404 (containing four units each) have been processed by wire bonding as described inFIG. 7, andarray1405 has been processed by flip-chip technique as described inFIG. 1. Each array includes a sheet-like substrate (1411,1412, etc.); the components may include one or more active or passive chips, or chips of different sizes. Encapsulation compound (1412,1422, etc.), which adheres to the substrate, embeds the connected components. Metal posts (1431,1432, etc.) traverse the encapsulation compound vertically. By means of the matching contact pads, all five arrays have been stacked by reflow assembly as a 3-dimensional system. Cutting alongline1440, astack1450 may be singulated. This stack includes a system of devices using mixed assembly technologies, wire bonding and flip-chip assembly, and also mixed component sizes.
• Another embodiment of the invention involving mixed assembly technologies is depicted inFIGS. 15 to 17. This embodiment concerns a stack of two or more chips, which are assembled by flip-chip as well as wire bonding techniques.FIG. 15 illustrates a portion, generally designated1500, of an array. The assembly site depicted inFIG. 15 shows asubstrate1501, which has afirst surface1501aand asecond surface1501b. The substrate is preferably made of a sheet-like insulating material such as polyimide- and/or epoxy-based compounds and has athickness1501cin the range from about 10 to 1000 μm. Betweensurfaces1501aand1501barelayers1502 of conductive horizontal lines (preferably copper), and extending fromsurfaces1501atosurface1501bis a network of conductive vertical vias1503 (preferably copper).
• Substrate1501 may have an array of assembly sites; one of these sites is illustrated inFIG. 15.Substrate1501 has on thefirst surface1501athree set of terminals. Theterminals1504 of the first set are component attachment sites, preferably copper, and have a metallurgical surface composition suitable for metallic connection such as solder bumps or gold studs (preferably nickel with a top layer of palladium or gold).Terminals1505 of the second set are in proximity ofcomponent1510, preferably made of copper and have a metallurgical surface composition suitable for wire bonding (for example gold surface layer).Substrate1501 further has a third set ofterminals1506 on thefirst surface1501a, preferably made of copper and with a metallurgical surface composition for metal post deposition (preferably copper).
• A fourth, a fifth, and a sixth set of terminals are on thesecond surface1501b. Preferred metal for these terminals is copper; they are suitable for attachment of solder bodies. The location of thefourth set terminals1507 match themetal posts1530; the location of thefifth set terminals1508 match thecontact pads1532 on the wire span tops; and the location of thesixth set terminals1509 match thecontact pads1533 on the wire loop tops.
• InFIG. 15, afirst semiconductor component1510 has an active surface with I/O ports1511, a passive surface, and athickness1510c.Component1510 is flip-attached with its active surface onto the substrate attachment sites (first set terminals1504) by means ofconnector bodies1512, preferably metal studs such as gold or copper bumps.Component1510 may be a discrete component, an integrated circuit chip, or a passive component.Thickness1510cmay vary from 10 to 400 μm; thicker or thinner components can be assembled.
• Asecond semiconductor component1560 has anactive surface1560awith a first and second set of I/O ports, apassive surface1560b, and athickness1560c. The first set of I/O ports1561 serves as bond pads for the wire spans, and the second set of I/O ports1562 serves as bond pads for the wire loops.Component1560 may be a discrete component, an integrated circuit chip, or it may be a passive component. Thethickness1560cof the component may vary from 10 to 400 μm; thicker or thinner components can be assembled.
• Thepassive surface1560bof thesecond component1560 is adhesively attached to the passive surface of thefirst component1510.
• FIG. 15 shows two modes of electrical connection for the components.Component1510 is flip-attached andcomponent1560 is connected by wire bonds. Bond wire spans1563 connect thefirst set ports1561 with the respective first set terminals1605. The wire spans reach a certain height over the active component surface.Bond wire loops1564 are on eachsecond set port1562. The tops of allloops1564 are in the same plane as the tops of the wire spans1563; theloops714 reach the same height over the active component surface as the wire spans1563.
• On at least portions of thethird set terminals1506 on thefirst substrate surface1501aaremetal posts1530, preferably made of copper or a copper alloy. The location of the posts matches thefourth set terminals1507 on thesecond substrate surface1501b.Posts1530 are preferably about vertical to thefirst substrate surface1501aand have aheight1530ataller than the sum of thecomponent thicknesses1510cand1560c, and the wire loop height. The posts serve the vertical electrical connectivity and have, therefore, a diameter sufficiently wide to keep losses from inductive and capacitive resistance minimal. The posts rest onterminals1506; on the top end, the posts are capped bypads1531. These pads match the locations of thefourth set terminals1507 on thesecond substrate surface1501b.
• In addition, the tops of the wire spans and the wire loops have contact pads. InFIG. 15,pads1532, contacting the wire span tops, match the locations of thefifth set terminals1508;pads1533, in contact with the wire loop tops, match thesixth set terminals1509.
• InFIG. 15,encapsulation compound1520 adheres tofirst substrate surface1501aand embeds theconnected components1510 and1560. Thethickness1521 of the compound is about equal to postheight1530a. Preferably, theencapsulation material1520 is an epoxy-based molding compound, which is processed by the transfer molding technique. The most preferable structure has anencapsulation compound thickness1522 on top of theactive surface1560aofcomponent1560 about equal to thethickness1501cofsubstrate1501.
• Attached topads1531 arereflow metal bodies1540, preferably made of tin or a tin alloy. Thesereflow bodies1540 have a fist reflow temperature and interconnect a first array with other arrays. After the assembly of all arrays into the semiconductor system,reflow bodies1550 may be attached toterminals1507,1508, and1509 on thesecond substrate surface1501b. The reflow temperature ofbodies1550 is lower than the reflow temperature ofbodies1540.
• A cross section along cut line A-A inFIG. 15 provides a top view as illustrated inFIG. 16. The rows ofposts1530 are shown in x- and y-direction. A cross section along cut line B-B inFIG. 15 provides a bottom view as illustrated inFIG. 17. The rows ofposts1530 are shown in x- and y-direction. In addition, the two-dimensional array ofmetal studs1512 on I/O ports1511 are indicated as round entities.
• Another embodiment of the invention is a method for fabricating a semiconductor system as illustrated inFIGS. 5 and 6. The method includes the steps for fabricating a first array of packaged devices exemplified inFIGS. 1 and 2, which includes the steps of:
• providing a sheet-like substrate with a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;
• forming an array of assembly sites on the first surface, each site including a first and a second set of terminals on the first surface, and a third set of terminals on the second surface;
• providing semiconductor components with a thickness and I/O ports;
• flip-attaching a component to each assembly site using metal studs for interconnecting the component ports to the first set terminals;
• forming metal posts at least on portions of the second set terminals, the posts being about vertical to the first surface and having a height taller than the component thickness, the post locations matching at least portions of the terminals on the second surface;
• embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound with a thickness at least equal to the post height;
• exposing the top surface of the posts;
• depositing pads on each exposed post surface; and
• depositing reflow metal of a certain reflow temperature on the pads.
• The method then continues by fabricating a second array of packaged devices using the same steps as fabricating the first array. The substrate of the second array has a third and a fourth surface; the terminals on the fourth surface match the reflow metal-covered pads of the first array; and the reflow metal has the same reflow temperature as for the first array.
• In the next step, a semiconductor system is assembled by aligning and contacting the terminals on the fourth surface of the second array with the reflow metal-covered pads of the first array; and then applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array.
• In an optional process step, the assembled arrays can be sawed vertically to singulate individual stacks of packaged devices.
• Another embodiment of the invention is a method for fabricating a semiconductor system as illustrated inFIGS. 10 to 14. The method includes the steps for fabricating a first array of packaged devices exemplified inFIG. 7, which includes the steps of:
• providing a sheet-like substrate with a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;
• forming an array of assembly sites, each site including a component attach location, a first and a second set of terminals on the first surface, and a third, a fourth, and a fifth set of terminals on the second surface;
• providing semiconductor components with a thickness, an active surface with a first and a second set of I/O ports, and a passive surface;
• attaching the passive surface of a component to each substrate attachment location;
• forming spans of bond wire to electrically connect the first set ports to the first set terminals, the top of all spans in a plane;
• forming loops of bond wire on the second set ports, the top of all loops in the same plane as the span tops;
• forming metal posts on the second set terminals to match the locations of the third set terminals, the posts being about vertical to the first surface and having a height to reach the plane of the wire span tops and wire loop tops;
• embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound with a thickness at least equal to the post height;
• exposing the top surface of the posts, the wire loops, and the wire spans;
• depositing a pad on the surface of each exposed top of posts, wire spans, and wire loops, the pads on the wire span tops matching the locations of the fourth set terminals, the pads on the wire loop tops matching the locations of the fifth set terminals; and
• depositing reflow metal of a certain reflow temperature on the pads.
• The method then continues by fabricating a second array of packaged devices using the same steps as fabricating the first array. The substrate of the second array has a third and a fourth surface; the terminals on the fourth surface match the reflow-metal covered pads of the first array; and the reflow metal has the same reflow temperature as in the first array.
• In the next step, a semiconductor system is assembled by aligning and contacting the terminals on the fourth surface of the second array with the reflow metal-covered pads of the first array; and then applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array.
• In an optional process step, the assembled arrays can be sawed vertically to singulate individual stacks of packaged devices.
• Another embodiment of the invention is a method for fabricating a semiconductor system, which includes the steps for fabricating a first array of packaged devices exemplified inFIG. 15:
• providing a sheet-like substrate with a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;
• forming an array of assembly sites, each site including a first, a second, and a third set of terminals on the first surface, and a fourth, a fifth, and a sixth set of terminals on the second surface;
• providing first semiconductor components with a first thickness, an active surface with I/O ports, and a passive surface;
• flip-attaching a first component to each assembly site using metal studs for interconnecting the ports to the first set terminals;
• providing second semiconductor components with a second thickness, an active surface with a first and a second set of I/O ports, and a passive surface;
• attaching the passive surface of a second component to the passive surface of each first component;
• forming spans of bond wire to electrically connect the first set ports to the second set terminals, the top of all spans in a plane;
• forming loops of bond wire on the second set ports, the top of all loops in the same plane as the span tops;
• forming metal posts at least on portions of the second set terminals to match the locations of the fourth set terminals, the posts being about normal to the first surface and having a height to reach the plane of the wire span tops and wire loop tops;
• embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound with a thickness at least equal to the post height;
• exposing the top surface of the posts, the wire loops, and the wire spans;
• depositing a pad on the surface of each exposed top of posts, wire spans, and wire loops, the pads on the wire span tops matching the locations of the fifth set terminals, the pads on the wire loop tops matching the locations of the sixth set terminals; and
• depositing reflow metal of a certain reflow temperature on the pads.
• The method then continues by fabricating a second array of packaged devices using the same steps as fabricating the first array. The substrate of the second array has a third and a fourth surface; the terminals on the fourth surface match the reflow-metal covered pads of the first array; and the reflow metal has the same reflow temperature as for the first array.
• In the next step, a semiconductor system is assembled by aligning and contacting the terminals on the fourth surface of the second array with the reflow metal-covered pads of the first array; and then applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array.
• In an optional process step, the assembled arrays can be sawed vertically to singulate individual stacks of packaged devices.
• While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims (34)

1. A semiconductor system comprising:

a first array of packaged devices including:

a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines and vertical vias, attachment sites on the first surface, and terminals on the first and the second surface;

semiconductor components attached to the substrate attachment sites;

electrical connections from the components to substrate terminals on the first surface;

encapsulation compound adhering to the first substrate surface and embedding the connected components;

metal posts traversing the encapsulation compound vertically to connect terminals on the first substrate surface with pads on the encapsulation surface; and

solder bodies attached to the pads;

a second array of packaged devices having a sheet-like substrate with a third and a fourth surface, terminals on the fourth surface matching the solder-covered pads of the first array; and

the second array aligned and connected with the first array at the matching terminals and pads to form a 3-dimensional system of packaged devices.

2. The system according toclaim 1 further including a distribution of the encapsulation compound so that the thickness of the compound over the components is about equal to the thickness of the substrate.

3. The system according toclaim 1 wherein the semiconductor components include chips of active and passive devices, and stacks of chips.

4. The system according toclaim 1 wherein the electrical connections include flip-chip assembly, wire bonds, or both.

5. The system according toclaim 1 wherein the assembled arrays are singulated vertically into stacks of packaged devices.

6. A semiconductor system comprising:

a first array of packaged devices including:

a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;

an array of assembly sites on the first surface, each site including a first and a second set of terminals on the first surface, and a third set of terminals on the second surface;

a semiconductor component, having a thickness and I/O ports, flip-attached to each assembly site using metal studs for interconnecting the chip ports to the first set terminals;

metal posts at least on portions of the second set terminals, the posts being about vertical to the first surface, having a height taller than the component thickness, and matching the locations of the third set terminals;

encapsulation compound adhering to the first substrate surface and embedding the connected components so that the compound has a thickness about equal to the post height;

a pad capping each post; and

reflow metal on the pads, the metal having a first reflow temperature;

a second array of packaged devices having a sheet-like substrate with a third and a fourth surface, terminals on the fourth surface matching the reflow metal covered pads of the first array; and

the second array aligned and connected with the first array at the matching terminals and pads to form a 3-dimensional system of packaged devices.

7. The system according toclaim 6 further including reflow metal bodies on the third set contact pads of the first array, the bodies having a second reflow temperature lower than the first reflow temperature.

8. The system according toclaim 6 further including a thickness of the encapsulation compound over the components about equal to the sheet thickness of the substrate.

9. The system according toclaim 6 wherein the assembled arrays are singulated vertically into stacks of packaged devices.

10. A semiconductor system comprising:

a first array of packaged devices including:

a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;

an array of assembly sites on the first surface, each site including a chip-attachment location, a first and a second set of terminals on the first surface and a third, a fourth, and a fifth set of terminals on the second surface;

a semiconductor component, having a thickness, an active surface with a first and second set of I/O ports, and a passive surface, attached with its passive surface to each attachment location;

a bond wire span with a height between each first set port and the respective first set terminal;

a bond wire loop on each second set port, the loops reaching the same height as the wire spans;

metal posts on the second set terminals, the posts being about vertical to the first surface, having a height taller than the sum of the component thickness and the wire loop height, and matching the locations of the third set terminals;

encapsulation compound adhering to the first substrate surface and embedding the connected components so that the compound has a thickness about equal to the post height;

a pad capping each post, wire span top, and wire loop top, the pads on the wire span tops matching the locations of the fourth set terminals, the pads on the wire loop tops matching the locations of the fifth set terminals; and

reflow metal on the pads, the metal having a first reflow temperature;

a second array of packaged devices having a sheet-like substrate with a third and a fourth surface, terminals on the fourth surface matching the reflow metal covered pads of the first array; and

the second array aligned and connected with the first array at the matching terminals and pads to form a 3-dimensional system of packaged devices.

11. The system according toclaim 10 further including reflow metal bodies on the third, the fourth, and the fifth set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature.

12. The system according toclaim 10 further including a thickness of the encapsulation compound over the components about equal to the sheet thickness of the substrate.

13. The system according toclaim 10 wherein the assembled arrays are singulated vertically into stacks of packaged devices.

14. A semiconductor system comprising:

a first array of packaged devices including:

a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;

an array of assembly sites on the first surface, each site including a first, a second, and a third set of terminals on the first surface, and a fourth, a fifth, and a sixth set of terminals on the second surface;

a first semiconductor component, having a first thickness, an active surface with I/O ports, and a passive surface, flip-attached to each assembly site using metal studs for interconnecting the component ports to the first set terminals;

a second component, having a second thickness, an active surface with a first and a second set of I/O ports, and a passive surface, attached with its passive surface to the passive surface of a first component;

a bond wire span with a height between each first set port and the respective second set terminal;

a bond wire loop on each second set port, the loops reaching the same height as the wire spans;

metal posts at least on portions of the third set terminals, the post being about vertical to the first surface, having a height taller than the sum of the first and second component thicknesses and the wire loop height, and matching the locations of the fourth set terminals;

encapsulation compound adhering to the first substrate surface and embedding the connected components so that the compound has a thickness about equal to the post height;

a pad capping each post, wire span top, and wire loop top, the pads on the wire span tops matching the locations of the fifth set terminals, the pads on the wire loop tops matching the locations of the sixth set terminals; and

reflow metal on the pads, the metal having a first reflow temperature;

a second array of packaged devices having a sheet-like substrate with a third and a fourth surface, terminals on the fourth surface matching the reflow metal covered aligned with the first array, the contact pads on the first array; and

the second array aligned and connected with the first array at the matching terminals and pads to form a 3-dimensional system of packaged devices.

15. The system according toclaim 14 further including reflow metal bodies on the fourth, the fifth, and the sixth set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature.

16. The system according toclaim 14 further including a thickness of the encapsulation compound over the components about equal to the sheet thickness of the substrate.

17. The system according toclaim 14 wherein the assembled arrays are singulated vertically into stacks of packaged devices.

18. A method for fabricating a semiconductor system comprising the steps of:

fabricating a first array of packaged devices including the steps of:

providing a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines and vertical vias;

forming attachment sites on the first surface, each site including terminals on the first and the second surface;

providing semiconductor components having a thickness and I/O ports;

attaching the components to the substrate attachment sites;

connecting the components electrically to the substrate terminals on the first surface;

forming metal posts at least on portions of the second set terminals, the posts being vertical to the first surface and having a height taller than the component thickness, the post locations matching at least portions of the terminals on the second surface;

embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound having a thickness about equal to the post height;

depositing pads on each post; and

depositing reflow metal on the pads, the metal having a reflow temperature;

fabricating a second array of packaged devices by the same steps as fabricating the first array, the substrate of the second array having a third and a fourth surface, the terminals on the fourth surface matching the solder-covered pads of the first array, and the reflow metal having the same reflow temperature as for the first array; and

assembling a semiconductor system including the steps of:

aligning and contacting the terminals on the fourth surface of the second array with the reflow metal-covered pads of the first array; and

applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array.

19. The method according toclaim 18 wherein the step of embedding the components is performed so that the encapsulation compound has a thickness over the components about equal the sheet thickness of the substrate.

20. A method for fabricating a semiconductor system, comprising the steps of:

fabricating a first array of packaged devices including the steps of:

providing a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;

forming an array of assembly sites on the first surface, each site including a first and a second set of terminals on the first surface, and a third set of terminals on the second surface;

providing semiconductor components having a thickness and I/O ports;

flip-attaching a component to each assembly site using metal studs for interconnecting the component ports to the first set terminals;

forming metal posts at least on portions of the second set terminals, the posts being about normal to the first surface, having a height taller than the component thickness, and matching the locations of the third set pads;

embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound having a thickness at least equal to the post height;

exposing the top surface of the posts;

depositing a pad on each exposed post surface; and

depositing reflow metal on the pads, the metal having a reflow temperature;

fabricating a second array of packaged devices by the same steps as fabricating the first array, the substrate having a third and a fourth surface, terminals on the fourth surface matching the reflow metal-covered pads of the first array, and the reflow metal having the same reflow temperature as in the first array; and

assembling a semiconductor system, including the steps of:

aligning and contacting the terminals on the fourth surface with the reflow metal-covered pads of the first array; and

applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array.

21. The method according toclaim 20 wherein the step of embedding the components is performed so that the encapsulation compound has a thickness over the components about equal to the sheet thickness of the substrate.

22. The method according toclaim 20 further including the step of depositing reflow metal bodies on the third set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature.

23. The method according toclaim 20 further including the steps of fabricating a third to an n^tharray of packaged devices, including depositing reflow metals on all pads, further the steps of assembling an array of stacked semiconductor packages by aligning the arrays of devices respectively, and applying thermal energy to reflow the reflow metals between all arrays in one step so that all arrays are concurrently electrically connected and a 3-dimensional system of packaged components is created.

24. The method according toclaim 20 further including the step of sawing the assembled arrays vertically so that individual stacks of packaged devices are singulated.

25. A method for fabricating a semiconductor system, comprising the steps of:

fabricating a first array of packaged devices including the steps of:

providing a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;

forming an array of assembly sites, each site including a component attach location, a first and a second set of terminals on the first surface, and a third, a fourth, and a fifth set of terminals on the second surface;

providing semiconductor components having a thickness, an active surface with a first and a second set of I/O ports, and a passive surface;

attaching the passive surface of a component to each substrate attachment location;

forming spans of bond wire to electrically connect the first set ports to the first set terminals, the top of all spans in a plane;

forming loops of bond wire on the second set ports, the top of all loops in the same plane as the span tops;

forming metal posts on the second set terminals to match the locations of the third set terminals, the posts being about normal to the first surface and having a height to reach the plane of the wire span tops and wire loop tops;

embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound having a thickness at least equal to the post height;

exposing the top surface of the posts, the wire loops, and the wire spans;

depositing a pad on the surface of each exposed top of posts, wire spans, and wire loops, the pads on the wire span tops matching the locations of the fourth set terminals, the pads on the wire loop tops matching the locations of the fifth set terminals; and

depositing reflow metal on the pads, the metal having a reflow temperature;

fabricating a second array of packaged devices by the same steps as fabricating the first array, the substrate having a third and fourth surface, terminals on the fourth surface matching reflow-metal covered pads of the first array, and the reflow metal having the same reflow temperature as in the first array; and

assembling a semiconductor system, including the steps of:

aligning and contacting the terminals on the fourth surface with the reflow metal-covered pads of the first array; and

applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array.

26. The method according toclaim 25 wherein the step of embedding the components is performed so that the encapsulation compound has a thickness over the components about equal to the sheet thickness of the substrate.

27. The method according toclaim 25 further including the step of depositing reflow metal bodies on the third, fourth and fifth set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature.

28. The method according toclaim 25 further including the steps of fabricating a third to an n^tharray of packaged devices, including depositing reflow metals on all pads, further the steps of assembling an array of stacked semiconductor packages steps by aligning the arrays of devices respectively, and applying thermal energy to reflow the reflow metals between all arrays in one step so that all arrays are concurrently electrically connected and a 3-dimensional system of packaged components is created.

29. The method according toclaim 25 further including the step of sawing the assembled arrays vertically so that individual stacks of packaged devices are singulated.

30. A method for fabricating a semiconductor system, comprising the steps of:

fabricating a first array of packaged devices including the steps of:

providing a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface;

forming an array of assembly sites, each site including a first, a second, and a third set of terminals on the first surface, and a fourth, a fifth, and a sixth set of terminals on the second surface;

providing first semiconductor components having a first thickness, an active surface with I/O ports, and a passive surface;

flip-attaching a first component to each assembly site using metal studs for interconnecting the ports to the first set terminals;

providing second semiconductor components having a second thickness, an active surface with a first and a second set of I/O ports, and a passive surface;

attaching the passive surface of a second component to the passive surface of each first component;

forming spans of bond wire to electrically connect the first set ports to the second set terminals, the top of all spans in a plane;

forming loops of bond wire on the second set ports, the top of all loops in the same plane as the span tops;

forming metal posts at least on portions of the second set terminals to match the locations of the fourth set terminals, the posts being about normal to the first surface and having a height to reach the plane of the wire span tops and wire loop tops;

embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound having a thickness at least equal to the post height;

exposing the top surface of the posts, the wire loops, and the wire spans;

depositing a pad on the surface of each exposed top of posts, wire spans, and wire loops, the pads on the wire span tops matching the locations of the fifth set terminals, the pads on the wire loop tops matching the locations of the sixth set terminals; and

depositing reflow metal on the pads, the metal having a reflow temperature;

fabricating a second array of packaged subsystems by the same steps as fabricating the first array, the substrate having a third and fourth surface, terminals on the fourth surface matching reflow-metal covered pads of the first array, and the reflow metal having the same reflow temperature as in the first array; and

assembling a semiconductor system, including the steps of:

aligning and contacting the terminals on the fourth surface with the reflow metal-covered pads of the first array; and

applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array.

31. The method according toclaim 30 wherein the step of embedding the components is performed so that the encapsulation compound has a thickness over the components about equal to the sheet thickness of the substrate.

32. The method according toclaim 30 further including the step of depositing reflow metal bodies on the fourth, fifth, and sixth set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature.

33. The method according toclaim 30 further including the steps of fabricating a third to an n^tharray of packaged devices, including depositing reflow metals on all pads, further the steps of assembling an array of stacked semiconductor package by aligning the arrays of devices respectively, and applying thermal energy to reflow the reflow metals between all arrays in one step so that all arrays are concurrently electrically connected and a 3-dimensional system of packaged components is created.

34. The method according toclaim 30 further including the step of sawing the assembled arrays vertically so that individual stacks of packaged devices are singulated.

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