US20070281465A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the sameDownload PDFInfo
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- US20070281465A1 US20070281465A1US11/808,165US80816507AUS2007281465A1US 20070281465 A1US20070281465 A1US 20070281465A1US 80816507 AUS80816507 AUS 80816507AUS 2007281465 A1US2007281465 A1US 2007281465A1
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Definitions
- the present inventionrelates to a semiconductor device having a multilayer interconnection structure and a method for fabricating the semiconductor device, more specifically a semiconductor device having a multilayer interconnection structure using low dielectric constant (low-k) films as the inter-layer insulation films and a method for fabricating the semiconductor device.
- low-klow dielectric constant
- the main material of the interconnectionsis shifting from Al (aluminum) to Cu (copper) having lower relative resistance and better electromigration characteristics.
- the process for forming the interconnectionsis shifting from the processing of depositing the interconnection materials and patterning them by lithography and dry etching as of RIE (Reactive Ion Etching) or others to the so-called damascene process (refer to, e.g., Japanese Patent Application Unexamined Publication No. 2001-298084).
- RIEReactive Ion Etching
- damascene processtrench patterns and hole patterns are formed in the interconnection insulation films, and the interconnection material is buried in the trenches and holes.
- the shift of the forming process to the damascene process accompanying the shift of the interconnection material to Cuis because Cu is difficult to process by RIE, while Al is not.
- SiO 2silicon dioxide
- FSGfluorinated silicate glass
- the interconnection layers interconnecting the transistors and supplying power sourcesare required to have various functions. That is, the source interconnections are required to be the interconnections of low resistance for making the voltage decreases small.
- the interconnections interconnecting short distancesare required to be micronized interconnections for higher circuit densities.
- the interconnections interconnecting circuit blocksare required to have lower resistance than the micronized interconnections and have pitches whish are more micronized than the upper interconnection layers.
- interconnection layer partseach formed of a plurality of layers and divided in functions, such as a lower layer interconnection which can define micronized pitches, an intermediate layer interconnection used as the interconnections among circuit blocks, and an upper layer interconnection used as source interconnections, clock interconnection, etc., are put together.
- FIG. 17is a sectional view of a semiconductor device having the conventional multilayer interconnection structure, which shows the structure thereof.
- a device isolation film 302 for defining a device regionis formed on a silicon substrate 300 .
- a MOS transistor including a gate electrode 304 and source/drain diffused layers 306is formed in the device region of the silicon substrate 300 .
- An inter-layer insulation film 310 with a contact plug 308 buried inis formed on the silicon substrate 300 with the MOS transistor formed on.
- an inter-layer insulation film 312is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an interconnection layer 314 a of a barrier metal layer of a Ta (tantalum) film and a Cu (copper) filmis buried, connected to the contact plug 308 .
- An interconnection layer 314 b of the barrier metal layer of the tantalum film and the Cu filmis buried in the other region of the inter-layer insulation film 312 .
- an inter-layer insulation film 316is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- An inter-layer insulation film 318is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an interconnection layer 320 a of a barrier metal layer of a tantalum film, and a Cu filmis buried, connected to the interconnection layer 314 a with the via portion buried in the inter-layer insulation film 316 and with the interconnection portion buried in the inter-layer insulation film 318 .
- an interconnection layer 320 b of a barrier metal layer of a tantalum film, and a Cu filmis buried.
- an inter-layer insulation film 322is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an inter-layer insulation film 324is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an interconnection layer 326 a of a barrier metal layer of a tantalum film, and a Cu filmis buried, connected to the interconnection layer 320 a with the via portion buried in the inter-layer insulation film 322 and with the interconnection portion buried in the inter-layer insulation film 324 .
- an interconnection layer 326 b of a barrier metal layer of a tantalum film, and a Cu filmis buried.
- an inter-layer insulation film 328is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an inter-layer insulation film 330is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an interconnection layer 332 a of a barrier metal layer of a tantalum film, and a Cu filmis buried, connected to the interconnection layer 326 a with the via portion buried in the inter-layer insulation film 328 and with the interconnection portion buried in the inter-layer insulation film 330 .
- an interconnection layer 332 b of a barrier metal layer of a tantalum film, and a Cu filmis buried.
- the lower interconnection part having the four-layer multilayer interconnection structure of the interconnection layers 314 a , 314 b , the interconnection layers 320 a , 320 b , the interconnection layers 326 a , 326 b and the interconnection layers 332 a , 332 bis formed on the silicon substrate 300 .
- an inter-layer insulation film 334is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an inter-layer insulation film 336is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an interconnection layer 338 a of a barrier metal layer of a tantalum film, and a Cu filmis buried, connected to the interconnection layer 332 a with the via portion buried in the inter-layer insulation film 334 and with the interconnection portion buried in the inter-layer insulation film 336 .
- an interconnection layer 338 b of a barrier metal layer of a tantalum film, and a Cu filmis buried.
- an inter-layer insulation film 340is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an inter-layer insulation film 342is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film.
- an interconnection layer 344 a of a barrier metal layer of a tantalum film, and a Cu filmis buried, connected to the interconnection layer 338 a with the via portion buried in the inter-layer insulation film 340 and with the interconnection portion buried in the inter-layer insulation film 342 .
- an interconnection layer 344 b of a barrier metal layer of a tantalum film, and a Cu filmis buried.
- the upper interconnection parthaving the two-layer multilayer interconnection structure of the interconnection layers 338 a , 338 b and the interconnection layers 344 a , 344 b having interconnection patterns of a larger pitch than the interconnection layers 314 a , 314 b , the interconnection layer 320 a , 320 b , the interconnection layer 326 a , 326 b and the interconnection layers 332 a , 332 b of the lower interconnection part is formed on the lower interconnection part.
- an inter-layer insulation film 346is formed of a silicon oxide film laid on a silicon nitride film. Contact plugs 348 are buried in the inter-layer insulation film 346 .
- an electrode 350is formed, connected to the interconnection layer 344 a through the contact plugs 348 .
- a cover film 352is formed of a silicon nitride film 352 a formed on a silicon oxide film 352 b .
- An opening 354is formed in the cover film 352 down to the electrode 350 .
- the interconnection layersare divided in terms of functions as described above, the structures of the respective interconnection layers are changed in accordance with required characteristics.
- the lower layer interconnectionsare formed at small pitches, and to decrease the interconnection capacitance, film thicknesses of the interconnection layers are made small.
- materials of the inter-layer insulation filmsmust be low-k materials.
- the upper layer interconnectionsare formed at larger interconnection pitches so as to allow the interconnections to be formed in a thicker thickness.
- the interconnection capacitancedoes not critically matter in the upper interconnection layers, which permits silicon oxide film to be used as the inter-layer insulation films.
- the intermediate layer interconnectionsare required to have characteristics which are middle between the lower layer interconnections and the upper layer interconnections described above.
- the intermediate layer interconnections, which interconnect the circuit blockshave the interconnection length larger than the lower layer interconnections, and the resistance must be made low. Accordingly, the thickness of the interconnection is larger than the lower layer interconnections, and the pitch of the interconnections is larger.
- the interconnection capacitance increase due to the thick interconnectionsmust be suppressed, and to this end, low-k materials must be used as the material of the inter-layer insulation films.
- An object of the present inventionis to provide a semiconductor device using low-k films as the inter-layer insulation films of the multilayer interconnection structure, which can achieve the suppression of the defect occurrence and the decrease of the interconnection capacitance corresponding to the functions of the interconnections, and a method for fabricating the semiconductor device.
- a semiconductor devicecomprising: a first inter-layer insulation film formed over a substrate and including a first low dielectric constant film and a hydrophilic insulation film formed on the first low dielectric constant film; a first interconnection layer buried in a first interconnection trench formed in the first inter-layer insulation film, whose minimum interconnection pitch is a first pitch; a second inter-layer insulation film formed over the first inter-layer insulation film and including a second low dielectric constant film; a second interconnection layer buried in a second interconnection trench formed in the second inter-layer insulation film, whose minimum interconnection pitch is a second pitch larger than the first pitch; and a diffusion preventing film formed directly on the second low dielectric constant film and the second interconnection layer.
- a semiconductor devicecomprising: a first multilayer interconnection layer formed over a substrate and including a plurality of interconnection layers whose minimum interconnection pitch is a first pitch; and a second multilayer interconnection layer formed over the first multilayer interconnection layer and including a plurality of interconnection layers whose minimum interconnection pitch is a second pitch larger than the first pitch, at least one of said plurality of interconnection layers forming the first multilayer interconnection layer being buried in an opening formed in a first inter-layer insulation film including a first low dielectric constant film and a hydrophilic insulation film formed on the first low dielectric constant film, the respective plurality of interconnection layers forming the second multilayer interconnection layer being buried in an opening formed in a second inter-layer insulation film including a diffusion preventing film and a second low dielectric constant film formed on the diffusion preventing film, and the diffusion preventing film of one second inter-layer insulation film being formed directly on the second low dielectric constant film of another second inter-layer insulation film underlying said
- a method for fabricating a semiconductor devicecomprising the steps of: forming over a substrate a first inter-layer insulation film including a first low dielectric constant film and a first hydrophilic insulation film formed on the first low dielectric constant film; forming a first interconnection trench in the first inter-layer insulation film; forming a first conductor film on the first inter-layer insulation film with the first interconnection trench formed in; polishing the first conductor film to expose the first hydrophilic insulation film while burying the first conductor film in the first interconnection trench to form a first interconnection layer whose minimum interconnection pitch is a first pitch; forming a second inter-layer insulation film including a second low dielectric constant film over the first inter-layer insulation film; forming a second interconnection trench in the second inter-layer insulation film; forming a second conductor film on the second inter-layer insulation film with the second interconnection trench formed in; and polishing the second conductor film to expose the second low dielectric constant film while burying
- the semiconductor devicecomprises: a first inter-layer insulation film formed over a substrate and including a first low dielectric constant film and a hydrophilic insulation film formed on the first low dielectric constant film; a first interconnection layer buried in a first interconnection trench formed in the first inter-layer insulation film, whose minimum interconnection pitch is a first pitch; a second inter-layer insulation film formed over the first inter-layer insulation film and including a second low dielectric constant film; a second interconnection layer buried in a second interconnection trench formed in the second inter-layer insulation film, whose minimum interconnection pitch is a second pitch larger than the first pitch; and a diffusion preventing film formed directly on the second low dielectric constant film and the second interconnection layer, whereby in a case that low dielectric constant films are used as the inter-layer insulation films of a multilayer interconnection structure, corresponding to functions of the interconnections, the first interconnection layer can suppress the occurrence of defects and the decreases the interconnection capacitance, while the second interconnection layer
- FIG. 1is an SEM picture showing corrosion of interconnections due to water marks.
- FIG. 2is a sectional view of the semiconductor device according to one embodiment of the present invention, which shows a structure thereof.
- FIGS. 3A-3Eare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 1 ).
- FIGS. 4A-4Dare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 2 ).
- FIGS. 5A-5Dare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 3 ).
- FIGS. 6A-6Care sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 4 ).
- FIGS. 7A-7Care sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 5 ).
- FIGS. 8A-8Bare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 6 ).
- FIGS. 9A-9Dare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 7 ).
- FIGS. 10A-10Dare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 8 ).
- FIGS. 11A-11Care sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 9 ).
- FIGS. 12A-12Dare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 10 ).
- FIGS. 13A-13Dare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 11 ).
- FIGS. 14A-14Care sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 12 ).
- FIGS. 15A-15Care sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 13 ).
- FIGS. 16A-16Bare sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part 14 )
- FIG. 17is a sectional view of a semiconductor device having the conventional multilayer interconnection structure, which shows the structure thereof.
- low-k materialsare known SiOC, SILK (registered trademark) by The Dow Chemical Company, FLARE (registered trademark) by Honeywell Electronic Materials, etc. Most of such low-k materials are water-repellent. This is for the following reason.
- the relative dielectric constant of wateris as high as 88 . Accordingly, when a film formed of a low-k material absorbs humidity, the dielectric constant of the film rises. To suppress the dielectric constant increase due to the humidity absorption, the low-k materials are terminated with Si—H, SiCH 3 for the processing for prohibiting the formation of Si—OH bonds, which are hydrophilic.
- the low-k materialsare terminated with hydrogen, methyl or others to be water-repellent.
- Earnest studies by the inventor of the present inventionhave made it clear that, as will be described below, in cases that the materials of the inter-layer insulation films of the interconnection layers are low-k materials, it is one of causes for the yield decrease that the low-k materials are made water-repellent.
- the lower interconnections for short-distant interconnectionswhich are formed at small pitches, are more vulnerable to defects due to foreign matter adhering thereto. Accordingly, it is necessary to lift off the foreign matter by HF (hydrofluoric acid) processing added to the cleaning following the CMP (chemical mechanical polishing) of the damascene process.
- HFhydrofluoric acid
- CMPchemical mechanical polishing
- FIG. 1is an SEM (Scanning Electron Microscope) picture showing the corrosion of the interconnection due to the water marks.
- the semiconductor device and the method for fabricating the same according to the present inventionsuppresses the occurrence of the defects, and realizes the interconnection capacitance decrease, corresponding to the functions of the interconnection layers of a multilayer interconnection structure even when the inter-layer insulation films are formed of such water-repellent low-k films.
- FIG. 2is a sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof.
- FIG. 2is a sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof.
- 3A-3E4 A- 4 D, 5 A- 5 D, 6 A- 6 C, 7 A- 7 C, 8 A- 8 B, 9 A- 9 D, 10 A- 10 D, 11 A- 11 C, 12 A- 12 D, 13 A- 13 D, 14 A- 14 C, 15 A- 15 C, and 16 A- 16 B are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which show the method.
- the semiconductor deviceincludes a lower interconnection part 12 formed on a silicon substrate 10 , an intermediate interconnection part 14 formed on the lower interconnection part 12 and an upper interconnection part 16 formed on the intermediate interconnection part 14 .
- the substrate 10additionally has semiconductor devices, such as MOS transistors, etc. formed on.
- interconnection layers having interconnection patterns of a smaller pitch than interconnection patterns of the interconnection layers formed in, e.g., the intermediate layer interconnection part 14 and the upper interconnection part 16are formed, connecting points separated by short distance.
- interconnection layers having interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers formed in, e.g., the lower interconnection part 12 , and a smaller pitch than interconnection patterns of the interconnection layers formed in, e.g., the upper interconnection part 16are formed, connecting circuit blocks.
- interconnection layers having interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers formed in, e.g., the lower interconnection part 12 and the intermediate interconnection part 14being utilized as source interconnections and clock interconnections.
- a device isolation film 18 for defining a device regionis formed on the silicon substrate 10 .
- a MOS transistor including a gate electrode 20 and source/drain diffused layers 22is formed in the device region of the silicon substrate 10 .
- An inter-layer insulation film 24 of a silicon oxide filmis formed on the silicon substrate 10 with the MOS transistor formed on.
- a via hole 26is formed in the inter-layer insulation film 24 down to the source/drain diffused layer 22 , and a contact plug 28 is buried in the via hole 26 .
- an inter-layer insulation film 36is formed of an SiC film 30 , a low-k film 32 of SiOC film formed on the SiC film 30 , and a hydrophilic insulation film 34 of silicon oxide film formed on the low-k film 32 .
- An interconnection trench 38 ais formed in the region of the inter-layer insulation film 36 , which includes the contact plug 28 .
- An interconnection layer 44 a of a barrier metal layer 40 of Ta (tantalum) film and a Cu film 42is buried in the interconnection trench 38 a , connected to the contact plug 28 .
- An interconnection trench 38 bis formed in the other region of the hydrophilic insulation film 34 , the low-k film 32 and the SiC film 30 .
- An interconnection layer 44 b of the barrier metal 40 of Ta film and the Cu film 42is buried in the interconnection trench 38 b.
- an inter-layer insulation film 56is formed of an SiC film 46 , a low-k film 48 of SiOC film formed on the SiC film 46 , an SiC film 50 formed on the low-k film 48 , a low-k film 52 of SiOC film formed on the SiC film 50 , and a hydrophilic insulation film 54 of silicon oxide film laid on the low-k film 52 .
- a via hole 58is formed in the low-k film 48 and the SiC film 46 of the inter-layer insulation film 56 down to the interconnection layer 44 a .
- An interconnection trench 60 ais formed in the region of the hydrophilic insulation film 54 , the low-k film 52 and the SiC film 50 , which includes the via hole 58 .
- An interconnection trench 60 bis formed in the other region of the hydrophilic insulation film 54 , the low-k film 52 and the SiC film 50 .
- an interconnection layer 66 b of the barrier metal layer 62 of Ta film and the Cu film 64is buried.
- an inter-layer insulation film 78is formed of an SiC film 68 , a low-k film 70 of SiOC film formed on the SiC film 68 , an SiC film 72 formed on the low-k film 70 , a low-k film 74 of SiOC film formed on the SiC film 72 , and a hydrophilic insulation film 76 of silicon oxide film laid on the low-k film 74 .
- a via hole 80is formed in the low-k film 70 and the SiC film 68 of the inter-layer insulation film 78 down to the interconnection layer 66 a .
- An interconnection trench 82 ais formed in the region of the hydrophilic insulation film 76 , the low-k film 74 and the SiC film 72 , which includes the via hole 80 .
- an interconnection layer 88 a of a barrier metal layer 84 of Ta film and a Cu film 86is buried, connected to the interconnection layer 66 a .
- an interconnection trench 82 bis formed in the other region of the hydrophilic insulation film 76 , the low-k film 74 and the SiC film 72 .
- an interconnection trench 82 bis formed in the other region of the hydrophilic insulation film 76 , the low-k film 74 and the SiC film 72 .
- an interconnection trench 82 bis formed in the interconnection trench 82 b .
- an inter-layer insulation film 100is formed of an SiC film 90 , a low-k film 92 of SiOC film formed on the SiC film 90 , an SiC film 94 formed on the low-k film 92 , a low-k film 96 of SiOC film formed on the SiC film 94 , and a hydrophilic insulation film 98 of silicon oxide film laid on the low-k film 96 .
- a via hole 102is formed in the low-k film 92 and the SiC film 90 of the inter-layer insulation film 100 down to the interconnection layer 88 a .
- An interconnection trench 104 ais formed in the region of the hydrophilic insulation film 98 , the low-k film 96 and the SiC film 94 , which includes the via hole 102 .
- an interconnection layer 110 a of a barrier metal layer 106 of Ta film and a Cu film 108is buried, connected to the interconnection layer 88 a .
- An interconnection trench 104 bis formed in the other region of the hydrophilic insulation film 98 , the low-k film 96 and the SiC film 94 .
- an interconnection layer 110 b of the barrier metal 106 of Ta film and the Cu film 108is buried.
- an inter-layer insulation film 122is formed of an SiC film 112 , a low-k film 114 of SiOC film formed on the SiC film 112 , an SiC film 116 formed on the low-k film 114 , a low-k film 118 of SiOC film formed on the SiC film 116 , and a hydrophilic insulation film 120 of silicon oxide film laid on the low-k film 118 .
- a via hole 124is formed in the low-k film 114 and the SiC film 112 of the inter-layer insulation film 122 down to the interconnection layer 110 a .
- An interconnection trench 126 ais formed in the region of the hydrophilic insulation film 120 , the low-k film 118 and the SiC film 116 , which includes the via hole 124 .
- an interconnection layer 132 a of a barrier metal layer 128 of Ta film and a Cu film 130is buried, connected to the interconnection layer 110 a .
- an interconnection trench 126 bis formed in the other region of the hydrophilic insulation film 120 , the low-k film 118 and the SiC film 116 .
- an interconnection trench 126 bis formed in the interconnection trench 126 b .
- an interconnection layer 132 b of the barrier metal layer 128 of Ta film and the Cu film 130is buried.
- the lower interconnection part 12 having the five-layer multilayer interconnection structureis formed on the silicon substrate 10 .
- the respective pitches of the interconnection patterns of the interconnection layer 44 a , 44 b , the interconnection layer 66 a , 66 b , the interconnection layers 88 a , 88 b , the interconnection layer 110 a , 110 b , and the interconnection layer 132 a , 132 b of the respective layersare, e.g., 0.28 ⁇ m.
- an inter-layer insulation film 142is formed of an SiC film 134 , a low-k film 136 of SiOC film formed on the SiC film 134 , an SiC film 138 formed on the low-k film 136 , and a low-k film 140 of SiOC film laid on the SiC film 138 .
- a via hole 144is formed in the low-k film 136 and the SiC film 134 of the inter-layer insulation film 142 down to the interconnection layer 132 a .
- An interconnection trench 146 ais formed in the region of the low-k film 140 and the SiC film 138 , which includes the via hole 144 .
- an interconnection layer 152 a of a barrier metal layer 148 of Ta film and a Cu film 150is buried, connected to the interconnection layer 132 a .
- an interconnection trench 146 bis formed in the other region of the low-k film 140 and the SiC film 138 .
- An interconnection layer 152 b of the barrier metal layer 148 of Ta film and the Cu film 150is buried in the interconnection trench 146 b.
- an inter-layer insulation film 162is formed of an SiC film 154 , a low-k film 156 of SiOC film formed on the SiC film 154 , an SiC film 158 formed on the low-k film 156 , and a low-k film 160 of SiOC film laid on the SiC film 158 .
- a via hole 164is formed in the low-k film 156 and the SiC film 154 of the inter-layer insulation film 162 down to the interconnection layer 152 a .
- An interconnection trench 166 ais formed in the region of the low-k film 160 and the SiC film 158 , which includes the via hole 164 .
- an interconnection layer 172 a of a barrier metal layer 168 of Ta film and a Cu film 170is buried, connected to the interconnection layer 152 a .
- an interconnection trench 166 bis formed in the other region of the low-k film 160 and the SiC film 158 .
- An interconnection layer 172 b of the barrier metal layer 168 of Ta film and the Cu film 170is buried in the interconnection trench 166 b.
- the intermediate interconnection part 14having the two-layer multilayer interconnection structure is formed on the lower interconnection part 12 .
- the respective pitches of the interconnection patterns of the interconnection layer 152 a , 152 b and the interconnection layer 172 a , 172 b of the respective layerare larger by, 1.5 times or more than the pitch of the interconnection patterns of the interconnection layers of the lower interconnection part 12 .
- the pitches of the interconnection patterns of the interconnection layer 152 a , 152 b and the interconnection layer 172 a , 172 bis 0.56 ⁇ m, which is respectively twice the pitch of the interconnection patterns of the interconnection layers of the lower interconnection part 12 .
- an inter-layer insulation film 182is formed of an SiC film 174 , a silicon oxide film 176 formed on the SiC film 174 , an SiC film 178 formed on the silicon oxide film 176 , and a silicon oxide film 180 laid on the SiC film 178 .
- a via hole 184is formed in the silicon oxide film 176 and the SiC film 174 of the inter-layer insulation film 182 down to the interconnection layer 172 a .
- An interconnection trench 186 ais formed in the region of the silicon oxide film 180 and the SiC film 178 , which includes the via hole 184 .
- an interconnection layer 192 a of a barrier metal layer 188 of Ta film and a Cu film 190is buried, connected to the interconnection layer 172 a .
- an interconnection trench 186 bis formed in the other region of the silicon oxide film 180 and the SiC film 178 .
- An interconnection layer 192 b of the barrier metal layer 188 of Ta film and the Cu film 190is buried in the interconnection trench 186 b.
- an inter-layer insulation film 202is formed of an SiC film 194 , a silicon oxide film 196 formed on the SiC film 194 , an SiC film 198 formed on the silicon oxide film 196 , and a silicon oxide film 200 laid on the SiC film 198 .
- a via hole 204is formed in the silicon oxide film 196 and the SiC film 194 of the inter-layer insulation film 202 down to the interconnection layer 192 a .
- An interconnection trench 206 ais formed in the region of the silicon oxide film 200 and the SiC film 198 , which includes the via hole 204 .
- an interconnection layer 212 a of a barrier metal layer 208 of Ta film and a Cu film 210is buried, connected to the interconnection layer 192 a .
- an interconnection trench 206 bis formed in the other region of the silicon oxide film 200 and the SiC film 198 .
- An interconnection layer 212 b of the barrier metal layer 208 of Ta film and the Cu film 210is buried in the interconnection trench 206 b.
- the upper interconnection part 16having the two-layer multilayer interconnection structure is formed on the intermediate interconnection part 14 .
- the pitches of the interconnection patterns of the interconnection layer 192 a , 192 b and the interconnection layer 212 a , 212 b of the respective layersare larger than the pitches of the interconnection patterns of the interconnection layers of the lower interconnection part 12 and the intermediate interconnection part 14 and are respectively, e.g., 0.84 ⁇ m.
- an inter-layer insulation film 218comprising a SiC film 214 formed on a silicon oxide film 216 is formed.
- Via holes 220are formed in the inter-layer insulation film 218 down to the interconnection layer 212 a .
- Contact plugs 222are buried in the via holes 220 .
- an electrode 224is formed, connected to the interconnection layer 212 a through the contact plugs 222 .
- a cover film 226is formed comprising a silicon nitride film 226 b formed on a silicon oxide film 226 a .
- An opening 228is formed in the cover film 226 down to the electrode 224 .
- the semiconductor device according to the present embodimentis constituted.
- the semiconductor deviceis characterized mainly in that the lower interconnection part 12 and the intermediate interconnection part 14 include low-k films of SiOC film as the inter-layer insulation films, and in the lower interconnection part 12 , in which the interconnection layers formed in the interconnection patterns of a smaller pitch than the interconnection patterns of the interconnection layers of the intermediate interconnection part 14 , the hydrophilic insulation film of silicon oxide film is formed on the low-k film, but in the intermediate interconnection part 14 , in which the interconnection layers has the interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers of the lower interconnection part 12 , the SiC film functioning as the diffusion preventing film is formed directly on the low-k film, without any hydrophilic insulation film formed.
- the lower interconnection part 12in which the interconnection patterns of the interconnection layers has a smaller pitch is more vulnerable to defects due to foreign matter adhering thereto.
- the hydrophilic insulation filmwhich is formed on the low-k film, is exposed on the surface.
- the hydrophilic insulation filmwhich is not water-repellent low-k film, is exposed, whereby foreign matter can be sufficiently removed by lift-off by HF processing following the polish by CMP or others.
- the exposure of the hydrophilic insulation filmwhich is not the water repellent low-k film, can suppress the generation of water marks due to water drops which are cause for corrosion of the interconnection layers after cleaning and drying following the polish by CMP or others.
- the use of the low-k film as the inter-layer insulation films in the lower interconnection part 12which is more vulnerable to defects due to adhering foreign matter can decrease the interconnection capacitance, suppressing the occurrence of defects.
- the interconnection layers of the intermediate interconnection part 14are used as the interconnection layers interconnecting circuit blocks. Accordingly, it is necessary that the interconnection layers of the intermediate interconnection part 14 have the interconnection resistance decreased and has the interconnection patterns of the pitch which is, e.g., 1.5-3 times the pitch of the interconnection patterns of the interconnection layers of the lower interconnection part 12 .
- the intermediate interconnection part 14 having such large interconnection pattern pitchis less vulnerable to defects due to foreign matter adhering thereto than the lower interconnection part 12 . Accordingly, even without removing the foreign matter by lift-off by HF processing following CMP, the yield is little affected. It is not necessary to leave the hydrophilic insulation film on the low-k film.
- the SiC film functioning the diffusion preventing filmis formed directly on the low-k film, and the hydrophilic insulation film, whose dielectric constant is higher than that of the low-k film, is not formed. Accordingly, the low-k film is used as the inter-layer insulation films, whereby the interconnection capacitance can be sufficiently decreased.
- the interconnection layers of the upper interconnection part 16are used as source interconnections and clock interconnections, and have interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers of the lower interconnection part 12 and the intermediate interconnection part 14 . Accordingly, the upper interconnection part 16 is less required to have the interconnection capacitance decreased by using the low-k film, as are the lower interconnection part 12 and the intermediate interconnection part 14 . Accordingly, in the upper interconnection part 16 , silicon oxide film, whose dielectric constant is higher than low-k film, is used. As the inter-layer insulation films of the upper interconnection part 16 , in addition to silicon oxide film, FSG (Fluorinated Silicate Glass) film or others may be used.
- FSGFluorinated Silicate Glass
- the interconnection capacitancecan be sufficiently decreased.
- FIGS. 3A-3E , 4 A- 4 D, 5 A- 5 D, 6 A- 6 C, 7 A- 7 C, and 8 A- 8 Bare sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which show the steps of fabricating the lower interconnection part 12 .
- FIGS. 9A-9D , 10 A- 10 D, and 11 A- 11 Care sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which show the steps of fabricating the intermediate interconnection part 14 .
- FIGS. 12A-12D , 13 A- 13 D, 14 A- 14 C, 15 A- 15 C, and 16 A- 16 Bare sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which show the steps of fabricating the upper interconnection part 16 , the electrode, etc.
- the device isolation film 18 for defining a device regionis formed on the silicon substrate 10 by, e.g., STI (Shallow Trench Isolation).
- MOS transistorincluding the gate electrode 20 and the source/drain diffused layers 22 is formed in the same way as in, e.g., the usual MOS transistor fabricating method (see FIG. 3A ).
- MOS transistor fabricating methodsee FIG. 3A .
- MOS transistorsnot only MOS transistors but also various semiconductor devices can be fabricated.
- the inter-layer insulation film 24 of a silicon oxide film of, e.g., a 700 nm-thicknessis formed by, e.g., CVD (Chemical Vapor Deposition) on the silicon substrate 10 with the MOS transistor formed on.
- CVDChemical Vapor Deposition
- the surface of the inter-layer insulation film 24is polished by, e.g., CMP until the film thickness of the inter-layer insulation film 24 becomes, e.g., 400 nm to thereby flatten the surface of the inter-layer insulation film 24 (see FIG. 3B ).
- the contact hole 26is formed in the inter-layer insulation film 24 by photolithography and dry etching down to the silicon substrate 10 .
- a Ti (titanium) film of, e.g., a 10 nm-thickness, a TiN (titanium nitride) film of, e.g., a 10 nm-thickness and a W (tungsten) film of, e.g., a 300 nm-thicknessare formed by, e.g., CVD.
- the W film, the TiN film and the Ti filmare removed flat by, e.g., CMP until the surface of the inter-layer insulation film 24 is exposed to thereby form the contact plug 28 of the Ti film, the TiN film and the W film buried in the contact hole 26 (see FIG. 3C ).
- the SiC film 30 of, e.g., a 30 nm-thicknessis formed by, e.g., plasma CVD.
- the low-k film 32 of an SiOC film of, e.g., a 200 nm-thicknessis formed on the SiC film 30 by, e.g., plasma CVD.
- the hydrophilic insulation film 34 of a silicon oxide film, of e.g., a 100 nm-thicknessis formed on the low-k film 30 by, e.g., plasma CVD using TEOS (tetraethyoxysilane) as the main material.
- the hydrophilic insulation film 34is formed in a larger film thickness than the hydrophilic insulation film 244 to be formed in the intermediate interconnection part 14 , which will be described later.
- the inter-layer insulation film 36 of the layer structure of the hydrophilic insulation film 34 /the low-k film 32 /the SiC film 30is formed (see FIG. 3D ).
- the SiC film 30functions as the etching stopper film and the Cu diffusion preventing film.
- the silicon nitride film 232 of, e.g., a 50 nm-thicknessis formed on the hydrophilic insulation film 34 by, e.g., CVD.
- the silicon nitride film 232functions as the ARC (Anti-reflection Coating) film in the following photolithography step.
- a photoresist film 234 for exposing regions for the interconnection trenches 38 a , 38 b to be formed in the inter-layer insulation film 36are formed on the silicon nitride film 232 by photolithography (see FIG. 3E ).
- the silicon nitride film 232 , the hydrophilic insulation film 34 and the low-k film 32are sequentially etched.
- the interconnection trenches 38 a , 38 bare formed in the hydrophilic insulation film 34 and the low-k film 32 (see FIG. 4A ).
- the SiC film 30 on the bottoms of the interconnection trenches 38 a , 38 bis etched to open the interconnection trenches 38 a , 38 b down to the inter-layer insulation film 24 .
- the silicon nitride film 232 on the hydrophilic insulation film 34is also etched off (see FIG. 4B ).
- the barrier metal layer 40 of a Ta film of, e.g., 10 nm-thickness and the Cu film of, e.g., a 100 nm-thicknessare continuously formed on the entire surface by, e.g., sputtering.
- a Cu filmis further deposited by electrolytic plating to form the Cu film 42 of, e.g., a 1.0 ⁇ m-total film thickness (see FIG. 4C ).
- the Cu film 42 and the barrier metal layer 40 of the Ta filmare polished off flat by CMP to thereby form the interconnection layer 44 a buried in the interconnection trench 38 a and the interconnection layer 38 b buried in the interconnection trench 38 b .
- the Cu film 42is selectively polished under conditions which provide a sufficient selectivity for the barrier metal layer 40 of Ta film, and the polish is stopped at the surface of the barrier metal layer (see FIG. 4D ).
- the polishing conditionsare suitably reset to polished the barrier metal layer 40 of Ta film to expose the hydrophilic insulation film 34 (see FIG. 5A ).
- the polishing conditions by CMPare thus set to thereby facilitate controlling the over-polish amount of the hydrophilic insulation film 34 of the silicon oxide film below the barrier metal layer 40 . Resultantly, after the Cu film 42 and the barrier metal layer 40 have been removed, the hydrophilic insulation film 34 can be easily set in a required film thickness.
- the film thickness of the hydrophilic insulation film 34 after the removal of the Cu film 42 and the barrier metal layer 40is, e.g., 50 nm.
- interconnection layer 44 aburied in the interconnection trench 38 a and including the barrier metal layer 40 of the Ta film for preventing the diffusion of the Cu, and the Cu film 42 forming the major part of the interconnection layer
- interconnection layer 44 bburied in the interconnection trench 38 b and including the barrier metal layer 40 of the Ta film for preventing the diffusion of the Cu, and the Cu film 42 forming the major part of the interconnection layer (see FIG. 5A ).
- the SiC film 46 of, e.g., a 50 nm-thicknessis formed by, e.g., plasma CVD on the inter-layer insulation film 36 with the interconnection layers 44 a , 44 b buried in.
- the low-k film 48 of a SiOC film of, e.g., a 250 nm-thicknessis formed on the SiC film 46 by, e.g., plasma CVD.
- the SiC film 50 of, e.g., a 30 nm-thicknessis formed on the low-k film 48 by, e.g., plasma CVD.
- the low-k film 52 of an SiOC film of, e.g., a 200 nm-thicknessis formed on the SiC film 50 by, e.g., plasma CVD.
- the hydrophilic insulation film 54 of a silicon oxide film of, e.g., a 100 nm-thicknessis formed on the low-k film 52 by plasma CVD using, e.g., TEOS as the main material.
- the hydrophilic insulation film 54is formed in a larger film thickness than the hydrophilic insulation film 244 to be formed in the intermediate interconnection part 14 , which will be described later.
- the inter-layer insulation film 56 of the layer structure of the hydrophilic insulation film 54 /the low-k film 52 /the SiC film 50 /the low-k film 48 /the SiC film 46is formed (see FIG. 5B ).
- the SiC films 46 , 50function as the etching stopper film and the Cu diffusion preventing film.
- the silicon nitride film 236 of, e.g., a 50 nm-thicknessis formed on the hydrophilic insulation film 54 by, e.g., CVD.
- the silicon nitride film 236functions as the ARC film in the following photolithography step.
- a photoresist film 238 for exposing the region for the via hole 58 to be formed in the low-k film 48 and the SiC film 46is formed on the silicon nitride film 236 by photolithography (see FIG. 5C ).
- the silicon nitride film 236 , the hydrophilic insulation film 54 , the low-k film 52 , the SiC film 50 and the low-k film 48are sequentially etched under suitably changed conditions.
- the via hole 58is formed in the low-k film 46 (see FIG. 5D ).
- the photoresist film 238is removed.
- a resin 240is buried in the via hole 58 by, e.g., spin coating. Then the resin 240 on the silicon nitride film 236 is removed by ashing using, e.g., O 2 plasma, and the resin 240 in the via hole 58 is etched back to a prescribed height until, for example, the upper surface of the resin 240 is positioned near the border between the SiC film 50 and the low-k film 52 (see FIG. 6A ).
- a photoresist film 242 for exposing the regions for the interconnection trenches 60 a , 60 b to be formed in the inter-layer insulation film 56is formed on the silicon nitride film 236 (see FIG. 6B ).
- the photoresist film 242is formed of a material which does not mix with the resin 240 and whose developer does not solve the resin 240 .
- the silicon nitride film 236 , the hydrophilic insulation film 54 and the low-k film 52are sequentially etched.
- the interconnection trenches 60 a , 60 bare formed in the hydrophilic insulation film 54 and the low-k film 52 (see FIG. 6C ).
- the photoresist film 242 and the resin 240 in the via hole 58are removed by ashing using, e.g., O 2 plasma and CF 4 plasma.
- the SiC film 50 on the bottoms of the interconnection trenches 60 a , 60 b and the SiC film 46 on the bottom of the via hole 58are etched to open the interconnection trenches 60 a , 60 b down to the low-k film 48 and the via hole 58 down to the interconnection layer 44 a .
- the silicon nitride film 236 on the hydrophilic insulation film 54is also etched off (see FIG. 7A ).
- the barrier metal layer 62 of a Ta film of, e.g., a 25 nm-thickness and a Cu film of, e.g., a 100 nm-thicknessare continuously deposited on the entire surface by, e.g., sputtering.
- pre-processingsuch as Ar (argon) sputtering, H 2 plasma processing, H 2 annealing, etc. may be performed in-situ.
- a Cu filmis further deposited by electrolytic plating to form the Cu film 64 of, e.g., a 1.0 ⁇ m-total thickness (see FIG. 7B ).
- the Cu film 64 and the barrier metal layer 62 of the Ta filmis polished off flat by CMP to form the interconnection layer 66 a buried in the interconnection trench 60 a and the via hole 58 and the interconnection layer 66 b buried in the interconnection trench 60 b .
- the Cu film 64is selectively polished under conditions which provide sufficient selectivity with respect to the barrier metal layer 62 of Ta film, and the polish is stopped at the surface of the barrier metal layer 62 (see FIG. 7C ).
- the polishing conditionsare suitably reset to polish the barrier metal layer 62 of Ta film to expose the hydrophilic insulation film 54 (see FIG. 8A ).
- the polishing conditions by CMPare thus set to thereby facilitate controlling the over-polish amount of the hydrophilic insulation film 54 of the silicon oxide film below the barrier metal layer 62 . Resultantly, after the Cu film 64 and the barrier metal layer 62 have been removed, the hydrophilic insulation film 54 can be easily set in a required film thickness.
- the film thickness of the hydrophilic insulation film 54 after the removal of the Cu film 64 and the barrier metal layer 62is, e.g., 50 nm.
- the interconnection layer 66 a buried in the via hole 58 and the interconnection trench 60 a and including the barrier metal 62 of Ta film for preventing the diffusion of the Cu and the Cu film 64 forming the major part of the interconnection layer, and the interconnection layer 66 b buried in the interconnection trench 60 b and including the barrier metal layer 62 of Ta film for preventing the diffusion of the Cu and the Cu film 64 forming the major part of the interconnection layerare formed (see FIG. 8A ).
- the lower interconnection part 12 having the five-layer multilayer interconnection structureis formed on the silicon substrate 10 (see FIG. 8B ).
- the interconnection layer 44 a , 44 b , the interconnection layer 66 a , 66 b , the interconnection layer 88 a , 88 b , the interconnection layer 110 a , 110 b and the interconnection layer 132 a , 132 b of the lower interconnection part 12are formed in the interconnection patterns of respectively, e.g., a 0.28 ⁇ m pitch.
- the SiC film 134 of, e.g., a 70 nm-thicknessis formed by, e.g., plasma CVD on the inter-layer insulation film 122 with the interconnection layer 132 a , 132 b of the interconnection part 12 buried in.
- the low-k film 136 of an SiOC film of, e.g., a 530 nm-thicknessis formed on the SiC film 134 by, e.g., plasma CVD.
- the SiC film 138 of, e.g., a 30 nm-thicknessis formed on the low-k film 136 by, e.g., plasma CVD.
- the low-k film 140 of an SiOC film of, e.g., a 400 nm-thicknessis formed on the SiC film 138 by, e.g., plasma CVD.
- the inter-layer insulation film 142 of the layer structure of the low-k film 140 /the SiC film 138 /the low-k film 136 /the SiC film 134is formed.
- the SiC films 134 , 138function as the etching stopper film and the Cu diffusion preventing film.
- the hydrophilic insulation film 244 of a silicon oxide film of, e.g., a 30 nm-thicknessis formed on the low-k film 140 by plasma CVS using, e.g., TEOS as the main material (see FIG. 9A ).
- the hydrophilic insulation film 244is formed in a smaller thickness than the hydrophilic insulation films 34 , 54 , 76 , 98 , 120 formed in the lower interconnection part 12 .
- the structure below the SiC film 134is omitted.
- the silicon nitride film 246 of, e.g., a 50 nm-thicknessis formed on the hydrophilic insulation film 244 by, e.g., CVD.
- the silicon nitride film 246functions as an ARC film in the following photolithography step.
- a photoresist film 248 for exposing the region for the via hole 144 which is to be formed in the low-k film 136 and the SiC film 134is formed on the silicon nitride film 246 by photolithography (see FIG. 9B ).
- the silicon nitride film 246 , the hydrophilic insulation film 244 , the low-k film 140 , the SiC film 138 and the low-k film 136are sequentially etched under suitably changed conditions.
- the via hole 144is formed in the low-k film 136 (see FIG. 9C ).
- the photoresist film 248is removed.
- the resin 250 on the silicon nitride film 246is removed by ashing using, e.g., O 2 plasma, and the resin 250 in the via hole 144 is etched back to a prescribed height until, for example, the upper surface of the resin 250 is positioned near the border between the SiC film 138 and the low-k film 140 (see FIG. 9C ).
- a photoresist film 252 for exposing the regions for the interconnection trenches 146 a , 146 b to be formed in the inter-layer insulation film 142is formed on the silicon nitride film 246 (see FIG. 10A ).
- the photoresist film 252is formed of a material which does not mix with the resin 250 and whose developer does not solve the resin 250 .
- the interconnection trenches 146 a , 146 bare formed in the low-k film 140 (see FIG. 10B ).
- the interconnection trenches 146 a , 146 bare formed in an interconnection pattern of a larger pitch than the interconnection pattern of the interconnection trenches of the lower interconnection part 12 .
- the photoresist film 252 and the resin 250 in the via hole 144are removed by ashing using, e.g., O 2 plasma and CF 4 plasma.
- the SiC film 138 on the bottoms of the interconnection trenches 146 a , 146 b and the SiC film 134 on the bottom of the via hole 144are etched to open the interconnection trenches 146 a , 146 b down to the low-k film 136 and the via hole 144 down to the interconnection layer 132 a of the lower interconnection part 12 .
- the silicon nitride film 246 on the hydrophilic insulation film 244is also etched off (see FIG. 10C ).
- the barrier metal layer 148 of a Ta film of, e.g., a 25 nm-thickness and a Cu film of, e.g., a 100 nm-thicknessare continuously deposited on the entire surface by, e.g., sputtering.
- pre-processingsuch as Ar (argon) sputtering, H 2 plasma processing, H 2 annealing, etc., may be performed in-situ.
- a Cu filmis further deposited by electrolytic plating to form the Cu film 150 of, e.g., a 1.0 ⁇ m-total thickness (see FIG. 10C ).
- the Cu film 150 , the barrier metal layer 148 of the Ta film, and hydrophilic insulation film 244are polished off flat by CMP to form the interconnection layer 152 a buried in the interconnection trench 146 a and the via hole 144 and the interconnection layer 152 b buried in the interconnection trench 146 b .
- the Cu film 150is selectively polished under conditions which provide a high selectivity with respect to the barrier metal layer 148 of Ta film, and the polish is stopped at the surface of the barrier metal layer 148 (see FIG. 11A ).
- the polishing conditionsare reset, and under conditions which make the polishing rate of the barrier metal layer 148 of Ta film approximate to the polishing rate of the hydrophilic insulation film 244 of silicon oxide film, the barrier metal layer 148 and the hydrophilic insulation film 244 are polished to expose the low-k film 140 (see FIG. 11B ).
- the interconnection layer 152 a buried in the via hole 144 and the interconnection trench 146 a and including the barrier metal 148 of Ta film for preventing the diffusion of the Cu and the Cu film 150 forming the major part of the interconnection layer, and the interconnection layer 152 b buried in the interconnection trench 146 b and including the barrier metal layer 148 of Ta film for preventing the diffusion of the Cu and the Cu film 150 forming the major part of the interconnection layerare formed (see FIG. 11B ).
- the intermediate interconnection part 14 having the two-layer multilayer interconnection structureis formed on the lower interconnection part 12 .
- the interconnection layer 152 a , 152 b and the interconnection layer 172 a , 172 b of the intermediate interconnection part 14are formed in the interconnection patterns respectively of a pitch which is larger by, e.g., 1.5 times or more than the pitch of the interconnection layers of the lower interconnection part 12 .
- the interconnection layer 152 a , 152 b and the interconnection layer 172 a , 172 bare formed in the interconnection patterns of respectively, e.g., a 0.56 ⁇ m pitch.
- the SiC film 174 of, e.g., a 70 nm-thicknessis formed by, e.g., plasma CVD on the inter-layer insulation film 162 with the interconnection layers 172 a , 172 b of the intermediate interconnection part 14 buried in.
- the silicon oxide film 176 of, e.g., a 530 nm-thicknessis formed on the SiC film 174 by, e.g., plasma CVD.
- the SiC film 178 of, e.g., a 30 nm-thicknessis formed on the silicon oxide film 176 by, e.g., plasma CVD.
- the silicon oxide film 180 of, e.g., a 900 nm-thicknessis formed on the SiC film 178 by, e.g., plasma CVD.
- the inter-layer insulation film 182 of the layer structure of the silicon oxide film 180 /the SiC film 178 /the silicon oxide film 176 /the SiC film 174is formed (see FIG. 12A ).
- the SiC films 174 , 178function as the etching stopper film and the Cu diffusion preventing film.
- the structure below the SiC film 174is omitted.
- the silicon nitride film 254 of, e.g., a 50 nm-thicknessis formed on the silicon oxide film 180 by, e.g., CVD.
- the silicon nitride film 254functions as the ARC film in the following photolithography step.
- a photoresist film 256 for exposing the region for the via hole 184 to be formed in the silicon oxide film 176 and the SiC film 174is formed on the silicon nitride film 254 by photolithography (see FIG. 12B ).
- the silicon nitride film 254 , the silicon oxide film 180 , the SiC film 178 and the silicon oxide film 176are sequentially etched under suitably changed conditions.
- the via hole 184is formed in the silicon oxide film 176 (see FIG. 12C ).
- the photoresist film 256is removed.
- the resin 258 on the silicon nitride film 254is removed by ashing using, e.g., O 2 plasma, and the resin 258 in the via hole 184 is etched back to a prescribed height until, for example, the upper surface of the resin 258 is positioned near the border between the SiC film 178 and the silicon oxide film 180 (see FIG. 12D ).
- a photoresist film 260 for exposing the region for the interconnection trenches 186 a , 186 b to be formed in the inter-layer insulation film 182is formed on the silicon nitride film 254 by photolithography (see FIG. 13A ).
- the photoresist film 260is formed of a material which does not mix with the resin 258 and whose developer does not solve the resin 258 .
- the silicon nitride film 254 and the silicon oxide film 180are sequentially etched.
- the interconnection trenches 186 a , 186 bare formed in the silicon oxide film 180 (see FIG. 13B ).
- the interconnection trenches 186 a , 186 bare formed in an interconnection pattern of a larger pitch than the interconnection patterns of the interconnection trenches of the lower interconnection part 12 and the intermediate interconnection part 14 .
- the photoresist film 260 and the resin 258 in the via hole 184are removed by ashing using, e.g., O 2 plasma and CF 4 plasma.
- the SiC film 178 at the bottoms of the interconnection trenches 186 a , 186 b and the SiC film 174 at the bottom of the via hole 184are etched to open the interconnection trenches 186 a , 186 b down to the silicon oxide film 176 and open the via hole 184 down to the interconnection layer 172 a .
- the silicon nitride film 154 on the silicon oxide film 180is also etched off (see FIG. 13C ).
- the barrier metal layer 188 of a Ta film of, e.g., 25 nm-thickness and a Cu film of, e.g., a 150 nm-thicknessare continuously deposited on the entire surface by, e.g., sputtering.
- preprocessingsuch as Ar (argon) sputtering, H 2 plasma processing, H 2 annealing, etc., may be performed in-situ.
- a Cu filmis further deposited by electrolytic plating to form the Cu film 190 of, e.g., a 1.5 ⁇ m-total thickness (see FIG. 13D ).
- the Cu film 190 and the barrier metal layer 188 of the Ta filmare polished off flat by CMP (see FIGS. 14A and 14B ).
- CMPCMP
- the upper interconnection part 16 having the two-layer multilayer interconnection structureis formed on the intermediate interconnection part 14 .
- the interconnection layer 192 a , 192 b and the interconnection layer 212 a , 212 bare formed in interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers of the lower interconnection part 12 and the intermediate interconnection part 14 .
- the interconnection layer 192 a , 192 b and the interconnection layer 212 a , 212 bare formed in the interconnection patterns of respectively, e.g., a 0.84 ⁇ m pitch.
- the SiC film 214 of, e.g., a 70 nm-thicknessis formed by, e.g., plasma CVD.
- the silicon oxide film 216 of, e.g., a 600 nm-thicknessis formed on the SiC film 214 by, e.g., plasma CVD.
- the inter-layer insulation film 218 of the layer structure of the silicon oxide film 216 /the SiC film 214is formed (see FIG. 15A ).
- the contact holes 220are formed in the silicon oxide film 216 and the SiC film 214 down to the interconnection layer 212 a of the upper interconnection part 16 by photolithography and dry etching.
- a TiN film of, e.g., a 50 nm-thickness and a W film of, e.g., a 300 nm-thicknessare formed by, e.g., CVD.
- the W film and the TiN filmare removed flat by, e.g., CMP until the surface of the silicon oxide film 216 is exposed to form the contact plugs 222 of the TiN film and the W film are formed, buried in the contact holes 220 (see FIG. 15B ).
- a metal filmis formed by, e.g., CVD.
- the metal filmmay be formed of, e.g., a TiN film, an Al (aluminum) film and a TiN film laid sequentially.
- the metal filmis patterned to form the electrode 224 connected to the contact plugs 222 (see FIG. 15C ).
- the silicon oxide film 226 a of, e.g., a 1400 nm-thickness and the silicon nitride film 226 b of, e.g., a 500 nm-thicknessare sequentially formed by, e.g., CVD on the inter-layer insulation film 218 with the electrode 224 formed on to form the cover film 226 of the layer film of the silicon oxide film 226 a and the silicon nitride film 226 b (see FIG. 16A ).
- the opening 228is formed in the cover film 226 down to the electrode 224 by photolithography and dry etching (see FIG. 16B ).
- the semiconductor device shown in FIG. 1is fabricated.
- the lower interconnection part 12 and the intermediate interconnection part 14include low-k films as the inter-layer insulation films, and in the lower interconnection part 12 , in which the interconnection layers have the interconnection patterns of a smaller pitch than the interconnection patterns of the interconnection layers of the intermediate interconnection part 14 , the hydrophilic insulation film of silicon oxide film is formed on the low-k film, but in the intermediate interconnection part 14 , in which the interconnection layers have the interconnection patterns of a larger pitch of the interconnection patterns of the interconnection layers of the lower interconnection part 12 , the SiC film functioning as the diffusion preventing film is formed directly on the low-k film, without any hydrophilic insulation film formed, whereby, corresponding to the functions of the interconnection layers of the multilayer interconnection structure, the lower interconnection part 12 , in which the interconnection layers are formed in the interconnection patterns of a smaller pitch than the interconnection pattern of the interconnection layers of the intermediate interconnection part 14 , can suppress the occurrence of defects due to the foreign matter adhe
- SiOC filmis used as the low-k film.
- the low-k filmis not limited to SiOC film and can be any film of flow-k material.
- the film of SiLK (registered trademark) by The Dow Chemical Company, FLARE (registered trademark) by Honeywell Electronic Materials, or BCB (benzocyclobutene), etc., for example, other than SiOCcan be used.
- Porous silicon oxide film having fine pores thereincan be also used as the low-k film.
- the hydrophilic insulation film formed on the low-k filmsilicon oxide film is used.
- the hydrophilic insulation filmis not limited to silicon oxide film and can be, e.g., FSG film other than silicon oxide film.
- SiC filmis used as the film functioning as the etching stopper film and the Cu diffusion preventing film.
- the film functioning as the etching stopper film and the Cu diffusion preventing filmis not limited to SiC film.
- silicon nitride film, for example, other than SiC filmcan be used other.
- the interconnection layersare formed by filling the barrier metal layer of Ta film and the Cu film in the via holes and the interconnection trenches.
- the interconnection layerscan be formed by burying various conductor films other than Ta film and Cu film.
- Major materials of the interconnection layerscan be various conductors, such as Al, etc., other than Cu.
- the barrier metal layer for preventing the diffusion of metalcan be formed of, e.g., TaN (tantalum nitride) film, Ti (titanium) film, TiN (titanium nitride) film, etc. other than Ta film.
- five interconnection layersare formed in the lower interconnection part 12
- two interconnection layersare formed in the intermediate interconnection part 14
- two interconnection layersare formed in the upper interconnection part 16 .
- numbers of the layers of the respective interconnection partscan be suitably designed as required.
- Ta film and Cu filmare concurrently buried in the via holes and the interconnection trenches by dual damascene process.
- the inter-layer insulation film of the low-k film and the hydrophilic insulation film formed on the low-k filmis formed, and the via hole is formed in the inter-layer insulation film.
- the conductor filmis buried in the via hole.
- the hydrophilic insulation filmis exposed on the surface after the conductor film has been buried in the via hole, which allows the lift-off of the foreign matter to be sufficiently performed by HF processing, and the generation of water marks, which are causes for corrosion can be suppressed.
- the conductor filmis buried in the interconnection trenches and the via holes interconnecting the interconnection layers.
- the present inventionis applicable to burying a conductor film in various openings, as of dummy patterns, etc.
- the interconnection patterns of the interconnection layers of the same interconnection partare in the same pitch.
- the pitches of the interconnection patterns of the interconnection layers of the same interconnection partcan be varied suitably as required as long as a minimum pitch of the interconnection patterns of the interconnection layers of the intermediate interconnection part 14 is larger than a minimum pitch of interconnection patterns of the interconnection layers of the lower interconnection part 12 .
- a minimum pitch of the interconnection patterns of the interconnection layers of the upper interconnection part 16may be larger than the minimum pitch of the interconnection patterns of the interconnection layer of the lower interconnection part 12 and the intermediate interconnection part 14 .
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Abstract
Description
- This application is a divisional of Ser. No. 10/816,955, filed on Apr. 5, 2004, which is based upon and claims priority of Japanese Patent Application No. 2003-372304, filed on Oct. 31, 2003, the contents being incorporated herein by reference.
- The present invention relates to a semiconductor device having a multilayer interconnection structure and a method for fabricating the semiconductor device, more specifically a semiconductor device having a multilayer interconnection structure using low dielectric constant (low-k) films as the inter-layer insulation films and a method for fabricating the semiconductor device.
- The recent increasing micronization of semiconductor devices requires decrease of the interconnection resistance and interconnection capacitance of the semiconductor devices.
- To meet such requirement, the main material of the interconnections is shifting from Al (aluminum) to Cu (copper) having lower relative resistance and better electromigration characteristics. Accompanying the shift of the major material of the interconnections to Cu, the process for forming the interconnections is shifting from the processing of depositing the interconnection materials and patterning them by lithography and dry etching as of RIE (Reactive Ion Etching) or others to the so-called damascene process (refer to, e.g., Japanese Patent Application Unexamined Publication No. 2001-298084). In the damascene process, trench patterns and hole patterns are formed in the interconnection insulation films, and the interconnection material is buried in the trenches and holes. The shift of the forming process to the damascene process accompanying the shift of the interconnection material to Cu is because Cu is difficult to process by RIE, while Al is not.
- As the materials of the inter-layer insulation films for the insulation between the interconnections, SiO2, FSG (fluorinated silicate glass), etc. have been so far used.
- As a countermeasure to the interconnection delay due to the recent micronization, decrease of the interconnection resistance and interconnection capacitance is required. However, it is difficult to further lower the resistance of the interconnections formed of Cu as the major material. It is being studied to use as the inter-layer insulation films low-k films whose dielectric constants are lower than silicon oxide film and silicon nitride film to thereby decrease the interconnection capacitance.
- As semiconductor elements are increasingly micronized, a number of transistors to be mounted on a chip is on increase and is even 100M pieces. The interconnection layers interconnecting the transistors and supplying power sources are required to have various functions. That is, the source interconnections are required to be the interconnections of low resistance for making the voltage decreases small. The interconnections interconnecting short distances are required to be micronized interconnections for higher circuit densities. The interconnections interconnecting circuit blocks are required to have lower resistance than the micronized interconnections and have pitches whish are more micronized than the upper interconnection layers.
- In the multilayer interconnection structure of semiconductor devices, in order to satisfy such various requirements of these interconnection layers, interconnection layer parts each formed of a plurality of layers and divided in functions, such as a lower layer interconnection which can define micronized pitches, an intermediate layer interconnection used as the interconnections among circuit blocks, and an upper layer interconnection used as source interconnections, clock interconnection, etc., are put together.
FIG. 17 is a sectional view of a semiconductor device having the conventional multilayer interconnection structure, which shows the structure thereof.- A
device isolation film 302 for defining a device region is formed on asilicon substrate 300. A MOS transistor including agate electrode 304 and source/drain diffusedlayers 306 is formed in the device region of thesilicon substrate 300. - An
inter-layer insulation film 310 with acontact plug 308 buried in is formed on thesilicon substrate 300 with the MOS transistor formed on. - On the
inter-layer insulation film 310 with thecontact plug 308 buried in, aninter-layer insulation film 312 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the region of theinter-layer insulation film 312, which includes thecontact plug 308, aninterconnection layer 314aof a barrier metal layer of a Ta (tantalum) film and a Cu (copper) film is buried, connected to thecontact plug 308. Aninterconnection layer 314bof the barrier metal layer of the tantalum film and the Cu film is buried in the other region of theinter-layer insulation film 312. - On the
inter-layer insulation film 312 with theinterconnection layers inter-layer insulation film 316 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. Aninter-layer insulation film 318 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of theinter-layer insulation films interconnection layer 314a, aninterconnection layer 320aof a barrier metal layer of a tantalum film, and a Cu film is buried, connected to theinterconnection layer 314awith the via portion buried in theinter-layer insulation film 316 and with the interconnection portion buried in theinter-layer insulation film 318. In the region of theinter-layer insulation film 318 over theinterconnection layer 314b, aninterconnection layer 320bof a barrier metal layer of a tantalum film, and a Cu film is buried. - On the
interconnection layer 318 with theinterconnection layers inter-layer insulation film 322 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. On theinter-layer insulation film 322, aninter-layer insulation film 324 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of theinter-layer insulation films interconnection layer 320a, aninterconnection layer 326aof a barrier metal layer of a tantalum film, and a Cu film is buried, connected to theinterconnection layer 320awith the via portion buried in theinter-layer insulation film 322 and with the interconnection portion buried in theinter-layer insulation film 324. In the region of theinter-layer insulation film 324 over theconnection layer 320b, aninterconnection layer 326bof a barrier metal layer of a tantalum film, and a Cu film is buried. - On the
interconnection layer 324 with theinterconnection layers inter-layer insulation film 328 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. On theinter-layer insulation film 328, an inter-layer insulation film330 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of theinter-layer insulation films 328,330 on theinterconnection layer 326a, aninterconnection layer 332aof a barrier metal layer of a tantalum film, and a Cu film is buried, connected to theinterconnection layer 326awith the via portion buried in theinter-layer insulation film 328 and with the interconnection portion buried in the inter-layer insulation film330. In the region of the inter-layer insulation film330 over theconnection layer 326b, aninterconnection layer 332bof a barrier metal layer of a tantalum film, and a Cu film is buried. - Thus, the lower interconnection part having the four-layer multilayer interconnection structure of the
interconnection layers interconnection layers interconnection layers interconnection layers silicon substrate 300. - On the interconnection layer330 with the
interconnection layers inter-layer insulation film 334 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. On theinter-layer insulation film 334, aninter-layer insulation film 336 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of theinter-layer insulation films interconnection layer 332a, aninterconnection layer 338aof a barrier metal layer of a tantalum film, and a Cu film is buried, connected to theinterconnection layer 332awith the via portion buried in theinter-layer insulation film 334 and with the interconnection portion buried in theinter-layer insulation film 336. In the region of theinter-layer insulation film 336 over theconnection layer 332b, aninterconnection layer 338bof a barrier metal layer of a tantalum film, and a Cu film is buried. - On the
interlayer insulation film 336 with theinterconnection layers inter-layer insulation film 340 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. On theinter-layer insulation film 340, aninter-layer insulation film 342 is formed of a silicon nitride film and one of a silicon oxide film or an FSG film laid on the silicon nitride film. In the regions of theinter-layer insulation films interconnection layer 338a, aninterconnection layer 344aof a barrier metal layer of a tantalum film, and a Cu film is buried, connected to theinterconnection layer 338awith the via portion buried in theinter-layer insulation film 340 and with the interconnection portion buried in theinter-layer insulation film 342. In the region of theinter-layer insulation film 342 over theconnection layer 338b, aninterconnection layer 344bof a barrier metal layer of a tantalum film, and a Cu film is buried. - Thus, the upper interconnection part having the two-layer multilayer interconnection structure of the
interconnection layers interconnection layers interconnection layers interconnection layer interconnection layer interconnection layers - On the
inter-layer insulation film 342 with theinterconnection layers inter-layer insulation film 346 is formed of a silicon oxide film laid on a silicon nitride film. Contactplugs 348 are buried in theinter-layer insulation film 346. - On the region of the
inter-layer insulation film 346 containing thecontact plugs 348, anelectrode 350 is formed, connected to theinterconnection layer 344athrough thecontact plugs 348. - On the
inter-layer insulation film 346 with theelectrode 350 formed on, acover film 352 is formed of asilicon nitride film 352aformed on asilicon oxide film 352b. Anopening 354 is formed in thecover film 352 down to theelectrode 350. - In the case that the interconnection layers are divided in terms of functions as described above, the structures of the respective interconnection layers are changed in accordance with required characteristics.
- For example, the lower layer interconnections are formed at small pitches, and to decrease the interconnection capacitance, film thicknesses of the interconnection layers are made small. In order to decrease the interconnection capacitance, materials of the inter-layer insulation films must be low-k materials.
- On the other hand, the upper layer interconnections are formed at larger interconnection pitches so as to allow the interconnections to be formed in a thicker thickness. The interconnection capacitance does not critically matter in the upper interconnection layers, which permits silicon oxide film to be used as the inter-layer insulation films.
- The intermediate layer interconnections are required to have characteristics which are middle between the lower layer interconnections and the upper layer interconnections described above. At this time, the intermediate layer interconnections, which interconnect the circuit blocks, have the interconnection length larger than the lower layer interconnections, and the resistance must be made low. Accordingly, the thickness of the interconnection is larger than the lower layer interconnections, and the pitch of the interconnections is larger. The interconnection capacitance increase due to the thick interconnections must be suppressed, and to this end, low-k materials must be used as the material of the inter-layer insulation films.
- However, when low-k films are used as the inter-layer insulation films in place of silicon oxide film, etc. for the end of decreasing the interconnection capacitance in the lower layer interconnections and the intermediate layer interconnections, an inconvenience that defects easily take place in the interconnections, which lowers the yield, and others have happened.
- An object of the present invention is to provide a semiconductor device using low-k films as the inter-layer insulation films of the multilayer interconnection structure, which can achieve the suppression of the defect occurrence and the decrease of the interconnection capacitance corresponding to the functions of the interconnections, and a method for fabricating the semiconductor device.
- According to one aspect of the present invention, there is provided a semiconductor device comprising: a first inter-layer insulation film formed over a substrate and including a first low dielectric constant film and a hydrophilic insulation film formed on the first low dielectric constant film; a first interconnection layer buried in a first interconnection trench formed in the first inter-layer insulation film, whose minimum interconnection pitch is a first pitch; a second inter-layer insulation film formed over the first inter-layer insulation film and including a second low dielectric constant film; a second interconnection layer buried in a second interconnection trench formed in the second inter-layer insulation film, whose minimum interconnection pitch is a second pitch larger than the first pitch; and a diffusion preventing film formed directly on the second low dielectric constant film and the second interconnection layer.
- According to another aspect of the present invention, there is provided a semiconductor device comprising: a first multilayer interconnection layer formed over a substrate and including a plurality of interconnection layers whose minimum interconnection pitch is a first pitch; and a second multilayer interconnection layer formed over the first multilayer interconnection layer and including a plurality of interconnection layers whose minimum interconnection pitch is a second pitch larger than the first pitch, at least one of said plurality of interconnection layers forming the first multilayer interconnection layer being buried in an opening formed in a first inter-layer insulation film including a first low dielectric constant film and a hydrophilic insulation film formed on the first low dielectric constant film, the respective plurality of interconnection layers forming the second multilayer interconnection layer being buried in an opening formed in a second inter-layer insulation film including a diffusion preventing film and a second low dielectric constant film formed on the diffusion preventing film, and the diffusion preventing film of one second inter-layer insulation film being formed directly on the second low dielectric constant film of another second inter-layer insulation film underlying said one second inter-layer insulation film.
- According to further another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming over a substrate a first inter-layer insulation film including a first low dielectric constant film and a first hydrophilic insulation film formed on the first low dielectric constant film; forming a first interconnection trench in the first inter-layer insulation film; forming a first conductor film on the first inter-layer insulation film with the first interconnection trench formed in; polishing the first conductor film to expose the first hydrophilic insulation film while burying the first conductor film in the first interconnection trench to form a first interconnection layer whose minimum interconnection pitch is a first pitch; forming a second inter-layer insulation film including a second low dielectric constant film over the first inter-layer insulation film; forming a second interconnection trench in the second inter-layer insulation film; forming a second conductor film on the second inter-layer insulation film with the second interconnection trench formed in; and polishing the second conductor film to expose the second low dielectric constant film while burying the second conductor film in the second interconnection trench to form a second interconnection layer whose minimum interconnection pitch is a second pitch larger than the first pitch.
- As described above, the semiconductor device according to the present invention comprises: a first inter-layer insulation film formed over a substrate and including a first low dielectric constant film and a hydrophilic insulation film formed on the first low dielectric constant film; a first interconnection layer buried in a first interconnection trench formed in the first inter-layer insulation film, whose minimum interconnection pitch is a first pitch; a second inter-layer insulation film formed over the first inter-layer insulation film and including a second low dielectric constant film; a second interconnection layer buried in a second interconnection trench formed in the second inter-layer insulation film, whose minimum interconnection pitch is a second pitch larger than the first pitch; and a diffusion preventing film formed directly on the second low dielectric constant film and the second interconnection layer, whereby in a case that low dielectric constant films are used as the inter-layer insulation films of a multilayer interconnection structure, corresponding to functions of the interconnections, the first interconnection layer can suppress the occurrence of defects and the decreases the interconnection capacitance, while the second interconnection layer can sufficiently decrease the interconnection capacitance.
FIG. 1 is an SEM picture showing corrosion of interconnections due to water marks.FIG. 2 is a sectional view of the semiconductor device according to one embodiment of the present invention, which shows a structure thereof.FIGS. 3A-3E are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part1).FIGS. 4A-4D are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part2).FIGS. 5A-5D are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part3).FIGS. 6A-6C are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part4).FIGS. 7A-7C are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part5).FIGS. 8A-8B are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part6).FIGS. 9A-9D are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part7).FIGS. 10A-10D are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part8).FIGS. 11A-11C are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part9).FIGS. 12A-12D are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part10).FIGS. 13A-13D are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part11).FIGS. 14A-14C are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part12).FIGS. 15A-15C are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part13).FIGS. 16A-16B are sectional views of the semiconductor device according to the embodiment of the present invention in the steps of the method for fabricating the semiconductor device, which show the method (Part14)FIG. 17 is a sectional view of a semiconductor device having the conventional multilayer interconnection structure, which shows the structure thereof.- In order to decrease the interconnection capacitance of semiconductor devices, as described above, the use of low-k materials as materials of the inter-layer insulation films is being studies. As the low-k materials are known SiOC, SILK (registered trademark) by The Dow Chemical Company, FLARE (registered trademark) by Honeywell Electronic Materials, etc. Most of such low-k materials are water-repellent. This is for the following reason. The relative dielectric constant of water is as high as88. Accordingly, when a film formed of a low-k material absorbs humidity, the dielectric constant of the film rises. To suppress the dielectric constant increase due to the humidity absorption, the low-k materials are terminated with Si—H, SiCH3for the processing for prohibiting the formation of Si—OH bonds, which are hydrophilic.
- As mentioned above, in order to suppress the dielectric constant increase due to the humidity absorption, the low-k materials are terminated with hydrogen, methyl or others to be water-repellent. Earnest studies by the inventor of the present invention have made it clear that, as will be described below, in cases that the materials of the inter-layer insulation films of the interconnection layers are low-k materials, it is one of causes for the yield decrease that the low-k materials are made water-repellent.
- The lower interconnections for short-distant interconnections, which are formed at small pitches, are more vulnerable to defects due to foreign matter adhering thereto. Accordingly, it is necessary to lift off the foreign matter by HF (hydrofluoric acid) processing added to the cleaning following the CMP (chemical mechanical polishing) of the damascene process. However, when the wafer surface is made water-repellent by using low-k films made water-repellent as the inter-layer insulation film materials, even the HF processing finds it difficult to remove the foreign matter by the lift-off.
- In addition, when the wafer surface is made water-repellent by the water-repellent low-k films, water marks of water drops remaining after the cleaning and drying tend to take place. Such water marks corrode the interconnections to resultantly cause defects. This is a cause of the yield decrease.
FIG. 1 is an SEM (Scanning Electron Microscope) picture showing the corrosion of the interconnection due to the water marks. - The semiconductor device and the method for fabricating the same according to the present invention suppresses the occurrence of the defects, and realizes the interconnection capacitance decrease, corresponding to the functions of the interconnection layers of a multilayer interconnection structure even when the inter-layer insulation films are formed of such water-repellent low-k films.
- The semiconductor device and the method for fabricating the same according to one embodiment of the present invention will be explained with reference to FIGS.2,3A-3E,4A-4D,5A-5D,6A-6C,7A-7C,8A-8B,9A-9D,10A-10D,11A-11C,12A-12D,13A-13D,14A-14C,15A-15C, and16A-16B.
FIG. 2 is a sectional view of the semiconductor device according to the present embodiment, which shows a structure thereof.FIGS. 3A-3E ,4A-4D,5A-5D,6A-6C,7A-7C,8A-8B,9A-9D,10A-10D,11A-11C,12A-12D,13A-13D,14A-14C,15A-15C, and16A-16B are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which show the method. - Then, the structure of the semiconductor device according to the present embodiment will be explained with reference to
FIG. 2 . - The semiconductor device according to the present embodiment includes a
lower interconnection part 12 formed on asilicon substrate 10, anintermediate interconnection part 14 formed on thelower interconnection part 12 and anupper interconnection part 16 formed on theintermediate interconnection part 14. Thesubstrate 10 additionally has semiconductor devices, such as MOS transistors, etc. formed on. In thelower interconnection part 12, interconnection layers having interconnection patterns of a smaller pitch than interconnection patterns of the interconnection layers formed in, e.g., the intermediatelayer interconnection part 14 and theupper interconnection part 16 are formed, connecting points separated by short distance. In theintermediate interconnection part 14, interconnection layers having interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers formed in, e.g., thelower interconnection part 12, and a smaller pitch than interconnection patterns of the interconnection layers formed in, e.g., theupper interconnection part 16 are formed, connecting circuit blocks. In theupper interconnection part 16, interconnection layers having interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers formed in, e.g., thelower interconnection part 12 and theintermediate interconnection part 14, being utilized as source interconnections and clock interconnections. - A
device isolation film 18 for defining a device region is formed on thesilicon substrate 10. A MOS transistor including agate electrode 20 and source/drain diffusedlayers 22 is formed in the device region of thesilicon substrate 10. - An
inter-layer insulation film 24 of a silicon oxide film is formed on thesilicon substrate 10 with the MOS transistor formed on. - A via
hole 26 is formed in theinter-layer insulation film 24 down to the source/drain diffusedlayer 22, and acontact plug 28 is buried in the viahole 26. - On the
inter-layer insulation film 24 with thecontact plug 28 buried in, aninter-layer insulation film 36 is formed of anSiC film 30, a low-k film 32 of SiOC film formed on theSiC film 30, and ahydrophilic insulation film 34 of silicon oxide film formed on the low-k film 32. Aninterconnection trench 38ais formed in the region of theinter-layer insulation film 36, which includes thecontact plug 28. Aninterconnection layer 44aof abarrier metal layer 40 of Ta (tantalum) film and aCu film 42 is buried in theinterconnection trench 38a, connected to thecontact plug 28. Aninterconnection trench 38bis formed in the other region of thehydrophilic insulation film 34, the low-k film 32 and theSiC film 30. Aninterconnection layer 44bof thebarrier metal 40 of Ta film and theCu film 42 is buried in theinterconnection trench 38b. - On the
inter-layer insulation film 36 with theinterconnection layer inter-layer insulation film 56 is formed of anSiC film 46, a low-k film 48 of SiOC film formed on theSiC film 46, anSiC film 50 formed on the low-k film 48, a low-k film 52 of SiOC film formed on theSiC film 50, and ahydrophilic insulation film 54 of silicon oxide film laid on the low-k film 52. A viahole 58 is formed in the low-k film 48 and theSiC film 46 of theinter-layer insulation film 56 down to theinterconnection layer 44a. Aninterconnection trench 60ais formed in the region of thehydrophilic insulation film 54, the low-k film 52 and theSiC film 50, which includes the viahole 58. In the viahole 58 and theinterconnection trench 60a, aninterconnection layer 66aof abarrier metal layer 62 of Ta film and aCu film 64 buried, connected to theinterconnection layer 44a. Aninterconnection trench 60bis formed in the other region of thehydrophilic insulation film 54, the low-k film 52 and theSiC film 50. In theinterconnection trench 60b, aninterconnection layer 66bof thebarrier metal layer 62 of Ta film and theCu film 64 is buried. - On the
inter-layer insulation film 56 with theinterconnection layer inter-layer insulation film 78 is formed of anSiC film 68, a low-k film 70 of SiOC film formed on theSiC film 68, anSiC film 72 formed on the low-k film 70, a low-k film 74 of SiOC film formed on theSiC film 72, and ahydrophilic insulation film 76 of silicon oxide film laid on the low-k film 74. A viahole 80 is formed in the low-k film 70 and theSiC film 68 of theinter-layer insulation film 78 down to theinterconnection layer 66a. Aninterconnection trench 82ais formed in the region of thehydrophilic insulation film 76, the low-k film 74 and theSiC film 72, which includes the viahole 80. In the viahole 80 and theinterconnection trench 82a, aninterconnection layer 88aof abarrier metal layer 84 of Ta film and aCu film 86 is buried, connected to theinterconnection layer 66a. In the other region of thehydrophilic insulation film 76, the low-k film 74 and theSiC film 72, aninterconnection trench 82bis formed. In theinterconnection trench 82b, aninterconnection layer 88bof thebarrier metal layer 84 of Ta film and theCu film 86 is buried. - On the
inter-layer insulation film 78 with theinterconnection layer inter-layer insulation film 100 is formed of anSiC film 90, a low-k film 92 of SiOC film formed on theSiC film 90, anSiC film 94 formed on the low-k film 92, a low-k film 96 of SiOC film formed on theSiC film 94, and ahydrophilic insulation film 98 of silicon oxide film laid on the low-k film 96. A viahole 102 is formed in the low-k film 92 and theSiC film 90 of theinter-layer insulation film 100 down to theinterconnection layer 88a. Aninterconnection trench 104ais formed in the region of thehydrophilic insulation film 98, the low-k film 96 and theSiC film 94, which includes the viahole 102. In the viahole 102 and theinterconnection trench 104a, aninterconnection layer 110aof abarrier metal layer 106 of Ta film and aCu film 108 is buried, connected to theinterconnection layer 88a. Aninterconnection trench 104bis formed in the other region of thehydrophilic insulation film 98, the low-k film 96 and theSiC film 94. In theinterconnection trench 104b, aninterconnection layer 110bof thebarrier metal 106 of Ta film and theCu film 108 is buried. - On the
inter-layer insulation film 100 with theinterconnection layer inter-layer insulation film 122 is formed of anSiC film 112, a low-k film 114 of SiOC film formed on theSiC film 112, anSiC film 116 formed on the low-k film 114, a low-k film 118 of SiOC film formed on theSiC film 116, and ahydrophilic insulation film 120 of silicon oxide film laid on the low-k film 118. A viahole 124 is formed in the low-k film 114 and theSiC film 112 of theinter-layer insulation film 122 down to theinterconnection layer 110a. Aninterconnection trench 126ais formed in the region of thehydrophilic insulation film 120, the low-k film 118 and theSiC film 116, which includes the viahole 124. In the viahole 124 and theinterconnection trench 126a, aninterconnection layer 132aof abarrier metal layer 128 of Ta film and aCu film 130 is buried, connected to theinterconnection layer 110a. In the other region of thehydrophilic insulation film 120, the low-k film 118 and theSiC film 116, aninterconnection trench 126bis formed. In theinterconnection trench 126b, aninterconnection layer 132bof thebarrier metal layer 128 of Ta film and theCu film 130 is buried. - Thus, the
lower interconnection part 12 having the five-layer multilayer interconnection structure is formed on thesilicon substrate 10. In thelower interconnection part 12, the respective pitches of the interconnection patterns of theinterconnection layer interconnection layer interconnection layer interconnection layer - On the
inter-layer insulation film 122 with theinterconnection layer inter-layer insulation film 142 is formed of anSiC film 134, a low-k film 136 of SiOC film formed on theSiC film 134, anSiC film 138 formed on the low-k film 136, and a low-k film 140 of SiOC film laid on theSiC film 138. A viahole 144 is formed in the low-k film 136 and theSiC film 134 of theinter-layer insulation film 142 down to theinterconnection layer 132a. Aninterconnection trench 146ais formed in the region of the low-k film 140 and theSiC film 138, which includes the viahole 144. In the viahole 144 and theinterconnection trench 146a, aninterconnection layer 152aof abarrier metal layer 148 of Ta film and aCu film 150 is buried, connected to theinterconnection layer 132a. In the other region of the low-k film 140 and theSiC film 138, aninterconnection trench 146bis formed. Aninterconnection layer 152bof thebarrier metal layer 148 of Ta film and theCu film 150 is buried in theinterconnection trench 146b. - On the
inter-layer insulation film 142 with theinterconnection layer inter-layer insulation film 162 is formed of anSiC film 154, a low-k film 156 of SiOC film formed on theSiC film 154, anSiC film 158 formed on the low-k film 156, and a low-k film 160 of SiOC film laid on theSiC film 158. A viahole 164 is formed in the low-k film 156 and theSiC film 154 of theinter-layer insulation film 162 down to theinterconnection layer 152a. Aninterconnection trench 166ais formed in the region of the low-k film 160 and theSiC film 158, which includes the viahole 164. In the viahole 164 and theinterconnection trench 166a, aninterconnection layer 172aof abarrier metal layer 168 of Ta film and aCu film 170 is buried, connected to theinterconnection layer 152a. In the other region of the low-k film 160 and theSiC film 158, aninterconnection trench 166bis formed. Aninterconnection layer 172bof thebarrier metal layer 168 of Ta film and theCu film 170 is buried in theinterconnection trench 166b. - Thus, on the
lower interconnection part 12, theintermediate interconnection part 14 having the two-layer multilayer interconnection structure is formed. In theintermediate interconnection part 14, the respective pitches of the interconnection patterns of theinterconnection layer interconnection layer lower interconnection part 12. For example, the pitches of the interconnection patterns of theinterconnection layer interconnection layer lower interconnection part 12. - On the
inter-layer insulation film 162 with theinterconnection layer inter-layer insulation film 182 is formed of anSiC film 174, asilicon oxide film 176 formed on theSiC film 174, anSiC film 178 formed on thesilicon oxide film 176, and asilicon oxide film 180 laid on theSiC film 178. A viahole 184 is formed in thesilicon oxide film 176 and theSiC film 174 of theinter-layer insulation film 182 down to theinterconnection layer 172a. Aninterconnection trench 186ais formed in the region of thesilicon oxide film 180 and theSiC film 178, which includes the viahole 184. In the viahole 184 and theinterconnection trench 186a, aninterconnection layer 192aof abarrier metal layer 188 of Ta film and aCu film 190 is buried, connected to theinterconnection layer 172a. In the other region of thesilicon oxide film 180 and theSiC film 178, aninterconnection trench 186bis formed. Aninterconnection layer 192bof thebarrier metal layer 188 of Ta film and theCu film 190 is buried in theinterconnection trench 186b. - On the
inter-layer insulation film 182 with theinterconnection layer inter-layer insulation film 202 is formed of anSiC film 194, asilicon oxide film 196 formed on theSiC film 194, anSiC film 198 formed on thesilicon oxide film 196, and asilicon oxide film 200 laid on theSiC film 198. A viahole 204 is formed in thesilicon oxide film 196 and theSiC film 194 of theinter-layer insulation film 202 down to theinterconnection layer 192a. Aninterconnection trench 206ais formed in the region of thesilicon oxide film 200 and theSiC film 198, which includes the viahole 204. In the viahole 204 and theinterconnection trench 206a, aninterconnection layer 212aof abarrier metal layer 208 of Ta film and aCu film 210 is buried, connected to theinterconnection layer 192a. In the other region of thesilicon oxide film 200 and theSiC film 198, aninterconnection trench 206bis formed. Aninterconnection layer 212bof thebarrier metal layer 208 of Ta film and theCu film 210 is buried in theinterconnection trench 206b. - Thus, on the
intermediate interconnection part 14, theupper interconnection part 16 having the two-layer multilayer interconnection structure is formed. In theupper interconnection part 16, the pitches of the interconnection patterns of theinterconnection layer interconnection layer lower interconnection part 12 and theintermediate interconnection part 14 and are respectively, e.g., 0.84 μm. - On the
inter-layer insulation film 202 with theinterconnection layer inter-layer insulation film 218 comprising aSiC film 214 formed on asilicon oxide film 216 is formed. Viaholes 220 are formed in theinter-layer insulation film 218 down to theinterconnection layer 212a. Contact plugs222 are buried in the via holes220. - On the region of the
inter-layer insulation film 218, which includes the contact plugs222, anelectrode 224 is formed, connected to theinterconnection layer 212athrough the contact plugs222. - On the
inter-layer insulation film 218 with theelectrode 224 formed on, acover film 226 is formed comprising asilicon nitride film 226bformed on asilicon oxide film 226a. Anopening 228 is formed in thecover film 226 down to theelectrode 224. - Thus, the semiconductor device according to the present embodiment is constituted.
- The semiconductor device according to the present embodiment is characterized mainly in that the
lower interconnection part 12 and theintermediate interconnection part 14 include low-k films of SiOC film as the inter-layer insulation films, and in thelower interconnection part 12, in which the interconnection layers formed in the interconnection patterns of a smaller pitch than the interconnection patterns of the interconnection layers of theintermediate interconnection part 14, the hydrophilic insulation film of silicon oxide film is formed on the low-k film, but in theintermediate interconnection part 14, in which the interconnection layers has the interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers of thelower interconnection part 12, the SiC film functioning as the diffusion preventing film is formed directly on the low-k film, without any hydrophilic insulation film formed. - The
lower interconnection part 12, in which the interconnection patterns of the interconnection layers has a smaller pitch is more vulnerable to defects due to foreign matter adhering thereto. In suchlower interconnection part 12, after the interconnection layer has been buried by CMP (Chemical Mechanical Polishing) or others, the hydrophilic insulation film, which is formed on the low-k film, is exposed on the surface. The hydrophilic insulation film, which is not water-repellent low-k film, is exposed, whereby foreign matter can be sufficiently removed by lift-off by HF processing following the polish by CMP or others. The exposure of the hydrophilic insulation film, which is not the water repellent low-k film, can suppress the generation of water marks due to water drops which are cause for corrosion of the interconnection layers after cleaning and drying following the polish by CMP or others. Thus, the use of the low-k film as the inter-layer insulation films in thelower interconnection part 12, which is more vulnerable to defects due to adhering foreign matter can decrease the interconnection capacitance, suppressing the occurrence of defects. - On the other hand, the interconnection layers of the
intermediate interconnection part 14 are used as the interconnection layers interconnecting circuit blocks. Accordingly, it is necessary that the interconnection layers of theintermediate interconnection part 14 have the interconnection resistance decreased and has the interconnection patterns of the pitch which is, e.g., 1.5-3 times the pitch of the interconnection patterns of the interconnection layers of thelower interconnection part 12. Theintermediate interconnection part 14 having such large interconnection pattern pitch is less vulnerable to defects due to foreign matter adhering thereto than thelower interconnection part 12. Accordingly, even without removing the foreign matter by lift-off by HF processing following CMP, the yield is little affected. It is not necessary to leave the hydrophilic insulation film on the low-k film. Thus, in theintermediate interconnection part 14, the SiC film functioning the diffusion preventing film is formed directly on the low-k film, and the hydrophilic insulation film, whose dielectric constant is higher than that of the low-k film, is not formed. Accordingly, the low-k film is used as the inter-layer insulation films, whereby the interconnection capacitance can be sufficiently decreased. - The interconnection layers of the
upper interconnection part 16 are used as source interconnections and clock interconnections, and have interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers of thelower interconnection part 12 and theintermediate interconnection part 14. Accordingly, theupper interconnection part 16 is less required to have the interconnection capacitance decreased by using the low-k film, as are thelower interconnection part 12 and theintermediate interconnection part 14. Accordingly, in theupper interconnection part 16, silicon oxide film, whose dielectric constant is higher than low-k film, is used. As the inter-layer insulation films of theupper interconnection part 16, in addition to silicon oxide film, FSG (Fluorinated Silicate Glass) film or others may be used. - As described above, in the semiconductor device according to the present embodiment, corresponding to the functions of the interconnection layers of the multilayer interconnection structure, in the
lower interconnection part 12, where the interconnection layers have the interconnection patterns of a smaller pitch than the interconnection patterns of the interconnection layers of theintermediate interconnection part 14, the occurrence of defects due to the adhesion of foreign matter is suppressed and the interconnection capacitance is decreased, and in theintermediate interconnection part 14, where the interconnection layers have the interconnection patterns of a larger pitch than the interconnection pattern of the interconnection layers of thelower interconnection part 12, the interconnection capacitance can be sufficiently decreased. - Then, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to
FIGS. 3A-3E ,4A-4D,5A-5D,6A-6C,7A-7C,8A-8B,9A-9D,10A-10D,11A-11C,12A-12D,13A-13D,14A-14C,15A-15C, and16A-16B.FIGS. 3A-3E ,4A-4D,5A-5D,6A-6C,7A-7C, and8A-8B are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which show the steps of fabricating thelower interconnection part 12.FIGS. 9A-9D ,10A-10D, and11A-11C are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which show the steps of fabricating theintermediate interconnection part 14.FIGS. 12A-12D ,13A-13D,14A-14C,15A-15C, and16A-16B are sectional views of the semiconductor device according to the present embodiment in the steps of the method for fabricating the semiconductor device, which show the steps of fabricating theupper interconnection part 16, the electrode, etc. - The
device isolation film 18 for defining a device region is formed on thesilicon substrate 10 by, e.g., STI (Shallow Trench Isolation). - Next, on the
silicon substrate 10 with thedevice isolation film 18 formed on, a MOS transistor including thegate electrode 20 and the source/drain diffusedlayers 22 is formed in the same way as in, e.g., the usual MOS transistor fabricating method (seeFIG. 3A ). On thesilicon substrate 10, not only MOS transistors but also various semiconductor devices can be fabricated. - Next, the
inter-layer insulation film 24 of a silicon oxide film of, e.g., a 700 nm-thickness is formed by, e.g., CVD (Chemical Vapor Deposition) on thesilicon substrate 10 with the MOS transistor formed on. - Next, the surface of the
inter-layer insulation film 24 is polished by, e.g., CMP until the film thickness of theinter-layer insulation film 24 becomes, e.g., 400 nm to thereby flatten the surface of the inter-layer insulation film24 (seeFIG. 3B ). - Then, the
contact hole 26 is formed in theinter-layer insulation film 24 by photolithography and dry etching down to thesilicon substrate 10. - Next, a Ti (titanium) film of, e.g., a 10 nm-thickness, a TiN (titanium nitride) film of, e.g., a10 nm-thickness and a W (tungsten) film of, e.g., a 300 nm-thickness are formed by, e.g., CVD.
- The W film, the TiN film and the Ti film are removed flat by, e.g., CMP until the surface of the
inter-layer insulation film 24 is exposed to thereby form thecontact plug 28 of the Ti film, the TiN film and the W film buried in the contact hole26 (seeFIG. 3C ). - Then, on the
inter-layer insulation film 24 with thecontact plug 28 buried in, theSiC film 30 of, e.g., a 30 nm-thickness is formed by, e.g., plasma CVD. - Next, the low-
k film 32 of an SiOC film of, e.g., a 200 nm-thickness is formed on theSiC film 30 by, e.g., plasma CVD. - Then, the
hydrophilic insulation film 34 of a silicon oxide film, of e.g., a 100 nm-thickness is formed on the low-k film 30 by, e.g., plasma CVD using TEOS (tetraethyoxysilane) as the main material. Thehydrophilic insulation film 34 is formed in a larger film thickness than thehydrophilic insulation film 244 to be formed in theintermediate interconnection part 14, which will be described later. - Thus, the
inter-layer insulation film 36 of the layer structure of thehydrophilic insulation film 34/the low-k film 32/theSiC film 30 is formed (seeFIG. 3D ). TheSiC film 30 functions as the etching stopper film and the Cu diffusion preventing film. - Next, the
silicon nitride film 232 of, e.g., a 50 nm-thickness is formed on thehydrophilic insulation film 34 by, e.g., CVD. Thesilicon nitride film 232 functions as the ARC (Anti-reflection Coating) film in the following photolithography step. - Then, a
photoresist film 234 for exposing regions for theinterconnection trenches inter-layer insulation film 36 are formed on thesilicon nitride film 232 by photolithography (seeFIG. 3E ). - Then, with the
photoresist film 234 as a mask and theSiC film 30 as a stopper, thesilicon nitride film 232, thehydrophilic insulation film 34 and the low-k film 32 are sequentially etched. Thus, theinterconnection trenches hydrophilic insulation film 34 and the low-k film32 (seeFIG. 4A ). - Then, after the
photoresist film 234 has been removed, theSiC film 30 on the bottoms of theinterconnection trenches interconnection trenches inter-layer insulation film 24. At this time, thesilicon nitride film 232 on thehydrophilic insulation film 34 is also etched off (seeFIG. 4B ). - Next, the
barrier metal layer 40 of a Ta film of, e.g., 10 nm-thickness and the Cu film of, e.g., a 100 nm-thickness are continuously formed on the entire surface by, e.g., sputtering. - Then, with the Cu film formed on the
barrier metal layer 40 as a seed, a Cu film is further deposited by electrolytic plating to form theCu film 42 of, e.g., a 1.0 μm-total film thickness (seeFIG. 4C ). - Then, the
Cu film 42 and thebarrier metal layer 40 of the Ta film are polished off flat by CMP to thereby form theinterconnection layer 44aburied in theinterconnection trench 38aand theinterconnection layer 38bburied in theinterconnection trench 38b. At this time, first, theCu film 42 is selectively polished under conditions which provide a sufficient selectivity for thebarrier metal layer 40 of Ta film, and the polish is stopped at the surface of the barrier metal layer (seeFIG. 4D ). Subsequently, the polishing conditions are suitably reset to polished thebarrier metal layer 40 of Ta film to expose the hydrophilic insulation film34 (seeFIG. 5A ). The polishing conditions by CMP are thus set to thereby facilitate controlling the over-polish amount of thehydrophilic insulation film 34 of the silicon oxide film below thebarrier metal layer 40. Resultantly, after theCu film 42 and thebarrier metal layer 40 have been removed, thehydrophilic insulation film 34 can be easily set in a required film thickness. The film thickness of thehydrophilic insulation film 34 after the removal of theCu film 42 and thebarrier metal layer 40 is, e.g., 50 nm. - Thus are formed the
interconnection layer 44aburied in theinterconnection trench 38aand including thebarrier metal layer 40 of the Ta film for preventing the diffusion of the Cu, and theCu film 42 forming the major part of the interconnection layer, and theinterconnection layer 44bburied in theinterconnection trench 38band including thebarrier metal layer 40 of the Ta film for preventing the diffusion of the Cu, and theCu film 42 forming the major part of the interconnection layer (seeFIG. 5A ). - After the
interconnection layer hydrophilic insulation film 34, not the water-repellent low-k film 32, which is exposed on the surface, the foreign matter can be sufficiently removed by the lift-off. The exposure of thehydrophilic insulation film 34, not the water-repellent low-k film 32, can suppress the occurrence of water marks due to water drops, which cause corrosion of the interconnection layers after cleaned and dried. - Next, the
SiC film 46 of, e.g., a 50 nm-thickness is formed by, e.g., plasma CVD on theinter-layer insulation film 36 with the interconnection layers44a,44bburied in. - Next, the low-
k film 48 of a SiOC film of, e.g., a 250 nm-thickness is formed on theSiC film 46 by, e.g., plasma CVD. - Then, the
SiC film 50 of, e.g., a 30 nm-thickness is formed on the low-k film 48 by, e.g., plasma CVD. - Next, the low-
k film 52 of an SiOC film of, e.g., a 200 nm-thickness is formed on theSiC film 50 by, e.g., plasma CVD. - Next, the
hydrophilic insulation film 54 of a silicon oxide film of, e.g., a 100 nm-thickness is formed on the low-k film 52 by plasma CVD using, e.g., TEOS as the main material. Thehydrophilic insulation film 54 is formed in a larger film thickness than thehydrophilic insulation film 244 to be formed in theintermediate interconnection part 14, which will be described later. - Thus, the
inter-layer insulation film 56 of the layer structure of thehydrophilic insulation film 54/the low-k film 52/theSiC film 50/the low-k film 48/theSiC film 46 is formed (seeFIG. 5B ). TheSiC films - Then, the
silicon nitride film 236 of, e.g., a 50 nm-thickness is formed on thehydrophilic insulation film 54 by, e.g., CVD. Thesilicon nitride film 236 functions as the ARC film in the following photolithography step. - Next, a
photoresist film 238 for exposing the region for the viahole 58 to be formed in the low-k film 48 and theSiC film 46 is formed on thesilicon nitride film 236 by photolithography (seeFIG. 5C ). - Then, with the
photoresist film 238 as a mask, thesilicon nitride film 236, thehydrophilic insulation film 54, the low-k film 52, theSiC film 50 and the low-k film 48 are sequentially etched under suitably changed conditions. Thus, the viahole 58 is formed in the low-k film46 (seeFIG. 5D ). - After the via
hole 58 has been formed, thephotoresist film 238 is removed. - Then, a
resin 240 is buried in the viahole 58 by, e.g., spin coating. Then theresin 240 on thesilicon nitride film 236 is removed by ashing using, e.g., O2plasma, and theresin 240 in the viahole 58 is etched back to a prescribed height until, for example, the upper surface of theresin 240 is positioned near the border between theSiC film 50 and the low-k film52 (seeFIG. 6A ). - Next, a
photoresist film 242 for exposing the regions for theinterconnection trenches inter-layer insulation film 56 is formed on the silicon nitride film236 (seeFIG. 6B ). At this time, thephotoresist film 242 is formed of a material which does not mix with theresin 240 and whose developer does not solve theresin 240. - Then, with the
photoresist film 242 as a mask and theSiC film 50 as a stopper, thesilicon nitride film 236, thehydrophilic insulation film 54 and the low-k film 52 are sequentially etched. Thus, theinterconnection trenches hydrophilic insulation film 54 and the low-k film52 (seeFIG. 6C ). - Then, the
photoresist film 242 and theresin 240 in the viahole 58 are removed by ashing using, e.g., O2plasma and CF4plasma. - Then under conditions which provide a sufficient selectivity with respect to SiOC film, the
SiC film 50 on the bottoms of theinterconnection trenches SiC film 46 on the bottom of the viahole 58 are etched to open theinterconnection trenches k film 48 and the viahole 58 down to theinterconnection layer 44a. At this time, thesilicon nitride film 236 on thehydrophilic insulation film 54 is also etched off (seeFIG. 7A ). - Next, the
barrier metal layer 62 of a Ta film of, e.g., a 25 nm-thickness and a Cu film of, e.g., a 100 nm-thickness are continuously deposited on the entire surface by, e.g., sputtering. After theinterconnection trenches hole 58 have been formed and before the Ta film is deposited, pre-processing, such as Ar (argon) sputtering, H2plasma processing, H2annealing, etc. may be performed in-situ. - Next, with the Cu film formed on the
barrier metal layer 62 as a seed, a Cu film is further deposited by electrolytic plating to form theCu film 64 of, e.g., a 1.0 μm-total thickness (seeFIG. 7B ). - Then, the
Cu film 64 and thebarrier metal layer 62 of the Ta film is polished off flat by CMP to form theinterconnection layer 66aburied in theinterconnection trench 60aand the viahole 58 and theinterconnection layer 66bburied in theinterconnection trench 60b. At this time, as in forming theinterconnection layer Cu film 64 is selectively polished under conditions which provide sufficient selectivity with respect to thebarrier metal layer 62 of Ta film, and the polish is stopped at the surface of the barrier metal layer62 (seeFIG. 7C ). Subsequently, the polishing conditions are suitably reset to polish thebarrier metal layer 62 of Ta film to expose the hydrophilic insulation film54 (seeFIG. 8A ). The polishing conditions by CMP are thus set to thereby facilitate controlling the over-polish amount of thehydrophilic insulation film 54 of the silicon oxide film below thebarrier metal layer 62. Resultantly, after theCu film 64 and thebarrier metal layer 62 have been removed, thehydrophilic insulation film 54 can be easily set in a required film thickness. The film thickness of thehydrophilic insulation film 54 after the removal of theCu film 64 and thebarrier metal layer 62 is, e.g., 50 nm. - Thus, the
interconnection layer 66aburied in the viahole 58 and theinterconnection trench 60aand including thebarrier metal 62 of Ta film for preventing the diffusion of the Cu and theCu film 64 forming the major part of the interconnection layer, and theinterconnection layer 66bburied in theinterconnection trench 60band including thebarrier metal layer 62 of Ta film for preventing the diffusion of the Cu and theCu film 64 forming the major part of the interconnection layer are formed (seeFIG. 8A ). - After the
interconnection layer hydrophilic insulation film 54, not the water-repellent low-k film 52, which is exposed on the surface, the foreign matter can be sufficiently removed by the lift-off. The exposure of thehydrophilic insulation film 54, not the water-repellent low-k film 52, can suppress the occurrence of water marks due to water drops, which cause corrosion of the interconnection layers after cleaned and dried. - Next, the same steps as shown in
FIGS. 5B toFIG. 8A are repeated to form theinterconnection layer inter-layer insulation film 78, theinterconnection layer 110a,10bburied in theinter-layer insulation film 100 and theinterconnection layer inter-layer insulation film 122. - Thus, the
lower interconnection part 12 having the five-layer multilayer interconnection structure is formed on the silicon substrate10 (seeFIG. 8B ). Theinterconnection layer interconnection layer interconnection layer interconnection layer interconnection layer lower interconnection part 12 are formed in the interconnection patterns of respectively, e.g., a 0.28 μm pitch. - Then, the
SiC film 134 of, e.g., a 70 nm-thickness is formed by, e.g., plasma CVD on theinter-layer insulation film 122 with theinterconnection layer interconnection part 12 buried in. - Then, the low-
k film 136 of an SiOC film of, e.g., a 530 nm-thickness is formed on theSiC film 134 by, e.g., plasma CVD. - Next, the
SiC film 138 of, e.g., a 30 nm-thickness is formed on the low-k film 136 by, e.g., plasma CVD. - Then, the low-
k film 140 of an SiOC film of, e.g., a 400 nm-thickness is formed on theSiC film 138 by, e.g., plasma CVD. - Thus, the
inter-layer insulation film 142 of the layer structure of the low-k film 140/theSiC film 138/the low-k film 136/theSiC film 134 is formed. TheSiC films - Then, the
hydrophilic insulation film 244 of a silicon oxide film of, e.g., a 30 nm-thickness is formed on the low-k film 140 by plasma CVS using, e.g., TEOS as the main material (seeFIG. 9A ). Thehydrophilic insulation film 244 is formed in a smaller thickness than thehydrophilic insulation films lower interconnection part 12. In the drawings ofFIG. 9A and the followers, the structure below theSiC film 134 is omitted. - Next, the
silicon nitride film 246 of, e.g., a 50 nm-thickness is formed on thehydrophilic insulation film 244 by, e.g., CVD. Thesilicon nitride film 246 functions as an ARC film in the following photolithography step. - Then, a
photoresist film 248 for exposing the region for the viahole 144 which is to be formed in the low-k film 136 and theSiC film 134 is formed on thesilicon nitride film 246 by photolithography (seeFIG. 9B ). - Then, with the
photoresist film 248 as a mask, thesilicon nitride film 246, thehydrophilic insulation film 244, the low-k film 140, theSiC film 138 and the low-k film 136 are sequentially etched under suitably changed conditions. Thus, the viahole 144 is formed in the low-k film136 (seeFIG. 9C ). - After the via
hole 144 has been formed, thephotoresist film 248 is removed. - Then, after the
resin 250 has been buried in the viahole 144 by, e.g., spin coating, theresin 250 on thesilicon nitride film 246 is removed by ashing using, e.g., O2plasma, and theresin 250 in the viahole 144 is etched back to a prescribed height until, for example, the upper surface of theresin 250 is positioned near the border between theSiC film 138 and the low-k film140 (seeFIG. 9C ). - Then, a
photoresist film 252 for exposing the regions for theinterconnection trenches inter-layer insulation film 142 is formed on the silicon nitride film246 (seeFIG. 10A ). At this time, thephotoresist film 252 is formed of a material which does not mix with theresin 250 and whose developer does not solve theresin 250. - Then, with the
photoresist film 252 as a mask and theSiC film 138 as a stopper, thesilicon nitride film 246, thehydrophilic insulation film 244 and the low-k film 140 are sequentially etched. Thus, theinterconnection trenches FIG. 10B ). Theinterconnection trenches lower interconnection part 12. - Then, the
photoresist film 252 and theresin 250 in the viahole 144 are removed by ashing using, e.g., O2plasma and CF4plasma. - Next, under conditions which provide a sufficient selectivity with respect to SiOC film, the
SiC film 138 on the bottoms of theinterconnection trenches SiC film 134 on the bottom of the viahole 144 are etched to open theinterconnection trenches k film 136 and the viahole 144 down to theinterconnection layer 132aof thelower interconnection part 12. At this time, thesilicon nitride film 246 on thehydrophilic insulation film 244 is also etched off (seeFIG. 10C ). - Then, the
barrier metal layer 148 of a Ta film of, e.g., a 25 nm-thickness and a Cu film of, e.g., a 100 nm-thickness are continuously deposited on the entire surface by, e.g., sputtering. After the formation of theinterconnection trenches hole 144, and before the formation of the Ta film, pre-processing, such as Ar (argon) sputtering, H2plasma processing, H2annealing, etc., may be performed in-situ. - Then, with the Cu film formed on the
barrier metal layer 148 as a seed, a Cu film is further deposited by electrolytic plating to form theCu film 150 of, e.g., a 1.0 μm-total thickness (seeFIG. 10C ). - Then, the
Cu film 150, thebarrier metal layer 148 of the Ta film, andhydrophilic insulation film 244 are polished off flat by CMP to form theinterconnection layer 152aburied in theinterconnection trench 146aand the viahole 144 and theinterconnection layer 152bburied in theinterconnection trench 146b. At this time, theCu film 150 is selectively polished under conditions which provide a high selectivity with respect to thebarrier metal layer 148 of Ta film, and the polish is stopped at the surface of the barrier metal layer148 (seeFIG. 11A ). Subsequently, the polishing conditions are reset, and under conditions which make the polishing rate of thebarrier metal layer 148 of Ta film approximate to the polishing rate of thehydrophilic insulation film 244 of silicon oxide film, thebarrier metal layer 148 and thehydrophilic insulation film 244 are polished to expose the low-k film140 (seeFIG. 11B ). - Thus, the
interconnection layer 152aburied in the viahole 144 and theinterconnection trench 146aand including thebarrier metal 148 of Ta film for preventing the diffusion of the Cu and theCu film 150 forming the major part of the interconnection layer, and theinterconnection layer 152bburied in theinterconnection trench 146band including thebarrier metal layer 148 of Ta film for preventing the diffusion of the Cu and theCu film 150 forming the major part of the interconnection layer are formed (seeFIG. 11B ). - Then, the same steps shown in
FIGS. 9A to11B are repeated to form theinterconnection layer FIG. 11C ). - Thus, the
intermediate interconnection part 14 having the two-layer multilayer interconnection structure is formed on thelower interconnection part 12. Theinterconnection layer interconnection layer intermediate interconnection part 14 are formed in the interconnection patterns respectively of a pitch which is larger by, e.g., 1.5 times or more than the pitch of the interconnection layers of thelower interconnection part 12. For example, theinterconnection layer interconnection layer - Next, the
SiC film 174 of, e.g., a 70 nm-thickness is formed by, e.g., plasma CVD on theinter-layer insulation film 162 with the interconnection layers172a,172bof theintermediate interconnection part 14 buried in. - Next, the
silicon oxide film 176 of, e.g., a 530 nm-thickness is formed on theSiC film 174 by, e.g., plasma CVD. - Then, the
SiC film 178 of, e.g., a 30 nm-thickness is formed on thesilicon oxide film 176 by, e.g., plasma CVD. - Then, the
silicon oxide film 180 of, e.g., a 900 nm-thickness is formed on theSiC film 178 by, e.g., plasma CVD. - Thus, the
inter-layer insulation film 182 of the layer structure of thesilicon oxide film 180/theSiC film 178/thesilicon oxide film 176/theSiC film 174 is formed (seeFIG. 12A ). TheSiC films FIG. 12A and the followers, the structure below theSiC film 174 is omitted. - Then, the
silicon nitride film 254 of, e.g., a 50 nm-thickness is formed on thesilicon oxide film 180 by, e.g., CVD. Thesilicon nitride film 254 functions as the ARC film in the following photolithography step. - Then, a
photoresist film 256 for exposing the region for the viahole 184 to be formed in thesilicon oxide film 176 and theSiC film 174 is formed on thesilicon nitride film 254 by photolithography (seeFIG. 12B ). - Then, with the
photoresist film 256 as a mask, thesilicon nitride film 254, thesilicon oxide film 180, theSiC film 178 and thesilicon oxide film 176 are sequentially etched under suitably changed conditions. Thus, the viahole 184 is formed in the silicon oxide film176 (seeFIG. 12C ). - After the via
hole 184 has been formed, thephotoresist film 256 is removed. - Next, after a
resin 258 is buried in the viahole 184 by, e.g., spin coating, theresin 258 on thesilicon nitride film 254 is removed by ashing using, e.g., O2plasma, and theresin 258 in the viahole 184 is etched back to a prescribed height until, for example, the upper surface of theresin 258 is positioned near the border between theSiC film 178 and the silicon oxide film180 (seeFIG. 12D ). - Then, a
photoresist film 260 for exposing the region for theinterconnection trenches inter-layer insulation film 182 is formed on thesilicon nitride film 254 by photolithography (seeFIG. 13A ). At this time, thephotoresist film 260 is formed of a material which does not mix with theresin 258 and whose developer does not solve theresin 258. - Next, with the
photoresist film 260 as a mask and with theSiC film 178 as a stopper, thesilicon nitride film 254 and thesilicon oxide film 180 are sequentially etched. Thus, theinterconnection trenches FIG. 13B ). Theinterconnection trenches lower interconnection part 12 and theintermediate interconnection part 14. - Then, the
photoresist film 260 and theresin 258 in the viahole 184 are removed by ashing using, e.g., O2plasma and CF4plasma. - Next, under conditions which provide a sufficient selectivity with respect to silicon oxide film, the
SiC film 178 at the bottoms of theinterconnection trenches SiC film 174 at the bottom of the viahole 184 are etched to open theinterconnection trenches silicon oxide film 176 and open the viahole 184 down to theinterconnection layer 172a. At this time, thesilicon nitride film 154 on thesilicon oxide film 180 is also etched off (seeFIG. 13C ). - Then, the
barrier metal layer 188 of a Ta film of, e.g., 25 nm-thickness and a Cu film of, e.g., a 150 nm-thickness are continuously deposited on the entire surface by, e.g., sputtering. After the formation of theinterconnection trenches hole 184 and before the deposition of the Ta films, preprocessing, such as Ar (argon) sputtering, H2plasma processing, H2annealing, etc., may be performed in-situ. - Next, with the Cu film formed on the
barrier metal layer 188 as a seed, a Cu film is further deposited by electrolytic plating to form theCu film 190 of, e.g., a 1.5 μm-total thickness (seeFIG. 13D ). - Then, the
Cu film 190 and thebarrier metal layer 188 of the Ta film are polished off flat by CMP (seeFIGS. 14A and 14B ). Thus are formed theinterconnection layer 192aburied in theinterconnection trench 186aand the viahole 184 and including thebarrier metal layer 188 of the Ta film for preventing the Cu diffusion and theCu film 190 forming the major part of the interconnection layer, and theinterconnection layer 192bburied in theinterconnection trench 186band including thebarrier metal layer 188 of the Ta film for preventing the Cu diffusion and theCu film 190 forming the major part of the interconnection layer. - Then, the steps shown in
FIGS. 12A to14B are repeated to form theinterconnection layer FIG. 14C ). - Thus, the
upper interconnection part 16 having the two-layer multilayer interconnection structure is formed on theintermediate interconnection part 14. Theinterconnection layer interconnection layer lower interconnection part 12 and theintermediate interconnection part 14. For example, theinterconnection layer interconnection layer - Next, on the
inter-layer insulation film 202 with theinterconnection layer SiC film 214 of, e.g., a 70 nm-thickness is formed by, e.g., plasma CVD. - Then, the
silicon oxide film 216 of, e.g., a 600 nm-thickness is formed on theSiC film 214 by, e.g., plasma CVD. - Thus, the
inter-layer insulation film 218 of the layer structure of thesilicon oxide film 216/theSiC film 214 is formed (seeFIG. 15A ). - Then, the contact holes220 are formed in the
silicon oxide film 216 and theSiC film 214 down to theinterconnection layer 212aof theupper interconnection part 16 by photolithography and dry etching. - Next, a TiN film of, e.g., a 50 nm-thickness and a W film of, e.g., a 300 nm-thickness are formed by, e.g., CVD.
- Then, the W film and the TiN film are removed flat by, e.g., CMP until the surface of the
silicon oxide film 216 is exposed to form the contact plugs222 of the TiN film and the W film are formed, buried in the contact holes220 (seeFIG. 15B ). - Next, on the
inter-layer insulation film 216 with the contact plugs222 buried in, a metal film is formed by, e.g., CVD. The metal film may be formed of, e.g., a TiN film, an Al (aluminum) film and a TiN film laid sequentially. Next, the metal film is patterned to form theelectrode 224 connected to the contact plugs222 (seeFIG. 15C ). - Then, the
silicon oxide film 226aof, e.g., a 1400 nm-thickness and thesilicon nitride film 226bof, e.g., a 500 nm-thickness are sequentially formed by, e.g., CVD on theinter-layer insulation film 218 with theelectrode 224 formed on to form thecover film 226 of the layer film of thesilicon oxide film 226aand thesilicon nitride film 226b(seeFIG. 16A ). - Next, the
opening 228 is formed in thecover film 226 down to theelectrode 224 by photolithography and dry etching (seeFIG. 16B ). - Thus, the semiconductor device shown in
FIG. 1 is fabricated. - As described above, according to the present embodiment, the lower interconnection part12 and the intermediate interconnection part14 include low-k films as the inter-layer insulation films, and in the lower interconnection part12, in which the interconnection layers have the interconnection patterns of a smaller pitch than the interconnection patterns of the interconnection layers of the intermediate interconnection part14, the hydrophilic insulation film of silicon oxide film is formed on the low-k film, but in the intermediate interconnection part14, in which the interconnection layers have the interconnection patterns of a larger pitch of the interconnection patterns of the interconnection layers of the lower interconnection part12, the SiC film functioning as the diffusion preventing film is formed directly on the low-k film, without any hydrophilic insulation film formed, whereby, corresponding to the functions of the interconnection layers of the multilayer interconnection structure, the lower interconnection part12, in which the interconnection layers are formed in the interconnection patterns of a smaller pitch than the interconnection pattern of the interconnection layers of the intermediate interconnection part14, can suppress the occurrence of defects due to the foreign matter adhesion and can decrease the interconnection capacitance, while the intermediate interconnection part14, in which the interconnection layers are formed in the interconnection patterns of a larger pitch than the interconnection patterns of the interconnection layers of the lower interconnection part12, can sufficiently decrease the interconnection capacitance.
- The present invention is not limited to the above-described embodiment and can cover other various modifications.
- For example, in the above-described embodiment, SiOC film is used as the low-k film. However, the low-k film is not limited to SiOC film and can be any film of flow-k material. As the low-k film, the film of SiLK (registered trademark) by The Dow Chemical Company, FLARE (registered trademark) by Honeywell Electronic Materials, or BCB (benzocyclobutene), etc., for example, other than SiOC can be used. Porous silicon oxide film having fine pores therein can be also used as the low-k film.
- In the above-described embodiment, as the hydrophilic insulation film formed on the low-k film, silicon oxide film is used. However, the hydrophilic insulation film is not limited to silicon oxide film and can be, e.g., FSG film other than silicon oxide film.
- In the above-described embodiment, SiC film is used as the film functioning as the etching stopper film and the Cu diffusion preventing film. However, the film functioning as the etching stopper film and the Cu diffusion preventing film is not limited to SiC film. As the film functioning as the etching stopper film and the Cu diffusion preventing film, silicon nitride film, for example, other than SiC film can be used other.
- In the above-described embodiment, the interconnection layers are formed by filling the barrier metal layer of Ta film and the Cu film in the via holes and the interconnection trenches. However, the interconnection layers can be formed by burying various conductor films other than Ta film and Cu film. Major materials of the interconnection layers can be various conductors, such as Al, etc., other than Cu. The barrier metal layer for preventing the diffusion of metal can be formed of, e.g., TaN (tantalum nitride) film, Ti (titanium) film, TiN (titanium nitride) film, etc. other than Ta film.
- In the above-described embodiment, five interconnection layers are formed in the
lower interconnection part 12, two interconnection layers are formed in theintermediate interconnection part 14, and two interconnection layers are formed in theupper interconnection part 16. However, numbers of the layers of the respective interconnection parts can be suitably designed as required. - In the above-described embodiment, Ta film and Cu film are concurrently buried in the via holes and the interconnection trenches by dual damascene process. However, it is possible to form the via hole and the interconnection trenches independently by single damascene process, and Ta film and Cu film are buried independently therein. In this case, in the
lower interconnection part 12, the inter-layer insulation film of the low-k film and the hydrophilic insulation film formed on the low-k film is formed, and the via hole is formed in the inter-layer insulation film. Then, in the same way as theinterconnection layer interconnection trenches - In the above-described embodiment, the conductor film is buried in the interconnection trenches and the via holes interconnecting the interconnection layers. However, the present invention is applicable to burying a conductor film in various openings, as of dummy patterns, etc.
- In the above-described embodiment, in the
lower interconnection part 12, theintermediate interconnection part 14 and theupper interconnection part 16, the interconnection patterns of the interconnection layers of the same interconnection part are in the same pitch. However, the pitches of the interconnection patterns of the interconnection layers of the same interconnection part can be varied suitably as required as long as a minimum pitch of the interconnection patterns of the interconnection layers of theintermediate interconnection part 14 is larger than a minimum pitch of interconnection patterns of the interconnection layers of thelower interconnection part 12. A minimum pitch of the interconnection patterns of the interconnection layers of theupper interconnection part 16 may be larger than the minimum pitch of the interconnection patterns of the interconnection layer of thelower interconnection part 12 and theintermediate interconnection part 14.
Claims (9)
1. A method for fabricating a semiconductor device comprising the steps of:
forming over a substrate a first inter-layer insulation film including a first low dielectric constant film and a first hydrophilic insulation film formed on the first low dielectric constant film;
forming a first interconnection trench in the first inter-layer insulation film;
forming a first conductor film on the first inter-layer insulation film with the first interconnection trench formed in;
polishing the first conductor film to expose the first hydrophilic insulation film while burying the first conductor film in the first interconnection trench to form a first interconnection layer whose minimum interconnection pitch is a first pitch;
forming a second inter-layer insulation film including a second low dielectric constant film over the first inter-layer insulation film;
forming a second interconnection trench in the second inter-layer insulation film;
forming a second conductor film on the second inter-layer insulation film with the second interconnection trench formed in; and
polishing the second conductor film to expose the second low dielectric constant film while burying the second conductor film in the second interconnection trench to form a second interconnection layer whose minimum interconnection pitch is a second pitch larger than the first pitch.
2. A method for fabricating a semiconductor device according toclaim 1 , further comprising, after the step of forming the second interconnection layer, the step of
forming a diffusion preventing film directly on the second low dielectric constant film and the second interconnection layer.
3. A method for fabricating a semiconductor device according toclaim 1 , wherein
in the step of forming the first conductor film, the first conductor film including a barrier metal layer and a metal layer formed on the barrier metal layer is formed,
in the step of forming the first interconnection layer, the metal film is polished selectively with respect to the barrier metal layer, the polish is stopped on the surface of the barrier metal layer, and then the barrier metal layer is polished to expose the first hydrophilic insulation film.
4. A method for fabricating a semiconductor device according toclaim 2 , wherein
in the step of forming the first conductor film, the first conductor film including a barrier metal layer and a metal layer formed on the barrier metal layer is formed,
in the step of forming the first interconnection layer, the metal film is polished selectively with respect to the barrier metal layer, the polish is stopped on the surface of the barrier metal layer, and then the barrier metal layer is polished to expose the first hydrophilic insulation film.
5. A method for fabricating a semiconductor device according toclaim 1 , wherein
the step of forming the second inter-layer insulation film includes the step of forming a second hydrophilic insulation film on the second low dielectric constant film, and
in the step of forming the second interconnection layer, the second conductor film and the second hydrophilic insulation film are polished to expose the second low dielectric constant film.
6. A method for fabricating a semiconductor device according toclaim 2 , wherein
the step of forming the second inter-layer insulation film includes the step of forming a second hydrophilic insulation film on the second low dielectric constant film, and
in the step of forming the second interconnection layer, the second conductor film and the second hydrophilic insulation film are polished to expose the second low dielectric constant film.
7. A method for fabricating a semiconductor device according toclaim 5 , wherein
in the step of forming the second conductor film, the second conductor film including a barrier metal layer and a metal film formed on the barrier metal layer, and
in the step of forming the second interconnection layer, the metal film is polished selectively with respect to the barrier metal layer, the polish is stopped on the surface of the barrier metal layer, and then the barrier metal layer and the second hydrophilic insulation film are polished to expose the second low dielectric constant film.
8. A method for fabricating a semiconductor device according toclaim 5 , wherein in the step of forming the first inter-layer insulation film, the first hydrophilic insulation film is formed in a larger thickness than the second hydrophilic insulation film.
9. A method for fabricating a semiconductor device according toclaim 1 , further comprising, after the step of burying the first conductor film in the first interconnection trench, the step of removing foreign matters by HF processing.
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| US11/808,165US20070281465A1 (en) | 2003-10-31 | 2007-06-07 | Semiconductor device and method for fabricating the same |
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| JP2003-372304 | 2003-10-31 | ||
| JP2003372304AJP4230334B2 (en) | 2003-10-31 | 2003-10-31 | Semiconductor device and manufacturing method thereof |
| US10/816,955US7250679B2 (en) | 2003-10-31 | 2004-04-05 | Semiconductor device and method for fabricating the same |
| US11/808,165US20070281465A1 (en) | 2003-10-31 | 2007-06-07 | Semiconductor device and method for fabricating the same |
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| US11/808,165AbandonedUS20070281465A1 (en) | 2003-10-31 | 2007-06-07 | Semiconductor device and method for fabricating the same |
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| JP (1) | JP4230334B2 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP4230334B2 (en) | 2009-02-25 |
| US7250679B2 (en) | 2007-07-31 |
| JP2005136301A (en) | 2005-05-26 |
| US20050093160A1 (en) | 2005-05-05 |
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