US20070272994A1 - Sensor semiconductor device - Google Patents
Sensor semiconductor deviceDownload PDFInfo
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- US20070272994A1 US20070272994A1US11/838,723US83872307AUS2007272994A1US 20070272994 A1US20070272994 A1US 20070272994A1US 83872307 AUS83872307 AUS 83872307AUS 2007272994 A1US2007272994 A1US 2007272994A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/804—Containers or encapsulations
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/809—Constructional details of image sensors of hybrid image sensors
Definitions
- the present inventionrelates to sensor semiconductor devices for fabricating the same, and more particularly, to a chip-scale packaged (CSP) semiconductor device for fabricating the sensor semiconductor device.
- CSPchip-scale packaged
- a sensor chipis mounted on a chip carrier and is electrically connected to the chip carrier via bonding wires, and a piece of glass is provided above the sensor chip to allow an image to be captured by the sensor chip.
- the image sensor packagecan be integrated to an external device such as a printed circuit board (PCB) to be used in various electronic products such as digital still camera (DSC), digital video camera (DVC), optical mouse, cellular phone, fingerprint scanner, and so on.
- PCBprinted circuit board
- IC packageshave been developed to have an advanced chip-scale packaged (CSP) structure in response to the requirements such as plenty input/output (I/O) connections, high heat dissipating efficiency and size miniaturization for integrated circuits. Therefore, a chip-scale packaged sensor semiconductor device is provided to effectively reduce a size of the conventional image sensor package, wherein the semiconductor device is merely slightly larger in size than a sensor chip incorporated therein and thus can be effectively applied to miniaturized electronic products.
- FIG. 1shows a chip-scale packaged sensor semiconductor device disclosed by U.S. Pat. No. 6,646,289.
- a piece of glass 12is applied over an active surface of the wafer to protect sensor regions 18 of the sensor chips 11 , and an epoxy layer 13 and a protective layer 14 are applied over a non-active surface of the wafer.
- An etching processis performed on the non-active surface of the wafer to form a plurality of inclined slots 15 , such that electrode pads 110 of the sensor chips 11 are exposed, and patterned circuit layers 16 are formed on side walls of the inclined slots 15 and extended to a bottom surface of the protective layer 14 , allowing the circuit layers 16 to be electrically connected to the electrode pads 110 of the sensor chips 11 .
- a plurality of solder balls 17can subsequently be implanted on the circuit layers 16 at the bottom surface of the protective layer 14 , and a singulation process is performed to form individual chip-scale packaged sensor semiconductor devices, such that the sensor semiconductor devices can directly be electrically connected to an external device by the solder balls 17 .
- the problem to be solved hereinis to provide a chip-scale sensor semiconductor device for fabricating the same, whereby the sensor semiconductor device can be cost-effectively fabricated and a circuit-cracking problem is avoided.
- an objective of the present inventionis to provide a cost-effective sensor semiconductor device for fabricating the same.
- Another objective of the present inventionis to provide a sensor semiconductor device, which can prevent circuit cracking.
- a further objective of the present inventionis to provide a chip-scale sensor semiconductor device.
- the present inventionalso proposes a sensor semiconductor device, comprising: a substrate having a first surface and a corresponding second surface; a plurality of metal bumps mounted on the first surface of the substrate; a sensor chip mounted on the first surface of the substrate, wherein an active surface of the sensor chip is formed with a sensor region and a plurality of electrode pads, and a non-active surface of the sensor chip is attached to the substrate; a dielectric layer applied on the substrate, the metal bumps and the sensor chip, wherein the dielectric layer is formed with a plurality of first openings corresponding in position to the metal bumps and the electrode pads of the sensor chip and a second opening corresponding in position to the sensor region of the sensor chip; a circuit layer formed on the dielectric layer, and electrically connected to the metal bumps and the electrode pads of the sensor chip; a light-penetrable lid mounted on the circuit layer, for covering the second opening of the dielectric layer corresponding to the sensor region of the sensor chip; and a plurality of solder balls implanted on the second
- metal bumps and a sensor chipare firstly mounted on a substrate, and then a dielectric layer and a circuit layer are formed on the substrate by a build-up process.
- the circuit layeris electrically connected to the metal bumps and the sensor chip, such that the sensor chip can be electrically connected to the substrate via the circuit layer and the metal bumps.
- the dielectric layeris formed with an opening for exposing a sensor region of the sensor chip.
- a light-penetrable lidis provided to cover the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip.
- FIG. 1is a cross-sectional view of a chip-scale packaged sensor semiconductor device as disclosed in U.S. Pat. No. 6,646,289;
- FIGS. 2A to 2 Fare cross-sectional views of steps of a method for fabricating a sensor semiconductor device according to the present invention.
- FIG. 3is a cross-sectional view of a sensor semiconductor device according to another preferred embodiment of the present invention.
- FIGS. 2A-2F and FIG. 3Preferred embodiments of a sensor semiconductor device and a method for fabricating the same proposed in the present invention are described below with reference to FIGS. 2A-2F and FIG. 3 .
- the drawingsare simplified schematic diagrams for illustrating the basic design of the present invention and thus only show relevant elements to the present invention. The drawings are not made with the actual amount, shape and size of the elements. In practice, the number, shape and size of the elements can be flexibly modified, and an element layout may be more complex.
- FIGS. 2A to 2 Fare cross-sectional views of steps of a method for fabricating a sensor semiconductor device according to the present invention.
- a batch-type methodis employed to fabricate the sensor semiconductor device.
- the sensor semiconductor device in the present inventioncan also be fabricated in a singular-type manner under suitable fabrication conditions.
- a substrate module plate 20comprising a plurality of substrates 200 is provided, wherein a plurality of metal bumps 21 are mounted on and electrically connected to each of the substrates 200 .
- the substrate module plate 20can be a matrix-type or strip-type substrate module plate.
- the metal bumps 21can be gold bumps or solder bumps.
- At least one sensor chip 22is mounted on each of the substrates 200 .
- the sensor chip 22has an active surface 221 and a corresponding non-active surface 222 , wherein the active surface 221 of the sensor chip 22 is formed with a sensor region 223 and a plurality of electrode pads 224 , and the non-active surface 222 of the sensor chip 22 is attached to each of the substrates 200 .
- a dielectric layer 23is formed on the substrate module plate 20 to cover the substrates 200 , the metal bumps 21 and the sensor chips 22 .
- a plurality of openings 230are formed in the dielectric layer 23 at positions corresponding to the metal bumps 21 and the electrode pads 224 of the sensor chips 22 .
- a circuit layer 24is formed on the dielectric layer 23 and is electrically connected to the metal bumps 21 and the electrode pads 224 of the sensor chips 22 .
- an opening 231is further formed in the dielectric layer 23 at a position corresponding to the sensor region 223 of the sensor chip 22 on each of the substrates 200 , such that the sensor regions 223 of the sensor chips 22 on the substrates 200 are exposed.
- the present inventionalso provides a sensor semiconductor device, comprising: a substrate 200 having a first surface and a corresponding second surface; metal bumps 21 mounted on the first surface of the substrate 200 ; a sensor chip 22 mounted on the first surface of the substrate 200 , wherein an active surface 221 of the sensor chip 22 is formed with a sensor region 223 and a plurality of electrode pads 224 , and a non-active surface 222 of the sensor chip 22 is attached to the substrate 200 ; a dielectric layer 23 applied on the substrate 200 , the metal bumps 21 and the sensor chip 22 , wherein the dielectric layer 23 is formed with a plurality of openings 230 corresponding in position to the metal bumps 21 and the electrode pads 224 of the sensor chip 22 and an opening 231 corresponding in position to the sensor region 223 of the sensor chip 22 ; a circuit layer 24 formed on the dielectric layer 23 , and electrically connected to the metal bumps 21 and the electrode pads 224 of the sensor chip 22 ; and a light-pe
- metal bumps and a sensor chipare firstly mounted on a substrate, and then a dielectric layer and a circuit layer are formed on the substrate by a build-up process.
- the circuit layeris electrically connected to the metal bumps and the sensor chip, such that the sensor chip can be electrically connected to the substrate via the circuit layer and the metal bumps.
- the dielectric layeris formed with an opening for exposing a sensor region of the sensor chip.
- a light-penetrable lidis provided to cover the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip.
- a plurality of solder ballsare implanted on a surface of the substrate not for mounting the sensor chip, so as to allow the sensor chip to be electrically connected to an external device by the solder balls.
- the sensor chipcan be subjected to a test and any defective chip failing in the test is eliminated in advance, such that the reliability of subsequent fabricating processes is improved and a known good die (KGD) problem is avoided.
- the sensor semiconductor devicecan be fabricated in a cost-effective manner as compared to the conventional technology, and a chip-cracking problem is prevented in the present invention.
- FIG. 3is a cross-sectional view of a sensor semiconductor device according to another preferred embodiment of the present invention.
- the sensor semiconductor device shown in FIG. 3is fabricated by a method similar to that of the foregoing embodiment, with a primary difference in that a circuit build-up process is performed on the circuit layer 24 that is electrically connected to the metal bumps 21 and the electrode pads 224 of the sensor chip 22 as shown in FIG. 3 .
- a dielectric layer 33is pressed on the circuit layer 24 , wherein the dielectric layer 33 is formed with openings to partly expose the circuit layer 24 .
- a circuit layer 34is formed on the dielectric layer 33 and is electrically connected to the circuit layer 24 underneath the dielectric layer 33 . Therefore, electrical performances of the sensor semiconductor device can be improved by the circuit build-up structure.
- the number of build-up circuit layersis not limited to that shown in the drawing and can be increased according to practical requirements of electrical design.
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Abstract
Description
- This is a divisional of co-pending application Ser. No. 11/163,310 filed Oct. 13, 2005, which is hereby incorporated by reference herein.
- The present invention relates to sensor semiconductor devices for fabricating the same, and more particularly, to a chip-scale packaged (CSP) semiconductor device for fabricating the sensor semiconductor device.
- In a conventional image sensor package, a sensor chip is mounted on a chip carrier and is electrically connected to the chip carrier via bonding wires, and a piece of glass is provided above the sensor chip to allow an image to be captured by the sensor chip. The image sensor package can be integrated to an external device such as a printed circuit board (PCB) to be used in various electronic products such as digital still camera (DSC), digital video camera (DVC), optical mouse, cellular phone, fingerprint scanner, and so on.
- Along with expansion of data transmission capacity and development of miniaturized and portable electronic products, integrated circuit (IC) packages have been developed to have an advanced chip-scale packaged (CSP) structure in response to the requirements such as plenty input/output (I/O) connections, high heat dissipating efficiency and size miniaturization for integrated circuits. Therefore, a chip-scale packaged sensor semiconductor device is provided to effectively reduce a size of the conventional image sensor package, wherein the semiconductor device is merely slightly larger in size than a sensor chip incorporated therein and thus can be effectively applied to miniaturized electronic products.
FIG. 1 (PRIOR ART) shows a chip-scale packaged sensor semiconductor device disclosed by U.S. Pat. No. 6,646,289. As shown inFIG. 1 (PRIOR ART), during fabrication of a wafer comprisingsensor chips 11, a piece ofglass 12 is applied over an active surface of the wafer to protectsensor regions 18 of thesensor chips 11, and anepoxy layer 13 and aprotective layer 14 are applied over a non-active surface of the wafer. An etching process is performed on the non-active surface of the wafer to form a plurality ofinclined slots 15, such thatelectrode pads 110 of thesensor chips 11 are exposed, and patternedcircuit layers 16 are formed on side walls of theinclined slots 15 and extended to a bottom surface of theprotective layer 14, allowing thecircuit layers 16 to be electrically connected to theelectrode pads 110 of thesensor chips 11. A plurality ofsolder balls 17 can subsequently be implanted on thecircuit layers 16 at the bottom surface of theprotective layer 14, and a singulation process is performed to form individual chip-scale packaged sensor semiconductor devices, such that the sensor semiconductor devices can directly be electrically connected to an external device by thesolder balls 17.- However, in the foregoing sensor semiconductor device, since the circuit layers formed on the side walls of the inclined slots have an acute angle relative to the electrode pads of the sensor chip electrically connected to the circuit layers, such acute-angle connection positions between the circuit layers and the electrode pads may easily be subject to stress concentration, thereby causing problems such as circuit cracking, failure in electrical connection, and so on. As fabrication of the foregoing sensor semiconductor device is directly performed on the wafer, which requires complicated fabrication processes and does not effectively solve a known good die (KGD) problem, making the fabrication costs greatly increased.
- Therefore, the problem to be solved herein is to provide a chip-scale sensor semiconductor device for fabricating the same, whereby the sensor semiconductor device can be cost-effectively fabricated and a circuit-cracking problem is avoided.
- In light of the above drawbacks in the conventional technology, an objective of the present invention is to provide a cost-effective sensor semiconductor device for fabricating the same.
- Another objective of the present invention is to provide a sensor semiconductor device, which can prevent circuit cracking.
- A further objective of the present invention is to provide a chip-scale sensor semiconductor device.
- In accordance with the foregoing and other objectives, the present invention proposes a sensor semiconductor device, comprising the steps of: mounting a plurality of metal bumps and at least one sensor chip on a substrate, wherein an active surface of the sensor chip is formed with a sensor region and a plurality of electrode pads, and a non-active surface of the sensor chip is attached to the substrate; applying a dielectric layer on the substrate, the metal bumps and the sensor chip, wherein the dielectric layer is formed with a plurality of first openings corresponding in position to the metal bumps and the electrode pads of the sensor chip; forming a circuit layer on the dielectric layer, wherein the circuit layer is electrically connected to the metal bumps and the electrode pads of the sensor chip; forming a second opening in the dielectric layer at a position corresponding to the sensor region of the senor chip; and providing a light-penetrable lid to cover the second opening of the dielectric layer corresponding to the sensor region of the sensor chip, and implanting a plurality of solder balls on a surface of the substrate not for mounting the sensor chip. If the fabrication method is performed in a batch-type manner, a singulation process is further required to form a plurality of individual sensor semiconductor devices.
- The present invention also proposes a sensor semiconductor device, comprising: a substrate having a first surface and a corresponding second surface; a plurality of metal bumps mounted on the first surface of the substrate; a sensor chip mounted on the first surface of the substrate, wherein an active surface of the sensor chip is formed with a sensor region and a plurality of electrode pads, and a non-active surface of the sensor chip is attached to the substrate; a dielectric layer applied on the substrate, the metal bumps and the sensor chip, wherein the dielectric layer is formed with a plurality of first openings corresponding in position to the metal bumps and the electrode pads of the sensor chip and a second opening corresponding in position to the sensor region of the sensor chip; a circuit layer formed on the dielectric layer, and electrically connected to the metal bumps and the electrode pads of the sensor chip; a light-penetrable lid mounted on the circuit layer, for covering the second opening of the dielectric layer corresponding to the sensor region of the sensor chip; and a plurality of solder balls implanted on the second surface of the substrate.
- By the sensor semiconductor device in the present invention, metal bumps and a sensor chip are firstly mounted on a substrate, and then a dielectric layer and a circuit layer are formed on the substrate by a build-up process. The circuit layer is electrically connected to the metal bumps and the sensor chip, such that the sensor chip can be electrically connected to the substrate via the circuit layer and the metal bumps. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid is provided to cover the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. A plurality of solder balls are implanted on a surface of the substrate not for mounting the sensor chip, so as to allow the sensor chip to be electrically connected to an external device by the solder balls. In the present invention, the sensor chip can be subjected to a test and any defective chip failing in the test is eliminated in advance, such that the reliability of subsequent fabricating processes is improved and a known good die (KGD) problem is avoided. By the arrangement that the sensor chip is electrically connected to the substrate via the circuit layer and the metal bumps and is subsequently electrically connected to the external device via the solder balls, the sensor semiconductor device can be fabricated in a cost-effective manner as compared to the conventional technology, and a chip-cracking problem is prevented in the present invention.
- The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
FIG. 1 (PRIOR ART) is a cross-sectional view of a chip-scale packaged sensor semiconductor device as disclosed in U.S. Pat. No. 6,646,289;FIGS. 2A to2F are cross-sectional views of steps of a method for fabricating a sensor semiconductor device according to the present invention; andFIG. 3 is a cross-sectional view of a sensor semiconductor device according to another preferred embodiment of the present invention.- Preferred embodiments of a sensor semiconductor device and a method for fabricating the same proposed in the present invention are described below with reference to
FIGS. 2A-2F andFIG. 3 . It should be noted that the drawings are simplified schematic diagrams for illustrating the basic design of the present invention and thus only show relevant elements to the present invention. The drawings are not made with the actual amount, shape and size of the elements. In practice, the number, shape and size of the elements can be flexibly modified, and an element layout may be more complex. FIGS. 2A to2F are cross-sectional views of steps of a method for fabricating a sensor semiconductor device according to the present invention. In this embodiment, a batch-type method is employed to fabricate the sensor semiconductor device. It should be understood that the sensor semiconductor device in the present invention can also be fabricated in a singular-type manner under suitable fabrication conditions.- Referring to
FIG. 2A , asubstrate module plate 20 comprising a plurality ofsubstrates 200 is provided, wherein a plurality ofmetal bumps 21 are mounted on and electrically connected to each of thesubstrates 200. Thesubstrate module plate 20 can be a matrix-type or strip-type substrate module plate. Themetal bumps 21 can be gold bumps or solder bumps. - Referring to
FIG. 2B , at least onesensor chip 22 is mounted on each of thesubstrates 200. Thesensor chip 22 has anactive surface 221 and a correspondingnon-active surface 222, wherein theactive surface 221 of thesensor chip 22 is formed with asensor region 223 and a plurality ofelectrode pads 224, and thenon-active surface 222 of thesensor chip 22 is attached to each of thesubstrates 200. - Referring to
FIG. 2C , adielectric layer 23 is formed on thesubstrate module plate 20 to cover thesubstrates 200, themetal bumps 21 and thesensor chips 22. A plurality ofopenings 230 are formed in thedielectric layer 23 at positions corresponding to themetal bumps 21 and theelectrode pads 224 of thesensor chips 22. - Referring to
FIG. 2D , acircuit layer 24 is formed on thedielectric layer 23 and is electrically connected to themetal bumps 21 and theelectrode pads 224 of thesensor chips 22. - Referring to
FIG. 2E , anopening 231 is further formed in thedielectric layer 23 at a position corresponding to thesensor region 223 of thesensor chip 22 on each of thesubstrates 200, such that thesensor regions 223 of thesensor chips 22 on thesubstrates 200 are exposed. - Referring to
FIG. 2F , a light-penetrable lid 25 is mounted on thecircuit layer 24 to cover thesensor regions 223 of the sensor chips22, and a plurality ofsolder balls 26 are implanted on a surface of each of thesubstrates 200 not for mounting thesensor chip 22. A singulation process is performed to form a plurality of sensor semiconductor devices. The light-penetrable lid 25 can be made of glass or transparent paste. Therefore, the sensor chip can be electrically connected to an external device via the electrode pads, the circuit layer, the metal bumps, internal conductive structures of the substrate, and the solder balls. - By the foregoing fabrication method, the present invention also provides a sensor semiconductor device, comprising: a
substrate 200 having a first surface and a corresponding second surface; metal bumps21 mounted on the first surface of thesubstrate 200; asensor chip 22 mounted on the first surface of thesubstrate 200, wherein anactive surface 221 of thesensor chip 22 is formed with asensor region 223 and a plurality ofelectrode pads 224, and anon-active surface 222 of thesensor chip 22 is attached to thesubstrate 200; adielectric layer 23 applied on thesubstrate 200, the metal bumps21 and thesensor chip 22, wherein thedielectric layer 23 is formed with a plurality ofopenings 230 corresponding in position to the metal bumps21 and theelectrode pads 224 of thesensor chip 22 and anopening 231 corresponding in position to thesensor region 223 of thesensor chip 22; acircuit layer 24 formed on thedielectric layer 23, and electrically connected to the metal bumps21 and theelectrode pads 224 of thesensor chip 22; and a light-penetrable lid 25 mounted on thecircuit layer 24 to cover thesensor region 223 of thesensor chip 22. The sensor semiconductor device further comprises a plurality ofsolder balls 26 implanted on the second surface of thesubstrate 200. - By the sensor semiconductor device and the method for fabricating the same in the present invention, metal bumps and a sensor chip are firstly mounted on a substrate, and then a dielectric layer and a circuit layer are formed on the substrate by a build-up process. The circuit layer is electrically connected to the metal bumps and the sensor chip, such that the sensor chip can be electrically connected to the substrate via the circuit layer and the metal bumps. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid is provided to cover the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. A plurality of solder balls are implanted on a surface of the substrate not for mounting the sensor chip, so as to allow the sensor chip to be electrically connected to an external device by the solder balls. In the present invention, the sensor chip can be subjected to a test and any defective chip failing in the test is eliminated in advance, such that the reliability of subsequent fabricating processes is improved and a known good die (KGD) problem is avoided. By the arrangement that the sensor chip is electrically connected to the substrate via the circuit layer and the metal bumps and is subsequently electrically connected to the external device via the solder balls, the sensor semiconductor device can be fabricated in a cost-effective manner as compared to the conventional technology, and a chip-cracking problem is prevented in the present invention.
FIG. 3 is a cross-sectional view of a sensor semiconductor device according to another preferred embodiment of the present invention.- The sensor semiconductor device shown in
FIG. 3 is fabricated by a method similar to that of the foregoing embodiment, with a primary difference in that a circuit build-up process is performed on thecircuit layer 24 that is electrically connected to the metal bumps21 and theelectrode pads 224 of thesensor chip 22 as shown inFIG. 3 . Firstly, adielectric layer 33 is pressed on thecircuit layer 24, wherein thedielectric layer 33 is formed with openings to partly expose thecircuit layer 24. Then, acircuit layer 34 is formed on thedielectric layer 33 and is electrically connected to thecircuit layer 24 underneath thedielectric layer 33. Therefore, electrical performances of the sensor semiconductor device can be improved by the circuit build-up structure. It should be noted that the number of build-up circuit layers is not limited to that shown in the drawing and can be increased according to practical requirements of electrical design. - The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (8)
1. A sensor semiconductor device, comprising:
at least one substrate having a first surface and a corresponding second surface;
a plurality of metal bumps mounted on the first surface of the substrate;
a sensor chip having an active surface and a corresponding non-active surface, wherein the active surface of the sensor chip is formed with a sensor region and a plurality of electrode pads, and the non-active surface of the sensor chip is mounted on the first surface of the substrate;
a dielectric layer applied on the substrate, the metal bumps and the sensor chip, wherein the dielectric layer is formed with a plurality of first openings corresponding in position to the metal bumps and the electrode pads of the sensor chip and a second opening corresponding in position to the sensor region of the sensor chip;
a circuit layer formed on the dielectric layer, and electrically connected to the metal bumps and the electrode pads of the sensor chip; and
a light-penetrable lid for covering the second opening of the dielectric layer corresponding to the sensor region of the sensor chip.
2. The sensor semiconductor device ofclaim 1 , further comprising a plurality of solder balls implanted on the second surface of the substrate.
3. The sensor semiconductor device ofclaim 1 , further comprising a circuit build-up structure formed on the circuit layer that is electrically connected to the metal bumps and the electrode pads of the sensor chip.
4. The sensor semiconductor device ofclaim 1 , wherein at least one substrate comprises at least one single substrate, a matrix of substrates, or a strip of substrates.
5. The sensor semiconductor device ofclaim 1 , wherein the light-penetrable lid is mounted on the circuit layer to cover the second opening of the dielectric layer.
6. The sensor semiconductor device ofclaim 1 , which is a chip-scale packaged sensor semiconductor device.
7. The sensor semiconductor device ofclaim 1 , wherein the metal bumps are gold bumps or solder bumps.
8. The sensor semiconductor device ofclaim 1 , wherein the light-penetrable lid is made of glass or transparent paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/838,723US20070272994A1 (en) | 2005-05-25 | 2007-08-14 | Sensor semiconductor device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW94117009 | 2005-05-25 | ||
| TW094117009ATW200642015A (en) | 2005-05-25 | 2005-05-25 | Sensor semiconductor device and fabrication method thereof |
| US11/163,310US7271024B2 (en) | 2005-05-25 | 2005-10-13 | Method for fabricating sensor semiconductor device |
| US11/838,723US20070272994A1 (en) | 2005-05-25 | 2007-08-14 | Sensor semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/163,310DivisionUS7271024B2 (en) | 2005-05-25 | 2005-10-13 | Method for fabricating sensor semiconductor device |
Publications (1)
| Publication Number | Publication Date |
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| US20070272994A1true US20070272994A1 (en) | 2007-11-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| US11/163,310Expired - LifetimeUS7271024B2 (en) | 2005-05-25 | 2005-10-13 | Method for fabricating sensor semiconductor device |
| US11/838,723AbandonedUS20070272994A1 (en) | 2005-05-25 | 2007-08-14 | Sensor semiconductor device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
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| US11/163,310Expired - LifetimeUS7271024B2 (en) | 2005-05-25 | 2005-10-13 | Method for fabricating sensor semiconductor device |
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| US (2) | US7271024B2 (en) |
| TW (1) | TW200642015A (en) |
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| CN102376678A (en)* | 2010-08-23 | 2012-03-14 | 矽品精密工业股份有限公司 | Chip scale package and fabrication method thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20060270089A1 (en) | 2006-11-30 |
| TW200642015A (en) | 2006-12-01 |
| US7271024B2 (en) | 2007-09-18 |
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| STCB | Information on status: application discontinuation | Free format text:ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |