US20070250658A1 - Memory system mounted directly on board and associated method - Google Patents

Abstract

The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. The first buffer and memory device are mounted on a motherboard. Likewise, the plurality of signal traces is routed on the motherboard. Doing so eliminates stub loads that cause signal reflection that, in turn, result in signal degradation.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
• This application is a continuation-in-part of U.S. patent application Ser. No. 10/750,093, filed Dec. 31, 2003, now pending, which claims priority from Korean patent application no. 2003-28175, filed May 2, 2003. We incorporate U.S. application Ser. No. 10/750,093 and Korean application no. 2003-28175 by reference in their entireties.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention
• The present invention relates to an improved memory system mounted directly on a motherboard and an associated method.
• 2. Description of the Related Art
• Most computer systems allow for memory expansion using memory modules. Memory modules—for example, single inline memory modules (SIMMs) and/or dual inline memory modules (DIMMs)—are small, compact circuit boards that are designed to connect easily into an expansion socket mounted on a main circuit or motherboard.
• FIGS. 1 and 2 are diagrams ofcomputer system100's memory architecture. Referring toFIGS. 1 and 2, asystem100 includes a plurality ofmemory modules106 controlled by amemory controller104. Thememory controller104 controls read and write operations relating to thememory modules106. Thememory controller104 is mounted on the main ormotherboard102. The operation of thememory controller104 is well known to a person of reasonable skill in the art and will not be discussed any further.
• Thememory modules106 oftentimes includeedge connectors114 comprising a plurality ofcontact pads116. Thecontact pads116 are typically present at both sides of themodules106. A plurality of receptacles, e.g.,sockets112, is mounted on themotherboard102. Thesockets112 receive theedge connectors114 to thereby electrically couple themotherboard102 to thememory modules106. More particularly, thesockets112 electrically couple traces routed on themotherboard102 to traces routed on thememory modules106.
• Thememory modules106 include a plurality ofmemory devices108. Thesememory devices108 are, for example, dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM). Abuffer110 controls and buffers commands and addresses (C/A) it receives from thememory controller104. The plurality ofmemory devices108 and the C/A buffer110 are mounted on thememory module106.
• Signal traces are routed on both themotherboard102 and themodules106. These signal traces might include a data bus DQ, system clock signal CLK, and C/A bus. Thememory devices108 and thebuffer110 receive signals from acontroller104 through thecorresponding socket112 mounted on themotherboard102.
• In any memory architecture, it is important to maintain the signal integrity of the address, control and clock signals. Maintaining signal integrity becomes more difficult as the operating frequency increases because of transmission line effects, including signal reflection.
• In transmission line theory, the connection between themotherboard102 and themodule106 through thesocket112 is termed a stub load. Stub loads present a transmission discontinuity that results in signal reflection and ultimately, adversely affects signal integrity. Referring toFIGS. 1-3, asignal trace302, e.g., the data bus DQ, is routed on themotherboard102. Thesignal trace302 is electrically coupled to asignal trace304 routed on themodule106 through thesocket312. But thesocket312 presents adiscontinuity306 between thesignal trace302 and thesignal trace304. Thediscontinuity306 causes a portion of the signal to reflect back injecting noise, as well as, decreasing timing margins and voltage windows.
• Referring toFIG. 4,stub resistors416 in thememory modules406 reduces signal reflection. But thesestub resistors416 improve memory read and write operations. As the value of thestub resistors416 increases to decrease reflection, the voltage drop across it increases attenuating the signal voltage. Attenuating signal voltages decrease the voltage window. And thestub resistors416 might cause RC parasitic loads that delay the signal.
• Accordingly, a need remains for a memory system capable of addressing disadvantages associated with existing memory systems.
BRIEF DESCRIPTION OF THE DRAWINGS
• The foregoing and other objects, features, and advantages of the invention will become more readily apparent from the detailed description of an embodiment that references the following drawings.
• FIG. 1 is a top view of a memory system.
• FIG. 2 is a side view of the memory system shown inFIG. 1.
• FIG. 3 is a transmission line diagram associated with the system shown inFIG. 1.
• FIG. 4 is a top view of a memory system.
• FIG. 5 is a top view of an embodiment of the memory system according to the present invention.
• FIG. 6 is a block diagram of the memory system shown inFIG. 5.
• FIG. 7 is a side view of an embodiment of the memory system according to the present invention.
• FIG. 8 is a side view of an embodiment of the memory system according to the present invention.
• FIG. 9 is a top view of an embodiment of the memory system according to the present invention.
• FIG. 10 is a top view of an embodiment of the memory system according to the present invention.
• FIG. 11 is a top view of an embodiment of the memory system according to the present invention.
• FIG. 12 is a top view of an embodiment of the memory system according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
• FIG. 5 is a top view of a memory system according to the present invention.FIG. 6 is a block diagram of the memory system shown inFIG. 5. Referring toFIGS. 5 and 6, thememory system500 includes amemory controller504 that controls a plurality ofmemory ranks516. Thememory controller504 controls read and write operations relating to thememory ranks516. Thememory controller504 is mounted on themotherboard502. The structure and operation of thememory controller504 is well known to a person of reasonable skill in the art and will not be discussed any further.
• The plurality of memory ranks516 is mounted directly on themotherboard502. That is, there is noseparate memory module106 as exists in thesystem100.
• Each memory rank includes a plurality ofmemory devices508 coupled to abuffer510. Thememory devices508 are directly mounted on themotherboard502. Eachmemory device508 is, for example, a DRAM or SDRAM. The structure and operation of thememory devices508 is well known to a person of reasonable skill in the art and will not be discussed any further.
• Thebuffer510 controls and buffers commands and addresses it receives from thememory controller504. Thebuffer510 might be a command and address buffer. Thebuffer510 is mounted to themotherboard502. Thebuffer510 might include inverters, drivers, and the like to allow it to drive the plurality ofmemory devices508 with the command and address signals it receives from thecontroller504. The structure and operation of thebuffer510 is well known to a person of reasonable skill in the art and will not be discussed any further.
• Signal traces are routed on themotherboard502. These signal traces might include a data bus DQ, system clock signal CLK, and command and address bus C/A as shown inFIGS. 5 and 6.
• Thesystem500 operates as follows. The controller generates command and address signals it transmits to the command andaddress buffer510 via signal traces routed on themotherboard502. The plurality ofmemory devices508 receive data signals DQ and the system clock signal CLK from thecontroller504 or other circuitry on the motherboard not shown inFIG. 5 or6. If the command signals indicate a read operation, thememory device508 will provide the data read from the corresponding memory cell indicated by the address signals responsive to the system clock CLK. If the command signals indicate a write operation, thememory device508 will write the data to the corresponding memory cell indicated by the address signals responsive to the system clock CLK.
• Thesystem500 eliminates stub loads that cause signal reflection by eliminating memory modules. If there are no memory modules, then there is no need for sockets that create transmission line discontinuities. If there are no transmission line discontinuities, then no signal reflection can exist that degrade its integrity in the manner we discussed above.
• FIG. 7 is a side view of amemory system700 according to the present invention. Referring toFIG. 7, thesystem700 includes the plurality of memory ranks516 and thecontroller504 discussed earlier with reference toFIGS. 5 and 6. The plurality of memory ranks516 and thecontroller504 are mounted on themotherboard502.
• Unlike thesystem500, however, thesystem700 includes amemory module716. Thememory module716 might include anedge connector714 comprising a plurality of contact pads (not shown), a plurality of memory devices (708), a module board (706), and a C/A buffer (710). The contact pads are typically present at both sides of theboard706. A plurality of receptacles, e.g.,sockets712, is mounted on themotherboard502. Thesockets712 receive theedge connectors714 to thereby electrically couple themotherboard502 to thememory module716. More particularly, thesockets712 electrically couple traces routed on themotherboard502 to traces routed on themodule board706 such that thememory module716 is coupled to themotherboard502 and the controller704.
• Thememory module716 includes a plurality ofmemory devices708. Thesememory devices708 are, for example, DRAM and SDRAM. Abuffer710 controls and buffers commands and addresses it receives from the memory controller704. The plurality ofmemory devices708 and thebuffer710 are mounted on themodule board706.
• In one embodiment, thememory module716 is positioned farthest from the controller704. Doing so eliminates signal reflection because there exists no branch point from signal traces on the motherboard702. That is, the branch point causes a signal to be transferred in as many directions as points emanating from the branch point, e.g., two or more directions. Undesired signal reflection might occur because of mismatching of a characteristic impedance (Z0) at the branch point.
• The signal path between the controller704 and thememory module716 extends from the controller704 to thememory708 to thememory module716. Since thememory708 is soldered directly to theboard706, no signal branch exists at that point and, therefore, no signal reflection. On the other hand, if thememory module716 is positioned between the controller704 andmemory708, the connector socket must be located between the signal trace creating a stub or branch from the module trace. This branch will create a signal reflection.
• FIG. 8 is a side view of amemory system800 according to the present invention. Thesystem800 is substantially similar to thesystem700 except that instead of asingle memory module716, thesystem800 might include two ormore memory modules716. Thesystem800 might exhibit some of the disadvantages associated with thesystem100 shown inFIG. 1 because a branch points exist from themotherboard502. This branch point might cause undesired signal reflection that might adversely affect signal integrity. Nonetheless, thesystem800 minimizes the signal degradation by mounting the plurality of memory ranks directly on themotherboard502.
• FIG. 9 is a top view of an embodiment of amemory system900 according to the present invention. Thesystem900 is substantially similar to thesystem500 with the addition of a phase locked loop (PLL)520 in eachmemory rank516. ThePLL520 is capable of generating afirst clock 1 stCLK responsive to the system clock CLK. ThePLL520 provides the 1 stCLK signal to itscorresponding memory devices508. By adding thePLL520, thesystem900 avoids having to route the system clock separately to eachmemory device508 from thememory controller504. In another embodiment, thePLL520 might likewise be replaced with a delay locked loop (DLL) that operates similarly to thePLL520. That is, the DLL is capable of generating the 1 stCLK responsive the system clock CLK and to provide the 1 stCLK to itscorresponding memory devices508.
• FIG. 10 is a top view of an embodiment of amemory system1000 according to the present invention. Thesystem1000 is substantially similar to thesystem900 with the addition of amemory module706. Thememory module716 operates substantially as described earlier with reference toFIG. 7. Thememory module716 includes aPLL720 that is capable of generating afirst clock 1 stCLK responsive to the system clock CLK and amodule board706. ThePLL720 provides the 1 stCLK signal to itscorresponding memory devices708 on thememory module716. By adding thePLL720, thesystem1000 avoids having to route the system clock separately to eachmemory device508,708 from thememory controller504. In another embodiment, thePLL520,720 might likewise be replaced with a delay locked loop (DLL) that operates similarly to thePLL520,720. That is, the DLL is capable of generating the 1 stCLK responsive the system clock CLK and to provide the 1 stCLK to itscorresponding memory devices508,708.
• In an embodiment, at least onefirst memory device708 receives the command and address signals outputted from the command and address buffer through a second command and address signal trace routed on the motherboard. In an embodiment, the first command and address signal trace is arranged substantially perpendicularly with the second command and address signal trace.
• FIG. 11 is a top view of an embodiment of the memory system according to the present invention. Thesystem1100 is substantially similar to thesystem500 shown inFIG. 5, with the exception that thecontroller504 can optionally provide the data signals DQ to thebuffer510 that, in turn, provides the data signals DQ to each of thedevices508. Similarly, the controller optionally504 can provide the system clock CLK to thebuffer510 that, in turn, provides the system clock CLK to each of thedevices508. Put differently, the plurality ofmemory devices508 can receive the data signals DQ and the system clock CLK directly from thebuffer510 that, in turn, receives the data signals DQ and the system clock CLK from thecontroller504.
• FIG. 12FIG. 12 is a top view of an embodiment of the memory system according to the present invention. Thesystem1200 is substantially similar to thesystem900 shown inFIG. 9, with the exception that thecontroller504 can provide the DQ data signals to thePLL520 that, in turn, provides the DQ data signals to thebuffer510 and to each of thedevices508. Similarly, thecontroller504 can provide the system CLK signal to thePLL520 that, in turn, provides the system CLK signal to thebuffer510 and to each of thedevices508.
• Having illustrated and described the principles of our invention(s), it should be readily apparent to those skilled in the art that the invention(s) can be modified in arrangement and detail without departing from such principles. We claim all modifications coming within the spirit and scope of the accompanying claims.

Claims (37)

1. A memory system, comprising:

a first buffer mounted on a motherboard;

at least one first memory device coupled to the first buffer and mounted to the motherboard;

a plurality of signal traces routed on the motherboard to the first buffer and the at least one first memory device; and

at least one memory module electrically coupled to a memory controller through a socket mounted on the motherboard.

2. The memory system ofclaim 1 where the at least one memory module comprises:

a second buffer mounted on a module board of the at least one memory module; and

at least one second memory device mounted on the module board of at least one memory module and coupled to the second buffer.

3. The memory system ofclaim 2 where the at least one second memory device is one of a DRAM and SDRAM.

4. The memory system ofclaim 1 where the at least one memory module is located farther from the memory controller on the motherboard than the at least one first memory device.

5. A memory system, comprising:

a first buffer mounted on a motherboard;

at least one first memory device coupled to the first buffer and mounted to the motherboard;

a plurality of signal traces routed on the motherboard to the first buffer and the at least one first memory device; and

a phase locked loop mounted on the motherboard and capable of generating a first clock signal on a second clock trace responsive to the system clock signal on a first clock trace;

where the at least one first memory device is synchronous with the first clock signal.

6. The memory system ofclaim 5 where the first clock trace for the system clock is arranged substantially perpendicularly with the second clock trace for the first clock.

7. A memory system, comprising:

a first buffer mounted on a motherboard;

at least one first memory device coupled to the first buffer and mounted to the motherboard;

a plurality of signal traces routed on the motherboard to the first buffer and the at least one first memory device; and

a delay locked loop mounted on the motherboard and capable of generating a first clock signal on a second clock trace responsive to the system clock signal on a first clock trace;

where the at least one first memory device is operated in synchronization with the first clock signal.

8. The memory system ofclaim 7 where the first clock trace for the system clock is arranged substantially perpendicularly with the second clock trace for the first clock.

9. A memory system, comprising:

at least one memory rank mounted directly on a motherboard;

a plurality of signal traces routed on the motherboard to the at least one memory rank; and

a phase locked loop capable of generating a first clock signal on a second clock trace responsive to a system clock signal on a first clock trace, where the at least one first memory device is operated in synchronization with the first clock signal;

where the at least one memory rank comprises:

at least one first memory device; and

a first buffer capable of driving address and command signals to the at least one first memory device through corresponding signal traces routed on the motherboard;

where the at least one first buffer receives a command and address signal through a first command and address signal trace routed on the motherboard; and

where the at least one first memory device is one of a DRAM and SDRAM.

10. The memory system ofclaim 9

where the at least one first memory device receives the command and address signal outputted from the at least one first buffer through a second command and address signal trace routed on the motherboard; and

where the first command and address signal trace is arranged substantially perpendicularly with the second command and address signal trace

11. The memory system ofclaim 9 where the at least one first memory device receives a data signal and a clock signal through corresponding data and clock signal traces routed on the motherboard.

12. The memory system ofclaim 9 where the first clock trace for the system clock signal is arranged substantially perpendicularly with the second clock trace for the first clock signal.

13. A memory system, comprising:

at least one memory rank mounted directly on a motherboard;

a plurality of signal traces routed on the motherboard to the at least one memory rank; and

a delay locked loop capable of generating a first clock signal on a second clock trace responsive to a system clock signal on a first clock trace;

where the at least one first memory device is synchronous with the first clock signal;

where the at least one memory rank comprises:

at least one first memory device; and

a first buffer capable of driving address and command signals to the at least one first memory device through corresponding signal traces routed on the motherboard;

where the at least one first buffer receives a command and address signal through a first command and address signal trace routed on the motherboard; and

where the at least one first memory device is one of a DRAM and SDRAM.

14. The memory system ofclaim 13 where the first clock trace for the system clock signal is arranged substantially perpendicularly with the second clock trace for the first clock signal.

15. A memory system comprising:

at least one memory rank mounted directly on a motherboard;

a plurality of signal traces routed on the motherboard to the at least one memory rank;

a memory module; and

a receptacle mounted on the motherboard and capable of receiving the memory module;

where the at least one memory rank comprises:

at least one first memory device; and

a first buffer capable of driving address and command signals to the at least one first memory device through corresponding signal traces routed on the motherboard;

where the at least on first buffer receives a command and address signal through a first command and address signal trace routed on the motherboard;

where the at least one first memory device receives the command and address signal outputted from the at least one first buffer through a second command and address signal trace routed on the motherboard; and

where the first command and address signal trace is arranged substantially perpendicularly with the second command and address signal trace.

16. The memory system ofclaim 15 where the memory module includes:

a plurality of second memory devices mounted on a module board of the memory module; and

a second buffer mounted on the module board of the memory module and capable of driving the plurality of second memory devices.

17. The memory system ofclaim 15 comprising a phase locked loop capable of generating a first clock responsive to a system clock, where the plurality of second memory devices are operated in synchronization with the first clock.

18. The memory system ofclaim 15 comprising a delay locked loop capable of generating a first clock responsive to a system clock, where the plurality of second memory devices are operated in synchronization with the first clock signal.

19. The memory system ofclaim 15 where the receptacle is located farther from a memory controller on the motherboard than the at least one first memory device.

20. A method comprising:

mounting a plurality of first memory devices on a motherboard; and

mounting a first command and address buffer capable of driving the plurality of memory devices on the motherboard with corresponding command and address signals.

21. The method ofclaim 20 comprising routing a first signal traces for the command and address signals from the buffer to the memory device on the motherboard.

22. The method ofclaim 21 comprising routing a second signal traces for the command and address signals from a memory controller mounted on the motherboard to the first command and address buffer, where the first signal traces is substantially perpendicular with the second signal traces.

23. The method ofclaim 21 comprising mounting a phase locked loop on the motherboard, the phase locked loop being capable of generating a first clock responsive to the system clock.

24. The method ofclaim 21 comprising mounting a delay locked loop on the motherboard, the delay locked loop being capable of generating a first clock responsive to the system clock.

25. The method ofclaim 21 comprising electrically coupling a memory module to a memory controller mounted on the motherboard through a receptacle mounted on the motherboard.

26. The method ofclaim 21 comprising:

mounting a second memory device on a module board of a memory module; and

mounting a second command and address buffer on the module board, where the module board is coupled to a memory controller through a socket mounted on the motherboard.

27. The method ofclaim 26 comprising mounting a phase locked loop on the motherboard, the phase locked loop being capable of generating a first clock responsive to the system clock.

28. The method ofclaim 27 comprising mounting a delay locked loop on the motherboard, the delay locked loop being capable of generating a first clock responsive to the system clock.

29. A memory system, comprising:

a memory controller mounted directly on a motherboard and generating a plurality of command and address signals;

a first buffer mounted directly on the motherboard and receiving the command and address signals;

at least one first memory device coupled to the first buffer and mounted directly to the motherboard;

at least one memory module comprising a second buffer mounted on a module board and receiving the command and address signals, and at least one second memory device coupled to the second buffer, the at least one second memory device being mounted on farther from the memory controller than the at least one first memory device;

a plurality of first signal traces routed on the motherboard to the first buffer and the at least one first memory device; and

a plurality of second signal traces routed on the module board to the second buffer and the at least one second memory device.

30. A memory system, comprising:

a memory controller mounted directly on a motherboard and generating a plurality of command and address signals

a first buffer mounted directly on the motherboard and receiving the command and address signals;

a phase locked loop mounted directly on the motherboard and receiving a clock signal;

at least one first memory device coupled to the first buffer and mounted directly to the motherboard; and

a plurality of signal traces routed on the motherboard to the first buffer and the at least one first memory device;

where the first memory device is synchronous with an internal clock signal outputted from the phase locked loop.

31. A memory system, comprising:

a memory controller mounted directly on a motherboard and generating a plurality of command and address signals;

a first buffer mounted directly on the motherboard and receiving the command and address signals;

a first phase locked loop mounted directly on the motherboard and receiving a clock signal;

at least one first memory device coupled to the first buffer and mounted directly to the motherboard;

at least one memory module comprising a second buffer mounted on a module board and receiving the command and address signals, and at least one second memory device coupled to the second buffer, the at least one second memory device being mounted on the motherboard farther from the memory controller than the at least one first memory device;

a second phase locked loop mounted on the module board and receiving the clock signal;

a plurality of first signal traces routed on the motherboard to the first buffer and the at least one first memory device; and

a plurality of second signal traces routed on the module board to the second buffer and the at least one second memory device;

where the first memory device operates synchronous with a first internal clock signal outputted from the first phase locked loop, the second memory device operates synchronous with a second internal clock signal outputted from the second phase locked loop.

32. A memory system, comprising:

a first buffer chip directly mounted on a motherboard;

at least one first memory chip coupled to the first buffer chip and directly mounted on the motherboard; and

a plurality of signal traces routed on the motherboard to the first buffer chip and the at least one first memory chip;

where the system eliminates signal reflection caused by signal trace discontinuities of the first buffer chip and the at least one first memory chip by directly mounting the first buffer chip and the at least one first memory chip on the motherboard without an intervening socket;

where the first buffer chip is capable of buffering a data signal and providing the data signal to the at least one first memory chip.

33. The memory system ofclaim 32 where the first buffer chip is capable of buffering a clock signal and providing the clock signal to the at least one first memory chip.

34. The memory system ofclaim 32 where the first buffer chip receives a command and address signal through a first command and address signal trace routed on the motherboard.

35. The memory system ofclaim 32

where the at least one first memory chip receives the command and address signals outputted from the first buffer chip through a second command and address signal trace routed on the motherboard; and

where the first command and address signal trace is arranged substantially perpendicular to the second command and address signal trace.

36. The memory system ofclaim 32 where the at least one first memory chip is one of a DRAM and SDRAM.

37. The memory system ofclaim 32 where the at least one first memory chip receives a data signal and a clock signal through corresponding data and clock signal traces routed on the motherboard.

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