US20070249094A1 - Method for fabricating multi-chip semiconductor package - Google Patents

Abstract

A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.

Description

FIELD OF THE INVENTION
• The present invention relates to multi-chip semiconductor packages and fabrication methods thereof, and more particularly, to a multi-chip semiconductor package with a packaged chip and a flip chip being incorporated on a substrate, and a method of fabricating the semiconductor package.
BACKGROUND OF THE INVENTION
• In accordance with electronic products being developed with compact size, light weight and high efficiency, semiconductor packages have been correspondingly reduced in profile and preferably incorporated with multiple chips to be suitable for use with the electronic products. Such structure with multiple semiconductor chips being mounted in a single package is customarily referred to as a multi-chip semiconductor package, wherein the multiple chips can be vertically stacked on a chip carrier (such as a substrate or lead frame) or individually attached to the substrate. The multi-chip package structure has a primary advantage for providing the semiconductor package with effectively enhanced or multiplied electrical and operational performances, making it suitably used in the highly efficient electronic product.
• U.S. Pat. Nos. 5,696,031 and 5,973,403 have disclosed a multi-chip semiconductor package. Referring toFIG. 5, in this semiconductor package, afirst chip21 is mounted on a surface of asubstrate20 in a flip-chip manner that anactive surface210 of thefirst chip21 faces downwards and is electrically connected to thesubstrate20 via a plurality ofsolder bumps22. Then, asecond chip23 is attached to anon-active surface211 of thefirst chip21 and is electrically connected to thesubstrate20 via a plurality ofbonding wires24. Anencapsulation body25 is formed on thesubstrate20 to encapsulate thefirst chip21,second chip23 andbonding wires24. Finally, a plurality of solder balls26 are implanted on an opposite surface of thesubstrate20. This completes fabrication of the multi-chip semiconductor package. Since the wire-bonding process performed on thesecond chip23 would generate shocks that may cause cracks of thesolder bumps22, an underfill process is carried out between thefirst chip21 and thesubstrate20 to fill an insulating material (such as a resin material, etc.) in gaps between theadjacent solder bumps22, so as to enhance the mechanical strength of thesolder bumps22 and prevent them from cracks due to the shocks generated by the wire-bonding process.
• However, during the underfill process for the above semiconductor package, the procedure of filling the insulating material may easily contaminate predetermined positions (such as bond fingers) on the substrate for connecting the bonding wires, and the bonding wires cannot be fly bonded to the contaminated bond fingers, such that the yield of the wire-bonding process and the quality of electrical connection between the second chip and the substrate would be degraded, and the reliability of the entire semiconductor package is thus deteriorated. Moreover, for the second chip that is electrically connected to the substrate via the bonding wires, since the second chip is directly incorporated in the semiconductor package with the quality and yield of the second chip being unknown, a known good die (KGD) issue is produced. In other words, if the second chip not passing a burn-in test incurs quality defects, the entire package having such second chip would fail and the product yield is reduced.
• U.S. Patent Publication No. 2004/0113275 has disclosed another multi-chip semiconductor package. As shown inFIG. 6, this semiconductor package allows afirst chip31 to be mounted on a surface of asubstrate30 in a flip-chip manner, wherein anactive surface310 of thefirst chip31 faces downwards and is electrically connected to thesubstrate30 via a plurality ofsolder bumps32. An insulating material (such as a resin material, etc.) is filled in gaps between theadjacent solder bumps32 using an underfill technique. Then, a land grid array (LGA) package structure33 is attached to anon-active surface311 of thefirst chip31 in an inverted manner, and asubstrate330 of the LGA package structure33 is electrically connected to thesubstrate30 via a plurality ofbonding wires34. Anencapsulation body35 is formed on thesubstrate30 to encapsulate thefirst chip31, LGA package structure33 andbonding wires34. Finally, a plurality ofsolder balls36 are implanted on an opposite surface of thesubstrate30. This completes fabrication of the multi-chip semiconductor package.
• Although the above fabrication method may solve the KGD problem, the multi-chip semiconductor package shown inFIG. 6 still have the similar drawback to that shown inFIG. 5. As the underfill process is required to fill the gaps between theadjacent solder bumps32 with the insulating material so as to enhance the mechanical strength of thesolder bumps32 and prevent them from cracks due to shocks during the wire-bonding process, the procedure of filling the insulating material may easily contaminate predetermined positions (such as bond fingers) on thesubstrate30 for connecting thebonding wires34, and thebonding wires34 cannot be firmly bonded to the contaminated bond fingers, thereby degrading the yield of the wire-bonding process and the quality of electrical connection between the LGA package structure33 and thesubstrate30, as well as deteriorating the reliability of the entire semiconductor package.
• Therefore, the problem to be solved here is to provide a multi-chip semiconductor package, which can prevent predetermined positions for electrical connection on a substrate from contamination and eliminate a KGD issue so as to assure the reliability and yield of the semiconductor package.
SUMMARY OF THE INVENTION
• In light of the above drawbacks in the prior art, an objective of the present invention is to provide a multi-chip semiconductor package and a fabrication method thereof, which do not require an underfill process, such that predetermined positions for electrical connection on a substrate can be prevented from contamination, and the electrical connection quality and reliability of the semiconductor package are assured.
• Another objective of the present invention is to provide a multi-chip semiconductor package and a fabrication method thereof, wherein a preformed package structure passing a burn-in test is incorporated in the semiconductor package, such that a known good die (KGD) issue can be eliminated, and the reliability and yield of the semiconductor package are assured.
• A further objective of the present invention is to provide a multi-chip semiconductor package and a fabrication method thereof, with a thermally conductive adhesive being applied between an upper packaged chip and a lower flip chip in the semiconductor package, such that heat generated by the upper chip can be transmitted to the lower chip and then to a substrate to be dissipated out of the semiconductor package, thereby effectively improving the heat dissipating efficiency of the semiconductor package.
• In accordance with the above and other objectives, the present invention proposes a multi-chip semiconductor package, comprising a substrate having an upper surface and a lower surface opposed to the upper surface; at least one first chip having an active surface and a non-active surface, wherein the active surface of the first chip is mounted on and electrically connected to the upper surface of the substrate via a plurality of solder bumps; a preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, wherein outer leads of the lead frame are exposed from the first encapsulation body and mounted on the upper surface of the substrate, such that the first encapsulation body, the exposed outer leads and the substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body; a second encapsulation body formed on the upper surface of the substrate to encapsulate the first chip, the solder bumps and the preformed package structure; and a plurality of solder balls implanted on the lower surface of the substrate. The present invention also proposes a fabrication method of the above multi-chip semiconductor package, comprising the steps of: preparing a substrate having an upper surface and a lower surface opposed to the upper surface; providing at least one first chip having an active surface and a non-active surface, and allowing the active surface of the first chip to be mounted on and electrically connected to the upper surface of the substrate via a plurality of solder bumps; mounting a preformed package structure on the upper surface of the substrate, the preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, wherein outer leads of the lead frame are exposed from the first encapsulation body and mounted on the upper surface of the substrate, such that the first encapsulation body, the exposed outer leads and the substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body; forming a second encapsulation body on the upper surface of the substrate to encapsulate the first chip, the solder bumps and the preformed package structure; and implanting a plurality of solder balls on the lower surface of the substrate.
• The above multi-chip semiconductor package can also be fabricated by a batch method comprising the steps of: providing a substrate strip comprising a plurality of substrates and having an upper surface and a lower surface opposed to the upper surface; mounting at least one first chip on the upper surface of each of the substrates, the first chip having an active surface and a non-active surface, and allowing the active surface of the first chip to be mounted on and electrically connected to the upper surface of each of the substrates via a plurality of solder bumps; mounting a preformed package structure on the upper surface of each of the substrates, the preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, wherein outer leads of the lead frame are exposed from the first encapsulation body and mounted on the upper surface of each of the substrates, such that the first encapsulation body, the exposed outer leads and the corresponding substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body; forming a second encapsulation body on the upper surface of the substrate strip to encapsulate all of the first chips, the solder bumps and the preformed package structures; implanting a plurality of solder balls on the lower surface of the substrate strip; and performing a singulation process to cut the second encapsulation body and the substrate strip so as to separate apart the plurality of substrates and form a plurality of individual semiconductor packages.
• The second chip in the preformed package structure is electrically connected to the lead frame via a plurality of bonding wires. The lead frame comprises a die pad and a plurality of leads, wherein each of the leads is composed of an inner lead and an outer lead. The second chip is mounted on an upper surface of the die pad and electrically connected to the inner leads. The inner leads and the bonding wires are encapsulated by the first encapsulation body. In one preferred embodiment, the die pad is encapsulated by the first encapsulation body, and the gap between the first chip and the first encapsulation body is filled with the second encapsulation body. In another preferred embodiment, a lower surface of the die pad is exposed from the first encapsulation body and abuts against the gap between the first chip and the first encapsulation body, such that a thermally conductive adhesive is filled in the gap between the first chip and the first encapsulation body prior to fabrication of the second encapsulation body.
• The above multi-chip semiconductor package and its fabrication methods allow a substrate to accommodate both a packaged chip and a flip chip. This is accomplished by firstly, electrically connecting a first chip in a flip-chip manner to the substrate via a plurality of solder bumps, and then mounting a preformed package structure on the substrate, wherein the preformed package structure is incorporated with a second chip and has exposed outer leads that are mounted and electrically connected to the substrate by surface mount technology (SMT), such that a first encapsulation body of the preformed package structure, the exposed outer leads and the substrate form a space where the first chip is received, and the first encapsulation body is supported above the first chip, with a gap being present between the first encapsulation body and the first chip. Since the preformed package structure is electrically connected to the substrate by the surface mount technology, the solder bumps located between the first chip and the substrate would not subject to cracks caused by shocks generated during a wire-bonding process in the prior art. Thus, an underfill process is not required in the present invention to fill gaps between the adjacent solder bumps located between the first chip and the substrate. On the other hand, in the present invention, a single molding process is carried out to form a second encapsulation body for encapsulating the first chip and the preformed package structure as well as filling the gap between the first encapsulation body and the first chip and the gaps between the adjacent solder bumps. This can prevent predetermined positions on the substrate for mounting the outer leads of the preformed package structure from contamination by the underfill process, and assure the preformed package structure to be well mounted and electrically connected to the substrate, such that the electrical connection quality and reliability of the entire semiconductor package would not be affected. Moreover, the fabricated preformed package structure before being mounted on the substrate is subjected to a burn-in test. Specifically, only the preformed package structure that has successfully passed the burn-in test would be mounted on the substrate. As a result, the preformed package structure would not contain a second chip that is defective or unknown with its quality, such that the conventional known good die (KGD) problem can be eliminated, and the reliability and yield of the entire semiconductor package are assured. Additionally, in another preferred embodiment of the present invention, a lead frame of the preformed package structure has a die pad exposed from the first encapsulation body, with a lower surface of the die pad abutting against the gap between the first encapsulation body and the first chip, and prior to fabricating the second encapsulation body, a thermally conductive adhesive is applied in the gap between the first encapsulation body and the first chip, such that heat generated by the second chip mounted on the die pad can be transmitted via the die pad and the thermally conductive adhesive to the first chip and then transmitted via the solder bumps and the substrate to be dissipated out of the semiconductor package. This thus effectively improves the heat dissipating efficiency of the entire semiconductor package. Furthermore, the semiconductor package in the present invention has a multi-chip structure containing at least the first and second chips, thereby providing the entire semiconductor package with enhanced electrical and operational performances.
BRIEF DESCRIPTION OF THE DRAWINGS
• The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
• FIG. 1 is a cross-sectional view of a multi-chip semiconductor package according to a first preferred embodiment of the present invention;
• FIGS. 2A to2E are schematic diagrams showing a set of steps of fabricating the semiconductor package inFIG. 1;
• FIGS. 3A to3F are schematic diagrams showing another set of steps of fabricating the semiconductor package inFIG. 1;
• FIG. 4 is a cross-sectional view of a multi-chip semiconductor package according to a second preferred embodiment of the present invention;
• FIG. 5 (PRIOR ART) is a cross-sectional view of a conventional multi-chip semiconductor package; and
• FIG. 6 (PRIOR ART) is a cross-sectional view of another conventional multi-chip semiconductor package.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• As shown inFIG. 1, a multi-chip semiconductor package according to a first preferred embodiment of the present invention comprises asubstrate10 having anupper surface100 and alower surface101 opposed to theupper surface100; at least onefirst chip11 mounted on and electrically connected to theupper surface100 of thesubstrate10 via a plurality ofsolder bumps12 in a flip-chip manner; apreformed package structure13 mounted on and electrically connected to theupper surface100 of thesubstrate10 viaouter leads143 exposed from afirst encapsulation body16 of thepreformed package structure13, wherein thefirst encapsulation body16, theouter leads143 and thesubstrate10 form a space S where thefirst chip11 is received, and a gap G is present between thefirst chip11 and thefirst encapsulation body16; asecond encapsulation body17 formed on theupper surface100 of thesubstrate10 to encapsulate thefirst chip11, thesolder bumps12 and thepreformed package structure13 and fill the space S and the gap G; and a plurality ofsolder balls18 implanted on thelower surface101 of thesubstrate10.
• Thesubstrate10 can be a normal substrate having predetermined circuitry (not shown) to accommodate both thepreformed package structure13 and the first chip11 (flip chip). Thesubstrate10 is primarily made of a resin material such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin or FR4 resin, etc.
• Thefirst chip11 has anactive surface110 and anon-active surface111 opposed to theactive surface110, wherein a plurality of electronic elements (not shown), electronic circuits (not shown) andbond pads112 are disposed on theactive surface110. Thebond pads112 are bonded to the plurality of solder bumps12 to allow theactive surface110 of thefirst chip11 to be mounted on and electrically connected to theupper surface100 of thesubstrate10 via the solder bumps12 in the flip-chip manner.
• The preformedpackage structure13 comprises alead frame14, at least onesecond chip15 mounted on and electrically connected to thelead frame14, and thefirst encapsulation body16 for encapsulating thesecond chip15 and a portion of thelead frame14. Thelead frame14 includes adie pad140 and a plurality ofleads141, wherein each of theleads141 is composed of aninner lead142 and anouter lead143.
• Thesecond chip15 is mounted on thedie pad140 and is electrically connected to the inner leads142 via a plurality ofbonding wires19. Thedie pad140 and the inner leads142 are encapsulated by thefirst encapsulation body16.
• Moreover, thefirst encapsulation body16 can be made of a same or different conventional resin material as or from thesecond encapsulation body17; for example, a commonly used resin material includes epoxy resin and the like.
• The multi-chip semiconductor package shown inFIG. 1 can be fabricated by the procedural steps shown inFIGS. 2A to2E.
• First referring toFIG. 2A, asubstrate10 is provided, which has anupper surface100 and alower surface101 opposed to theupper surface100. Thesubstrate10 can be a normal substrate having predetermined circuitry (not shown), and is primarily made of a resin material such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin or FR4 resin, etc. Since the structure and fabrication of the substrate are both known in the art, they are not to be further described here.
• Referring toFIG. 2B, at least onefirst chip11 is provided, which has anactive surface110 and anon-active surface111 opposed to theactive surface110, wherein a plurality of electronic elements (not shown), electronic circuits (not shown) andbond pads112 are disposed on theactive surface110. Next, a plurality of solder bumps12 are formed on thebond pads112 of theactive surface110 of thefirst chip11. Then, thefirst chip11 is mounted on theupper surface100 of thesubstrate10 in a flip-chip manner that theactive surface110 of thefirst chip11 faces downwards and is electrically connected to theupper surface100 of thesubstrate10 via the plurality of solder bumps12. The fabrication of the first chip and solder bumps is known in the art and thus not to be further detailed herein.
• Referring toFIG. 2C, a preformedpackage structure13 is mounted on theupper surface100 of thesubstrate10. The preformedpackage structure13 can be a pre-fabricated lead-frame-based quad flat package (QFP) and successfully passes the conventional burn-in test. The preformedpackage structure13 comprises alead frame14, at least onesecond chip15 mounted on and electrically connected to thelead frame14, and afirst encapsulation body16 for encapsulating thesecond chip15 and a portion of thelead frame14, wherein thefirst encapsulation body16 is made of a conventional resin material such as epoxy resin, etc. Thelead frame14 includes adie pad140 and a plurality ofleads141, wherein each of theleads141 is composed of aninner lead142 and anouter lead143. Thesecond chip15 is mounted on an upper surface of thedie pad140 and is electrically connected to the inner leads142 via a plurality ofbonding wires19. Thedie pad140, the inner leads142 and thebonding wires19 are encapsulated by thefirst encapsulation body16, with the outer leads143 being exposed from thefirst encapsulation body16. The exposedouter leads143 are used to mount and electrically connect the preformedpackage structure13 to theupper surface100 of thesubstrate10 via for example, surface mount technology (SMT), etc. As a result, thefirst encapsulation body16 is supported above thefirst chip11 and forms a space S together with the outer leads143 and thesubstrate10 to receive thefirst chip11 therein, and a gap G is present between thefirst encapsulation body16 and thenon-active surface111 of thefirst chip11. The surface mount technology is known in the art and thus not to be further detailed herein.
• Referring toFIG. 2D, a molding process is performed using an encapsulation mold having an upper mold and a lower mold (not shown), wherein the upper mold is formed with a cavity, and the lower mold can be a flat mold. Thesubstrate10 mounted with thefirst chip11 and the preformedpackage structure13 thereon is placed in the encapsulation mold, wherein thefirst chip11 and the preformedpackage structure13 are received in the cavity of the upper mold, and thesubstrate10 is clamped between the upper and lower molds, with thelower surface101 of thesubstrate10 abutting against the flat lower mold. Then, a conventional resin material (such as epoxy resin, etc.) is injected into the cavity of the upper mold to encapsulate thefirst chip11, the solder bumps12 and the preformedpackage structure13 on theupper surface100 of thesubstrate10, and fill the space S, the gap G between thefirst chip11 and thefirst encapsulation body16, and gaps between the adjacent solder bumps12. When the resin material is cured, the encapsulation mold can be removed from thesubstrate10, such that asecond encapsulation body17 is formed on theupper surface100 of thesubstrate10. Since thelower surface101 of thesubstrate10 abuts against the flat lower mold during molding, no resin material orsecond encapsulation body17 would be formed on thelower surface101 of thesubstrate10, and thus thelower surface101 of thesubstrate10 is exposed after the encapsulation mold is removed. Thesecond encapsulation body17 can be made of a same or different conventional resin material as or from thefirst encapsulation body16.
• Finally, referring toFIG. 2E, a ball-implanting process is carried out to implant a plurality ofsolder balls18 on the exposedlower surface101 of thesubstrate10. This thus completes fabrication of the multi-chip semiconductor package in the present invention. Thesolder balls18 may serve as input/output (I/O) connections of the semiconductor package to be connected to an external device such as a printed circuit board (not shown), so as to establish an electrical connection between the semiconductor package and the external device via thesolder balls18. The ball-implanting process is known in the art and not to be further described herein.
• In addition, the multi-chip semiconductor package shown inFIG. 1 can also be fabricated by a batch method with reference toFIGS. 3A to3F.
• First referring toFIG. 3A, asubstrate strip1 is provided, which comprises a plurality of integrally formedsubstrates10 and has anupper surface100 and alower surface101 opposed to theupper surface100, wherein theadjacent substrates10 are bordered by dotted cutting lines shown in the drawing. Thesubstrate strip1 is formed with predetermined circuitry (not shown), and is primarily made of a resin material such as epoxy resin, polyimide resin, BT resin or FR4 resin, etc.
• Referring toFIG. 3B, a plurality offirst chips11 are provided, each of thefirst chips11 having anactive surface110 and anon-active surface111, wherein a plurality of electronic elements (not shown), electronic circuits (not shown) andbond pads112 are disposed on theactive surface110 of each of thefirst chips11. Then, a plurality of solder bumps12 are formed on thebond pads112 of theactive surface110 of each of thefirst chips11. Subsequently, at least one of thefirst chips11 is mounted on theupper surface100 of each of thesubstrates10 in a flip-chip manner that theactive surface110 of thefirst chip11 faces downwards and is electrically connected to theupper surface100 of the correspondingsubstrate10 via the solder bumps12.
• Referring toFIG. 3C, a preformedpackage structure13 is mounted on theupper surface100 of each of thesubstrates10. The preformedpackage structure13 can have a structure as that shown inFIG. 2C, comprising alead frame14, at least onesecond chip15 mounted on and electrically connected to thelead frame14, and a first encapsulation body16 (made of a resin material such as epoxy resin, etc.) for encapsulating thesecond chip15 and a portion of thelead frame14. Thelead frame14 includes adie pad140 and a plurality ofleads141, wherein each of theleads141 is composed of aninner lead142 and anouter lead143. Thesecond chip15 is mounted on an upper surface of thedie pad140 and is electrically connected to the inner leads142 via a plurality ofbonding wires19. Thedie pad140, the inner leads142 and thebonding wires19 are encapsulated by thefirst encapsulation body16, with the outer leads143 being exposed from thefirst encapsulation body16. The exposedouter leads143 are used to mount and electrically connect the preformedpackage structure13 to theupper surface100 of each of thesubstrates10 via for example, surface mount technology (SMT), etc. As a result, thefirst encapsulation body16 of the preformedpackage structure13 is supported above each of thefirst chips11 and forms a space S together with the outer leads143 and the correspondingsubstrate10 to receive the correspondingfirst chip11 therein, and a gap G is present between thefirst encapsulation body16 and thenon-active surface111 of the correspondingfirst chip11.
• Referring toFIG. 3D, a molding process is performed to form asecond encapsulation body17 on theupper surface100 of thesubstrate strip1. First, thesubstrate strip1 mounted with the plurality offirst chips11 and preformedpackage structures13 is placed in an encapsulation mold (not shown), allowing the plurality offirst chips11 and preformedpackage structures13 to be received in a cavity of the encapsulation mold. Then, a resin material (such as epoxy resin, etc.) is injected into the cavity to encapsulate all of thefirst chips11, the solder bumps12 and the preformedpackage structures13, and fill all of the foregoing spaces S, the gaps between thefirst chips11 and thefirst encapsulation bodies16, and gaps between the adjacent solder bumps12. When the resin material is cured, the encapsulation mold can be removed from thesubstrate strip1, and thus thesecond encapsulation body17 is completely fabricated. Thesecond encapsulation body17 can be made of a same or different conventional resin material as or from thefirst encapsulation body16.
• Subsequently, referring toFIG. 3E, a ball-implanting process is carried out to implant a plurality ofsolder balls18 on thelower surface101 of each of thesubstrates10.
• Finally, referring toFIG. 3F, a singulation process is performed to cut thesubstrate strip1 and thesecond encapsulation body17 along the cutting lines on thesubstrate strip1, so as to separate apart the plurality ofsubstrates10 and form a plurality of individual semiconductor packages. The singulation process is known in the art and thus not to be further detailed herein. The singulated semiconductor packages each has the plurality ofsolder balls18 that may serve as I/O connections of the corresponding semiconductor package to be electrically connected to an external device such as a printed circuit board (not shown), so as to establish an electrical connection between the semiconductor package and the external device via thesolder balls18.
• FIG. 4 shows a multi-chip semiconductor package according to a second preferred embodiment of the present invention. As shown inFIG. 4, this semiconductor package differs from that of the above first embodiment in that the preformedpackage structure13 is a lead-frame-based package with an exposed die pad. In particular, a lower surface of thedie pad140 of thelead frame14 is exposed from thefirst encapsulation body16 and is flush with thefirst encapsulation body16. The exposed lower surface of thedie pad140 abuts against the gap G between thefirst chip11 and thefirst encapsulation body16. A thermallyconductive adhesive2, instead of thesecond encapsulation body17 for encapsulating thefirst chip11, is applied in the gap G. The thermallyconductive adhesive2 allows the preformedpackage structure13 to be thermally connected via its exposeddie pad140 to thefirst chip11, such that heat generated by thesecond chip15 mounted on thedie pad140 can be transmitted to thefirst chip11 and then to the solder bumps12 and thesubstrate10 to be dissipated out of the semiconductor package. Such additional heat dissipating path can effectively improve the heat dissipating efficiency of the semiconductor package.
• The multi-chip semiconductor package in the second embodiment can be fabricated by the steps similar to those shown inFIGS. 2A to2E or by a batch method similar to that shown inFIGS. 3A to3F. The fabrication processes of the semiconductor package in the second embodiment differ from those shown inFIGS. 2A to2E orFIGS. 3A to3F in that, after thesubstrate10 is provided and thefirst chip11 is mounted on thesubstrate10 inFIGS. 2A to2B andFIGS. 3A to3B, a thermallyconductive adhesive2 is applied on thenon-active surface111 of thefirst chip11. Then, a process similar toFIG. 2C or3C for mounting the preformedpackage structure13 on thesubstrate10 is performed, wherein the exposed lower surface of thedie pad140 and thefirst encapsulation body16 of the preformedpackage structure13 are attached to the thermallyconductive adhesive2, making the thermallyconductive adhesive2 fill the gap G between thefirst chip11 and thefirst encapsulation body16. Subsequently, the processes shown inFIGS. 2D to2E orFIGS. 3D to3F are carried out. Since the thermallyconductive adhesive2 is filled in the gap G between thefirst chip11 and thefirst encapsulation body16 prior to the molding process ofFIG. 2D or3D, thesecond encapsulation body17 formed by molding would not fill the gap G. Further as described above, the provision of thermallyconductive adhesive2 facilitates dissipation of heat generated by thesecond chip15 in the preformedpackage structure13, thereby effectively improving the overall heat dissipating efficiency of the semiconductor package.
• The above multi-chip semiconductor package and its fabrication methods according to the present invention allow a substrate to accommodate both a packaged chip and a flip chip. This is accomplished by firstly, electrically connecting a first chip in a flip-chip manner to the substrate via a plurality of solder bumps, and then mounting a preformed package structure on the substrate, wherein the preformed package structure is incorporated with a second chip and has exposed outer leads that are mounted and electrically connected to the substrate by surface mount technology (SMT), such that a first encapsulation body of the preformed package structure, the exposed outer leads and the substrate form a space where the first chip is received, and the first encapsulation body is supported above the first chip, with a gap being present between the first encapsulation body and the first chip. Since the preformed package structure is electrically connected to the substrate by the surface mount technology, the solder bumps located between the first chip and the substrate would not subject to cracks caused by shocks generated during a wire-bonding process in the prior art. Thus, an underfill process is not required in the present invention to fill gaps between the adjacent solder bumps located between the first chip and the substrate. On the other hand, in the present invention, a single molding process is carried out to form a second encapsulation body for encapsulating the first chip and the preformed package structure as well as filling the gap between the first encapsulation body and the first chip and the gaps between the adjacent solder bumps. This can prevent predetermined positions on the substrate for mounting the outer leads of the preformed package structure from contamination by the underfill process, and assure the preformed package structure to be well mounted and electrically connected to the substrate, such that the electrical connection quality and reliability of the entire semiconductor package would not be affected. Moreover, the fabricated preformed package structure before being mounted on the substrate is subjected to a burn-in test. Specifically, only the preformed package structure that has successfully passed the burn-in test would be mounted on the substrate. As a result, the preformed package structure would not contain a second chip that is defective or unknown with its quality, such that the conventional known good die (KGD) problem can be eliminated, and the reliability and yield of the entire semiconductor package are assured. Additionally, in another preferred embodiment of the present invention, a lead frame of the preformed package structure has a die pad exposed from the first encapsulation body, with a lower surface of the die pad abutting against the gap between the first encapsulation body and the first chip, and prior to fabricating the second encapsulation body, a thermally conductive adhesive is applied in the gap between the first encapsulation body and the first chip, such that heat generated by the second chip mounted on the die pad can be transmitted via the die pad and the thermally conductive adhesive to the first chip and then transmitted via the solder bumps and the substrate to be dissipated out of the semiconductor package. This thus effectively improves the heat dissipating efficiency of the entire semiconductor package. Furthermore, the semiconductor package in the present invention has a multi-chip structure containing at least the first and second chips, thereby providing the entire semiconductor package with enhanced electrical and operational performances.
• The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (18)

1-8. (canceled)

9. A fabrication method of a multi-chip semiconductor package, comprising the steps of:

providing a substrate having an upper surface and a lower surface opposed to the upper surface;

providing at least one first chip having an active surface and a non-active surface, and allowing the active surface of the first chip to be mounted on and electrically connected to the upper surface of the substrate via a plurality of solder bumps;

mounting a preformed package structure on the upper surface of the substrate, the preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, with outer leads of the lead frame being exposed from the first encapsulation body and mounted on the upper surface of the substrate, wherein the first encapsulation body, the exposed outer leads and the substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body; and

forming a second encapsulation body on the upper surface of the substrate to encapsulate the first chip, the solder bumps and the preformed package structure.

10. The fabrication method ofclaim 9, further comprising a step of implanting a plurality of solder balls on the lower surface of the substrate.

11. The fabrication method ofclaim 9, wherein the preformed package structure is mounted on the upper surface of the substrate by surface mount technology.

12. The fabrication method ofclaim 9, wherein the second chip is electrically connected to the lead frame via a plurality of bonding wires.

13. The fabrication method ofclaim 12, wherein the lead frame comprises a die pad and a plurality of leads, each of the leads comprising an inner lead and one of the outer leads, such that the second chip is mounted on an upper surface of the die pad and electrically connected to the inner leads, and the inner leads are encapsulated by the first encapsulation body.

14. The fabrication method ofclaim 13, wherein the die pad is encapsulated by the first encapsulation body.

15. The fabrication method ofclaim 14, wherein the gap between the first chip and the first encapsulation body is filled with the second encapsulation body.

16. The fabrication method ofclaim 13, wherein a lower surface of the die pad is exposed from the first encapsulation body and abuts against the gap between the first chip and the first encapsulation body.

17. The fabrication method ofclaim 16, wherein the gap between the first chip and the first encapsulation body is applied with a thermally conductive adhesive.

18. A fabrication method of multi-chip semiconductor packages, comprising the steps of:

providing a substrate strip, the substrate strip comprising a plurality of substrates and having an upper surface and a lower surface opposed to the upper surface;

mounting at least one first chip on the upper surface of each of the substrates, the first chip having an active surface and a non-active surface; and allowing the active surface of the first chip to be electrically connected to the upper surface of each of the substrates via a plurality of solder bumps;

mounting a preformed package structure on the upper surface of each of the substrates, the preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, with outer leads of the lead frame being exposed from the first encapsulation body and mounted on the upper surface of each of the substrates, wherein the first encapsulation body, the exposed outer leads and the corresponding substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body;

forming a second encapsulation body on the upper surface of the substrate strip to encapsulate all of the first chips, the solder bumps and the preformed package structures;

implanting a plurality of solder balls on the lower surface of the substrate strip; and

performing a singulation process to cut the second encapsulation body and the substrate strip so as to separate apart the plurality of substrates and form a plurality of the individual semiconductor packages.

19. The fabrication method ofclaim 18, wherein the preformed package structure is mounted on each of the substrates by surface mount technology.

20. The fabrication method ofclaim 18, wherein the second chip is electrically connected to the lead frame via a plurality of bonding wires.

21. The fabrication method ofclaim 20, wherein the lead frame comprises a die pad and a plurality of leads, each of the leads comprising an inner lead and one of the outer leads, such that the second chip is mounted on an upper surface of the die pad and electrically connected to the inner leads, and the inner leads are encapsulated by the first encapsulation body.

22. The fabrication method ofclaim 21, wherein the die pad is encapsulated by the first encapsulation body.

23. The fabrication method ofclaim 22, wherein the gap between the first chip and the first encapsulation body is filled with the second encapsulation body.

24. The fabrication method ofclaim 21, wherein a lower surface of the die pad is exposed from the first encapsulation body and abuts against the gap between the first chip and the first encapsulation body.

25. The fabrication method ofclaim 24, wherein the gap between the first chip and the first encapsulation body is applied with a thermally conductive adhesive.

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