US20070222065A1 - Method for precision assembly of integrated circuit chip packages - Google Patents

Abstract

An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Description

• This invention was made with Government support under Contract No.: H98230-04-C-0920, NBCH3039004 awarded by DARPA. The Government has certain rights in this invention.
FIELD OF THE INVENTION
• The present invention relates to the field of integrated circuit packaging; more specifically, it relates to method and apparatus for precision assembly of integrated circuit packages.
BACKGROUND OF THE INVENTION
• Integrated circuit chips are mounted to modules that provide fan out of the interconnections for the next level of assembly. As the size of the interconnections of the integrated circuit chip decrease and the density increases, it becomes more difficult to align the chip pads to the module substrate pads and keep them aligned during the subsequent attachment processes. This problem becomes more difficult when the weight of the integrated circuit chips decrease. Present solutions are costly and time-consuming. Therefore, there is an ongoing need for a method of precision attachment of integrated circuit chips to modules.
SUMMARY OF THE INVENTION
• A first aspect of the present invention is a method of fabricating an electronic device, comprising: placing a placement guide over a top surface of a module substrate, a bottom surface of the placement guide facing a top surface of the module substrate, the placement guide having one or more guide openings, the guide openings extending from a top surface of the placement guide to the bottom surface of the placement guide; aligning the placement guide to at least one integrated circuit chip position of one or more integrated circuit chip positions on the module substrate; fixing the aligned placement guide to the module substrate; placing one or more integrated circuit chips in corresponding guide openings of the one or more guide openings, bottom surfaces of the one or more integrated circuit chips facing the top surface of the module substrate, for each of the placed integrated circuit chips, sidewalls of the corresponding placement guide openings constraining electrically conductive bonding structures on bottom surfaces of the placed one or more integrated circuit chips to self-align to corresponding electrically conductive module substrate contact pads on the top surface of the module substrate at corresponding integrated circuit chip positions of the one or more integrated circuit chip positions; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
• A second aspect of the present invention is an electronic device, comprising a placement guide fixed to a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; and an integrated circuit chip in the guide opening, bonding structures on a bottom surface the integrated circuit chip in direct physical and electrical contact with corresponding module substrate contact pads on the top surface of the module substrate, a width of the guide opening equal to a corresponding width of the integrated circuit chip plus one half or less a first distance between centers of a first pair of adjacent module substrate contact pads of the module substrate contact pads in a widthwise direction and a length of the guide opening equal to a corresponding length of the integrated circuit chip plus one half or less a second distance between centers of a second pair of adjacent module substrate contact pads of the module substrate contact pads in a lengthwise direction.
BRIEF DESCRIPTION OF DRAWINGS
• The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
• FIG. 1A is a top view andFIG. 1B is a cross-section throughline1B-1B ofFIG. 1A illustrating a precision integrated circuit chip placement guide according to embodiments of the present invention;
• FIG. 2A is a top view andFIG. 2B is a cross-section throughline2B-2B ofFIG. 2A illustrating a precision integrated circuit chip module substrate according to embodiments of the present invention;
• FIGS. 3 through 7 are cross-sectional views throughline1B-1B ofFIG. 1A andline2B-2B ofFIG. 2A illustrating fabrication of precision aligned integrated circuit modules according to a first embodiment of the present invention;
• FIGS. 8 through 12 are cross-sectional views throughline1B-1B ofFIG. 1A andline2B-2B ofFIG. 2A illustrating fabrication of precision aligned integrated circuit modules according to a second embodiment of the present invention;
• FIGS. 13 through 17 are cross-sectional views throughline1B-1B ofFIG. 1A andline2B-2B ofFIG. 2A illustrating fabrication of precision aligned integrated circuit modules according to a third embodiment of the present invention;
• FIG. 18 is cross-section of an integrated circuit guide, an integrated circuit chip and an integrated circuit module assembly illustrating the alignment tolerances of the chip to the module substrate according to the embodiments of the present invention;
• FIGS. 19A through 19D are cross-sectional views illustrating details of the edges integrated circuit placement guides and integrated circuit chips according to embodiments of the present invention;
• FIG. 20 is a cross-section of an exemplary integrated circuit chip mounted to an exemplary integrated circuit module according to embodiments of the present invention;
• FIG. 21 is a cross-section of an integrated circuit chip and an integrated circuit module assembly utilizing a handle substrate; and
• FIG. 22 is a flowchart of the methodology of fabricating precision aligned integrated circuit modules according to embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
• FIG. 1A is a top view andFIG. 1B is a cross-section throughline1B-1B ofFIG. 1A illustrating a precision integrated circuit chip placement guide according to embodiments of the present invention. InFIGS. 1A and 1B, aplacement guide100 includes a multiplicity of throughguide openings105 extending from atop surface107 to abottom surface108 of the guide. Top andbottom surfaces107 and108 are parallel to each other. Through holes have a length G1 and a width G2.Placement guide100 has a thickness H1. The values of G1, G2 and H1 are chosen based on the dimensions of the integrated circuit chips that will be placed withinguide openings105 as described infra.Guide openings105 may be formed using a photolithographic process in combination with wet etching or reactive ion etching (RIE). In one example,guide openings105 are formed by a deep RIE process. A deep RIE process is an RIE process designed to etch deep opening (e.g. greater than 10 microns) with substantially straight sidewalls relative to top andbottom surfaces107 and108 ofplacement guide100. Following a process known in the art as the “Bosch Process”, a deep RIE processes alternates, up to several times per minute, in situ, between a first process that etches the substrate and a second process that forms polymer on the sidewalls of the opening being etched. After etching is complete, the polymer may be removed with a plasma ash. Placement guide surfaces may be coated with an oxide or a nitride.
• Placement guide100 may advantageously be fabricated from the same material as the substrate used in the fabrication of the integrated circuit chips that will be placed withinguide openings105. In one example,placement guide100 is fabricated from silicon. In one example,placement guide100 comprises a silicon disk. In one example H1 is between about 25 microns and about 800 microns.
• While a regular pattern of identically sizedopening105 are illustrated inFIG. 1A,different guide openings105 may be of different sizes (length, width or both length and width) to accommodate different size integrated circuit chips.
• Placement guide100 may include alignment aids as is known in the art. InFIGS. 1A and 1B,placement guide100 is illustrated withexemplary alignment holes109 that will mate with alignment pins as described infra. Alignment holes109 are formed at the same time asguide openings105. and are defined on the same photomask. Alternatively, alignment holes109 may be visually aligned to alignment targets as described infra.
• FIG. 2A is a top view andFIG. 2B is a cross-section throughline2B-2B ofFIG. 2A illustrating a precision integrated circuit chip module substrate according to embodiments of the present invention. InFIGS. 2A and 2B, amodule substrate110 includes a multiplicity of integratedcircuit chip positions115 having electrically conductive modulesubstrate contact pads120. Integratedcircuit chip positions115 are positions onmodule substrate110 where integrated circuit chips will be electrically bonded.Module substrate110 includes asubstrate layer125 containing electricallyconductive pins130 and aninterconnect layer135 containingwires140.Wires140 electrically connect modulesubstrate contact pads120 topins130. In one example, modulesubstrate contact pads120 comprise copper, tungsten, tantalum, aluminum or combinations thereof.Interconnect layer135 may contain two or moreinterconnected wiring levels125. Details ofsubstrate layer125 andinterconnect layer135 are described infra in relationship toFIG. 20.Module substrate110 has a thickness H2.
• Module substrate110 may comprise silicon wafers having one or more wiring levels, ceramic substrates having one or more wiring levels or organic substrates (i.e. printed circuit boards, flexible circuit boards, fiberglass circuit boards, plastic boards) having one or more wiring levels.Module substrate110, though illustrated with front to backside connections may have frontside contact pads instead ofpins130. In one example, pins130 may extend past the backside ofmodule substrate110. In one example, pins130 may have copper or solder balls fixed thereto for attachment to module sockets.
• Module substrate110 may advantageously be fabricated from the same material as the substrate used in the fabrication of the integrated circuit chips that will be placed withinguide openings105 of placement guide100 (seeFIGS. 1A and 1B). In one example,module substrate110 is fabricated from silicon. In one example,module substrate110 comprises a silicon disk. In one example H2 is between about 25 microns and about 800 microns.Module substrate110 may advantageously be fabricated using the same processes used to fabricate integrated circuit chips.
• Module substrate110 may include alignment aids as is known in the art. InFIGS. 2A and 2B,module substrate110 is illustrated with exemplary alignment pins142 that will mate with alignment holes109 (seeFIGS. 1A and 1B). Alternatively, instead of alignment pins,module substrate110 may include alignment targets that may be aligned to alignment marks onalignment guide100 or through holes in alignment guide100 (seeFIGS. 1A and 1B) and which may be held in place by clamping or adhesive or alternate method known in the art. InFIG. 2B, integratedcircuit chip positions115 includeplateaus143 separated by recessedregions144 ofinterconnect layer135.
• FIGS. 3 through 7 are cross-sectional views throughline1B-1B ofFIG. 1A andline2B-2B ofFIG. 2A illustrating fabrication of precision aligned integrated circuit modules according to a first embodiment of the present invention. InFIG. 3,placement guide100 is aligned overmodule substrate110 so guideopenings105 are precision aligned over integrated circuit chip positions115. Precision alignment ofplacement guide100 tomodule substrate110 is described infra in reference toFIG. 18. Since there are a variety of alignment methodologies known in the art that may be used, no alignment structures are illustrated inFIG. 3. Alignment schemes that may be used to alignplacement guide100 tomodule substrate110 include, but are not limited to, using alignment targets and marks with visual or infrared optics in combination with precision tooling and/or image recognition software for optimization of X, Y and rotational alignment. After alignment,placement guide100 is permanently or removeably attached (fixed) tomodule substrate110 using any number of schemes known in the art, including, but not limited to, mechanical clamping with and without alignment pins and adhesive attachment with and without alignment pins.
• InFIG. 4, integratedcircuit chips145 having electrical/mechanical bonding structures150 are placed into openings105 (seeFIG. 3). Examples of bonding structures include, but are not limited to, metal pads, copper pads and solder bumps.Bonding structures150 self-align to module substrate contact pads120 (see, for example, FIG.20) because of the precision alignment ofplacement guide100 tomodule substrate110 and the size of guide openings105 (seeFIG. 3). Next, an electromechanical bond between modulesubstrate contact pads120 andbonding structures150 is formed. Anoptional weight152 may be placed over integratedcircuit chips145 to aid in the bonding process. When bonding structures are solder bumps, the assembly may be heated to reflow the solder bumps in a inert or reducing gas such as nitrogen or nitrogen and hydrogen mixture, respectively to minimize solder or pad oxidation. An optional fluxing gas such as formic acid may be added to the inert or reducing gas used during reflow to enhance joining. When the bonding structures and module substrate contact pads include terminal layers of copper, a copper to copper weld may be formed, for example, by heating the assembly to between about 350° C. and about 450° C. under about 100 pounds per square inch of pressure in the presence of an inert gas (i.e. nitrogen, argon or helium) or and inert gas (i.e., nitrogen, argon or helium)/reducing gas (i. e, hydrogen) mixture. When the bonding structures and module substrate contact pads include terminal layers of gold, a gold to gold weld may be formed, for example, by heating the assembly to between about 350° C. and about 450° C. under about 100 pounds per square inch of pressure in the presence of air or an inert gas, or with the aide of an ultrasonic bonding force. The former solder and gold bonding processes are also known in the art as a chip attaching process, simply chip attach, reflow, assembly or ultrasonic bonding.
• InFIG. 5, placement guide100 (seeFIG. 4) is removed and inFIG. 6, module substrate110 (seeFIG. 5) is singulated (i.e. by mechanical dicing, laser dicing, wet etching, RIE, or mechanical fracturing) intoindividual modules155 each including a singleintegrated circuit chip145.
• Alternatively, placement guide100 (seeFIG. 4) is not removed and inFIG. 7, module substrate110 (seeFIG. 5) is singulated (i.e. by mechanical dicing, laser dicing, wet etching, RIE, or mechanical fracturing) intoindividual modules155 each including a singleintegrated circuit chip145 surrounded by a portion of placement guide10A. In the case placement guide100 (seeFIG. 3) is not removed, all exposed surfaces of the placement guide and exposed interconnections may be coated with a dielectric film, covered by a dielectric layer or all exposed interconnections encapsulated with an adhesive/sealant such as is known in the art as “chip underfill” or “wafer to wafer bonding adhesive”. The encapsulation may enhance module substrate mechanical properties and minimize interconnection corrosion or degradation. Thus, direct physical contact betweenintegrated circuit chip145 and portion ofplacement guide100A will not result in electrical shorting of the integrated circuit chip to the placement guide or of the placement guide to the module substrate and the assembly can achieve improved manufacturability/handling and product or application reliability.
• FIGS. 8 through 12 are cross-sectional views throughline1B-1B ofFIG. 1A andline2B-2B ofFIG. 2A illustrating fabrication of precision aligned integrated circuit modules according to a second embodiment of the present invention.FIGS. 8, 9 and10 are similar to respectiveFIGS. 3, 4 and5 except inFIGS. 8, 9 and10, integratedcircuit chip positions115 are designed to interconnect to more than oneintegrated circuit chip145. However, eachintegrated circuit chip145 is still within aguide opening105.
• InFIG. 1, module substrate110 (seeFIG. 10) is singulated (i.e. by mechanical dicing, laser dicing, wet etching, RIE, or mechanical fracturing) intoindividual modules155 each including a two or more integrated circuit chips145.
• Alternatively, placement guide100 (seeFIG. 9) is not removed and inFIG. 12, module substrate110 (seeFIG. 10) is singulated (i.e. by mechanical dicing, laser dicing, wet etching, RIE, or mechanical fracturing) intoindividual modules155 each including two or moreintegrated circuit chips145, each chip surrounded by and separated from each other by a portion of placement guide10A.
• FIGS. 13 through 17 are cross-sectional views throughline1B-1B ofFIG. 1A andline2B-2B ofFIG. 2A illustrating fabrication of precision aligned integrated circuit modules according to a third embodiment of the present invention.FIG. 13 is the same asFIG. 3 andFIGS. 14 and 15 are similar to respectiveFIGS. 4 and 5 except inFIGS. 14 and 15, integratedcircuit chips145A are thinner thanintegrated circuit chips145 ofFIG. 5 and thus do not extend abovetop surface107 of placement guide100 (seeFIG. 14). Therefore,optional weight152 includes protrudingregions162 extending into guide opening105 (seeFIG. 13) and contacting integrated circuit chips145.
• InFIG. 16, module substrate110 (seeFIG. 15) is singulated (i.e. by mechanical dicing, laser dicing, wet etching, RIE, or mechanical fracturing) intoindividual modules155 each including a two or more integrated circuit chips145.
• Alternatively, placement guide100 (seeFIG. 14) is not removed and inFIG. 17, module substrate110 (seeFIG. 15) is singulated (i.e. by mechanical dicing, laser dicing, wet etching, RIE, or mechanical fracturing) intoindividual modules155 each including one integratedcircuit chip145 surrounded by and separated from each other by a portion of placement guide10A.
• Other embodiments of the present invention include, mounting two or more thin chips on the same module substrate, mounting a combination of thick and thin chips on the same module substrate, mounting different (width, length or both width and length) sized chips on the same module substrate, and mounting one or more stacked chips on the same module substrate and combinations thereof.
• FIG. 18 is cross-section of an integrated circuit guide, an integrated circuit chip and an integrated circuit module assembly illustrating the alignment tolerances of the chip to the module according to the embodiments of the present invention. InFIG. 18,bonding structures150 and modulesubstrate contact pads120 have apitch P. Sidewalls163 ofintegrated circuit chip145 are separated from opposingsidewalls164 ofplacement guide100 by a distance T. In one example, T is equal or less than 0.5*P. If the opposing sidewalls are not parallel to each other, then T is the value of the smallest distance between the opposing sidewalls (see for example,FIG. 19B). Note, the pitch P for different integrated circuit chip positions115 (seeFIG. 2A) can be different. If an integrated circuit chip has a length C1 and a width C2, then (referring toFIG. 1A), G1 is less than or equal to C1+0.5*P and G2 is less than or equal to C2+0.5*P. It should be understood that there are two pitches in a rectangular integrated circuit, a pitch in the widthwise direction and a pitch in the lengthwise direction. These pitches may or may not be the same. Thus, the distance T in the widthwise (Tw) direction may be different from the distance T in the lengthwise direction (TL). Alternatively, the smaller value of T_Wand T_Lmay be used in both the lengthwise and widthwise directions.
• FIGS. 19A through 19D are cross-sectional views illustrating details of the edges integrated circuit placement guides and integrated circuit chips according to embodiments of the present invention. InFIG. 19A, the corner formed bytop surface107 and top edge ofsidewall164 ofplacement guide100 has been chamfered. InFIG. 19B, theentire sidewall164 fromtop surface107 tobottom surface108 ofplacement guide100 is tapered at an angle α. A first distance (T) from the edge formed bysidewall164 andbottom surface108 to sidewall163 being smaller than a second distance from the edge formed bysidewall164 andtop surface107 tosidewall163. In one example a is between about 1° and about 9°. In another example a is between about 1° and about 45°.
• InFIG. 19C, theentire sidewall164 fromtop surface107 tobottom surface108 ofplacement guide100 is tapered at an angle β measured betweensidewall164 andbottom surface108. Theentire sidewall163 ofintegrated circuit chip145 is likewise tapered at the angle β, however, sidewalls163 and164 are parallel and spaced distance T apart. In one example β between about 1° and about 45°. Because integratedcircuit chip145overlays placement guide100 the placement guide cannot be removed frommodule substrate110.
• InFIG. 19D, theentire sidewall164 fromtop surface107 tobottom surface108 ofplacement guide100 is tapered at an angle β measured betweensidewall164 andtop surface107. Theentire sidewall163 ofintegrated circuit chip145 is likewise tapered at the angle β, however, sidewalls163 and164 are parallel and spaced distance T apart. Becauseplacement guide100 overlays integratedcircuit chip145 the integrated circuit chip must be placed onmodule substrate110 before the placement guide is placed on the module substrate.
• While only one edge ofplacement guide100 and one edge ofintegrated circuit chip145 have been illustrated inFIGS. 19A, 19B,19C and19D, it should be recognized that all edges of the placement guide and all edges of the integrated circuits may be the same as the single edges illustrated inFIGS. 19A, 19B,19C and19D.
• FIG. 20 is a cross-section of an exemplary integrated circuit chip mounted to an exemplary integrated circuit module according to embodiments of the present invention. InFIG. 20,interconnect layer135 ofmodule substrate110 includes first, second and thirddielectric layers165A,165B and165C containing respective damascene wires andvias170A,170B and170C.Wires170A,170B and170C electrically connect modulesubstrate contact pads120 to electricallyconductive pins130 insubstrate layer125.Pins130 are isolated from each other and fromsubstrate layer125 bydielectric layers180 and185. InFIG. 20,bonding structures150 includechip contact pads172 on which solder bumps173 (or solder balls) have been formed. In one example solder bumps comprise a mixture of lead and tin.Chip contact pads120 may comprise layers of chrome, gold, nickel, copper, tungsten, tantalum, titanium, and aluminum. A common name for these layers is ball-limiting metallurgy (BLM). This structure produces a solder connection, also know as a controlled-chip-collapse-connection (C4). Alternatively,bonding structures150 may consist only ofchip contact pads172, both the chip contact pads and modulesubstrate contact pads120 having at least outer layers of copper. This structure produces a copper-to-copper bond. Alternatively,bonding structures150 may consist only ofchip contact pads172, both the chip contact pads and modulesubstrate contact pads120 having at least outer layers of gold where the structure produces a gold-to-gold bond.
• FIG. 21 is a cross-section of an integrated circuit chip and an integrated circuit module assembly utilizing ahandle substrate190. In cases wheremodule substrate110 is thin and fragile,handle substrate190 is temporarily attached tosubstrate layer125 by an adhesive195 in order to prevent breakage of the module substrate during aligning, clamping, singulation and bonding processes.
• FIG. 22 is a flowchart of the methodology of fabricating precision aligned integrated circuit modules according to embodiments of the present invention. Instep200, a handle substrate is optionally attached to a module substrate. Afterstep200 the method can proceed through eithersteps205,210 and215 or throughsteps220,225 and230.
• Instep205, a placement guide is aligned to a module substrate and instep210 the module substrate and placement guide are temporarily (clamped/glued) or permanently (glued or bonded) attached so as not to be able to move during the integrated circuit chip to module substrate bonding operation ofstep235. Instep215, the integrated circuit chips are placed the guide openings of the placement guide. The method then continues withstep235.
• Instep220, the integrated circuit chips are placed on a module substrate and in step225 a placement guide is placed on the module substrate, the guide openings are rough-aligned to the integrated circuit chips and fine aligned to the module substrate. Instep230, the module substrate and placement guide are temporarily (clamped/glued) or permanently (glued or bonded) attached so as not to be able to move during the integrated circuit chip to module substrate bonding operation ofstep235. The method then continues withstep235.
• Instep235, the integrated circuits are bonded to the module substrate. For copper-to-copper bonding, heat and pressure are applied under an inert or inert/reducing atmosphere. For solder bump connections, heat is applied to reflow the solder bumps (optionally under an inert or inert/reducing atmosphere). For solder bump attachment, flux may or may not be applied prior to or after placing the integrated circuit chip on the module substrate or during joining. Depending on flux, the assembly may require post assembly cleaning. No clean fluxes may be deployed or controlled ambient gas during joining to enhance joining without post-assembly cleaning.
• Instep240, the placement guide is optionally removed and instep245 the module substrate is singulated into single-chip, multi-chip or both single and multi-chip module substrates. Instep250, the handle substrate may optionally be removed. Optional testing may be performed immediately aftersteps235,245 and250.
• Thus, the embodiments of the present invention provide methods of precision attachment of integrated circuit chips to module substrates.
• The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims (23)

1. (canceled)

2. A method of fabricating an electronic device, comprising:

placing a placement guide over a top surface of a module substrate, a bottom surface of said placement guide facing a top surface of said module substrate, said placement guide having one or more guide openings, said guide openings extending from a top surface of said placement guide to said bottom surface of said placement guide;

aligning said placement guide to at least one integrated circuit chip position of one or more integrated circuit chip positions on said module substrate;

fixing said aligned placement guide to said module substrate;

placing one or more integrated circuit chips in corresponding guide openings of said one or more guide openings, bottom surfaces of said one or more integrated circuit chips facing said top surface of said module substrate, for each of said placed integrated circuit chips, sidewalls of said corresponding placement guide openings constraining electrically conductive bonding structures on bottom surfaces of said placed one or more integrated circuit chips to self-align to corresponding electrically conductive module substrate contact pads on said top surface of said module substrate at corresponding integrated circuit chip positions of said one or more integrated circuit chip positions;

bonding said bonding structures to said module substrate contact pads, said bonding structures and said module substrate contact pads in direct physical and electrical contact after said bonding; and

after said bonding, removing said placement guide from said module substrate.

3. The method ofclaim 2, wherein said bonding structures are solder bumps on chip contact pads and said bonding creates a soldered connection between said chip contact pads and said module substrate contact pads.

4. The method ofclaim 2, wherein said bonding structures comprise copper chip contact pads, said module substrate contact pads comprise copper and said bonding creates a copper to copper weld between said chip contact pads and said module substrate contact pads.

5. The method ofclaim 2, wherein said placement guide comprises silicon, said integrated circuit chip comprises silicon, and said module substrate comprises silicon.

6. The method ofclaim 2, further including:

attaching a handle substrate to a bottom surface of said module substrate.

7. A method of fabricating an electronic device, comprising:

placing a placement guide over a top surface of a module substrate, a bottom surface of said placement guide facing a top surface of said module substrate, said placement guide having one or more guide openings, said guide openings extending from a top surface of said placement guide to said bottom surface of said placement guide;

aligning said placement guide to at least one integrated circuit chip position of one or more integrated circuit chip positions on said module substrate;

fixing said aligned placement guide to said module substrate;

placing one or more integrated circuit chips in corresponding guide openings of said one or more guide openings, bottom surfaces of said one or more integrated circuit chips facing said top surface of said module substrate, for each of said placed integrated circuit chips, sidewalls of said corresponding placement guide openings constraining electrically conductive bonding structures on bottom surfaces of said placed one or more integrated circuit chips to self-align to corresponding electrically conductive module substrate contact pads on said top surface of said module substrate at corresponding integrated circuit chip positions of said one or more integrated circuit chip positions;

bonding said bonding structures to said module substrate contact pads, said bonding structures and said module substrate contact pads in direct physical and electrical contact after said bonding; and

wherein a distance between at least one sidewall of each of said one or more placement guide openings and at least one opposing sidewall of corresponding placed integrated circuit chips is equal to less than one half a distance between centers of a pair of adjacent module substrate contact pads of said module substrate contact pads at each of said corresponding integrated circuit chip positions.

8. The method ofclaim 2, wherein corresponding center to center spacing of adjacent module substrate contact pads of at least two of said one or more integrated circuit chip positions is different.

9. The method ofclaim 2, wherein said integrated circuit chip is placed on said module substrate after said aligning and fixing said placement guide to said module substrate.

10. A method of fabricating an electronic device, comprsing:

placing a placement guide over a top surface of a module substrate, a bottom surface of said placement guide facing a top surface of said module substrate, said placement guide having one or more guide openings, said guide openings extending from a top surface of said placement guide to said bottom surface of said placement guide;

aligning said placement guide to at least one integrated circuit chip position of one or more integrated circuit chip positions on said module substrate;

fixing said aligned placement guide to said module substrate;

placing one or more integrated circuit chips in corresponding guide openings of said one or more guide openings, bottom surfaces of said one or more integrated circuit chips facing said top surface of said module substrate, for each of said placed integrated circuit chips, sidewalls of said corresponding placement guide openings constraining electrically conductive bonding structures on bottom surfaces of said placed one or more integrated circuit chips to self-align to corresponding electrically conductive module substrate contact pads on said top surface of said module substrate at corresponding integrated circuit chip positions of said one or more integrated circuit chip positions;

bonding said bonding structures to said module substrate contact pads, said bonding structures and said module substrate contact pads in direct physical and electrical contact after said bonding; and

wherein said placing said integrated circuit chip on said module substrate is performed before said aligning and fixing said placement guide to said module substrate.

11. A method of fabricating an electronic device comprising:

placing a placement guide over a top surface of a module substrate, a bottom surface of said placement guide facing a top surface of said module substrate, said placement guide having one or more guide openings said guide openings extending from a top surface of said placement guide to said bottom surface of said placement guide,

aligning said placement guide to at least one integrated circuit chip position of one or more integrated circuit chip positions on said module substrate;

fixing said aligned placement guide to said module substrate;

placing one or more integrated circuit chips in corresponding guide openings of said one or more guide openings, bottom surfaces of said one or more integrated circuit chips facing said top surface of said module substrate, for each of said placed integrated circuit chips, sidewalls of said corresponding placement guide openings constraining electrically conductive bonding structures on bottom surfaces of said placed one or more integrated circuit chips to self-align to corresponding electrically conductive module substrate contact pads on said top surface of said module substrate at corresponding integrated circuit chip positions of said one or more integrated circuit chip positions;

bonding said bonding structures to said module substrate contact pads, said bonding structures and said module substrate contact pads in direct physical and electrical contact after said bonding

after said bonding, removing said placement guide from said module substrate; and

after said removing said placement guide, singulating said module substrate into individual modules, each module containing one or more integrated circuit chips.

12. The method ofclaim 2, further including:

singulating said module substrate into individual modules, each module substrate containing one or more integrated circuit chips.

13. The method ofclaim 2, wherein at least one of said one or more integrated circuit chips includes an additional integrated circuit chip stacked on top of and electrically connected to said at least one of said one or more integrated circuit chips.

14. An electronic device, comprising:

a placement guide fixed to a top surface of a module substrate, said placement guide having a guide opening, said guide opening extending from a top surface of said placement guide to a bottom surface of said placement guide; and

an integrated circuit chip in said guide opening, bonding structures on a bottom surface said integrated circuit chip in direct physical and electrical contact with corresponding module substrate contact pads on said top surface of said module substrate, a width of said guide opening equal to a corresponding width of said integrated circuit chip plus one half or less a first distance between centers of a first pair of adjacent module substrate contact pads of said module substrate contact pads in a widthwise direction and a length of said guide opening equal to a corresponding length of said integrated circuit chip plus one half or less a second distance between centers of a second pair of adjacent module substrate contact pads of said module substrate contact pads in a lengthwise direction.

15. The device ofclaim 14, wherein said bonding structures are solder bumps on chip contact pads and said chip pads are soldered to said module substrate contact pads.

16. The device ofclaim 14, wherein said bonding structures comprise copper or gold chip contact pads, said module substrate contact pads comprise copper or gold and said chip contact pads and said module substrate contact pads are bonded to each other by a copper to copper weld or form gold to gold bonds.

17. The device ofclaim 14, wherein said placement guide comprises silicon, said integrated circuit chip comprises silicon, and said module substrate comprises silicon.

18. The device ofclaim 14, further including:

an additional integrated circuit chip stacked on top of and electrically connected to said integrated circuit chip.

19. The device ofclaim 14, further including:

an additional guide opening in said placement guide; and

an additional integrated circuit chip in said additional guide opening, bonding structures on a bottom surface of said additional integrated circuit chip in direct physical and electrical contact with corresponding additional module substrate contact pads on said top surface of said module substrate.

20. The device ofclaim 14, wherein sidewalls of said integrated circuit chip and sidewalls said one or more additional integrated circuit chips are separated from each other by an unbroken region of said placement guide.

21. The method ofclaim 2, wherein a distance between at least one sidewall of each of said one or more placement guide openings and at least one opposing sidewall of corresponding placed integrated circuit chips is equal to less than one half a distance between centers of a pair of adjacent module substrate contact pads of said module substrate contact pads at each of said corresponding integrated circuit chip positions.

22. The method ofclaim 2, wherein said placing said integrated circuit chip on said module substrate is performed before said aligning and fixing said placement guide to said module substrate.

23. The method ofclaim 2, further including:

after said removing said placement guide, singulating said module substrate into individual modules, each module containing one or more integrated circuit chips.

Images