US20070187838A1 - Pad structure for bonding pad and probe pad and manufacturing method thereof - Google Patents
Pad structure for bonding pad and probe pad and manufacturing method thereofDownload PDFInfo
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- US20070187838A1 US20070187838A1US11/691,606US69160607AUS2007187838A1US 20070187838 A1US20070187838 A1US 20070187838A1US 69160607 AUS69160607 AUS 69160607AUS 2007187838 A1US2007187838 A1US 2007187838A1
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- 239000000523sampleSubstances0.000titledescription32
- 238000004519manufacturing processMethods0.000titledescription3
- 229910052751metalInorganic materials0.000claimsabstractdescription52
- 239000002184metalSubstances0.000claimsabstractdescription52
- 239000004065semiconductorSubstances0.000claimsabstractdescription31
- 239000000758substrateSubstances0.000claimsabstractdescription25
- 238000002161passivationMethods0.000claimsabstractdescription7
- 238000000034methodMethods0.000claims5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-NSilicium dioxideChemical compoundO=[Si]=OVYPSYNLAJGMNEJ-UHFFFAOYSA-N0.000description14
- RYGMFSIKBFXOCR-UHFFFAOYSA-NCopperChemical compound[Cu]RYGMFSIKBFXOCR-UHFFFAOYSA-N0.000description10
- 239000000956alloySubstances0.000description10
- 229910045601alloyInorganic materials0.000description10
- 229910052782aluminiumInorganic materials0.000description10
- XAGFODPZIPBFFR-UHFFFAOYSA-NaluminiumChemical compound[Al]XAGFODPZIPBFFR-UHFFFAOYSA-N0.000description10
- 229910052802copperInorganic materials0.000description10
- 239000010949copperSubstances0.000description10
- 238000013461designMethods0.000description7
- 239000000377silicon dioxideSubstances0.000description5
- 229910052814silicon oxideInorganic materials0.000description4
- 239000005380borophosphosilicate glassSubstances0.000description3
- 239000003550markerSubstances0.000description3
- 238000012986modificationMethods0.000description3
- 230000004048modificationEffects0.000description3
- 229910052581Si3N4Inorganic materials0.000description2
- 238000004100electronic packagingMethods0.000description2
- 238000012544monitoring processMethods0.000description2
- HQVNEWCFYHHQES-UHFFFAOYSA-Nsilicon nitrideChemical compoundN12[Si]34N5[Si]62N3[Si]51N64HQVNEWCFYHHQES-UHFFFAOYSA-N0.000description2
- 238000005259measurementMethods0.000description1
- 238000004806packaging method and processMethods0.000description1
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Definitions
- the present inventionrelates to an integrated circuit device structure, and more particularly to a mark-shaped pad structure for a bonding pad and a probe pad.
- the top metal layeris defined as a plurality of bonding pads to form a multi-layered wiring with the metal lines below.
- the waferis then cut into dies for further IC chip electronic packaging.
- the dies cut from the waferare bonded to a lead frame with a bonder, and the bonding pads on the IC chip are electrically connected with corresponding electrical leads on the lead frame by wire bonding.
- the bonding pads on IC chipsare the interface between the integrated circuits on the semiconductor substrate and the packaging leads on the lead frame to connect electrical signals.
- the electrical signalscan be power signals, ground signals, and/or input/output signals.
- the active devicese.g., MOS transistors or resistances
- the active devicesare laid on the central area (active area) of an IC chip and bonding pads are disposed around the active area to protect the active devices on the active area from damage during wire bonding.
- bonding padsare laid on the central area of IC chip and active devices are disposed around the bonding pads for the same reason.
- FIG. 1shows a conventional die array on a wafer.
- scribe lines 16on a wafer 10 to define several die areas, e.g. 12 A and 12 B, and the wafer 10 is cut into dies along the scribe lines 16 .
- alignment markerse.g. 14 A- 14 C
- the dicing machinecuts the die area 12 A from the wafer 10 by aligning with the markers 14 A and 14 B which are disposed along the diagonal line of area 12 A.
- the fragmental die area 12 Bthere is no corresponding diagonal markers on scribe lines for alignment, and therefore, there is difficulty cutting die area 12 B.
- FIGS. 2A and 2Bshow a conventional design of bonding pads.
- the rectangular bonding pads 22 A with equal sizeare disposed along the two longer sides of the rectangular chip 20 A which is cut from a wafer.
- Another bonding pad designis shown in FIG. 2B .
- the rectangular bonding pads 22 B with equal sizeare disposed on the central area of the rectangular chip 20 B which is also cut from a wafer.
- the electrical layout in the chip 20 A or 20 Bis predetermined and the bonding pads 22 A or 22 D on the IC chip 20 A or 20 B respectively are wire bonded with corresponding electrical leads on a lead frame according to the interior layout.
- it is hard to identify the bonding orientation of a chip and the leads on a lead framebecause the IC chips 20 A and 20 B are rectangular and the bonding pads 22 A and 22 B are disposed on the IC chips 20 A and 20 B symmetrically.
- FIG. 3shows the conventional design for probe pads.
- the inspectormeasures the probe pads 36 on the circuit 34 by using a micro-probe under a microscope to obtain the electrical data.
- One object of the present inventionis to provide a bonding structure which is used as an orientation marker for wire bonding and a manufacturing method thereof.
- Another object of the present inventionis to provide a bonding pad structure which can be an alignment marker for wafer dicing.
- Still another object of the present inventionis to provide a mark-shaped pad structure for probe pads as position markers to identify the orientation of the checking circuits.
- the present inventionprovides a bonding pad structure disposed on the surface of a semiconductor substrate with a circuit therein and a manufacturing method thereof.
- the structurecomprises a bottom metal layer disposed over the surface of the semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, a plurality of metal plugs formed therein to connect with the bottom metal layer below, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with a plurality of openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped to indicate the orientation of the bonding pads on the semiconductor substrate.
- the shape of the mark-shaped bonding pad on the above bonding pad structurecan be, for example, a shape, a shape, a cross shape or a shape.
- the top metal and the bottom metal layers on the bonding pad structurecan be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica.
- the inter-metal dielectric layercan be silicon oxide and the passivation layer can be silicon oxide or borophosphosilicate glass and silicon nitride.
- the mark-shaped bonding pads on a wafercan be used as alignment markers for wafer dicing.
- the dicing machinecan cut dies from a wafer by aligning with the mark-shaped bonding pads on the wafer surface. When the dies are cut from the wafer for further wire bonding, the orientation of circuits in the dies can be easily identified according to the mark-shaped bonding pads on the die surface.
- a probe pad with a mark-shapeis further provided according to the present invention.
- the probe padis disposed on a semiconductor circuit for electric characteristic measurement which has a mark-shape to indicate the relative location of the probe pad on the semiconductor circuit.
- the shape of the mark-shaped probe pad on the semiconductor circuitcan be, for example, a shape, a shape, a cross shape or a shape.
- the probe padcan be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica.
- An inspectorcan easily identify the orientation of the target circuit under a microscopic with the mark-shaped probe pads according to the present invention.
- FIG. 1schematically shows a conventional die array on a wafer
- FIGS. 2A and 2Bschematically show the conventional design of bonding pads (a plan view);
- FIG. 3schematically shows the conventional design for probe pads (a plan view);
- FIG. 4schematically shows a bonding pad structure according to one embodiment of the present invention
- FIGS. 5A-5Dschematically show the shapes of bonding pads (a plan view) according to one preferred embodiment of the present invention.
- FIG. 6schematically shows a probe pad (a plan view) according to one embodiment of the present invention.
- FIG. 4is a cross-sectional view showing a bonding pad structure according to one embodiment of the present invention.
- a bonding pad structureis formed on the surface of a semiconductor substrate 40 with a circuit (not shown) therein.
- a bottom metal layer 42is disposed over the surface of the semiconductor substrate 40 and connected with the circuit electrically on the semiconductor substrate 40 .
- the preferred bottom metal layer 42is an alloy of aluminum and copper or an alloy of aluminum, copper and silica.
- An inter-metal dielectric layer 44is then disposed over the bottom metal layer 42 .
- a plurality of metal plugs 46is then formed in the inter-metal dielectric layer 44 to connect with the bottom metal layer 42 in below.
- the inter-metal dielectric layer 44can be, but is not limited to, silicon oxide.
- a top metal layer 48is disposed over the inter-metal dielectric layer 44 and connected electrically with the metal plugs 46 in the inter-metal dielectric layer 44 .
- a preferred top metalis an alloy of aluminum and copper or an alloy of aluminum, copper and silica.
- a passivation layer 49is disposed over the top metal layer 48 .
- a plurality of openingsis defined thereon to expose the top metal portions below (e.g. 40 ⁇ 40 ⁇ m per opening) as bonding pads 50 for wire bonding.
- the passivation layer 49can be a silicon oxide layer or a layer of borophosphosilicate glass (BPSG) and silicon nitride.
- At least one opening 50is defined as a certain shape to form a mark-shaped bonding pad on the semiconductor substrate 40 . For example, in having at least one mark-shaped bonding pad on the semiconductor substrate 40 , it can be used to indicate the orientation of the circuit in the semiconductor substrate 40 .
- the preferred shapes of the mark-shaped bonding pads formed on the semiconductor substrate 40are shown in FIGS. 5A to 5 D (plan views).
- the mark-shaped bonding pad on a rectangular semiconductor substrate 40can be a shape 50 A as FIG. 5A shows, a shape 50 B as FIG. 5B shows, a cross shape 50 C as FIG. 5C shows or a shape as FIG. 50D shows.
- the mark-shaped bonding pads 50 A to 50 Dthere are two advantages of the mark-shaped bonding pads 50 A to 50 D that have special shapes other than conventional rectangular bonding pads on the semiconductor substrate 40 .
- One advantagesis the mark-shaped bonding pads 50 A to 50 D can be used as alignment markers for wafer dicing.
- a dicing machinecan cut dies from a wafer by aligning the mark-shaped bonding pads on the wafer surface, especially when cutting the fragmental portions of a wafer.
- mark-shaped bonding pads in the present inventionis that it is easy to identify the orientation of the rectangular semiconductor substrate 40 with the mark-shaped bonding pads 50 A to 50 D. As shown in FIGS. 5A-5D , there are bonding pads lined up in a row on the surface of the rectangular semiconductor substrate 40 . There is difficulty identifying the orientation of the rectangular semiconductor substrate 40 only with the rectangular bonding pads 51 . However, it is easy to identify the orientation of the rectangular semiconductor substrate 40 according to the invention by defining a least one bonding pad as a mark-shaped bonding pad, e.g. bonding pads 50 A- 50 D.
- the relative position between the mark-shaped bonding pads 50 A- 50 D and the other normal rectangular bonding padsdenotes the orientation of circuits in the semiconductor substrate 40 .
- the orientation of the circuitscan still be identified according to the mark-shaped bonding pads on the surface, which makes wire bonding easier to connect the interior circuit by bonding the bonding pads with corresponding leads on a lead frame.
- FIG. 6shows a schematic plan view of a probe pad design according to one embodiment of the invention.
- a mark-shaped bonding pad 50disposed on the surface of a rectangular semiconductor chip 40 to indicate the substrate 40 's orientation and there is a checking area 62 on the semiconductor chip 40 .
- a plurality of mark-shaped probe padsis disposed on certain circuits inside the checking area 62 , e.g. a shape probe pad 60 A or a shape probe pad 60 B.
- the preferred probe padscan be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica.
- the electric performance of certain circuits on the checking area 62is obtained by removing the surface of the area 62 and then measuring the interior probe pads with a micro-probe under a microscope. Since the microscope magnifies the scale of the checking area 62 , an inspector can clearly identify the orientation of the checking area 62 according to the mark-shaped probe pads 60 A or 60 B on the checking circuits. According to the present invention, it is easier to identify the circuit orientation with the mark-shaped probe pads than the conventional rectangular probe pads on the checking circuits, and therefore, the in-line monitoring or electrical checking of the circuits are more efficient.
- the mark-shaped pads according to the present inventioncan be applied on a bonding pad structure on the surface of a semiconductor chip or a probe pad on a circuit.
- a bonding pad structure with at least one mark-shaped padcan be used as an alignment marker of wafer dicing and/or an indicator of chip orientation in wire bonding.
- Mark-shaped probe pads on circuits of a checking areacan be used as indicators showing the relative positions with each other.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
- The present invention relates to an integrated circuit device structure, and more particularly to a mark-shaped pad structure for a bonding pad and a probe pad.
- After integrated circuits are formed on a semiconductor wafer, the top metal layer is defined as a plurality of bonding pads to form a multi-layered wiring with the metal lines below. The wafer is then cut into dies for further IC chip electronic packaging.
- In the electronic packaging of an IC chip, the dies cut from the wafer are bonded to a lead frame with a bonder, and the bonding pads on the IC chip are electrically connected with corresponding electrical leads on the lead frame by wire bonding. In other words, the bonding pads on IC chips are the interface between the integrated circuits on the semiconductor substrate and the packaging leads on the lead frame to connect electrical signals. The electrical signals can be power signals, ground signals, and/or input/output signals.
- Conventionally, the active devices, e.g., MOS transistors or resistances, are laid on the central area (active area) of an IC chip and bonding pads are disposed around the active area to protect the active devices on the active area from damage during wire bonding. In some cases, bonding pads are laid on the central area of IC chip and active devices are disposed around the bonding pads for the same reason.
- The conventional shape of a bonding pad is a square or a rectangle.
FIG. 1 shows a conventional die array on a wafer. There arescribe lines 16 on awafer 10 to define several die areas, e.g.12A and12B, and thewafer 10 is cut into dies along thescribe lines 16. There are alignment markers (e.g.14A-14C) disposed at corners of the dieareas scribe lines 16 for cutting alignment. For theintact die area 12A, the dicing machine cuts thedie area 12A from thewafer 10 by aligning with themarkers area 12A. However, for thefragmental die area 12B, there is no corresponding diagonal markers on scribe lines for alignment, and therefore, there is difficulty cutting diearea 12B. FIGS. 2A and 2B show a conventional design of bonding pads. InFIG. 2A , therectangular bonding pads 22A with equal size are disposed along the two longer sides of therectangular chip 20A which is cut from a wafer. Another bonding pad design is shown inFIG. 2B . Therectangular bonding pads 22B with equal size are disposed on the central area of therectangular chip 20B which is also cut from a wafer. The electrical layout in thechip bonding pads 22A or22D on theIC chip IC chips bonding pads IC chips - The same orientation problem occurs on probe pads. The probe pads are disposed in certain positions on a circuit for in-line monitoring or checking the electrical performance of the circuit design.
FIG. 3 shows the conventional design for probe pads. There are severaltiny probe pads 36 disposed in acertain circuit 34 onIC chip 30. The inspector measures theprobe pads 36 on thecircuit 34 by using a micro-probe under a microscope to obtain the electrical data. - Since the square-shaped probe pads on the circuit are very tiny (e.g., 5×5 μm), it is hard and time consuming for an inspector to identify the layout orientation between the
probe pads 36 on thecircuit 34 under a microscope. - One object of the present invention is to provide a bonding structure which is used as an orientation marker for wire bonding and a manufacturing method thereof.
- Another object of the present invention is to provide a bonding pad structure which can be an alignment marker for wafer dicing.
- Still another object of the present invention is to provide a mark-shaped pad structure for probe pads as position markers to identify the orientation of the checking circuits.
- To achieve the above-mentioned object, the present invention provides a bonding pad structure disposed on the surface of a semiconductor substrate with a circuit therein and a manufacturing method thereof. The structure comprises a bottom metal layer disposed over the surface of the semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, a plurality of metal plugs formed therein to connect with the bottom metal layer below, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with a plurality of openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped to indicate the orientation of the bonding pads on the semiconductor substrate.
- According to the present invention, the shape of the mark-shaped bonding pad on the above bonding pad structure can be, for example, ashape, a
shape, a cross shape
or a
shape.
- According to the present invention, the top metal and the bottom metal layers on the bonding pad structure can be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica. The inter-metal dielectric layer can be silicon oxide and the passivation layer can be silicon oxide or borophosphosilicate glass and silicon nitride.
- The mark-shaped bonding pads on a wafer can be used as alignment markers for wafer dicing. The dicing machine can cut dies from a wafer by aligning with the mark-shaped bonding pads on the wafer surface. When the dies are cut from the wafer for further wire bonding, the orientation of circuits in the dies can be easily identified according to the mark-shaped bonding pads on the die surface.
- A probe pad with a mark-shape is further provided according to the present invention. The probe pad is disposed on a semiconductor circuit for electric characteristic measurement which has a mark-shape to indicate the relative location of the probe pad on the semiconductor circuit.
- According to the present invention, the shape of the mark-shaped probe pad on the semiconductor circuit can be, for example, ashape, ashape, a cross shapeor ashape. The probe pad can be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica.
- An inspector can easily identify the orientation of the target circuit under a microscopic with the mark-shaped probe pads according to the present invention.
- The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention. In the drawings,
FIG. 1 schematically shows a conventional die array on a wafer;FIGS. 2A and 2B schematically show the conventional design of bonding pads (a plan view);FIG. 3 schematically shows the conventional design for probe pads (a plan view);FIG. 4 schematically shows a bonding pad structure according to one embodiment of the present invention;FIGS. 5A-5D schematically show the shapes of bonding pads (a plan view) according to one preferred embodiment of the present invention; andFIG. 6 schematically shows a probe pad (a plan view) according to one embodiment of the present invention.- This invention will be described in further detail by way of example with reference to the accompanying drawings.
FIG. 4 is a cross-sectional view showing a bonding pad structure according to one embodiment of the present invention. A bonding pad structure is formed on the surface of asemiconductor substrate 40 with a circuit (not shown) therein. Abottom metal layer 42 is disposed over the surface of thesemiconductor substrate 40 and connected with the circuit electrically on thesemiconductor substrate 40. The preferredbottom metal layer 42 is an alloy of aluminum and copper or an alloy of aluminum, copper and silica. An inter-metaldielectric layer 44 is then disposed over thebottom metal layer 42. A plurality of metal plugs46 is then formed in the inter-metaldielectric layer 44 to connect with thebottom metal layer 42 in below. The inter-metaldielectric layer 44 can be, but is not limited to, silicon oxide.- A
top metal layer 48 is disposed over the inter-metaldielectric layer 44 and connected electrically with the metal plugs46 in the inter-metaldielectric layer 44. A preferred top metal is an alloy of aluminum and copper or an alloy of aluminum, copper and silica. Apassivation layer 49 is disposed over thetop metal layer 48. A plurality of openings is defined thereon to expose the top metal portions below (e.g. 40×40 μm per opening) asbonding pads 50 for wire bonding. Thepassivation layer 49 can be a silicon oxide layer or a layer of borophosphosilicate glass (BPSG) and silicon nitride. At least oneopening 50 is defined as a certain shape to form a mark-shaped bonding pad on thesemiconductor substrate 40. For example, in having at least one mark-shaped bonding pad on thesemiconductor substrate 40, it can be used to indicate the orientation of the circuit in thesemiconductor substrate 40. - The preferred shapes of the mark-shaped bonding pads formed on the
semiconductor substrate 40 are shown inFIGS. 5A to5D (plan views). The mark-shaped bonding pad on arectangular semiconductor substrate 40 can be ashape 50A asFIG. 5A shows, ashape 50B asFIG. 5B shows, a cross shape50C asFIG. 5C shows or ashape asFIG. 50D shows. - According to the present invention, there are two advantages of the mark-shaped
bonding pads 50A to50D that have special shapes other than conventional rectangular bonding pads on thesemiconductor substrate 40. One advantages is the mark-shapedbonding pads 50A to50D can be used as alignment markers for wafer dicing. In addition to conventional markers on scribe lines, a dicing machine can cut dies from a wafer by aligning the mark-shaped bonding pads on the wafer surface, especially when cutting the fragmental portions of a wafer. - Another advantage of the mark-shaped bonding pads in the present invention is that it is easy to identify the orientation of the
rectangular semiconductor substrate 40 with the mark-shapedbonding pads 50A to50D. As shown inFIGS. 5A-5D , there are bonding pads lined up in a row on the surface of therectangular semiconductor substrate 40. There is difficulty identifying the orientation of therectangular semiconductor substrate 40 only with therectangular bonding pads 51. However, it is easy to identify the orientation of therectangular semiconductor substrate 40 according to the invention by defining a least one bonding pad as a mark-shaped bonding pad,e.g. bonding pads 50A-50D. - Therefore, the relative position between the mark-shaped
bonding pads 50A-50D and the other normal rectangular bonding pads denotes the orientation of circuits in thesemiconductor substrate 40. Although the circuits layout cannot be seen from the surface of therectangular semiconductor substrate 40, the orientation of the circuits can still be identified according to the mark-shaped bonding pads on the surface, which makes wire bonding easier to connect the interior circuit by bonding the bonding pads with corresponding leads on a lead frame. - According to the present invention, a probe pad is further provided.
FIG. 6 shows a schematic plan view of a probe pad design according to one embodiment of the invention. There is a mark-shapedbonding pad 50 disposed on the surface of arectangular semiconductor chip 40 to indicate thesubstrate 40's orientation and there is a checkingarea 62 on thesemiconductor chip 40. A plurality of mark-shaped probe pads is disposed on certain circuits inside the checkingarea 62, e.g. ashape probe pad 60A or ashape probe pad 60B. The preferred probe pads can be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica. - The electric performance of certain circuits on the checking
area 62 is obtained by removing the surface of thearea 62 and then measuring the interior probe pads with a micro-probe under a microscope. Since the microscope magnifies the scale of the checkingarea 62, an inspector can clearly identify the orientation of the checkingarea 62 according to the mark-shapedprobe pads - The mark-shaped pads according to the present invention can be applied on a bonding pad structure on the surface of a semiconductor chip or a probe pad on a circuit. A bonding pad structure with at least one mark-shaped pad, can be used as an alignment marker of wafer dicing and/or an indicator of chip orientation in wire bonding. Mark-shaped probe pads on circuits of a checking area can be used as indicators showing the relative positions with each other.
- The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.
Claims (6)
1.-14. (canceled)
15. A method for forming a bonding pad structure on a surface of a semiconductor substrate with a circuit therein, comprising:
disposing a bottom metal layer over the surface of the semiconductor substrate to connect the circuit electrically;
disposing an inter-metal dielectric layer over the bottom metal layer;
forming a plurality of metal plugs in the inter-metal dielectric layer to connect with the bottom metal layer;
disposing a top metal layer over the inter-metal dielectric layer to connect with the metal plugs;
disposing a passivation layer over the top metal layer; and
defining a plurality of openings on the passivation layer to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is defined as a mark-shape to indicate the orientation of the bonding pads on the semiconductor substrate.
16. The method as claimed as inclaim 15 , wherein the mark-shaped bonding pad is defined as a shape.
17. The method as claimed as inclaim 15 , wherein the mark-shaped bonding pad is defined as a shape.
18. The method as claimed as inclaim 15 , wherein the mark-shaped bonding pad is defined as a cross shape
19. The method as claimed as inclaim 15 , wherein the mark-shaped bonding pad is defined as a shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/691,606US20070187838A1 (en) | 2002-03-21 | 2007-03-27 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW91105490 | 2002-03-21 | ||
| TW091105490ATW531776B (en) | 2002-03-21 | 2002-03-21 | Metal pad structure suitable for connection pad and inspection pad |
| US10/150,389US6734572B2 (en) | 2002-03-21 | 2002-05-17 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
| US10/776,714US7211904B2 (en) | 2002-03-21 | 2004-02-09 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
| US11/691,606US20070187838A1 (en) | 2002-03-21 | 2007-03-27 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/776,714DivisionUS7211904B2 (en) | 2002-03-21 | 2004-02-09 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20070187838A1true US20070187838A1 (en) | 2007-08-16 |
Family
ID=28037883
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/150,389Expired - LifetimeUS6734572B2 (en) | 2002-03-21 | 2002-05-17 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
| US10/776,714Expired - LifetimeUS7211904B2 (en) | 2002-03-21 | 2004-02-09 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
| US11/691,606AbandonedUS20070187838A1 (en) | 2002-03-21 | 2007-03-27 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
Family Applications Before (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/150,389Expired - LifetimeUS6734572B2 (en) | 2002-03-21 | 2002-05-17 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
| US10/776,714Expired - LifetimeUS7211904B2 (en) | 2002-03-21 | 2004-02-09 | Pad structure for bonding pad and probe pad and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| US (3) | US6734572B2 (en) |
| TW (1) | TW531776B (en) |
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| JP2003338519A (en)* | 2002-05-21 | 2003-11-28 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| US7199039B2 (en)* | 2003-05-19 | 2007-04-03 | Intel Corporation | Interconnect routing over semiconductor for editing through the back side of an integrated circuit |
| KR100675275B1 (en)* | 2004-12-16 | 2007-01-26 | 삼성전자주식회사 | Semiconductor Device and Pad Arrangement Method |
| CN100552935C (en)* | 2006-10-09 | 2009-10-21 | 日月光半导体制造股份有限公司 | Substrate strip and substrate structure and manufacturing method thereof |
| KR101136708B1 (en)* | 2007-03-13 | 2012-04-19 | 쿨리케 앤드 소파 인더스트리즈, 인코포레이티드 | Method of teaching eyepoints for wire bonding and related semiconductor processing operations |
| US20080303177A1 (en)* | 2007-06-06 | 2008-12-11 | United Microelectronics Corp. | Bonding pad structure |
| US8742599B2 (en)* | 2012-08-30 | 2014-06-03 | Freescale Semiconductor, Inc. | Identification mechanism for semiconductor device die |
| US9536810B1 (en)* | 2015-06-12 | 2017-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flat pad structure for integrating complementary metal-oxide-semiconductor (CMOS) image sensor processes |
| US10109666B2 (en) | 2016-04-13 | 2018-10-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pad structure for backside illuminated (BSI) image sensors |
| CN118099133A (en)* | 2022-11-15 | 2024-05-28 | 长鑫存储技术有限公司 | Semiconductor structure |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW531776B (en) | 2003-05-11 |
| US20040159952A1 (en) | 2004-08-19 |
| US20030181029A1 (en) | 2003-09-25 |
| US6734572B2 (en) | 2004-05-11 |
| US7211904B2 (en) | 2007-05-01 |
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| STCB | Information on status: application discontinuation | Free format text:ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |